Intel® Pentium® P6000 and U5000 Mobile Processor Series Datasheet This is volume 1 of 2.
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Contents 1 Features Summary .................................................................................................... 9 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 2 Introduction .......................................................................................................9 Processor Feature Details ................................................................................... 11 1.2.1 Supported Technologies ..........................................................................
3 Technologies............................................................................................................36 3.1 4 Power Management .................................................................................................37 4.1 4.2 4.3 4.4 4.5 4.6 4.7 5 5.2 Thermal Design Power and Junction Temperature...................................................52 5.1.1 Intel Graphics Dynamic Frequency ............................................................52 5.1.
6.10 6.11 6.12 6.13 6.14 7 Electrical Specifications ........................................................................................... 84 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 8 Error and Thermal Protection .............................................................................. 78 Power Sequencing ............................................................................................. 79 Processor Power Signals ................................................................
Figure Figure Figure Figure Figure Figure Figure 8-22 8-23 8-24 8-25 8-26 8-27 8-28 BGA1288 Ballmap (Top View, Upper-Right Quadrant) ................................ 138 BGA1288 Ballmap (Top View, Lower-Left Quadrant) .................................. 139 BGA1288 Ballmap (Top View, Lower-Right Quadrant) ................................ 140 rPGA Mechanical Package (Sheet 1 of 2) ................................................. 178 rPGA Mechanical Package (Sheet 2 of 2) ...................................
Table 7-41 Table 7-42 Table 7-43 Table Table Table Table Table Table Table Table Table 7-44 7-45 7-46 7-47 7-48 8-49 8-50 8-51 8-52 Datasheet Processor Core (VCC) Active and Idle Mode DC Voltage and Current Specifications......................................................................................... 95 Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications..... 97 Processor Graphics VID based (VAXG) Supply DC Voltage and Current Specifications..................................
Revision History Revision Number Description 001 Initial release 002 Added Pentium P6000 sku information 003 Added Pentium P6100 and P6200 sku information 004 Added Pentium U5600 SKU information Revision Date May 2010 June 2010 September 2010 January 2011 § 8 Datasheet
Features Summary 1 Features Summary 1.1 Introduction Intel® Pentium® P6000 and U5000 Mobile Processor Series is the next generation of 64-bit, multi-core mobile processor built on 32-nanometer process technology. Based on the low-power/high-performance Nehalem micro-architecture, the processor is designed for a two-chip platform as opposed to the traditional three-chip platforms (processor, GMCH, and ICH).
Features Summary Figure 1-1. Intel® Pentium® P6000 and U5000 Mobile Processor Series on the Calpella Platform Dual Core Processor Discrete Graphics (PEG) PCI Express* x16 Processor OR Embedded DisplayPort* (eDP) GPU, Memory Controller 800/1066 MT/s 2 Channels 1 SO-DIMM / Channel DDR3 SO-DIMMs PCI Express x 1 Intel® Flexible Display Interface Digital Display x 3 DMI2 (x4) Intel® Management Engine LVDS Flat Panel Mobile Intel® 5 Series Chipset PCH Analog CRT Serial ATA 6 Ports 3 Gb/s USB 2.
Features Summary 1.2 Processor Feature Details Two execution cores A 32-KB instruction and 32-KB data first-level cache (L1) for each core A 512-KB shared instruction/data second-level cache (L2), 256-KB for each core Up to 3-MB shared instruction/data third-level cache (L3), shared among all cores 1.2.
Features Summary Dual-channel symmetric (Interleaved) Dual-channel asymmetric Command launch modes of 1n/2n Partial Writes to memory using Data Mask (DM) signals On-Die Termination (ODT) Intel® Fast Memory Access (Intel® FMA): Just-in-Time Command Scheduling Command Overlap Out-of-Order Scheduling 1.3.2 PCI Express* The Processor PCI Express ports are fully compliant to the PCI Express Base Specification Revision 2.0. One 16-lane PCI Express* port intended for graphics attach.
Features Summary non-zero) with an Unsupported Request response. Upstream write transactions to addresses above 64 GB will be dropped. Re-issues configuration cycles that have been previously completed with the Configuration Retry status. PCI Express reference clock is 100-MHz differential clock buffered out of system clock generator. Power Management Event (PME) functions.
Features Summary Processor core -> DMI APIC and MSI interrupt messaging support: Message Signaled Interrupt (MSI and MSI-X) messages Downstream SMI, SCI and SERR error indication. Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port DMA, floppy drive, and LPC bus masters. DC coupling no capacitors between the processor and the PCH. Polarity inversion. PCH end-to-end lane reversal across the link. Supports Half Swing low-power/low-voltage. 1.3.
Features Summary 1.3.6 Embedded DisplayPort* (eDP*) Shared with PCI Express Graphics port Shared on upper four logical lanes, after any lane reversal eDP[3:0] map to PEG[12:15] (non-reversed) eDP[3:0] map to PEG[3:0] (reversed) Concurrent eDP and PEG x1 supported 1.3.7 Intel® Flexible Display Interface (Intel® FDI) Carries display traffic from the integrated graphics controller in the processor to the legacy display connectors in the PCH. Based on DisplayPort standard.
Features Summary 1.4.3 Memory Controller Conditional self-refresh (Intel® Rapid Memory Power Management (Intel® RMPM)) Dynamic power-down 1.4.4 PCI Express* L0s and L1 ASPM power management capability 1.4.5 DMI L0s and L1 ASPM power management capability 1.4.6 Integrated Graphics Controller Intel Smart 2D Display Technology (Intel S2DDT) Intel® Display Power Saving Technology (Intel® DPST) Graphics Render C-State (RC6) 1.
Features Summary 1.
Features Summary Term 18 Description Nehalem Intels 45-nm processor design, follow-on to the 45-nm Penryn design. PCH Platform Controller Hub. The new, 2009 chipset with centralized platform capabilities including the main I/O interfaces along with display connectivity, audio features, power management, manageability, security and storage features. The PCH may also be referred to using the name (Mobile) Intel® 5 Series Chipset PECI Platform Environment Control Interface.
Features Summary 1.8 Related Documents Document Number/ Location Document Public Specifications Advanced Configuration and Power Interface Specification 3.0 http://www.acpi.info/ PCI Local Bus Specification 3.0 http://www.pcisig.com/ specifications PCI Express Base Specification 2.0 http://www.pcisig.com DDR3 SDRAM Specification http://www.jedec.org DisplayPort Specification http://www.vesa.org Intel® 64 and IA-32 Architectures Software Developer's Manuals http://www.intel.
Interfaces 2 Interfaces This chapter describes the interfaces supported by the processor. 2.1 System Memory Interface 2.1.1 System Memory Technology Supported The Integrated Memory Controller (IMC) supports DDR3 protocols with two, independent, 64-bit wide channels each accessing one SO-DIMM. It supports a maximum of one, unbuffered non-ECC DDR3 SO-DIMM per-channel thus allowing up to two device ranks per-channel.
Interfaces Table 2-1. Supported SO-DIMM Module Configurations1 Raw Card Version DIMM Capacity DRAM Device Technology DRAM Organization # of DRAM Devices # of Physical Device Ranks # of Row/ Col Address Bits # of Banks Inside DRAM Page Size D2 4 GB 2 Gb 256 M x 8 16 2 15/10 8 8K F 2 GB 1 Gb 128 M x 8 16 2 14/10 8 8K F 4 GB 2 Gb 256 M x 8 16 2 15/10 8 8K NOTES: 1. System memory configurations are based on availability and are subject to change. 2.
Interfaces 2.1.3.1 Single-Channel Mode In this mode, all memory cycles are directed to a single-channel. Single-channel mode is used when either Channel A or Channel B SO-DIMM connectors are populated in any order, but not both. 2.1.3.2 Dual-Channel Mode - Intel® Flex Memory Technology Mode The IMC supports Intel Flex Memory Technology Mode. This mode combines the advantages of the Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes.
Interfaces When both channels are populated with the same memory capacity and the boundary between the dual channel zone and the single channel zone is the top of memory, IMC operates completely in Dual-Channel Symmetric mode. Note: 2.1.3.2.2 The DRAM device technology and width may vary from one channel to the other. Dual-Channel Asymmetric Mode This mode trades performance for system design flexibility.
Interfaces connector per channel. For dual-channel modes both channels must have an SO-DIMM connector populated. For single-channel mode, only a single-channel can have an SO-DIMM connector populated. 2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA) The following sections describe the Just-in-Time Scheduling, Command Overlap, and Out-of-Order Scheduling Intel FMA technology enhancements. 2.1.5.
Interfaces 2.2 PCI Express Interface This section describes the PCI Express interface capabilities of the processor. See the PCI Express Base Specification for details of PCI Express. The processor has one PCI Express controller that can support one external x16 PCI Express Graphics Device or two external x8 PCI Express Graphics Devices. The primary PCI Express Graphics port is referred to as PEG 0 and the secondary PCI Express Graphics port is referred to as PEG 1. 2.2.
Interfaces packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer of the receiving device. Figure 2-5. Packet Flow through the Layers 2.2.1.1 Transaction Layer The upper layer of the PCI Express architecture is the Transaction Layer. The Transaction Layer's primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs).
Interfaces 2.2.2 PCI Express Configuration Mechanism The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge structure. Figure 2-6. PCI Express Related Register Structures in the Processor PCI Express Device PEG0 PCI-PCI Bridge representing root PCI Express port (Device 1) PCI Compatible Host Bridge Device (Device 0) DMI PCI Express extends the configuration space to 4096 bytes per-device/function, as compared to 256 bytes allowed by the Conventional PCI Specification.
Interfaces 2.2.3.1 PCI Express Bifurcated Mode When bifurcated, the signals which had previously been assigned to Lanes 15:8 of the single x16 Primary port are reassigned to lanes 7:0 of the x8 Secondary Port. This assignment applies whether the lane numbering is reversed or not. PCI Express Port 0 is mapped to PCI Device 1 and PCI Express Port 1 is mapped to PCI Device 6. 2.2.3.
Interfaces 2.4 Intel® HD Graphics Controller This section details the 2D, 3D and video pipeline and their respective capabilities. The integrated graphics is powered by a refresh of the fifth generation graphics core and supports twelve, fully-programmable execution cores. Full-precision, floating-point operations are supported to enhance the visual experience of compute-intensive applications.
Interfaces Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel processing. 2.4.1.2 3D Pipeline 2.4.1.2.1 Vertex Fetch (VF) Stage The VF stage executes 3DPRIMITIVE commands. Some enhancements have been included to better support legacy D3D APIs as well as SGI OpenGL*. 2.4.1.2.2 Vertex Shader (VS) Stage The VS stage performs shading of vertices output by the VF function.
Interfaces 2.4.1.3 Video Engine The Video Engine handles the non-3D (media/video) applications. It includes support for VLD and MPEG2 decode in hardware. 2.4.1.4 2D Engine The 2D Engine contains BLT (Block Level Transfer) functionality and an extensive set of 2D instructions. To take advantage of the 3D during engines functionality, some BLT functions make use of the 3D renderer. 2.4.1.4.
Interfaces 2.4.2 Integrated Graphics Display Pipes The integrated graphics controller display pipe can be broken down into three components: Display Planes Display Pipes Embedded DisplayPort and Intel FDI Figure 2-8. Processor Display Block Diagram Plane A eDP Sprite A Pipe A Cursor A VGA Plane B Sprite B Alpha Blend/ Gamma/ Panel Fitter M U X Intel® FDI Pipe B Cursor B 2.4.2.
Interfaces 2.4.2.1.3 Cursors A and B Cursors A and B are small, fixed-sized planes dedicated for mouse cursor acceleration, and are associated with Planes A and B respectively. These planes support resolutions up to 256 x 256 each. 2.4.2.1.4 VGA Used for boot, safe mode, legacy games, etc. Can be changed by an application without OS/driver notification, due to legacy requirements. 2.4.2.
Interfaces Table 2-3. eDP/PEG Ball Mapping eDP Signal PEG Signal Lane Reversal eDP_TX[0] PEG_TX[15] PEG_TX[0] eDP_TX#[0] PEG_TX#[15] PEG_TX#[0] eDP_TX[1] PEG_TX[14] PEG_TX[1] eDP_TX#[1] PEG_TX#[14] PEG_TX#[1] eDP_TX[2] PEG_TX[13] PEG_TX[2] eDP_TX#[2] PEG_TX#[13] PEG_TX#[2] eDP_TX[3] PEG_TX[12] PEG_TX[3] eDP_TX#[3] PEG_TX#[12] PEG_TX#[3] When eDP is enabled, the lower logical lanes are still available for standard PCIe devices, using the PEG 0 controller. PEG 0 is limited to x1.
Interfaces Allow communication of processor thermal and other information to the PECI master. Read averaged Digital Thermal Sensor (DTS) values for fan speed control. 2.6 Interface Clocking 2.6.1 Internal Clocking Requirements Table 2-4.
Technologies 3 Technologies 3.1 Intel Graphics Dynamic Frequency Graphics render frequency are selected by the Intel graphics driver dynamically based on graphics workload demand as permitted by Intel Turbo Boost Technology Driver. The processor core die and the integrated graphics and memory controller core die have an individual TDP limit.
Power Management 4 Power Management This chapter provides information on the following power management topics: ACPI States Processor Core Integrated Memory Controller (IMC) PCI Express Direct Media Interface (DMI) Integrated Graphics Controller 4.1 ACPI States Supported The ACPI states supported by the processor are described in this section. 4.1.1 System States Table 4-5. System States State 4.1.2 Description G0/S0 Full On G1/S3-Cold Suspend-to-RAM (STR).
Power Management 4.1.3 Integrated Memory Controller States Table 4-7. Integrated Memory Controller States State 4.1.4 Description Power up CKE asserted. Active mode. Pre-charge Power down CKE deasserted (not self-refresh) with all banks closed. Active Power down CKE deasserted (not self-refresh) with minimum one bank active. Self-Refresh CKE deasserted using device self-refresh. PCIe Link States Table 4-8. PCIe Link States State L0 4.1.5 Description Full on Active transfer state.
Power Management 4.1.7 Interface State Combinations Table 4-11.
Power Management 4.2.1 Enhanced Intel SpeedStep® Technology The following are the key features of Enhanced Intel SpeedStep Technology: Multiple frequency and voltage points for optimal performance and power efficiency. These operating points are known as P-states. Frequency selection is software controlled by writing to processor MSRs. The voltage is optimized based on the selected frequency and the number of active processor cores.
Power Management Figure 4-9. Idle Power Management Breakdown of the Processor Cores Thread 0 Thread 0 Core 0 State Core 1 State Processor Package State Entry and exit of the C-States at the thread and core level are shown in below figure. Figure 4-10.
Power Management Table 4-13.Coordination of Thread Power States at the Core Level Processor Core C-State Thread 1 C0 C1 C3 C6 C0 C0 C0 C0 C0 C1 C0 C11 C11 C11 C3 C0 C11 C3 C3 C6 C0 C11 C3 C6 NOTE:If enabled, the core C-state will be C1E if all actives cores have also resolved a core C1 state or higher 4.2.
Power Management 4.2.4 Core C-states The following are general rules for all core C-states, unless specified otherwise: A core C-State is determined by the lowest numerical thread state (e.g., Thread 0 requests C1E while Thread 1 requests C3, resulting in a core C1E state). See Table 4-11.
Power Management 4.2.4.4 Core C6 State Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an MWAIT(C6) instruction. Before entering core C6, the core will save its architectural state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero volts. During exit, the core is powered on and its architectural state is restored. 4.2.4.
Power Management The processor exits a package C-state when a break event is detected. Depending on the type of break event, the processor does the following: If a core break event is received, the target core is activated and the break event message is forwarded to the target core. If the break event is not masked, the target core enters the core C0 state and the processor enters package C0. If the break event is masked, the processor attempts to re-enter its previous package state.
Power Management Figure 4-11.Package C-State Entry and Exit C0 C3 C1 4.2.5.1 C6 Package C0 The normal operating state for the processor. The processor remains in the normal state when at least one of its cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low power state. Individual cores may be in lower power idle states while the package is in C0. 4.2.5.
Power Management No notification to the system occurs upon entry to C1/C1E. 4.2.5.3 Package C3 State A processor enters the package C3 low power state when: At least one core is in the C3 state. The other cores are in a C3 or lower power state, and the processor has been granted permission by the platform. The platform has not granted a request to a package C6 state but has allowed a package C6 state. In package C3-state, the L3 shared cache is snoopable. 4.2.5.
Power Management 4.3.1 Disabling Unused System Memory Outputs Any system memory (SM) interface signal that goes to a memory module connector in which it is not connected to any actual memory devices (such as SO-DIMM connector is unpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SM signals are: Reduced power consumption.
Power Management Table 4-16.Targeted Memory State Conditions Mode Memory State with Internal Graphics Memory State with External Graphics C0, C1, C1E Dynamic memory rank power down based on idle conditions. Dynamic memory rank power down based on idle conditions. C3, C6 If the internal graphics engine is idle and there are no pending display requests when in single display mode, then enter self-refresh. Otherwise use dynamic memory rank power down based on idle conditions.
Power Management 4.5 DMI Power Management Active power management support using L0s/L1 state. 4.6 Integrated Graphics Power Management 4.6.1 Intel® Display Power Saving Technology 5.0 (Intel® DPST 5.0) Intel DPST maintains visual experience by managing display image brightness and contrast while adaptively dimming the backlight. As a result, the display backlight power can be reduced by up to 25% depending on Intel DPST settings and system use. Intel DPST 5.
Power Management 4.7 Thermal Power Management See Section 5, Thermal Management on page 52 for all graphics thermal power management-related features.
Thermal Management 5 Thermal Management A multi-chip package (MCP) processor requires a thermal solution to maintain temperatures of the processor core and graphics/memory core within operating limits. A complete thermal solution provides both the component-level and the system-level thermal management.
Thermal Management system that is shipped with the customers platform and Intel Graphics Dynamic Frequency is enabled, the Intel Turbo Boost Technology driver and graphics driver must be installed and operating to keep the product operating within specification limits. Caution: 5.1.2 The TURBO_POWER_CURRENT_LIMIT MSR is exclusively reserved for Intel Turbo Technology Driver use. Under no circumstances should this value be altered from the default register value after reset of the processor.
Thermal Management Note Definition 5 Processor core and integrated graphics and memory controller junction temperatures are monitored by their respective DTS. A DTS outputs a temperature relative to the maximum supported junction temperature. The error associated with DTS measurements will not exceed ±5°C within the operating range. 6 The power supply to the processor core and the integrated graphics /Memory core should be designed as per Intels guidelines.
Thermal Management Table 5-18.Intel Pentium P6000 Mobile Processor Series Dual-Core SV Thermal Power Specifications TDP1,2,6,7 HFM 25 12.5 Power Sharing Design Points8 Frequency 35 1.86 500 up to 667 LFM 20 12.5 32.5 933 MHz N/A HFM 25 12.5 35 2.00 500 up to 667 LFM 20 12.5 32.5 933 MHz N/A HFM 25 12.5 35 2.13 500 up to 667 LFM 5.1.3 20 12.5 32.
Thermal Management Table 5-20.35 W Standard Voltage (SV) Processor Idle Power Symbol Parameter Min Typ Max Tj PC1E Idle power in the Package C1e state - - 16 W 50 ºC PC3 Idle power in the Package C3 state - - 7.5 W 35 ºC 5.1.
Thermal Management 5.1.5 Component Power Measurement/Estimation Error The processor input pin (ISENSE) informs the processor core of how much amperage the processor core is consuming. This information is provided by the processor core VR. The process will calculate its current power based upon the ISENSE input information and current voltage state. The internal graphics and memory controller power is estimated by the GFX driver using PMON.
Thermal Management Adjusting the operating frequency (via the core ratio multiplier) and input voltage (via the VID signals). Modulating (starting and stopping) the internal processor core clocks (duty cycle). The Adaptive Thermal Monitor dynamically selects the appropriate method. BIOS is not required to select a specific method as with previous-generation processors supporting Intel® Thermal Monitor 1 (TM1) or Intel® Thermal Monitor 2 (TM2).
Thermal Management Figure 5-12.Frequency and Voltage Ordering Once a target frequency/bus ratio is resolved, the processor core will transition to the new target automatically. On an upward operating point transition, the voltage transition precedes the frequency transition. On a downward transition, the frequency transition precedes the voltage transition. When transitioning to a target core operating voltage, a new VID code to the voltage regulator is issued.
Thermal Management If a processor load-based Enhanced Intel SpeedStep Technology/P-state transition (through MSR write) is initiated while the Adaptive Thermal Monitor is active, there are two possible outcomes: If the P-state target frequency is higher than the processor core optimized target frequency, the p-state transition will be deferred until the thermal event has been completed.
Thermal Management Code execution is halted in C1-C6. Therefore temperature cannot be read via the processor MSR without bringing a core back into C0. However, temperature can still be monitored through PECI in lower C-states. Unlike traditional thermal devices, the DTS outputs a temperature relative to the maximum supported operating temperature of the processor (Tj,max). It is the responsibility of software to convert the relative temperature to an absolute temperature.
Thermal Management 5.2.1.3.2 Voltage Regulator Protection PROCHOT# may be used for thermal protection of voltage regulators (VR). System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low) and activating the TCC, the VR will cool down as a result of reduced processor power consumption.
Thermal Management bi-directional PROCHOT#. Platforms must not rely on software usage of this mechanism to limit the processor temperature. On-Demand Mode can be done via processor MSR or chipset I/O emulation. On-Demand Mode may be used in conjunction with the Adaptive Thermal Monitor. However, if the system software tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the On-Demand mode.
Thermal Management 5.2.
Thermal Management 5.2.2.1.3 Catastrophic Trip Point This trip point is set at the temperature at which the integrated graphics and memory controller must be shut down immediately without any software support. This trip point may be programmed to generate an interrupt, enable throttling, or immediately shut down the system (via Halt or via THERMTRIP# assertion). Crossing a trip point in either direction may generate several types of interrupts. 5.2.2.1.
Thermal Management digital thermal sensor (DTS) and initiates duty cycle throttling to delay memory transactions and thereby reducing MCH power. Power reduction is memory configuration and application dependant but duty cycle throttling intervals can be customized for maximum throttling efficiency. The TDP Controller can also be used as a bandwidth limiter using programmable memory read/write bandwidth thresholds.
Thermal Management controller will shut off its internal clocks (thus halting program execution) in an attempt to reduce the core junction temperature. Once activated, THERMTRIP# remains latched until RSTIN# is asserted. 5.2.2.5 Render Thermal Throttling Render Thermal Throttling of the integrated graphics and memory controller allows for the reduction the render core engine frequency and voltage, thus reducing internal graphics controller power and integrated graphics and memory controller thermals.
Thermal Management 5.2.3.2 Processor Thermal Data Sample Rate and Filtering The processor digital thermal sensor (DTS) provides an improved capability to monitor device hot spots, which inherently leads to more varying temperature readings over short time intervals. To reduce the sample rate requirements on PECI and improve thermal data stability vs. time the processor DTS implements an averaging algorithm that filters the incoming data.
Signal Description 6 Signal Description This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. The following notations are used to describe the signal type: Notations Signal Type I Input Pin O Output Pin I/O Bi-directional Input/Output Pin The signal description also includes the type of buffer used for the particular signal: Table 6-21.
Signal Description 6.1 System Memory Interface Table 6-22.Memory Channel A (Sheet 1 of 2) Signal Name Description SA_BS[2:0] Bank Select: These signals define which banks are selected within each SDRAM rank. SA_WE# SA_RAS# SA_CAS# SA_DM[7:0] SA_DQS[7:0] SA_DQS#[7:0] SA_DQ[63:0] SA_MA[15:0] SA_CK[1:0] SA_CK#[1:0] 70 Direction/Buffer Type O DDR3 Write Enable Control Signal: Used with SA_RAS# and SA_CAS# (along with SA_CS#) to define the SDRAM Commands.
Signal Description Table 6-22.Memory Channel A (Sheet 2 of 2) Signal Name SA_CKE[1:0] Description Clock Enable: (1 per rank) Used to: - Initialize the SDRAMs during power-up Direction/Buffer Type O DDR3 - Power-down SDRAM ranks - Place all SDRAM ranks into and out of selfrefresh during STR SA_CS#[1:0] SA_ODT[1:0] Chip Select: (1 per rank) Used to select particular SDRAM components during the active state. There is one Chip Select for each SDRAM rank. On Die Termination: Active Termination Control.
Signal Description Table 6-23.Memory Channel B (Sheet 2 of 2) Signal Name Description Direction/ Buffer Type SB_MA[15:0] Memory Address: These signals are used to provide the multiplexed row and column address to the SDRAM. DDR3 SB_CK[1:0] SB_CK#[1:0] SB_CKE[1:0] SDRAM Differential Clock: Channel B SDRAM Differential clock signal pair. The crossing of the positive edge of SB_CK and the negative edge of its complement SB_CK# are used to sample the command and control signals on the SDRAM.
Signal Description 6.3 Reset and Miscellaneous Signals Table 6-25.Reset and Miscellaneous Signals (Sheet 1 of 2) Signal Name SM_DRAMRST# PM_EXT_TS#[0] PM_EXT_TS#[1] COMP0 COMP1 COMP2 COMP3 PM_SYNC RESET_OBS# RSTIN# BPM#[7:0] DBR# Datasheet Description DDR3 DRAM Reset: Reset signal from processor to DRAM devices. One for all channels or SO-DIMMs.
Signal Description Table 6-25.Reset and Miscellaneous Signals (Sheet 2 of 2) Signal Name PRDY# PREQ# RSVD RSVD_TP RSVD_NCTF 6.4 Direction/Buffer Type Description PRDY#: A processor output used by debug tools to determine processor debug readiness. O Asynchronous GTL PREQ#: Used by debug tools to request debug operation of the processor. I Asynchronous GTL RESERVED. All signals that are RSVD and RSVD_NCTF must be left unconnected on the board.
Signal Description 6.5 Embedded DisplayPort (eDP) Embedded Display Port Signals Description eDP_TX[3:0] Embedded DisplayPort Transmit Differential Pair: Nominally, eDP_TX[3:0] is multiplexed with PEG_TX[12:15] and eDP_TX#[3:0] is multiplexed with PEG_TX#[12:15].
Signal Description Table 6-27.Intel® Flexible Display Interface (Sheet 2 of 2) Signal Name FDI_TX[7:4] FDI_TX#[7:4] FDI_FSYNC[1] FDI_LSYNC[1] FDI_INT 6.7 Description Intel® Flexible Display Interface Transmit Differential Pair - Pipe B Direction/Buffer Type O FDI Intel® Flexible Display Interface Frame Sync - Pipe B CMOS I Intel® Flexible Display Interface Line Sync - Pipe B CMOS Intel® Flexible Display Interface Hot Plug Interrupt CMOS I I DMI Table 6-28.
Signal Description 6.9 TAP Signals Table 6-30.TAP Signals Signal Name Description Direction/Buffer Type TCK TCK (Test Clock): Provides the clock input for the processor Test Bus (also known as the Test Access Port). CMOS TDI (Test Data In): Transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support.
Signal Description 6.10 Error and Thermal Protection Table 6-31.Error and Thermal Protection Signal Name Description CATERR# Catastrophic Error: This signal indicates that the system has experienced a catastrophic error and cannot continue to operate. The processor will set this for non-recoverable machine check errors or other unrecoverable internal errors. External agents are allowed to assert this pin which will cause the processor to take a machine check exception.
Signal Description 6.11 Power Sequencing Table 6-32.Power Sequencing Signal Name VCCPWRGOOD_0 VCCPWRGOOD_1 Description VCCPWRGOOD_0 and VCCPWRGOOD_1 (Power Good) Processor Input: The processor requires these signals to be a clean indication that: Direction/Buffer Type I Asynchronous CMOS -VCC, VCCPLL, and VTT supplies are stable and within their specifications -BCLK is stable and has been running for a minimum number of cycles. Both signals must then transition monotonically to a high state.
Signal Description 6.12 Processor Power Signals Table 6-33.Processor Power Signals (Sheet 1 of 3) Signal Name Direction/Buffer Type VCC Processor core power rail. Ref VTT Processor I/O power rail (1.05 V). VTT0 and VTT1 should share the same VR Ref DDR3 power rail (1.5 V) Ref VCCPLL Power rail for filters and PLLs (1.8 V) Ref ISENSE Current Sense from an Intel® MVP6.5 Compliant Regulator to the processor core.
Signal Description Table 6-33.Processor Power Signals (Sheet 2 of 3) Signal Name Description Direction/Buffer Type VID[6] VID[6:0] (Voltage ID) Pins: Used to support automatic selection of power supply voltages (VCC). These are CMOS signals that are driven by the processor. CMOS VID[5:3]/CSC[2:0] VID[2:0]/MSID[2:0] O CSC[2:0]/VID[5:3] - Current Sense Configuration bits, for ISENSE gain setting. This value is latched on the rising edge of VTTPWRGOOD.
Signal Description Table 6-33.Processor Power Signals (Sheet 3 of 3) Direction/Buffer Type Signal Name Description GFX_DPRSLPVR GPU output signal to Intel MVP6.5 compliant VR. When asserted this signal indicates that the GPU is in render suspend mode. This signal is also used to control render suspend state exit slew rate. GFX_IMON O CMOS Current Sense from an Intel MVP6.5 Compliant Regulator to the GPU.
Signal Description Table 6-35.
Electrical Specifications 7 Electrical Specifications 7.1 Power and Ground Pins The processor has VCC, VTT, VDDQ, VCCPLL, VAXG and VSS (ground) inputs for on-chip power distribution. All power pins must be connected to their respective processor power planes, while all VSS pins must be connected to the system ground plane. Use of multiple power and ground planes is recommended to reduce I*R drop.
Electrical Specifications 7.3.1 PLL Power Supply An on-die PLL filter solution is implemented on the processor. Refer to Table 7-36 for DC specifications 7.4 Voltage Identification (VID) The processor uses seven voltage identification pins, VID[6:0], to support automatic selection of the processor power supply voltages. VID pins for the processor are CMOS outputs driven by the processor VID circuitry.
Electrical Specifications Table 7-36.Voltage Identification Definition (Sheet 2 of 4) 86 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 0 0 0 0 1 1 1 1.4125 0 0 0 1 0 0 0 1.4000 0 0 0 1 0 0 1 1.3875 0 0 0 1 0 1 0 1.3750 0 0 0 1 0 1 1 1.3625 0 0 0 1 1 0 0 1.3500 0 0 0 1 1 0 1 1.3375 0 0 0 1 1 1 0 1.3250 0 0 0 1 1 1 1 1.3125 0 0 1 0 0 0 0 1.3000 0 0 1 0 0 0 1 1.2875 0 0 1 0 0 1 0 1.
Electrical Specifications Table 7-36.Voltage Identification Definition (Sheet 3 of 4) Datasheet VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 0 1 1 0 1 0 1 0.8375 0 1 1 0 1 1 0 0.8250 0 1 1 0 1 1 1 0.8125 0 1 1 1 0 0 0 0.8000 0 1 1 1 0 0 1 0.7875 0 1 1 1 0 1 0 0.7750 0 1 1 1 0 1 1 0.7625 0 1 1 1 1 0 0 0.7500 0 1 1 1 1 0 1 0.7375 0 1 1 1 1 1 0 0.7250 0 1 1 1 1 1 1 0.7125 1 0 0 0 0 0 0 0.
Electrical Specifications Table 7-36.Voltage Identification Definition (Sheet 4 of 4) 88 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 1 1 0 0 0 1 1 0.2625 1 1 0 0 1 0 0 0.2500 1 1 0 0 1 0 1 0.2375 1 1 0 0 1 1 0 0.2250 1 1 0 0 1 1 1 0.2125 1 1 0 1 0 0 0 0.2000 1 1 0 1 0 0 1 0.1875 1 1 0 1 0 1 0 0.1750 1 1 0 1 0 1 1 0.1625 1 1 0 1 1 0 0 0.1500 1 1 0 1 1 0 1 0.1375 1 1 0 1 1 1 0 0.
Electrical Specifications Table 7-37.Market Segment Selection Truth Table for MSID[2:0] 1. 2. Description1,2 MSID[2] MSID[1] MSID[0] 0 0 0 Reserved 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved 1 0 0 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved Notes Standard Voltage (SV) 35-W Supported 3 NOTES: MSID[2:0] signals are provided to indicate the maximum platform capability to the processor. MSID is used on rPGA988A platforms only. 3.
Electrical Specifications 7.6 Signal Groups Signals are grouped by buffer type and similar characteristics as listed in Table 7-38. The buffer type indicates which signaling technology and specifications apply to the signals. All the differential signals, and selected DDR3 and Control Sideband signals have On-Die Termination (ODT) resistors. There are some signals that do not have ODT and need to be terminated on the board. Table 7-38.
Electrical Specifications Table 7-38.
Electrical Specifications Table 7-38.
Electrical Specifications 7.8 Absolute Maximum and Minimum Ratings Table 7-39 specifies absolute maximum and minimum ratings. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected.
Electrical Specifications device storage conditions for a sustained period of time. At conditions outside sustained limits, but within absolute maximum and minimum ratings, quality and reliability may be affected. Table 7-40.Storage Condition Ratings Symbol Parameter Tabsolute storage The non-operating device storage temperature. Damage (latent or otherwise) may occur when exceeded for any length of time.
Electrical Specifications 7.10.1 Voltage and Current Specifications Table 7-41.Processor Core (VCC) Active and Idle Mode DC Voltage and Current Specifications Symbol HFM_VID LFM_VID Parameter Segment Min Typ Max Unit Note V 1,2,7 V 1,2 V 2, 3, 4 A 5,7 A 6,7 A 6 VID Range for Highest Frequency Mode SV 0.800 1.4 ULV 0.750 1.4 VID Range for Lowest Frequency Mode SV 0.775 1.0 ULV 0.725 1.
Electrical Specifications Figure 7-13.Active VCC and ICC Loadline (PSI# Asserted) V CC [V ] S lo p e = S L O P E LL V C C _ S E N S E , V S S _ S E N S E p in s . D i f f e r e n t ia l R e m o t e S e n s e r e q u i r e d . V CC m ax V C C, V DC CC V C C, m ax 1 3 m V = R IP P L E nom DC m in V C C m in ± V C C T o le r a n c e = V R S t. P t.
Electrical Specifications Table 7-42.Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note Voltage for the memory controller and shared cache defined at the motherboard Vtt pinfield via 0.9975 1.05 1.1025 V 1 Voltage for the memory controller and shared cache defined across VTT_SENSE and VSS_SENSE_VTT 0.9765 1.05 1.1235 V 2 VDDQ(DC+AC) Processor I/O supply voltage for DDR3 (DC + AC specification) 1.425 1.5 1.
Electrical Specifications Table 7-43.Processor Graphics VID based (VAXG) Supply DC Voltage and Current Specifications Symbol GFX_VID Parameter Min Typ Unit Note1 V 2,3,4 VID Range for VAXG SV 0 1.4 ULV 0 1.35 VAXG Graphics core voltage See Figure 7-15 TOLAXG VAXG Tolerance See Figure 7-15 Non-VR LL contribution Non-VR Load Line Contribution for VAXG 4 rPGA m 4.
Electrical Specifications Table 7-44.DDR3 Signal Group DC Specifications Symbol Parameter Alpha Group Min Typ VIL Input Low Voltage (e,f) VIH Input High Voltage (e,f) VOL Output Low Voltage (c,d,e,f) (VDDQ / 2)* (RON / (RON+R VTT_TERM)) VOH Output High Voltage (c,d,e,f) VDDQ - ((VDDQ / 2)* (RON/ (RON+R VTT_TERM)) RON DDR3 Clock Buffer On Resistance Max Units Notes1 0.43*VDDQ V 2,4 V 3 0.
Electrical Specifications Table 7-45.
Electrical Specifications Table 7-46.PCI Express DC Specifications Symbol Alpha Group Parameter Min 0.8 Typ Max Units Notes1 1.
Electrical Specifications Table 7-47.eDP DC Specifications Symbol Parameter Min Typ Max Units Notes4 eDP_HPD# VIL Input Low Voltage -0.3 0.3 V VIH Input High Voltage 0.6 1.155 V eDP_AUX, eDP_AUX# VAUX-DIFFp-p (Tx) AUX Peak-to-Peak Voltage at the transmitting device 0.39 1.38 1 VAUX-DIFFp-p (Rx) AUX Peak-to-Peak Voltage at the receiving device 0.32 1.36 eDP_ICOMPO Comp Resistance 49.5 50 50.5 2,3 eDP_ICOMPI Comp Resistance 49.5 50 50.
Electrical Specifications Table 7-48.PECI DC Electrical Limits Symbol Definition and Conditions Vin Input Voltage Range Vhysteresis Hysteresis Vn Min Max Units -0.150 VTT V 0.1 * VTT N/A V Negative-edge Threshold Voltage 0.275 * VTT 0.500 * VTT V Vp Positive-edge Threshold Voltage 0.550 * VTT 0.725 * VTT V Isource High-Level Output Source -6.0 N/A mA 0.5 1.0 mA Notes 1 (VOH = 0.75 * VTT) Isink Low-Level Output Sink (VOL = 0.
Processor Pin and Signal Information 8 Processor Pin and Signal Information 8.1 Processor Pin Assignments Provides a listing of all processor pins ordered alphabetically by pin name for the rPGA988A and BGA1288 package respectively. Table 8-49 and Table 8-52 provides a listing of all processor pins ordered alphabetically by pin number for the rPGA988A and BGA1288 package respectively Figure 8-21, Figure 8-22, Figure 8-23, Figure 8-24 show the Top-Down view of the rPGA988A pinmap.
Processor Pin and Signal Information Figure 8-17.
Processor Pin and Signal Information Figure 8-18.
Processor Pin and Signal Information Figure 8-19.
Processor Pin and Signal Information Figure 8-20.
Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin List by Pin Number Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number Datasheet Pin Name A2 KEY A3 RSVD_NCTF A4 SB_DQ[6] Buffer Type DDR3 Dir.
Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number 110 Pin Name Buffer Type Dir. Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number Pin Name Buffer Type Dir.
Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number Datasheet Pin Name Buffer Type Dir. O Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number Pin Name Buffer Type Dir.
Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number 112 Pin Name Table 8-49.rPGA988A Processor Pin List by Pin Number Buffer Type Dir. Pin Number Buffer Type Dir.
Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number 113 Pin Name Table 8-49.rPGA988A Processor Pin List by Pin Number Buffer Type Dir. Pin Number Buffer Type Dir.
Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number Datasheet Pin Name Table 8-49.rPGA988A Processor Pin List by Pin Number Buffer Type Dir. Pin Number Pin Name Buffer Type Dir.
Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number 115 Pin Name Buffer Type Dir. Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number Pin Name Buffer Type Dir.
Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number Datasheet Pin Name Buffer Type Dir. Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number Pin Name Buffer Type Dir.
Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number 117 Pin Name Buffer Type Dir. D3 VSS GND D4 SB_DM[0] DDR3 D5 SB_DQS#[0] DDR3 D6 VSS GND D7 SA_DM[1] DDR3 O D8 SA_DQ[8] DDR3 I/O D9 VSS GND D10 SA_DQ[5] DDR3 D11 VTT0 REF D12 VTT0 D13 Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number Pin Name Buffer Type Dir.
Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number 118 Pin Name Table 8-49.rPGA988A Processor Pin List by Pin Number Buffer Type Dir. Pin Number Pin Name Buffer Type Dir.
Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number Datasheet Pin Name Buffer Type Dir. O H7 SA_DM[2] DDR3 H8 VSS GND H9 SA_DQS[2] DDR3 H10 SA_DQ[16] DDR3 H11 VSS GND H12 VTT0 H13 VSS H14 H15 H16 Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number Pin Name Buffer Type Dir.
Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number 120 Pin Name Buffer Type Dir. Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number Pin Name Buffer Type Dir.
Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number Datasheet Pin Name Buffer Type Dir. Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number Pin Name Buffer Type Dir.
Processor Pin and Signal Information Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number 122 Pin Name Buffer Type Dir. Table 8-49.rPGA988A Processor Pin List by Pin Number Pin Number Pin Name Buffer Type Dir.
Processor Pin and Signal Information Table 8-50.rPGA988A Processor Pin List by Pin Name Pin Number Buffer Type Dir. A16 DIFF CLK I BCLK_ITP AR30 DIFF CLK BCLK_ITP# AT30 DIFF CLK BCLK# B16 BPM#[0] AJ22 BPM#[1] Pin Number Buffer Type Dir.
Processor Pin and Signal Information Table 8-50.rPGA988A Processor Pin List by Pin Name Pin Number Buffer Type Dir. FDI_TX#[4] G21 FDI O FDI_TX#[5] E19 FDI FDI_TX#[6] F21 FDI Pin Name 124 Table 8-50.rPGA988A Processor Pin List by Pin Name Pin Number Buffer Type Dir.
Processor Pin and Signal Information Table 8-50.rPGA988A Processor Pin List by Pin Name Pin Number Buffer Type Dir. PEG_TX#[1] M35 PCIe O RSVD AJ15 PEG_TX#[2] M33 PCIe O RSVD AJ26 PEG_TX#[3] M30 PCIe O RSVD AJ27 Pin Name Datasheet Table 8-50.
Processor Pin and Signal Information Table 8-50.rPGA988A Processor Pin List by Pin Name Pin Name 126 Pin Number Buffer Type Dir. Table 8-50.rPGA988A Processor Pin List by Pin Name Pin Name Pin Number Buffer Type Dir.
Processor Pin and Signal Information Table 8-50.rPGA988A Processor Pin List by Pin Name Pin Number Buffer Type Dir. SA_DQ[12] E9 DDR3 I/O SA_DQ[13] B7 DDR3 SA_DQ[14] E7 DDR3 Pin Name Datasheet Table 8-50.rPGA988A Processor Pin List by Pin Name Pin Number Buffer Type Dir.
Processor Pin and Signal Information Table 8-50.rPGA988A Processor Pin List by Pin Name Pin Number Buffer Type Dir. SA_MA[4] V1 DDR3 O SA_MA[5] AA9 DDR3 SA_MA[6] V8 SA_MA[7] SA_MA[8] SA_MA[9] Pin Number Buffer Type Dir.
Processor Pin and Signal Information Table 8-50.rPGA988A Processor Pin List by Pin Name Pin Number Buffer Type Dir. Pin Name Pin Number Buffer Type Dir.
Processor Pin and Signal Information Table 8-50.rPGA988A Processor Pin List by Pin Name Pin Number Buffer Type Dir.
Processor Pin and Signal Information Table 8-50.
Processor Pin and Signal Information Table 8-50.
Processor Pin and Signal Information Table 8-50.rPGA988A Processor Pin List by Pin Name Pin Number Buffer Type VSS AH27 GND VSS AH28 VSS AH29 Pin Name Datasheet Table 8-50.rPGA988A Processor Pin List by Pin Name Pin Number Buffer Type VSS AM14 GND GND VSS AM17 GND GND VSS AM2 GND Dir.
Processor Pin and Signal Information Table 8-50.
Processor Pin and Signal Information Table 8-50.
Processor Pin and Signal Information Table 8-50.
Processor Pin and Signal Information Figure 8-21.
Processor Pin and Signal Information Figure 8-22.
Processor Pin and Signal Information Figure 8-23.
Processor Pin and Signal Information Figure 8-24.
Processor Pin and Signal Information Table 8-51.BGA1288 Processor Ball List by Ball Name (Sheet 1 of 37) Pin Name BCLKAC71 AK7 Buffer Type Dir DIFF CLK I BCLK # AK8 DIFF CLK I BCLK_ITP K71 DIFF CLK O BCLK_ITP # Datasheet Pin # J70 Table 8-51.
Processor Pin and Signal Information Table 8-51.BGA1288 Processor Ball List by Ball Name (Sheet 3 of 37) Pin # Buffer Type Dir DMI_TX[3] J11 DMI O DMI_TX#[0] H17 DMI DMI_TX#[1] K15 DMI DMI_TX#[2] J13 DMI_TX#[3] Pin Name DPLL_REF_SSCLK 142 Table 8-51.
Processor Pin and Signal Information Table 8-51.BGA1288 Processor Ball List by Ball Name (Sheet 5 of 37) Pin # Buffer Type Dir D29 PCIe I PEG_TX#[11] PEG_RX#[8] B26 PCIe I PEG_RX#[9] D26 PCIe I PEG_RX#[10] B23 PCIe PEG_RX#[11] D22 PCIe Pin Name PEG_RX#[7] Datasheet Table 8-51.
Processor Pin and Signal Information Table 8-51.
Processor Pin and Signal Information Table 8-51.BGA1288 Processor Ball List by Ball Name (Sheet 9 of 37) Pin Name SA_DQ[19] Datasheet Table 8-51.
Processor Pin and Signal Information Table 8-51.
Processor Pin and Signal Information Table 8-51.
Processor Pin and Signal Information Table 8-51.
Processor Pin and Signal Information Table 8-51.
Processor Pin and Signal Information Table 8-51.
Processor Pin and Signal Information Table 8-51.
Processor Pin and Signal Information Table 8-51.
Processor Pin and Signal Information Table 8-51.
Processor Pin and Signal Information Table 8-51.
Processor Pin and Signal Information Table 8-51.
Processor Pin and Signal Information Table 8-51.
Processor Pin and Signal Information Table 8-51.
Processor Pin and Signal Information Table 8-51.
Processor Pin and Signal Information Table 8-51.
Processor Pin and Signal Information Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 3 of 37) Pin # 160 Pin Name Buffer Type Dir Table 8-52.
Processor Pin and Signal Information Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 5 of 37) Pin # Datasheet Pin Name AD26 VAXG AD28 AD30 Buffer Type Dir Table 8-52.
Processor Pin and Signal Information Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 7 of 37) Pin # 162 Pin Name AH12 VAXG AH14 AH15 Buffer Type Dir Table 8-52.
Processor Pin and Signal Information Table 8-52.
Processor Pin and Signal Information Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 11 of 37) Pin # 164 Pin Name AN46 VCAP1 AN48 AN50 Buffer Type Dir Table 8-52.
Processor Pin and Signal Information Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 13 of 37) Pin # Datasheet Pin Name Buffer Type Dir Table 8-52.
Processor Pin and Signal Information Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 15 of 37) Pin # 166 Pin Name Buffer Type Dir Table 8-52.
Processor Pin and Signal Information Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 17 of 37) Pin # Datasheet Pin Name Buffer Type Dir Table 8-52.
Processor Pin and Signal Information Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 19 of 37) Pin # 168 Pin Name Table 8-52.
Processor Pin and Signal Information Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 21 of 37) Pin # Datasheet Pin Name Buffer Type BJ1 VSS BJ4 SB_DQ[12] DDR3 BJ5 SA_DQS[1] DDR3 BJ7 SA_DQS#[1] DDR3 BJ9 VSS BJ10 SA_DM[1] DDR3 BJ12 SM_DRAMRST# DDR3 BJ20 SA_DQ[28] DDR3 BJ21 VSS BJ28 SA_MA[12] DDR3 BJ30 SA_MA[7] DDR3 BJ38 VDDQ BJ40 SA_DQ[32] DDR3 BJ47 SA_CS#[1] BJ48 SA_DQ[45] BJ55 Dir GND Table 8-52.
Processor Pin and Signal Information Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 23 of 37) Pin # 170 Pin Name Buffer Type BM70 VSS BN1 VSS BN4 SB_DQS[1] BN6 VSS BN8 SA_DQ[15] DDR3 BN9 SA_DQ[17] BN11 SA_DQ[16] BN13 Dir GND Table 8-52.
Processor Pin and Signal Information Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 25 of 37) Pin # Datasheet Pin Name Table 8-52.
Processor Pin and Signal Information Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 27 of 37) Pin # 172 Pin Name Buffer Type Dir Table 8-52.
Processor Pin and Signal Information Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 29 of 37) Pin # Datasheet Pin Name Buffer Type Dir Table 8-52.
Processor Pin and Signal Information Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 31 of 37) Pin # 174 Pin Name Buffer Type Dir J9 VSS GND J20 PEG_TX#[15] PCIe J21 PEG_CLK# DIFF CLK J28 PEG_RX[4] PCIe I J30 PEG_TX[8] PCIe O J38 PEG_RX[1] PCIe I J40 VSS J47 J48 Table 8-52.
Processor Pin and Signal Information Table 8-52.
Processor Pin and Signal Information Table 8-52.BGA1288 Processor Ball List by Ball Number (Sheet 35 of 37) Pin # 176 Pin Name Buffer Type Dir Table 8-52.
Processor Pin and Signal Information Table 8-52.
Processor Pin and Signal Information 8.2 Package Mechanical Information Figure 8-25.
Processor Pin and Signal Information Figure 8-26.
Processor Pin and Signal Information Figure 8-27.
Processor Pin and Signal Information Figure 8-28.
