R Intel® E7205 Chipset Memory Controller Hub (MCH) Specification Update December 2002 ® Notice: The Intel E7205 chipset MCH may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
® R Intel E7205 Chipset MCH INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
® R Intel E7205 Chipset MCH Contents Revision History ...................................................................................................................4 Preface.................................................................................................................................5 Errata ...................................................................................................................................9 Specification Changes ......................................
® R Intel E7205 Chipset MCH Revision History Revision 4 Description Date -001 Initial Release November 2002 -002 Updated Errata E1 & E2.
® R Intel E7205 Chipset MCH Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
® R Intel E7205 Chipset MCH Component Identification via Programming Interface The Intel® E7205 chipset MCH stepping can be identified by the following register contents: 1 2 3 Stepping Vendor ID Device ID Revision Number B0 8086h 255Dh 03h NOTES: 1. The Vendor ID corresponds to bits 15:0 of the Vendor ID Register located at offset 00–01h in the PCI function 0 configuration space. 2.
® R Intel E7205 Chipset MCH Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed Intel® E7205 chipset MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
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® R Intel E7205 Chipset MCH Errata 1. tVAL(min) Timing Is Not Meeting AGP 3.0 Specification Problem: During simulation studies, it was determined that the AGP signals were not meeting the tVAL(min) of 1ns. Implication: AGP interface is susceptible to latching invalid data. Workaround: Minimum trace lengths for the AGP common clock and source synchronous signals have increased to offset this timing violation. Refer to latest platform design guide. Status: No fix planned for this erratum.
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® R Intel E7205 Chipset MCH Specification Changes There are no Specification Changes in this Specification Update revision.
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® R Intel E7205 Chipset MCH Specification Clarifications There are no specification clarifications in this Specification Update revision.
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® R Intel E7205 Chipset MCH Documentation Changes There are no Documentation Changes in this Specification Update revision.
