R Intel 852GME / 852PM Chipset Graphics and Memory Controller Hub (GMCH) Specification Update November 2004 Notice: The Intel 852GME/852PM chipset may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
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R Contents Revision History .................................................................................................................. 5 Preface ................................................................................................................................ 6 Summary Table of Changes ............................................................................................... 8 Errata..................................................................................................
R Revision History Revision - 001 - 002 - 003 Description Date Initial Release June 2003 ® ® Added specification update on support for Mobile Intel Pentium 4 Processors with Hyper-Threading Technology.
R Preface This document is an update to the specifications contained in the Intel® 852GME/852PM Chipset GMCH/MCH Datasheet. It is intended for hardware system manufacturers. It contains Specification Changes, Errata, Specification Clarifications, and Documentation Changes. This NDA document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table.
R Component Identification via Programming Interface The Intel 852GME and Intel 852PM chipset GMCH/MCH may be identified by the following register contents. 1 2 Stepping Vendor ID Device ID Revision Number A2 8086h 3580h 02h 3 NOTES: 1. The Vendor ID corresponds to bits 15-0 of the Vendor ID Register located at offset 00-01h in the PCI function 0 configuration space. 2.
R Summary Table of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes that apply to the listed Intel 852GME/852PM chipset GMCH/MCH steppings. Intel intends to fix some of the errata in a future stepping of the component and to account for the other outstanding issues through documentation or Specification Changes as noted.
R Stepping NO. PLANS ERRATA A2 A6,B6 X No Fix Display may flicker when integrated graphics and ECC support are enabled A7,B7 X No Fix Anomalous System Behavior May Occur When AGP GART Size Is 64MB and APBASE bit 27 Is Set Specification Changes Stepping NO. PLANS SPECIFICATION CHANGES A2 1 X Added support for Mobile Intel® Pentium® 4 Processors with Hyper-Threading Technology. 2 X 24-Bit LVDS Will Not Be Supported On 852GME Platforms Specification Clarifications Stepping NO.
R Errata 1. A1,B1 - VGA Panning Problem: VGA text mode diagnostic and stress test applications that use pixel panning can experience temporary visual anomalies under certain memory configurations. This issue is seen in two test configurations. 1. Test applications using a single VGA font table with a 32KB font buffer range could fail. The failure can occur using 64MB technology products that use 2KB and 4KB page sizes. This failure was seen in a diagnostic utility. 2.
R 3. A3,B3 - Intermittent system hangs during BIOS memory testing when power cycle testing Problem: Systems may intermittently hang during BIOS memory testing as a result of the internal RCOMP state machine colliding with BIOS induced RCOMP cycle. Implication: System hang may occur during boot-up or resume from S3. No other failures have been identified or reported. Issues are resolved with a BIOS workaround. Workaround: Please refer to your Intel representative for BIOS workaround details.
R 6. A6,B6 - Display may flicker when integrated graphics and ECC support are enabled. Problem: Display flicker and flashing may occur when integrated graphics and ECC support are enabled under certain graphics resolution modes. Implication: A potentially undesirable amount of display flicker may occur. Workaround: No workaround available. Status: There are no plans to fix this erratum in silicon. 7.
R Specification Changes 1. Mobile Intel® Pentium® 4 processors with Hyper-Threading Technology is supported by the Intel® 852GME GMCH and the Intel® 852PM MCH. The following text should be added to the section titled “Intel 852PM Chipset MCH Features” under bullet “Processor/Host Bus Support” (p 12). - 2.
R Specification Clarifications 1. Strapping Option Clarification Notes 1, 2, and 3 have been added to Table 53, “Strapping Configuration Table” in Section 7.1, pg 227 of the 852GME/852PM datasheet. GST[2] §Clock Config: Bit_2 Note: Intel 852GME GMCH Only PSB 400 = 0 See notes 1, 2, 3 DVO Hi-Z PSB 533 = 1 NOTES: 1. External pull-ups/downs will be required on the board to enable the non-default state of the straps. 2.
R Documentation Changes 1. Ball definition for RSTIN# incorrectly shown in Table 49 Section 6.2 Table 49, “XOR Chains Exclusion List” incorrectly shows the ball definition for RSTIN# to be D28. Actual ball definition is AD28. D28 is a VSS ball. This is the only reference where RSTIN# is incorrectly defined. Ballout and Package Information in Section 8 are correct. 2. Sections 6.3 and 8 incorrectly show some signal pins as reserved Section 6.
