R Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH) Datasheet April 2005 Document Number: 252615-005
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R Contents 1 Introduction ....................................................................................................................... 19 1.1 1.2 2 Intel® 855GM/855GME Chipset GMCH Overview ............................................................ 23 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 3 3.4 3.5 3.6 3.7 Datasheet System Architecture ............................................................................................. 23 2.1.1 Intel® 855GM Chipset GMCH ...................
R 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4 Conceptual Overview of the Platform Configuration Structure ............................ 51 Nomenclature for Access Attributes..................................................................... 52 Standard PCI Bus Configuration Mechanism....................................................... 53 Routing Configuration Accesses .......................................................................... 53 4.4.1 PCI Bus #0 Configuration Mechanism...................
R 4.9.2 4.9.3 4.9.4 4.9.5 4.9.6 4.9.7 4.9.8 4.9.9 4.9.10 4.9.11 4.9.12 4.9.13 4.9.14 4.9.15 4.10 4.11 Datasheet DID – Device Identification Register..................................................... 87 PCICMD – PCI Command Register ..................................................... 88 PCISTS – PCI Status Register ............................................................. 89 RID – Revision Identification Register ..................................................
R 4.11.21 PMCS – Power Management Control/Status Register (Device #2) ... 121 5 ® Intel 855GM/GME GMCH System Address Map .......................................................... 123 5.1 5.2 5.3 5.4 6 Functional Description .................................................................................................... 137 6.1 6.2 6.3 6.4 6 System Memory Address Ranges...................................................................... 123 DOS Compatibility Area ............................
R 6.5 Datasheet 6.4.2.8 Scan Converter.................................................................. 143 6.4.2.9 Texture Engine .................................................................. 143 6.4.2.10 Perspective Correct Texture Support................................ 144 6.4.2.11 Texture Decompression .................................................... 144 6.4.2.12 Texture Chromakey........................................................... 144 6.4.2.13 Anti-Aliasing.........................
R 6.5.3 6.5.4 6.5.5 6.5.6 7 Power and Thermal Management................................................................................... 165 7.1 7.2 7.3 7.4 7.5 8 Strapping Configuration...................................................................................... 201 Ballout and Package Information .................................................................................... 203 11.1 8 XOR Test Mode Entry ............................................................................
R Figures Figure 1. Intel® 855GM GMCH Chipset System Block Diagram ...................................... 16 Figure 2. Intel® 855GME GMCH Chipset System Block Diagram .................................... 18 Figure 3. Configuration Address Register......................................................................... 56 Figure 4. Configuration Data Register .............................................................................. 57 Figure 5. PAM Registers ...........................................
R Table 26. PAM Registers and Associated System Memory Segments............................ 71 Table 27. Host-Hub I/F Bridge/System Memory Controller Configuration Space (Device #0, Function#1) .......................................................................................................... 86 Table 28. Configuration Process Configuration Space (Device#0, Function #3) ........... 105 Table 29. Intel® 855GM GMCH Configurations and Some Resolution Examples.......... 111 Table 30.
R Revision History Revision Number Description 001 Initial release 002 Updates include: Date July 2003 • Edited 855GM features under Host Bus Support September 2003 • Changed naming convention for Host Bus from Processor System Bus (PSB) to Front Side Bus (FSB) • Added 855GME features and system diagram to features section • Section 1: Added disclaimer for Intel Centrino™ mobile technology ® • Updated Reference Documents list • Section 2: Added System architecture details for 855GM/855GME • Sect
R Revision Number 005 Description Updates include: Date April 2005 • Added new Chapter 8 Electrical Characteristics ⎯ Absolute Maximum Ratings ⎯ Thermal Characteristics ⎯ Power Characteristics ⎯ Signal Groups ⎯ DC Characteristics • Testability moved to Chapter 9 • Intel 855GM/GME GMCH Strap Pins is now Chapter 10 Ballout and Package Information is now Chapter 11 12 Datasheet
R Intel® 855GM Chipset GMCH Features Processor/Host Bus Support ⎯ Intel® Pentium® M processor and Intel® Celeron® M processor ⎯ 2X address, 4X data ⎯ Supports 400 MHz Front Side Bus (FSB) ⎯ Supports Host bus dynamic bus inversion (DBI) ⎯ Supports 64-bit host data bus and 32-bit addressing ⎯ 8-deep in-order queue ⎯ AGTL+ bus driver technology with integrated AGTL+ termination resistors and low voltage operation (Vtt = 1.
R ⎯ DVO (DVOB and DVOC) support • • Digital video out ports DVOB and DVOC with 165 MHz dot clock on each 12-bit interface; two 12-bit channels can be combined to form one dual channel 24-bit interface with an effective dot clock of 330 MHz The combined DVO B/C ports as well as individual DVO B/C ports can drive a variety of DVO devices (TV-Out Encoders, TMDS and LVDS transmitters, etc.) with pixel resolution up to 1600x1200 at 85 Hz and up to 2048x1536 at 72 Hz. • Compliant with DVI Specification 1.
R • Twelve level of detail MIP map sizes from 1x1 to 2k x 2k • Z Bias support • • Dithering Numerous texture formats including 32bit RGBA • Line and full-scene anti-aliasing • Alpha and Luminance maps • 16 and 24-bit Z buffering • Texture chromakeying • 16 and 24-bit W buffering • Bilinear, trilinear, and anisotropic MIP map filtering • 8-bit Stencil buffering • Double and triple render buffer support • Cubic environment reflection mapping • 16 and 32-bit color • Dot product bu
R Figure 1. Intel® 855GM GMCH Chipset System Block Diagram Intel® Pentium® M Processor OR Intel® Celeron® M Processor CK-408 DVI Device LVDS IMVP-IV VR 400 MHz FSB DVOB & DVOC 1.5 V CRT Intel® 855GM GMCH 732 MicroFCBGA 200/266 MHz DDR Hub Interface 1.5 Mini-PCI ATA100 IDE (2) USB2.0/1.1 (6) Intel® 82801DBM 421 BGA (ICH4-M) Intel® PRO/ Wireless Network Connection PCI Bus Cardbus LAN AC'97 2.2/2.
R Intel® 855GME Chipset GMCH Features Note: The Intel 855GME chipset GMCH has identical features to the Intel 855GM chipset GMCH except for the additional features listed below.
R Figure 2. Intel® 855GME GMCH Chipset System Block Diagram Intel® Pentium® M Processor OR Intel® Celeron® M Processor CK-408 DVI/AGP Device LVDS IMVP-IV VR 400 MHz FSB DVOB/C or AGP 1.5 V CRT Intel® 855GME GMCH 732 MicroFCBGA 200/266/333 MHz DDR SDRAM Hub Interface 1.5 Mini-PCI ATA100 IDE (2) USB2.0/1.1 (6) Intel® 82801DBM 421 BGA (ICH4-M) Intel® PRO/ Wireless Network Connection PCI Bus Cardbus LAN AC'97 2.2/2.
Introduction R 1 Introduction This datasheet provides Intel’s specifications for the Intel® 855GM/855GME chipset based system. The Intel 855GM/855GME chipset graphics and memory controller hub (GMCH) is also an Intel® Centrino™ mobile technology component. Intel Centrino mobile technology with integrated wireless LAN capabilities was designed specifically for wireless notebook PCs – delivering outstanding mobile performance and enabling extended battery life, and thinner, lighter designs.
Introduction R Term Description or destined for the ICH4-M are generally referred to as “Hub interface cycles.” Hub cycles originating from or destined for the primary PCI interface on are sometimes referred to as “Hub interface/PCI cycles” 20 Host This term is used synonymously with processor IGD Integrated Graphics Device Intel 855GM/GME GMCH Refers to the GMCH component. Throughout this datasheet, the Intel 855GM/GME GMCH will be referred to as the GMCH.
Introduction R 1.2 Reference Documents Document Location ® ® http://www.intel.com/design/mobile/datashts/252612.h tm ® ® http://developer.intel.com/design/mobile/datashts/302 189.htm Intel Pentium M Processor Datasheet (252612) Intel Pentium M Processor on 90 nm Process with 2MB L2 Cache Datasheet (302189) ® ® Intel Celeron M Processor Datasheet (300302) http://www.intel.com/design/mobile/datashts/300302.
Introduction R 22 Datasheet
Intel® 855GM/855GME Chipset GMCH Overview R 2 Intel® 855GM/855GME Chipset GMCH Overview 2.1 System Architecture The Intel 855GM/855GME GMCH components provide the processor interface, DDR SDRAM interface, display interface, and Hub interface. The Intel 855GME also has an option for AGP external graphics port, in addition to integrated graphics support for added board flexibility options. 2.1.
Intel® 855GM/855GME Chipset GMCH Overview R 2.2 Processor Host Interface The Intel 855GM/855GME GMCH is optimized for the Intel Pentium M processor and Intel Celeron M processor Key features of the front side bus (FSB) are: • Support for a 400 MHz system bus frequency. • Source synchronous double pumped address (2X) • Source synchronous quad pumped data (4X) • Front side bus interrupt delivery • Low voltage swing Vtt (1.
Intel® 855GM/855GME Chipset GMCH Overview R Table 1. DDR SDRAM Memory Capacity Technology Width System Memory Capacity System Memory Capacity with Stacked Memory 128 Mb 16 256 MB - 256 Mb 16 512 MB - 512 Mb 16 1 GB - 128 Mb 8 256 MB 512 MB 256 Mb 8 512 MB 1 GB 512 Mb 8 1 GB 2 GB The GMCH system memory interface supports a thermal throttling scheme to selectively throttle reads and/or writes.
Intel® 855GM/855GME Chipset GMCH Overview R 2.5 Display Features The Intel 855GM/855GME GMCH has four display ports, one analog and three digital. With these interfaces, the GMCH can provide support for a progressive scan analog monitor, a dedicated dual channel LVDS LCD panel, and two DVO devices. Each port can transmit data according to one or more protocols. The data that is sent out the display port is selected from one of the two possible sources, Pipe A or Pipe B. 2.5.
Intel® 855GM/855GME Chipset GMCH Overview R selected during system initialization. Both upstream and downstream addressing is limited to 32bits for AGP and AGP/PCI transactions. The GMCH/MCH contains a 32-deep AGP request queue. High priority accesses are supported. All accesses from the AGP/PCI interface that fall within the Graphics Aperture address range pass through an address translation mechanism with a fully associative 20 entry TLB.
Intel® 855GM/855GME Chipset GMCH Overview R Table 2. Intel® 855GM/855GME GMCH Interface Clocks Interface Clock Speed CPU Bus DDR SDRAM CPU System Bus Frequency Ratio Samples Per Clock Data Rate (Megasamples/s) Data Width (Bytes) Peak Bandwidth (MB/s) 100 MHz Reference 4 400 8 3200 100 MHz 1:1 Synchronous 2 200 8 1600 133 MHz 1:1 Synchronous 2 266 8 2128 166 MHz 1:1 Synchronous 2 333 8 2664 LVDS Flat Panel 35 MHz-112 MHz (single channel) Asynchronous 1 112 2.
Signal Descriptions R 3 Signal Descriptions This section describes the GMCH signals. These signals are arranged in functional groups according to their associated interface. The following notations are used to describe the signal type: I Input pin O Output pin I/O Bi-directional Input/Output pin The signal description also includes the type of buffer used for the particular signal: AGTL+ Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for complete details.
Signal Descriptions R 3.1 Host Interface Signals Table 3. Host Interface Signal Descriptions Signal Name Type Description ADS# I/O AGTL+ Address Strobe: The system bus owner asserts ADS# to indicate the first of two cycles of a request phase. The GMCH can assert this signal for snoop cycles and interrupt messages. BNR# I/O AGTL+ Block Next Request: Used to block the current request bus owner from issuing a new request. This signal is used to dynamically control the CPU bus pipeline depth.
Signal Descriptions R Signal Name DRDY# Type I/O Description Data Ready: Asserted for each cycle that data is transferred. AGTL+ HA[31:3]# I/O AGTL+ Host Address Bus: HA[31:3]# connects to the CPU address bus. During processor cycles the HA[31:3]# are inputs. The GMCH drives HA[31:3]# during snoop cycles on behalf of Hub interface. HA[31:3]# are transferred at 2X rate. Note that the address is inverted on the CPU bus.
Signal Descriptions R Signal Name RS[2:0]# 3.2 Type Description O AGTL+ Response Status: Indicates the type of response according to the following the table: RS[2:0]# Response type 000 Idle state 001 Retry response 010 Deferred response 011 Reserved (not driven by GMCH) 100 Hard Failure (not driven by GMCH) 101 No data response 110 Implicit Write back 111 Normal data response DDR SDRAM Interface Table 4.
Signal Descriptions R Signal Name SDQS[8:0] Type I/O SSTL_2 Description Data Strobes: Data strobes are used for capturing data. During writes, SDQS is centered on data. During reads, SDQS is edge aligned with data. The following list matches the data strobe with the data bytes. There is an associated data strobe (DQS) for each data signal (DQ) and check bit (CB) group.
Signal Descriptions R 3.3 AGP Interface Signals Note: AGP interface is only supported on the Intel 855GME GMCH. Unless otherwise specified, the voltage level for all signals in this interface is 1.5 volts. 3.3.1 AGP Addressing Signals Table 5. AGP Addressing Signal Descriptions Signal Name GPIPE# Type Description I AGP Pipelined Read: This signal is asserted by the AGP master to indicate a full width address is to be enqueued on by the target using the AD bus.
Signal Descriptions R 3.3.2 AGP Flow Control Signals Table 6. AGP Flow Control Signals Signal Name GRBF# Type Description I AGP Read Buffer Full: Read buffer full indicates if the master is ready to accept previously requested low priority read data. When RBF# is asserted the GMCH is not allowed to initiate the return low priority read data. That is, the GMCH can finish returning the data for the request currently being serviced. RBF# is only sampled at the beginning of a cycle.
Signal Descriptions R 3.3.4 AGP Strobes Table 8. AGP Strobe Descriptions Signal Name Type Description GADSTB[0] I/O AGP Address/Data Bus Strobe-0: provides timing for 2X and 4X data on AD[15:0] and C/BE[1:0]# signals. The agent that is providing the data will drive this signal. GADSTB#[0] I/O AGP Address/Data Bus Strobe-0 Complement: With AD STB0, forms a differential strobe pair that provides timing information for the AD[15:0] and C/BE[1:0]# signals.
Signal Descriptions R Signal Name GIRDY# Type I/O AGP Description G_IRDY#: Initiator Ready. During PIPE# and SBA Operation: Not used while enqueueing requests via AGP SBA and PIPE#, but used during the data phase of PIPE# and SBA transactions. During FRAME# Operation: G_IRDY# is an output when GMCH acts as a FRAME#based AGP initiator and an input when the GMCH acts as a FRAME#-based AGP target.
Signal Descriptions R Signal Name GGNT# GAD[31:0] Type Description O AGP G_GNT#: Grant. I/O AGP G_AD[31:0]: Address/Data Bus. During SBA, PIPE# and FRAME# Operation: G_GNT#, along with the information on the ST[2:0] signals (status bus), indicates how the AGP interface will be used next. Refer to the AGP Interface Specification, Revision 2.0 for further explanation of the ST[2:0] values and their meanings.
Signal Descriptions R 3.4 Hub Interface Signals Table 10. Hub Interface Signals Signal Name HL[10:0] Type I/O Description Packet Data: Data signals used for HI read and write operations. Hub HLSTB I/O Hub HLSTB# I/O Hub 3.5 Packet Strobe: One of two differential strobe signals used to transmit or receive packet data over HI. Packet Strobe Complement: One of two differential strobe signals used to transmit or receive packet data over HI. Clocks Table 11.
Signal Descriptions R Signal Name DVOCCLK DVOCCLK# Type O DVO Description Differential DVO Clock Output: These pins provide a differential pair reference clock that can run up to 165 MHz. DVOCCLK corresponds to the primary clock out. DVOCCLK# corresponds to the primary complementary clock out. DVOCCLK and DVOCCLK# should be left as NC (“Not Connected”) if the DVO C port is not implemented.
Signal Descriptions R 3.6 Internal Graphics Display Signals The IGD has support for a dedicated LVDS LCD Flat Panel Interface, DVOB/C interfaces, and an Analog CRT port. 3.6.1 Dedicated LVDS LCD Flat Panel Interface Table 12. Dedicated LVDS LCD Flat Panel Interface Signal Descriptions Name ICLKAP Type O Voltage Description 1.25 V ±225 mV Channel A differential clock pair output (true): 245–800 MHz 1.25 V ±225 mV Channel A differential clock pair output (compliment): 245– 800 MHz. 1.
Signal Descriptions R 3.6.2 Digital Video Output B (DVOB) Port Table 13. Digital Video Output B (DVOB) Port Signal Descriptions Name Type DVOBD[11:0] O DVO Description DVOB Data: This data bus is used to drive 12-bit RGB data on each edge of the differential clock signals, DVOBCLK and DVOBCLK#. This provides 24-bits of data per clock period. In dual channel mode, this provides the lower 12-bits of pixel data. DVOBD[11:0] should be left as left as NC (“Not Connected”) if not used.
Signal Descriptions R Table 14.
Signal Descriptions R 3.6.4 Digital Video Output C (DVOC) Port Table 15. Digital Video Output C (DVOC) Port Signal Descriptions Name DVOCD[11:0] Type O DVO Description DVOC Data: This data bus is used to drive 12-bit RGB data on each edge of the differential clock signals, DVOCCLK and DVOCCLK#. This provides 24-bits of data per clock period. In dual channel mode, this provides the upper 12-bits of pixel data. DVOCD[11:0] should be left as left as NC (“Not Connected”) if not used.
Signal Descriptions R 3.6.5 Analog CRT Display Table 17. Analog CRT Display Signal Descriptions Pin Name VSYNC Type O Description CRT Vertical Synchronization: This signal is used as the vertical sync signal. CMOS HSYNC O CRT Horizontal Synchronization: This signal is used as the horizontal sync signal. CMOS RED O Analog RED# O Red (Analog Video Output): This signal is a CRT Analog video output from the internal color palette DAC. The DAC is designed for a 37.5 Ω equivalent load on each pin (e.
Signal Descriptions R 3.6.6 General Purpose Input/Output Signals Table 18. GPIO Signal Descriptions GPIO I/F Total RSTIN# Type I Comments Reset: Primary Reset, Connected to PCIRST# of ICH4-M. CMOS PWROK I Power OK: Indicates that power to GMCH is stable. CMOS AGPBUSY# EXTTS_0 LCLKCTLA O AGPBUSY: Output of the GMCH IGD to the ICH4-M, which indicates that certain graphics activity is taking place. It will indicate to the ACPI software not to enter the C3 state.
Signal Descriptions R GPIO I/F Total MDVICLK Type I/O DVO MDVIDATA I/O DVO MDDCDATA I/O DVO MDDCCLK I/O DVO Datasheet Comments DVI DDC Clock: This signal is used as the DDC clock for a digital display connector (i.e. primary digital monitor). This signal is tri-stated during a hard reset. DVI DDC Data: The signal is used as the DDC data for a digital display connector (i.e. primary digital monitor). This signal is tri-stated during a hard reset.
Signal Descriptions R 3.7 Voltage References, PLL Power Table 19. Voltage References, PLL Power Signal Name Type Description Host Processor HXRCOMP Analog Host RCOMP: Used to calibrate the Host AGTL+ I/O buffers. HYRCOMP Analog Host RCOMP: Used to calibrate the Host AGTL+ I/O buffers. HXSWING Analog Host Voltage Swing (RCOMP reference voltage): These signals provide a reference voltage used by the FSB RCOMP circuit.
Signal Descriptions R Signal Name Type PSWING Analog HLVREF Ref Analog VCCHL Description RCOMP reference voltage: This is connected to the RCOMP buffer differential amplifier and is used to calibrate the buffers. Input buffer VREF: Input buffer differential amplifier to determine a high versus low input voltage. Power Power supply for Hub interface buffers Analog Compensation for DVO: This signal is used to calibrate the DVO I/O buffers.
Signal Descriptions R 50 Datasheet
Register Description R 4 Register Description 4.1 Conceptual Overview of the Platform Configuration Structure The Intel 855GM GMCH and ICH4-M are physically connected by Hub interface. From a configuration standpoint, the Hub interface is logically PCI bus #0. As a result, all devices internal to the GMCH and ICH4-M appear to be on PCI bus #0.
Register Description R 4.2 Nomenclature for Access Attributes Table 21 provides the nomenclature for the access attributes. Table 21. Nomenclature for Access Attributes RO Read Only. If a register is Read Only, Writes to this register have no effect. R/W Read/Write. A register with this attribute can be Read and Written. R/W/L Read/Write/Lock. A register with this attribute can be Read, Written, and Locked. R/WC Read/Write Clear. A register bit with this attribute can be Read and Written.
Register Description R 4.3 Standard PCI Bus Configuration Mechanism The PCI Bus defines a slot based “configuration space” that allows each device to contain up to eight functions with each function containing up to 256, 8-bit configuration registers. The PCI Specification defines two bus cycles to access the PCI Configuration Space: Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the CPU.
Register Description R 4.4.2 Primary PCI and Downstream Configuration Mechanism If the Bus Number in the CONFIG_ADDRESS is non-zero, and is less than the value in the HostAGP/PCI_B device’s Secondary bus number register or greater than the value in the HostAGP/PCI_B device’s Subordinate bus number register, the GMCH will generate a Type 1 Hub interface Configuration Cycle. A[1:0] of the Hub interface request packet for the Type 1 configuration cycle will be “01”.
Register Description R 4.5 Register Definitions The GMCH contains four sets of software accessible registers accessed via the Host CPU I/O Address Space, and they are as follows: • Control registers: I/O Mapped into the CPU I/O Space, which control access to PCI Configuration Space via Configuration Mechanism #1 in the PCI 2.2 specification.
Register Description R 4.6 I/O Mapped Registers The GMCH contains two registers that reside in the CPU I/O Address Space: the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register. The Configuration Address Register enables/disables the Configuration Space and determines what portion of Configuration Space is visible through the Configuration Data window. 4.6.
Register Description R Bit Description 31 Configuration Enable (CFGE): When this bit is set to 1, accesses to PCI Configuration Space are enabled. If this bit is Reset to 0, accesses to PCI Configuration Space are disabled. 30:24 Reserved 23:16 Bus Number: When the Bus Number is programmed to 00h, the target of the Configuration Cycle is a Hub interface agent (GMCH, ICH4-M, etc.).
Register Description R Bit 31:0 4.7 Descriptions Configuration Data Window (CDW). If bit 31 of CONFIG_ADDRESS is 1, then any I/O access to the CONFIG_DATA register will be mapped to Configuration Space using the contents of CONFIG_ADDRESS. VGA I/O Mapped Registers If Device #2 is enabled, and Function #0 within Device #2 is enabled for VGA, and IO_EN is set within Function #0 then GMCH claims a set of I/O registers for legacy VGA function.
Register Description R Intel® 855GM/GME GMCH Host-Hub Interface Bridge Device Registers (Device #0, Function #0) 4.8 Table 24 summarizes the configuration space for Device #0, Function#0. Table 24.
Register Description R Register Symbol Register Start Register End Default Value Access AGP Command AGPCMD A8 AB 0000 0000h RO, R/W AGP Control AGPCTRL B0 B1 0000h RO, R/W AFT B2 B3 E9F0h R/W, R/WC Aperture Translation Table Base ATTBASE B8 BB 00000000h RO, R/W AGP Interface Multi Transaction Timer AMTT BC BC 00h R/W Low Priority Transaction Timer LPTT BD BD 00h R/W Host Error Control/Status/Obs HEM F0 F3 00000000h RO, R/W Register Name AGP Functional Test 4.
Register Description R 4.8.3 PCICMD – PCI Command Register Address Offset: Default Value: Access: Size: 04-05h 0006h Read Only, Read/Write 16 bits Since GMCH Device #0 does not physically reside on PCI_A many of the bits are not implemented. Bit Descriptions 15:10 Reserved 9 Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast back-toback Write. Since Device #0 is strictly a target, this bit is not implemented and is hardwired to 0.
Register Description R 4.8.4 PCI Status Register Address Offset: Default Value: Access: Size: 06-07h 0090h Read Only, Read/WriteClear 16 bits PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0’s PCI Interface. Bit 14 is Read/Write Clear. All other bits are Read Only. Since GMCH Device #0 does not physically reside on PCI_A many of the bits are not implemented.
Register Description R 4.8.5 RID – Register Identification Address Offset: Default Value: Access: Size: 08h 02h Read Only 8 bits This register contains the revision number of the GMCH Device #0. These bits are read only and writes to this register have no effect. Bit 7:0 4.8.6 Description Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification number for the GMCH Device #0.
Register Description R 4.8.8 HDR – Header Type Register Address Offset: Default Value: Access: Size: 0Eh 80h Read Only 8 bits This register identifies the header layout of the configuration space. No physical register exists at this location. Bit 7:0 4.8.9 Description PCI Header (HDR): This field always returns 80 to indicate that Device #0 is a multifunction device.
Register Description R 4.8.11 CAPPTR – Capabilities Pointer Register Bit 7:0 4.8.12 Description Pointer to the offset of the first capability ID register block: In this case the first capability is the Product-Specific Capability, which is located at offset 40h.
Register Description R 4.8.13 GMC – GMCH Miscellaneous Control Register (Device #0) Address Offset: Default Value: Access: Size: 50–51h 0000h Read/Write 16 bits Bit Description 15:10 Reserved 9 Reserved 8 RRBAR Access Enable—R/W: 1 = Enables the RRBAR space. 0 = Disable 7:1 Reserved 0 MDA Present (MDAP)—R/W: This bit should not be set when the VGA Enable bit is not set. If the VGA enable bit is set, then accesses to IO address range x3BCh–x3BFh are forwarded to Hub interface.
Register Description R 4.8.14 GGC – GMCH Graphics Control Register (Device 0) Address Offset: Default Value: Access: Size: Bit 52–53h 0030h Read/Write 16 bits Description 15:7 Reserved 6:4 Graphics Mode Select (GMS): This field is used to select the amount of Main system memory that is pre-allocated to support the Internal Graphics Device in VGA (non-linear) and Native (linear) modes. The BIOS ensures that system memory is pre-allocated only when Internal Graphics is enabled.
Register Description R 4.8.15 DAFC – Device and Function Control Register (Device 0) Address Offset: Default Value: Access: Size: 54–55h 0000h Read/Write 16 bits This 16-bit register controls the visibility of devices and functions within the GMCH to configuration software. Bit Description 15:8 Reserved 7 Device #2 Disable: 1 = Disabled. 0 = Enabled. 6:3 Reserved 2 Device #0 Function #3 Disable: 1 = Disable Function #3 registers within Device #0 and all associated DDR SDRAM and I/O ranges.
Register Description R 4.8.17 PAM(6:0) – Programmable Attribute Map Register (Device #0) Address Offset: Default Value: Attribute: Size: 59–5Fh 00h Each Read/Write 4 bits/register, 14 registers The GMCH allows programmable DDR SDRAM attributes on 13 Legacy system memory segments of various sizes in the 640 kB –1 MB address range. Seven Programmable Attribute Map (PAM) registers are used to support these features. Cacheability of these areas is controlled via the MTRR registers in the P6 processor.
Register Description R Bits [7, 3] Reserved Bits [6, 2] Reserved Bits [5, 1] WE Bits [4, 0] RE Description X X 1 1 Read/Write. This is the normal operating mode of main system memory. Both Read and Write cycles from the host are claimed by the GMCH and forwarded to DDR SDRAM. The GMCH will respond as a Hub interface target for both Read and Write accesses. As an example, consider a BIOS that is implemented on the Expansion bus.
Register Description R Table 26.
Register Description R Extended System BIOS Area (E0000h–EFFFFh) This 64-kB area is divided into four 16-kB segments that can be assigned with different attributes via PAM Control register as defined in Figure 5 and Table 26. System BIOS Area (F0000h–FFFFFh) This area is a single 64-kB segment that can be assigned with different attributes via PAM Control register as defined in Figure 5 and Table 26. 4.8.
Register Description R 4.8.19 ESMRAMC – Extended System Management RAM Control (Device #0) Address Offset: Default Value: Access: Size: 61h 38h Read/Write/Lock 8 bits The Extended SMRAM register controls the configuration of Extended SMRAM Space. The Extended SMRAM (E_SMRAM) Memory provides a Write-Back cacheable SMRAM Memory Space that is above 1 MB. Bit 7 Description H_SMRAM_EN (H_SMRAME): Controls the SMM Memory Space location (i.e., above 1 MB or below 1 MB).
Register Description R 4.8.20 ERRSTS – Error Status Register (Device #0) Address Offset: Default Value: Access: Size: 62–63h 0000h Read/Write Clear 16 bits This register is used to report various error conditions via Hub Interface Special cycles. An SERR, SMI, or SCI Error Hub Interface Special cycle may be generated on a zero to one transition of any of these flags when enabled in the PCICMD/ERRCMD, SMICMD, or SCICMD registers respectively.
Register Description R 4.8.21 ERRCMD – Error Command Register (Device #0) Address Offset: Default Value: Access: Size: 64–65h 0000h Read/Write 16 bits This register enables various errors to generate a SERR Hub Interface Special cycle. Since the GMCH does not have a SERR# signal, SERR messages are passed from the GMCH to the ICH4M over Hub interface. The actual generation of the SERR message is globally enabled for Device #0 via the PCI Command register.
Register Description R Bit 5 Description SERR on Receiving Unimplemented Special Cycle Hub Interface Completion Packet: 1 = The GMCH generates an SERR Hub Interface Special cycle when a GMCH initiated Hub interface request is terminated with a Unimplemented Special cycle completion packet. 0 = Reporting of this condition is disabled. 4:2 Reserved 1 SERR on Multiple-bit ECC Error: 1 = For systems that support ECC, this field must be set to 1.
Register Description R 4.8.23 SCICMD – SCI Error Command Register (Device 0) Address Offset: Default Value: Access: Size: 67h 00h Read/Write 8 bits This register enables various errors to generate a SCI Hub Interface Special cycle. When an Error Flag is set in the ERRSTS register, it can generate a SERR, SMI, or SCI Hub Interface Special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers respectively. Note: An error can generate one and only one Hub Interface Error Special cycle.
Register Description R 4.8.24 SHIC – Secondary Host Interface Control Register (Device #0) Address Offset: Default Value: Access: Size: 74-77h 00006010h Read Only, Read/Write 32 bits Bit Description 31 Reserved 30 BREQ0# Control of FSB Address and Control bus power management: 0 = Disable FSB address and control bus power management. 1 = Enable FSB address and control bus power management. 29:28 Reserved 27 On Die Termination (ODT) Gating Disable: 0 = Enable. 1 = Disable.
Register Description R Bit Description AGP/DVO Mux Strap (Read only) 1 Specifies the use of AGP bus muxed with DVO. This bit is defined at Reset by a strap on the G_PAR/DVO_DETECT signal. By default the AGP bus pulls this signal high. The presence of an DVO device pulls this signal low. The presence of a DVO device disables Device #1 and associated memory and io spaces are disabled.
Register Description R 4.8.26 AGPSTAT – AGP Status Register (Device #0) Address Offset: Default Value: Access: Size: A4–A7h 1F000217h Read Only 32 bits This register reports AGP device capability/status. Bit 31:24 Description Request (RQ). Indicates a maximum of 32 outstanding AGP command requests can be handled by the GMCH . Default =1Fh to allow a maximum of 32 outstanding AGP command requests. 23:10 Reserved 9 Side Band Addressing (SBA). Indicates that the GMCH supports side band addressing.
Register Description R 4.8.27 AGPCMD – AGP Command Register (Device #0) Address Offset: Default Value: Access: Size: A8–ABh 00000000h Read/Write 32 bits This register provides control of the AGP operational parameters. Bit Description 31:10 Reserved 9 Side Band Addressing Enable (SBA_EN). When this bit is set to 1, the side band addressing mechanism is enabled. 8 AGP Enable. 0 = Disable. When this bit is reset to 0, the GMCH will ignore all AGP operations, including the sync cycle.
Register Description R 4.8.28 AGPCTRL – AGP Control Register (Device #0) Address Offset: Default Value: Access: Size: B0–B1h 0000h Read/Write 16 bits This register provides for additional control of the AGP interface. Bit 7 is visible to the operating system and must be retained in this position. Bit Description 15:8 Reserved 7 GTLB Enable (and GTLB Flush Control). NOTE: This bit can be changed dynamically (i.e., while an access to GTLB occurs).
Register Description R Bit 2 Description AGP/PCI1 Discard Timer Disable. 0 = Enable (default). Enables the Discard Timer for the delayed transactions on the PCI1/AGP interface (initiated by the AGP agent using PCI protocol). The counter starts once the delayed transaction request is ready to complete as far as GMCH is concerned (i.e., read data is pending on the top of AGP Outbound queue).
Register Description R 4.8.31 ATTBASE – Aperture Translation Table Base Register (Device #0) Address Offset: Default Value: Access: Size: B8–BBh 00000000h Read/Write 32 bits This register provides the starting address of the Graphics Aperture Translation Table Base located in the main DDR SDRAM.
Register Description R 4.8.33 LPTT – Low Priority Transaction Timer Register (Device #0) Address Offset: Default Value: Access: Size: BDh 00h Read/Write 8 bits LPTT is an 8-bit register similar in a function to AMTT. This register is used to control the minimum tenure on the AGP for low priority data transaction (both reads and writes) issued using PIPE# or SB mechanisms.
Register Description R 4.9 Intel® 855GM/GME GMCH Main Memory Control, Memory I/O Control Registers (Device #0, Function #1) The following table shows the GMCH Configuration Space for Device #0, Function #1. See Section 4.2f or access nomenclature. Table 27.
Register Description R 4.9.1 VID – Vendor Identification Register Address Offset: Default Value: Access: Size: 00-01h 8086h Read Only 16 bits The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identifies any PCI device. Writes to this register have no effect. Bit 15:0 4.9.2 Description Vendor Identification (VID): This register field contains the PCI standard identification for Intel.
Register Description R 4.9.3 PCICMD – PCI Command Register Address Offset: Default Value: Access: Size: 04-05h 0006h Read Only, Read/Write 16 bits Since Intel chipset Device #0 does not physically reside on PCI_A, many of the bits are not implemented. Bit 88 Description 15:10 Reserved 9 Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast back-toback Write. Since Device #0 is strictly a target, this bit is not implemented and is hardwired to 0.
Register Description R 4.9.4 PCISTS – PCI Status Register Address Offset: Default Value: Access: Size: 06-07h 0080h Read Only, Read/WriteClear 16 bits PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0’s PCI Interface. Bit 14 is Read/Write Clear. All other bits are Read Only. Since GMCH Device #0 does not physically reside on PCI_A, many of the bits are not implemented.
Register Description R 4.9.5 RID – Revision Identification Register Address Offset: Default Value: Access: Size: 08h 02h Read Only 8 bits This register contains the revision number of the Intel 855GM/GME GMCH Device #0. These bits are Read Only and Writes to this register have no effect. Bit 7:0 4.9.6 Description Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification number for the GMCH Device #0.
Register Description R 4.9.8 HDR – Header Type Register Address Offset: Default Value: Access: Size: 0Eh 80h Read Only 8 bits This register identifies the header layout of the configuration space. No physical register exists at this location. Bit 7:0 4.9.9 Description PCI Header (HDR): This field always returns 80 to indicate that Device #0 is a multifunction device. Reads and Writes to this location have no effect.
Register Description R 4.9.11 CAPPTR – Capabilities Pointer Register Address Offset: Default Value: Access: Size: 34h 00h Read Only 8 bits The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list. Bit 7:0 4.9.12 Description Pointer to the offset of the first capability ID register block: In this case there are no capabilities, therefore these bits are hardwired to 00h to indicate the end of the capability linked list.
Register Description R 4.9.13 DRA – DRAM Row Attribute Register (Device #0) Address Offset: Default Value: Access: Size: 50-51h 77h Each Read/Write 8 bits The DDR SDRAM Row Attribute Register defines the page sizes to be used when accessing different pairs of Rows. Each Nibble of information in the DRA registers describes the page size of a pair of Rows: Row0, 1: 50h Row2, 3: 51h 52h-5Fh: Reserved.
Register Description R 4.9.14 DRT – DRAM Timing Register (Device #0) Address Offset: Default Value: Access: Size: 60-63h 18004425h Read/Write 32 bits This register controls the timing of the DDR SDRAM controller. Bit 31 Description DDR Internal Write to Read Command delay (tWTR): The tWTR is a std. DDR SDRAM timing parameter with a value of 1 CK for CL=2 and 2.5. The tWTR is used to time RD command after a WR command (to same Row): 0: tWTR is set to 1 Clock (CK), used for DDR SDRAM CL=2 or 2.
Register Description R Bit 27:26 Description Back To Back Read-Write commands spacing (DDR, same or different Rows/Bank): This field determines the RD-WR command spacing, in terms of common clocks based on the following formula: CL + 0.5xBL + TA (RD-WR) – DQSS DQSS: is time from Write command to data and is always 1 CK BL: is Burst Length which is set to 4 TA (RD-WR): is required DQ turn-around, can be set to 1, 2 or 3 CK CL: is CAS latency, can be set to 2 or 2.
Register Description R Bit 14:12 Description Refresh Cycle Time (tRFC): Refresh Cycle Time is measured for a given row from REF command (to perform a refresh) until following ACT to same row (to perform a Read or Write). It is tracked separately from tRC for DDR SDRAM. Current DDR SDRAM spec requires tRFC of 75 ns (DDR266) and 80 ns (DDR200). Therefore, this field will be set to 8 clocks for DDR200, 10 clocks for DDR266.
Register Description R Bit 3:2 Description DDR SDRAM RAS# to CAS# Delay (tRCD): This bit controls the number of clocks inserted between a Row Activate command and a Read or Write command to that row. Encoding 1:0 Datasheet tRCD 00: 4 DDR SDRAM Clocks (DDR 333 SDRAM) 01: 3 DDR SDRAM Clocks 10: 2 DDR SDRAM Clocks 11: Reserved DDR SDRAM RAS# Precharge (tRP): This bit controls the number of clocks that are inserted between a row precharge command and an activate command to the same row.
Register Description R 4.9.15 PWRMG – DRAM Controller Power Management Control Register (Device #0) Address Offset: Default Value: Access: Size: 68h-6Bh 00000000h Read/Write 32 bits Bit Description 31:24 Reserved 23:20 Row State Control: This field determines the number of clocks the System Memory Controller will remain in the idle state before it begins pre-charging all pages or powering down rows.
Register Description R Bit Description 11 Rcven DLL shutdown disable: 0 = Normal operation. RCVEN DLL is turned off when the corresponding SO-DIMM is unpopulated. 1 = RCVEN DLL is turned on irrespective of SO-DIMM population. 10 ECC SO-DIMM Clock tri-state Disable: 0 = When DDR SDRAM ECC is not enabled, the ECC clocks (i.e., SCK2/SCK2#, SCK5/SCK5#,) are tri- stated. 1 = When DDR SDRAM ECC is enabled, the ECC clocks (i.e., SCK2/SCK2#, SCK5/SCK5#,) are treated just like the other clocks.
Register Description R Bit Description 19:16 Reserved 15 RAS Lock-Out Enable: Set to a 1 if all populated rows support RAS Lock-Out. Defaults to 0. If this bit is set to a 1 the DDR SDRAM Controller assumes that the DDR SDRAM guarantees tRAS min before an auto precharge (AP) completes (Note: An AP is sent with a Read or a Write command). Also, the DDR SDRAM Controller does not issue an activate command to the auto pre-charged bank for tRP.
Register Description R Bit Description 011: Mode Register Set Enable – All CPU cycles to DDR SDRAM result in a Mode Register set command on the DDR SDRAM Interface. Host address lines are mapped to DDR SDRAM address lines in order to specify the command sent. Host address HA[13:3] are mapped to Memory address SMA[11,9:0]. SMA3 must be driven to 1 for interleave wrap type. For Double Data Rate MA[6:4] needs to be driven based on the value programmed in the CAS# Latency field. CAS Latency MA[6:4] 1.
Register Description R consumed during the sampling period. Although bandwidth from/to independent rows and GMCH Write bandwidth is measured independently, once Tripped all transactions except high priority graphics Reads are subject to throttling. Bit 31:28 Description DDR SDRAM Throttle Mode (TMODE): Four bits control which mechanisms for Throttling are enabled in an “OR” fashion. Counter-based Throttling is lower priority than Thermal Trips Throttling when both are enabled and Tripped.
Register Description R Bit 27:24 Description Read Counter Based Power Throttle Control (RCTC): These bits select the Counter based Power Throttle Bandwidth Limits for Read operations to system memory. R/W, RO if Throttle Lock. 0h = 85% 1h = 70% 2h = 65% 3h = 60% 4h = 55% 5h = 50% 6h = 45% 7h = 40% 8h = 35% 9h = 30% Ah = 20% B-Fh = Reserved 23:20 Write Counter Based Power Throttle Control (WCTC): These bits select the counter based Power Throttle Bandwidth Limits for Write operations to system memory.
Register Description R Bit 19:16 Description Read Thermal Based Power Throttle Control (RTTC): These bits select the Thermal Sensor based Power Throttle Bandwidth Limits for Read operations to system memory. R/W, RO if Throttle Lock.
Register Description R Bit Description 8 High Priority Stream Throttling Enable: Normally High Priority Streams are not Throttled when either the counter based mechanism or Thermal Sensor mechanism demands Throttling. 0 = Normal operation. 1 = Block High priority streams during Throttling.
Register Description R 4.10.1 VID – Vendor Identification Register The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification register uniquely identifies any PCI device. Writes to this register have no effect. Bit 15:0 4.10.2 Description Vendor Identification (VID): This register field contains the PCI standard identification for 8086h.
Register Description R Bit 4.10.4 Description 4 Memory Write and Invalidate Enable (MWIE): The GMCH will never issue Memory Write and Invalidate commands. This bit is therefore hardwired to 0. Writes to this bit position will have no effect. 3 Special Cycle Enable (SCE): The GMCH does not implement this bit and it is hardwired to a 0. Writes to this bit position have no effect. 2 Bus Master Enable (BME): The GMCH is always enabled as a master on HI. This bit is hardwired to a 1.
Register Description R 4.10.5 RID – Revision Identification Register Address Offset: Default Value: Access: Size: 08h 02h Read Only 8 bits This register contains the revision number of the Intel 855GM/GME GMCH. These bits are Read Only and Writes to this register have no effect. Bit 7:0 4.10.6 Description Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification number for the GMCH.
Register Description R 4.10.8 HDR – Header Type Register Address Offset: Default Value: Access: Size: 0Eh 80h Read Only 8 bits This register identifies the header layout of the configuration space. No physical register exists at this location. Bit 7:0 4.10.9 Description PCI Header (HDR): This field always returns 80 to indicate that Device #0 is a multifunction device.
Register Description R 4.10.11 CAPPTR – Capabilities Pointer Register Address Offset: Default Value: Access: Size: 34h 00h Read Only 8 bits The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list. Bit 7:0 4.10.12 Description Pointer to the offset of the first capability ID register block: In this case there are no capabilities therefore these bits are hardwired to 00h to indicate the end of the capability-linked list.
Register Description R Table 29.
Register Description R Table 30.
Register Description R Intel® 852GM GMCH Integrated Graphics Device Registers (Device #2, Function #0) 4.11 This section contains the PCI configuration registers listed in order of ascending offset address. Device #2 incorporates Function #0. See Section 4.2 for access nomenclature. Note: C0F0 = Copy of Function #0 and U1F1 = Unique in Function #1. Table 31.
Register Description R 4.11.1 VID – Vendor Identification Register (Device #2) Address Offset: Default Value: Access Attributes: Size: 00−01h 8086h Read Only 16 bits The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identifies any PCI device. Writes to this register have no effect. Bit 15:0 4.11.2 Description Vendor Identification Number: This is a 16-bit value assigned to Intel.
Register Description R Bit 2 Description Bus Master Enable (BME) ⎯R/W: This bit determines if the IGD is to function as a PCI compliant master. 0= Disable IGD bus mastering (default). 1 = Enable IGD bus mastering. 1 Memory Access Enable (MAE) ⎯R/W: This bit controls the IGD’s response to System Memory Space accesses. 0= Disable (default). 1 = Enable. 0 I/O Access Enable (IOAE) ⎯R/W: This bit controls the IGD’s response to I/O Space accesses. 0 = Disable (default). 1 = Enable. 4.11.
Register Description R 4.11.5 RID – Revision Identification Register (Device #2) Address Offset: Default Value: Access: Size: 08h 02h Read Only 8 bits This register contains the revision number of the IGD. These bits are Read Only and Writes to this register have no effect. 4.11.6 Bit Description 7:0 Revision Identification Number: This is an 8-bit value that indicates the revision identification number for the GMCH.
Register Description R 4.11.8 MLT – Master Latency Timer Register (Device #2) Address Offset: Default Value: Access: Size: 0Dh 00h Read Only 8 bits The IGD does not support the programmability of the master latency timer because it does not perform bursts. Bit 7:0 4.11.9 Description Master Latency Timer Count Value – RO HDR – Header Type Register (Device #2) Address Offset: Default Value: Access: Size: 0Eh 00h Read Only 8 bits This register contains the Header Type of the IGD. Bit 4.11.
Register Description R 4.11.11 MMADR – Memory Mapped Range Address Register (Device #2) Address Offset: Default Value: Access: Size: 14−17h 00000000h Read/Write, Read Only 32 bits This register requests allocation for the IGD registers and instruction ports. The allocation is for 512-kB and the base address is defined by bits [31:19]. Bit 4.11.12 Description 31:19 Memory Base Address⎯R/W: Set by the OS, these bits correspond to address signals [31:19].
Register Description R 4.11.13 SVID – Subsystem Vendor Identification Register (Device #2) Address Offset: Default Value: Access: Size: Bit 15:0 4.11.14 Description Subsystem Vendor ID: This value is used to identify the vendor of the subsystem. This register should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This register can only be cleared by a reset. SID – Subsystem Identification Register (Device #2) Address Offset: Default Value: Access: Size: Bit 15:0 4.
Register Description R 4.11.16 INTRLINE – Interrupt Line Register (Device #2) Address Offset: Default Value: Access: Size: Bit 7:0 4.11.17 Description Interrupt Connection: Used to communicate interrupt line routing information. POST software Writes the routing information into this register as it initializes and configures the system. The value in this register indicates which input of the System Interrupt controller that the device’s interrupt pin is connected to.
Register Description R 4.11.20 PMCAP – Power Management Capabilities Register (Device #2) Address Offset: Default Value: Access: Size: D2h−D3h 0221h Read Only 16 bits Bit 4.11.21 Description 15:11 PME Support: This field indicates the power states in which the IGD may assert PME#. Hardwired to 0 to indicate that the IGD does not assert the PME# signal.
Register Description R 122 Datasheet
Intel® 855GM/GME GMCH System Address Map R 5 Intel® 855GM/GME GMCH System Address Map A system based on the GMCH supports 4 GB of addressable system memory space and 64 kB+3B of addressable I/O space. The I/O and system memory spaces are divided by system configuration software into regions. The system memory ranges are useful either as system memory or as specialized system memory, while the I/O regions are used solely to control the operation of devices in the system.
Intel® 855GM/GME GMCH System Address Map R Figure 6.
Intel® 855GM/GME GMCH System Address Map R Figure 7.
Intel® 855GM/GME GMCH System Address Map R Table 32.
Intel® 855GM/GME GMCH System Address Map R Monochrome Display Adapter (MDA) Range (0B0000h - 0B7FFFh) Legacy support requires the ability to have a second graphics controller (monochrome) in the system. Accesses in the standard VGA range are forwarded to IGD and the Hub interface (depending on configuration bits). Since the monochrome adapter may be mapped to anyone of these devices, the GMCH must decode cycles in the MDA range and forward them either to IGD or to Hub interface.
Intel® 855GM/GME GMCH System Address Map R 5.4 Main System Memory Address Range (0010_0000h to Top of Main Memory) The address range from 1 MB to the top of main system memory is mapped to main DDR SDRAM address range controlled by the GMCH. The GMCH will forward all accesses to addresses within this range to the DDR SDRAM unless a hole in this range is created using the fixed hole as controlled by the FDHC register. Accesses within this hole are forwarded to Hub interface.
Intel® 855GM/GME GMCH System Address Map R 5.4.2.1 Extended SMRAM Address Range (HSEG and TSEG) The HSEG and TSEG SMM transaction address spaces reside in this extended system memory area. 5.4.2.2 HSEG SMM mode CPU accesses to enabled HSEG are remapped to 000A0000h-000BFFFFh. NonSMM mode CPU accesses to enabled HSEG are considered invalid are terminated immediately on the FSB. The exceptions to this rule are Non-SMM mode Write Back cycles that are remapped to SMM space to maintain cache coherency.
Intel® 855GM/GME GMCH System Address Map R ⎯ Addresses decoded to the AGP Memory Window defined by the MBASE,MLIMIT,PMBASE, and PMLIMIT registers are mapped to AGP. ⎯ Addresses decoded to the Graphics Aperture range defined by the APBASE and APSIZE registers are mapped to the main DDR SDRAM. There are two sub-ranges within the PCI Memory address range defined as APIC configuration space and High BIOS Address range.
Intel® 855GM/GME GMCH System Address Map R • Above 1-MB option that allows new SMI handlers to execute with Write-back cacheable SMRAM. • Above 1-MB solutions require changes to compatible SMRAM handlers code to properly execute above 1 MB. Note: Hub interface is not allowed to access the SMM space. 5.4.3.
Intel® 855GM/GME GMCH System Address Map R 5.4.4 System Memory Shadowing Any block of system memory that can be designated as Read-Only or Write-Only can be “shadowed” into GMCH DDR SDRAM. Typically this is done to allow ROM code to execute more rapidly out of main DDR SDRAM. ROM is used as a Read-Only during the copy process while DDR SDRAM at the same time is designated Write-Only. After copying, the DDR SDRAM is designated Read-Only so that ROM is shadowed. CPU bus transactions are routed accordingly.
Intel® 855GM/GME GMCH System Address Map R The GMCH also forwards accesses to the Legacy VGA I/O ranges according to the settings in the Device #1 configuration registers BCTRL (VGA Enable) and PCICMD1 (IOAE1), unless a second adapter (monochrome) is present on the Hub interface/PCI (or ISA). The presence of a second graphics adapter is determined by the MDAP configuration bit. When MDAP is set, the GMCH will decode legacy monochrome IO ranges and forward them to the Hub interface.
Intel® 855GM/GME GMCH System Address Map R target device (DDR SDRAM) will complete normally. The remaining portion of the access that crosses a device boundary (targets a different device than that of the starting address) or hits an invalid address will be remapped to system memory address 0h, snooped on the Host Bus, and dispatched to DDR SDRAM. Reads will return all 1’s with Master Abort completion.
Intel® 855GM/GME GMCH System Address Map R should be disconnected by the target on potential device boundaries. The GMCH will disconnect AGP/PCI transactions on 4-kB boundaries. AGPPIPE# and SBA accesses are limited to 256 bytes and must hit DDR SDRAM. AGP accesses are dispatched to DDR SDRAM on naturally aligned 32 byte block boundaries. The portion of the request that hits a valid address will complete normally.
Intel® 855GM/GME GMCH System Address Map R 136 Datasheet
Functional Description R 6 Functional Description 6.1 Host Interface Overview The GMCH front side bus uses source synchronous transfer for the address and data signals. The address signals are double pumped and two addresses can be generated every bus clock. At 100 MHz bus frequency, the two address signals run at 200 MHz for a maximum address queue rate of 50-M addresses/sec. The data is quad pumped and an entire 64-B cache line can be transferred in two bus clocks.
Functional Description R In a GMCH platform, the ICH4-M contains IOxAPICs and its interrupts are generated as upstream Hub interface Memory Writes. Furthermore, PCI 2.2 defines MSI’s (Message Signaled Interrupts) that are also in the form of Memory Writes. A PCI 2.2 device may generate an interrupt as an MSI cycle on its PCI bus instead of asserting a hardware signal to the IOxAPIC. The MSI may be directed to the IOxAPIC, which in turn generates an interrupt as an upstream Hub interface memory write.
Functional Description R 6.3.2 System Memory Organization and Configuration 6.3.2.1 Configuration Mechanism for SO-DIMMs Detection of the type of DDR SDRAM installed on the SO-DIMM is supported via Serial Presence Detect mechanism as defined in the JEDEC 200-pin SO- DIMM specification. Before any cycles to the system memory interface can be supported, the GMCH DDR SDRAM registers must be initialized. The GMCH must be configured for operation with the installed system memory types.
Functional Description R 6.3.3 DDR SDRAM Performance Description The overall system memory performance is controlled by the DDR SDRAM timing register, pipelining depth used in GMCH, system memory speed grade and the type of DDR SDRAM used in the system. Besides this, the exact performance in a system is also dependent on the total system memory supported, external buffering and system memory array layout.
Functional Description R Figure 8. Intel® 855GM GMCH Graphics Block Diagram DDR/SDRAM Memory Control DAC Overlay Sprite Video Engine (MPEG2 Decode) Cursor Primary Display 3D Engine Setup/Transform Scan Conversion Texture Engine Raster Engine LVDS Cursor 2D Engine Instr./ Data Pipe A Secondary Display Alpha Blend/ Gamma/ CRC Pipe B Cntl Mux Port DVOB DVOC Display C 2nd Overlay High bandwidth access to data is provided through the system memory port.
Functional Description R • Bilinear, Trilinear, and Anisotropic MIP map filtering • Gouraud shading and Flat shading • Alpha-blending • Per-Vertex and per- pixel fog • Z/W buffering These features are independently controlled via a set of 3D instructions. The 3D pipeline subsystem performs the 3D rendering acceleration. The main blocks of the pipeline are the Setup Engine, Scan Converter, Texture Pipeline, and Raster Pipeline.
Functional Description R 6.4.2.5 3D Primitives and Data Formats Support The 3D primitives rendered by the GMCH are points, lines, discrete triangles, line strips, triangle strips, triangle fans, and polygons. In addition to this, the GMCH supports DirectX’s* Flexible Vertex Format* (FVF), which enables the application to specify a variable length parameter list, obviating the need for sending unused information to the hardware.
Functional Description R 6.4.2.10 Perspective Correct Texture Support A textured polygon is generated by mapping a 2D texture pattern onto each pixel of the polygon. A texture map is like wallpaper pasted onto the polygon. Since polygons are rendered in perspective, it is important that texture be mapped in perspective as well. Without perspective correction, texture is distorted when an object recedes into the distance.
Functional Description R 6.4.2.14 Texture Map Filtering Many texture-mapping modes are supported. Perspective correct mapping is always performed. As the map is fitted across the polygon, the map can be tiled, mirrored in either the U or V directions, or mapped up to the end of the texture and no longer placed on the object (this is known as clamp mode). The way a texture is combined with other object attributes is also definable.
Functional Description R Flexible vertex format support allows multi-texturing because it makes it possible to pass more than one texture in the vertex structure. 6.4.2.16 Cubic Environment Mapping Environment maps allow applications to render scenes with complex lighting and reflections while significantly decreasing CPU load. There are several methods to generate environment maps such as spherical, circular and cubic.
Functional Description R 6.4.3.3 Color Shading Modes The Raster engine supports the Flat and Gouraud shading modes. These shading modes are programmed by the appropriate state variables issued through the command stream. • Flat shading is performed by smoothly interpolating the vertex intrinsic color components (Red, Green, Blue), Specular (R, G, B), Fog, and Alpha to the pixel, where each vertex color has the same value.
Functional Description R 6.4.3.7 Color Buffer Formats: (Destination Alpha) The Raster engine supports 8-bit, 16-bit, and 32-bit Color Buffer formats. The 8-bit format is used to support planar YUV4:2:0 format, which is used only in Motion Compensation and Arithmetic Stretch format. The bit format of Color and Z is allowed to mix. The GMCH can support an 8-bit destination alpha in 32-bit mode. Destination alpha is supported in 16-bit mode in 1:5:5:5 or 4:4:4:4 format.
Functional Description R test. The selection of the stencil operation to be performed is based upon the result of the stencil test and the depth test. A stencil write mask is also included that controls the writing of particular bits into the stencil buffer. It selects between the destination value and the updated value on a perbit basis. The mask is 8-bit wide. 6.4.3.10 Projective Textures The GMCH supports two simultaneous projective textures at full rate processing.
Functional Description R 6.4.4.2 Alpha Stretch BLT The stretch BLT function can stretch source data in the X and Y directions to a destination larger or smaller than the source. Stretch BLT functionality expands a region of system memory into a larger or smaller region using replication and interpolation. The stretch BLT function also provides format conversion and data alignment. 6.4.5 Planes and Engines The GMCH display can be functionally delineated into planes and engines (pipes and ports).
Functional Description R 6.4.6.1 Cursor Color Formats Color data can be in an indexed format or a true color format. Indexed data uses the entries in the four-entry cursor palette to convert the two-bit index to a true color format before being passed to the blenders. The index can optionally specify that a cursor pixel be transparent or cause an inversion of the pixel value below it or one of two colors from the cursor palette.
Functional Description R 6.4.7.3 Gamma Correction To compensate for overlay color intensity loss, the overlay engine supports independent gamma correction. This allows the overlay data to be converted to linear data or corrected for the display device when not blending. 6.4.7.4 YUV to RGB Conversion The format conversion can be bypassed in the case of RGB source data. 6.4.7.5 Color Control Color control provides a method of changing the color characteristics of the pixel data.
Functional Description R 6.4.8.2 Hardware Motion Compensation The HWMC process consists of reconstructing a new picture by predicting (either forward, backward, or bi-directional) the resulting pixel colors from one or more reference pictures. The GMCH receives the video stream and implements Motion Compensation and subsequent steps in hardware. Performing Motion Compensation in hardware reduces the processor demand of software-based MPEG-2 decoding, and thus improves system performance. 6.4.8.
Functional Description R 6.5.1.1 Integrated RAMDAC The display function contains a 350 MHz, integrated, 24-bit, RAM-based Digital-to-Analog Converter (RAMDAC) that transforms up to 2048X1536 digital pixels at a maximum refresh rate of 75 Hz. Three, 8-bit DACs provide the R, G, and B signals to the monitor. 6.5.1.2 DDC (Display Data Channel) DDC is defined by VESA. It allows communication between the host system and display.
Functional Description R 6.5.2.2 LVDS Interface Signals LVDS for flat panel is compatible with the ANSI/TIA/EIA-644 specification. This is an electrical standard only defining driver output characteristics and receiver input characteristics. There are two LVDS transmitter channels (channel A and channel B) in the LVDS interface. Each channel consists of four data pairs and a clock pair. The interface consists of a total of ten differential signal pairs of which eight are data and two are clocks.
Functional Description R 6.5.2.7 Panel Power Sequencing This section provides details for the power sequence timing relationship of the panel power, the backlight enable and the LVDS data timing delivery. In order to meet the panel power timing specification requirements, two signals, PANELVDDEN and PANELBKLTEN are provided to control the timing sequencing function of the panel and the backlight power supplies. 6.5.2.7.
Functional Description R Table 38. Panel Power Sequencing Timing Parameters Panel Power Sequence Timing Parameters Name Spec Name T1+T2 Vdd On to LVDS Active From To .1 Vdd LVDS Active LVDS Active Backlight on Backlight Off LVDS off LVDS Off Start power off Power Off Power On Sequence Start Panel Vdd must be on for a minimum time before the LVDS data stream is enabled. T5 Backlight LVDS data must be enabled for a minimum time before the backlight is turned on.
Functional Description R Optionally the FIELD pin can indicate to the overlay which field is currently being displayed at the display device. 6.5.2.10 Intel 855GME GMCH AGP Interface Overview The GMCH support 1.5 V AGP 1X/2X/4X devices. The AGP signal buffers are 1.5 V drive/receive (buffers are not 3.3 V tolerant). The GMCH support 2X/4X source synchronous clocking transfers for read and write data, and sideband addressing.
Functional Description R AGP Command Hi-Priority Long Read C/BE[3:0]# Encoding 1001 GMCH Host Bridge Cycle Destination Main Memory The Hub interface Response as PCIx Target High Priority Read Complete locally with random data; does not go to the hub interface Flush 1010 GMCH Complete with QW of Random Data Reserved 1011 N/A Fence 1100 GMCH Reserved 1101 N/A No Response Reserved 1110 N/A No Response Reserved 1111 N/A No Response No Response No Response - Flag inserted in GMCH requ
Functional Description R The 4X data rate transfer provides 1.06 GB/s transfer rates. The control signal protocol for the 4X data transfer protocol is identical to 1X/2X protocol. In 4X mode 16 bytes of data are transferred on every 66 MHz clock edge. The minimum throttleable block size remains four, 66 MHz clocks, which means 64 bytes of data are transferred per block. Three additional signal pins are required to implement the 4X data transfer protocol.
Functional Description R Table 41.
Functional Description R • Fast Back-to-Back Transactions. GMCH as a target supports fast back-to-back cycles from an AGP FRAME# initiator. As an initiator of AGP FRAME# cycle, the GMCH only supports the following transactions: • Memory Read and Memory Read Line. GMCH supports reads from host to AGP. GMCH does not support reads from the hub interface to AGP. • Memory Read Multiple. This command is not supported by the GMCH as an AGP FRAME# initiator. • Memory Write.
Functional Description R 6.5.6 Concurrent and Simultaneous Display The GMCH has two independent pipes, each with its own timing generator and dot clock, and thus is able to support two displays concurrently. Windows 98* and Windows 2000* have enabled support for multi-monitor display. There are two types of multi-monitor solutions: concurrent and simultaneous. Concurrent displays different data on two screens whereas simultaneous displays the same information on both displays.
Functional Description R 164 Datasheet
Power and Thermal Management R 7 Power and Thermal Management The Intel 855GM/855GME GMCH chipset platform is intended to be compliant with the following specifications and technologies: • APM Rev 1.2 • PCI Power Management Rev 1.0 • PC’99, Rev 1.0, PC’99A, and PC’01, Rev 1.0 • ACPI 1.0b and 2.
Power and Thermal Management R will transition from the C0 state to the C3 state when software reads the Level 3 Register. This is an ACPI defined register but BIOS or APM (via BIOS) can use this facility when entering a low power state. The Host Clock PLL within the GMCH can be programmed to be shut off for increased power savings and the GMCH uses the DPSLP signal input for this purpose.
Power and Thermal Management R 7.3 Enhanced Intel SpeedStep® Technology Overview With Enhanced Intel SpeedStep technology the processor core voltage changes and allows true CPU core frequency changes versus only clock throttling. Table 42. Enhanced Intel SpeedStep® Technology Overview 7.
Power and Thermal Management R should include an Active-Low Open-Drain signal indicating an Over-Temp condition, which remains asserted for as long as the Over-Temp Condition exists, and deasserts when temperature has returned to within normal operating range. This External sensor output will be connected to the GMCH input (EXTTS_0) and will trigger a Preset Interrupt and/or Read-Throttle on a levelsensitive basis.
Electrical Characteristics R 8 Electrical Characteristics 8.1 Absolute Maximum Ratings Table 43 lists the Intel 855GM/855GME GMCH maximum environmental stress ratings. Functional operation at the absolute maximum and minimum is neither implied nor guaranteed. Functional operating parameters are listed in the AC and DC tables. Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only.
Electrical Characteristics R Symbol Parameter Min Max Unit VCCAHPLL, VCCAGPLL, VCCADPLLA, VCCADPLLB Power supply for the Host PLL, Power Supply for the Hub PLL, Power supply for the Display PLL A, Power supply for the Display PLL B, respectively -0.3 1.65 V Notes Intel 855GME GMCH Only VCC 1.35 V Core Supply Voltage with respect to VSS -0.3 1.65 V VCCHI 1.35 V Hub Interface Supply Voltage with respect to VSS -0.3 1.65 V VCCASM (DDR333 SDRAM) 1.
Electrical Characteristics R 8.3 Power Characteristics Table 45. Power Characteristics Symbol Parameter Min Typ Max Unit Notes Intel 855GM GMCH Only TDPTyp Thermal Design Power < 3.2 W Intel 855GME GMCH Only TDPTyp (max performance) Thermal Design Power (Internal Graphics) < 4.3 W TDPTyp (max performance) Thermal Design Power (AGP Discrete Graphics) < 3.2 W IVCCmax 1.35 V Core Supply Current 2.24 A IVCCHI 1.35 V Hub Interface Supply Current 0.09 A IVCCASM 1.
Electrical Characteristics R Symbol IVCCQSM Parameter Min Typ Max Unit 2.5 V DDR SDRAM System Memory Clock Buffers Supply Current (DDR266 SDRAM) 0.14 A 2.5 V DDR SDRAM System Memory Clock Buffers Supply Current (DDR333 SDRAM) 0.18 A ISUS_VCCSM 2.5 V DDR SDRAM System Memory Interface Standby Supply Current 1 mA ISMVREF_0 1.25 V DDR SDRAM System Memory Interface Reference Voltage Supply Current 0.05 mA ISUS_SMVREF_0 1.
Electrical Characteristics R Table 46.
Electrical Characteristics R Signal Group Signal Type Signals Notes Hub Interface Signal Groups (l) CMOS HL[10:0], HLSTB, HLSTB# HI Inputs/Outputs (m) Analog/Ref HLRCOMP, PSWING, HLVREF HI Miscellaneous DDR SDRAM Interface Signal Groups (n) SSTL_2 DDR Input/Outputs (o) SSTL_2 DDR Outputs (p) Analog/Ref DDR Miscellaneous SDQ[63:0], SDQS[7:0] SCS[3:0]#, SMA[12:0], SBA[1:0], SRAS#, SCAS#, SWE#, SCKE[3:0], SMAB[5,4,2,1], SDM[7:0] SMVREF_0, SMVSWINGH, SMVSWINGL, SMRCOMP Clocks, Reset, and Misce
Electrical Characteristics R Signal Group Signal Type (q1) 1.35V DDR SDRAM DLL Supply Signals Notes VCCASM I/O Buffer Supply Voltages/Grounds (Intel 855GM/855GME GMCH Common) Datasheet (m1) AGTL+ Power Supply VTTLF (d1) 1.2 V Core (e1) 1.2 V Hub Interface (f1) 1.2 V PLL (g1) 2.5 V DDR SDRAM Supply (g1) 1.2V DDR SDRAM DLL Supply VCCASM (h1) 1.5 V DVO Supply VCCDVO (i1) 1.5 V DAC Supply VCCADAC (j1) 3.3 V GPIO Supply VCCGPIO (k1) 1.5 V LVDS Digital Supply VCCDLVDS (k1) 2.
Electrical Characteristics R 8.5 DC Characteristics 8.5.1 General DC Characteristics Table 47. DC Characteristics Symbol Signal Group Parameter Min Nom Max Unit Notes Supply Voltages (Intel 855GME GMCH Only) VCC (n1) Core Voltage 1.28 1.35 1.42 V VCCHL (p1) HI I/O Supply Voltage 1.28 1.35 1.42 V VCCASM (q1) DDR SDRAM I/O Supply Voltage 1.28 1.35 1.42 V VCCAGPLL VCCAHPLL VCCADPLLA VCCADPLLB (s1) PLL Supply Voltage 1.28 1.35 1.
Electrical Characteristics R Symbol Signal Group Parameter Min Nom Max Unit VCCALVDS (k1) Analog LVDS Supply Voltage 1.425 1.5 1.575 V VCCADAC (i1) DAC Supply Voltage 1.425 1.5 1.575 V VCCGPIO (j1) CMOS Supply Voltage 3.135 3.3 3.465 V HAVREF (d) Host Address and Reference Voltage (0.66 x VTTLF) – 2% 0.66 x VTTLF (0.66 x VTTLF)+ 2% V HDVREF[2:0] (d) Host Data Reference Voltage (0.66 x VTTLF) – 2% 0.66 x VTTLF (0.
Electrical Characteristics R Symbol SMVSWINGL Signal Group (p) Parameter System Memory RCOMP Buffer Differential Amp Reference Voltage Min Nom Max Unit (VCCSM * 0.2) - 2 % VCCSM * 0.2 (VCCSM * 0.2) + 2% V Notes Host Interface VIL_H (a), (c) Host AGTL+ Input Low Voltage -0.10 0 (0.66 x VTTLF) – 0.1 V VIH_H (a),(c) Host AGTL+ Input High Voltage (0.66 x VTTLF) + 0.1 VTT VTTLF+ 0.1 V VOL_H (a),(b) Host AGTL+ Output Low Voltage (0.33 x VTTLF) + 0.
Electrical Characteristics R Symbol Signal Group Parameter Min (n) DDR SDRAM Input High Voltage SMVREF + 0.
Electrical Characteristics R Symbol Signal Group Parameter Min Nom Max Unit GVREF – 0.15 V Notes 1.5 V DVO Interface: Functional Operating Range (VCC=1.
Electrical Characteristics R Symbol Signal Group Parameter Min Nom Max Unit CPAD (l) Hub Interface Input Capacitance 2 3 4 pF CPCKG (l) Hub Interface Input Capacitance 1 2 3 pF 345 450 mV 50 mV 1.375 V 50 mV -3.5 -10 mA ±1 ±10 µA 0.80 V Notes LVDS Interface: Functional Operating Range (VCC=2.
Electrical Characteristics R Symbol Signal Group Parameter ILEAK (q) Input Leakage Current Min Nom Max Unit Notes ±10 µA 0
Electrical Characteristics R Symbol Signal Group Parameter Min Nom Max Unit VIH (t), (a1) Input High Voltage (CMOS/LVTT L CLK Inputs) 2.0 CPAD (t) Input Capacitance (CMOS CLK Inputs) 1 1.25 1.5 pF CPCKG (t) Input Capacitance (CMOS CLK Inputs) 1 2 3 pF Notes V 1 NOTES: 1. CPCKG is the trace capacitance in the GMCH/MCH package. 8.5.2 DAC DC Characteristics Table 48. DAC DC Characteristics: Functional Operating Range (VCCDAC = 1.
Electrical Characteristics R 8.5.3 DAC Reference and Output Specifications Table 49. DAC Reference and Output Specifications Parameter Reference resistor Min Typical Max Units Notes 124 127 130 Ω 1% tolerance, 1/16 W R,G,B termination resistor 75 Ω (1) 1% tolerance, 1/16 W Video Filter Ferrite Bead 75 Ω @ 100- MHz, (each R,G,B output) Video Filter Capacitors 3.3 pF Two capacitors per R,G,B output NOTES: 1. VESA Video Signal Standard 2.
Video Filter Capacitors and Ferrite Bead Arranged in a PI Configuration (One PI Filter Testability) R 9 Video Filter Capacitors and Ferrite Bead Arranged in a PI Configuration (One PI Filter Testability) In the Intel 855GM/GME GMCH, testability for automated test equipment (ATE) board level testing has been implemented as an XOR chain. An XOR-tree is a chain of XOR gates, each with one input pin connected to it.
Video Filter Capacitors and Ferrite Bead Arranged in a PI Configuration (One PI Filter Testability) R 9.1 XOR Test Mode Entry Figure 11. XOR Chain Test Mode Entry Events Diagram p o w e ro k VSYNC HSYNC LC LKC TLA D o n 't c a r e D o n 't c a r e D o n 't c a r e R S T IN # ( P C I r e s e t) NOTE: HSYNC and LCLKCTLA = XOR Chain Test Mode Activation; No clock is required for XOR Chain Test Mode. A minimum of 50 ns PWROK assertion prior to RSTIN# assertion is recommended.
Video Filter Capacitors and Ferrite Bead Arranged in a PI Configuration (One PI Filter Testability) R 9.2 XOR Chain Differential Pairs Table 50 provides differential signals in the XOR chains that must be treated as pairs. Pin1 and Pin2 as shown below need to drive to the opposite value always. Table 50. Differential Signals in the XOR Chains 9.
Video Filter Capacitors and Ferrite Bead Arranged in a PI Configuration (One PI Filter Testability) R 9.4 Item# IN/OUT Ball Pin/VHDL I/O Type Voltage Connectivity 18 - B12 LVBG Analog N/A N/A 19 - F12 LVREFL Analog 1.1 1.1 20 IN B17 DREFSSCLK PLL CLK 3.3 0 21 - J17 HDVREF[2] Analog 2/3 VTTLF 1.0 22 - B20 HXRCOMP Analog N/A N/A 23 - B18 HXSWING Analog N/A N/A 24 - J21 HDVREF[1] Analog 2/3 VTTLF 1.0 25 IN AD29 BCLK# Diff 0.
Video Filter Capacitors and Ferrite Bead Arranged in a PI Configuration (One PI Filter Testability) R 10 INOUT P3 RSVD DVO 1.5 11 INOUT P6 RSVD N/A N/A 12 INOUT P5 RSVD N/A N/A 13 INOUT N2 RSVD N/A N/A 14 INOUT N3 RSVD N/A N/A 15 INOUT M1 RSVD N/A N/A 16 INOUT N5 RSVD N/A N/A 17 INOUT M2 RSVD N/A N/A 18 INOUT M5 RSVD N/A N/A 19 INOUT M3 DVOBCCLKINT DVO 1.5 20 INOUT L2 RSVD N/A N/A 21 INOUT P7 MDDCCLK DVO 1.
Video Filter Capacitors and Ferrite Bead Arranged in a PI Configuration (One PI Filter Testability) R 16 INOUT H3 DVOCD[8] DVO 1.5 17 INOUT H5 DVOCFLDSTL DVO 1.5 18 INOUT H6 DVOCD[10] DVO 1.5 19 INOUT G2 DVOBCINT# DVO 1.5 20 INOUT G3 DVOCD[11] DVO 1.5 21 IN D2 RSVD N/A N/A 22 IN D3 RSVD N/A N/A 23 IN F4 ADDID[5] DVO 1.5 24 IN F5 ADDID[1] DVO 1.5 25 IN F6 ADDID[7] DVO 1.5 26 IN E2 ADDID[3] DVO 1.5 27 IN E5 ADDID[0] DVO 1.
Video Filter Capacitors and Ferrite Bead Arranged in a PI Configuration (One PI Filter Testability) R 14 INOUT D20 HD[52]# AGTL+ 1.5 15 INOUT E20 HD[50]# AGTL+ 1.5 16 INOUT E19 HD[49]# AGTL+ 1.5 17 INOUT G19 DINV[3]# AGTL+ 1.5 18 INOUT F19 HD[53]# AGTL+ 1.5 19 INOUT G18 HD[48]# AGTL+ 1.5 20 INOUT B21 HD[32]# AGTL+ 1.5 21 INOUT C20 HD[46]# AGTL+ 1.5 22 INOUT C23 HD[35]# AGTL+ 1.5 23 INOUT B23 HD[43]# AGTL+ 1.5 24 INOUT B22 HD[42]# AGTL+ 1.
Video Filter Capacitors and Ferrite Bead Arranged in a PI Configuration (One PI Filter Testability) R 192 6 INOUT G23 HD[30]# AGTL+ 1.5 7 INOUT E26 HD[9]# AGTL+ 1.5 8 INOUT D26 HDSTBP[1]# AGTL+ 1.5 9 INOUT C27 HDSTBN[1]# AGTL+ 1.5 10 INOUT G22 HD[27]# AGTL+ 1.5 11 INOUT G24 HD[24]# AGTL+ 1.5 12 INOUT C28 HD[25]# AGTL+ 1.5 13 INOUT E27 HD[20]# AGTL+ 1.5 14 INOUT F2 HD[17]# AGTL+ 1.5 15 INOUT D27 HD[23]# AGTL+ 1.5 16 INOUT G25 HD[21]# AGTL+ 1.
Video Filter Capacitors and Ferrite Bead Arranged in a PI Configuration (One PI Filter Testability) R XOR Chain FSB 3 IN/OUT Ball Pin I/O Type Voltage OUT AC6 SMA[8] SSTL_2 2.5 1 OUT F15 CPURST# AGTL+ 1.5 2 IN Y23 DPSLP# CMOS 1.5 3 INOUT N27 HIT# AGTL+ 1.5 4 INOUT N28 HITM# AGTL+ 1.5 5 INOUT N25 BNR# AGTL+ 1.5 6 INOUT N24 DRDY# AGTL+ 1.5 7 IN P27 HLOCK# AGTL+ 1.5 8 INOUT M23 BREQ0# AGTL+ 1.5 9 OUT M25 HTRDY# AGTL+ 1.
Video Filter Capacitors and Ferrite Bead Arranged in a PI Configuration (One PI Filter Testability) R 35 INOUT V23 HA[19]# AGTL+ 1.5 36 INOUT W27 HA[25]# AGTL+ 1.5 37 INOUT Y25 HA[21] AGTL+ 1.5 38 INOUT W24 HA[23]# AGTL+ 1.5 39 INOUT Y27 HA[26]# AGTL+ 1.5 40 INOUT Y24 HA[17]# AGTL+ 1.5 41 INOUT AA27 HA[22]# AGTL+ 1.5 42 INOUT W23 HA[24]# AGTL+ 1.5 43 INOUT AB28 HA[31]# AGTL+ 1.5 44 INOUT AB27 HA[29]# AGTL+ 1.5 45 INOUT AA28 HA[27] AGTL+ 1.
Video Filter Capacitors and Ferrite Bead Arranged in a PI Configuration (One PI Filter Testability) R 7 IN V5 Hl[9] HL1.5 1.2 8 INOUT V4 HL[10] HL1.5 1.2 9 INOUT V3 HL[3] HL1.5 1.2 10 INOUT U4 HL[1] HL1.5 1.2 11 INOUT U3 HL[2] HL1.5 1.2 12 INOUT U7 HL[0] HL1.5 1.2 13 OUT T3 HL[8] HL1.5 1.2 IN/OUT Ball Pin I/O Type Voltage OUT AD17 SMA[3] SSTL_2 2.5 1 INOUT F10 ICLKBP LVDS 1.5 2 INOUT E10 ICLKBM LVDS 1.5 3 INOUT G10 IYBP[3] LVDS 1.
Video Filter Capacitors and Ferrite Bead Arranged in a PI Configuration (One PI Filter Testability) R 4 INOUT AG26 SDQ[60] SSTL_2 2.5 5 OUT AC25 SCS[3]# SSTL_2 2.5 6 OUT AD24 SDM[6] SSTL_2 2.5 7 INOUT AH24 SDQS[6] SSTL_2 2.5 8 OUT AD25 SWE# SSTL_2 2.5 9 OUT AC18 SMA[0] SSTL_2 2.5 10 INOUT AH17 SDQS[4] SSTL_2 2.5 11 OUT AD19 SDM[4] SSTL_2 2.5 12 CLK AC26 SCK[1] SSTL_2 2.5 13 CLK AB23 SCK[4] SSTL_2 2.5 14 CLK AA3 SCK[5] SSTL_2 2.
Video Filter Capacitors and Ferrite Bead Arranged in a PI Configuration (One PI Filter Testability) R Datasheet 5 INOUT AE26 SDQ[57] SSTL_2 2.5 6 INOUT AH26 SDQ[56] SSTL_2 2.5 7 INOUT AH25 SDQ[51] SSTL_2 2.5 8 INOUT AG25 SDQ[55] SSTL_2 2.5 9 INOUT AF25 SDQ[54] SSTL_2 2.5 10 INOUT AE24 SDQ[50] SSTL_2 2.5 11 INOUT AH23 SDQ[49] SSTL_2 2.5 12 INOUT AF23 SDQ[53] SSTL_2 2.5 13 INOUT AE23 SDQ[48] SSTL_2 2.5 14 INOUT AG23 SDQ[52] SSTL_2 2.
Video Filter Capacitors and Ferrite Bead Arranged in a PI Configuration (One PI Filter Testability) R 42 OUT AB7 SCKE[1] SSTL_2 2.5 DDR SDRAM IN/OUT Ball Pin I/O Type Voltage OUT AC22 SCS[2]# SSTL_2 2.5 1 OUT AC24 SCAS# SSTL_2 2.5 2 INOUT AG22 SDQ[47] SSTL_2 2.5 3 INOUT AH22 SDQ[43] SSTL_2 2.5 4 INOUT AF22 SDQ[42] SSTL_2 2.5 5 INOUT AG20 SDQ[41] SSTL_2 2.5 6 INOUT AF20 SDQ[44] SSTL_2 2.5 7 INOUT AH21 SDQ[46] SSTL_2 2.
Video Filter Capacitors and Ferrite Bead Arranged in a PI Configuration (One PI Filter Testability) R Datasheet 34 INOUT AF7 SDQ[14] SSTL_2 2.5 35 INOUT AG7 SDQ[10] SSTL_2 2.5 36 INOUT AE8 SDQ[11] SSTL_2 2.5 37 INOUT AH6 SDQ[15] SSTL_2 2.5 38 INOUT AF5 SDQ[12] SSTL_2 2.5 39 INOUT AD6 SDQ[8] SSTL_2 2.5 40 INOUT AH4 SDQ[13] SSTL_2 2.5 41 INOUT AG5 SDQ[9] SSTL_2 2.5 42 INOUT AH2 SDQ[3] SSTL_2 2.5 43 INOUT AF4 SDQ[2] SSTL_2 2.
Video Filter Capacitors and Ferrite Bead Arranged in a PI Configuration (One PI Filter Testability) R 9.4.1 VCC/VSS Voltage Groups Table 53. Voltage Levels and Ball Out for Voltage Groups Name Voltage Level Ballout VCC 1.2 (855GM) 1.35 (855GME) H14,J15,N14,N16,P13,P15,P17,R14,R16,T13,T15, VCCADAC 1.5 A9,B9 VCCDVO 1.5 E1,E4,E6,H7,J1,J4,J8,K9,L8,M4,M8,M9,N1,N8,P9,R8 VCCASM 1.2 (855GM) 1.35 (855GME) AD1,AF1 VCCDLVDS 1.5 B14,B15,G13,J13 VCCGPIO 3.3 A3,A4 VCCHL 1.2 (855GM) 1.
Intel® 855GM/GME GMCH Strap Pins R 10 Intel® 855GM/GME GMCH Strap Pins 10.1 Strapping Configuration Table 54. Strapping Signals and Configuration Pin Name Strap Description Configuration I/F Type Buffer Type HSYNC XOR Chain Test Low = Normal Ops (Default) High = XOR Test On GPIO OUT VSYNC ALL Z Test Low = Normal Ops (Default) High = AllZ Test On GPIO OUT LCLKCTLB VTT Voltage Select High = 1.
Intel® 855GM/GME GMCH Strap Pins R 202 Datasheet
Ballout and Package Information R 11 Ballout and Package Information Figure 13.
Ballout and Package Information R Table 55.
Ballout and Package Information R Row Column Datasheet Signal Name Row Column Signal Name Row Column Signal Name T 25 HA[4]# B 21 HD[32]# L 25 HD[8]# T 28 HA[5]# G 21 HD[33]# J 24 HD[9]# R 27 HA[6]# C 24 HD[34]# J 28 HDSTBN[0]# U 23 HA[7]# C 23 HD[35]# C 27 HDSTBN[1]# U 24 HA[8]# D 22 HD[36]# E 22 HDSTBN[2]# R 24 HA[9]# C 25 HD[37]# D 18 HDSTBN[3]# T 26 HADSTB[0]# E 24 HD[38]# K 27 HDSTBP[0]# AA 26 HADSTB[1]# D 24 HD[39]# D 26 HD
Ballout and Package Information R Row Column Signal Name Row Column Signal Name Row Column Signal Name H 10 HSYNC AH 29 NC D 2 RSVD M 25 HTRDY# B 29 NC C 2 GST[2] B 20 HXRCOMP A 29 NC B 2 RSVD B 18 HXSWING AJ 28 NC D 7 RSVD H 28 HYRCOMP A 28 NC AD 22 SBA[0] K 28 HYSWING AA 9 NC AD 20 SBA[1] D 14 ICLKAM AJ 4 NC AC 24 SCAS# E 13 ICLKAP AJ 2 NC AB 2 SCK[0] E 10 ICLKBM A 2 NC AA 2 SCK[0]# F 10 ICLKBP AH 1 NC AC 26 SC
Ballout and Package Information R Row Column Datasheet Signal Name Row Column Signal Name Row Column Signal Name AF 2 SDQ[0] AG 20 SDQ[41] AG 2 SDQS[0] AE 3 SDQ[1] AF 22 SDQ[42] AH 5 SDQS[1] AG 7 SDQ[10] AH 22 SDQ[43] AH 8 SDQS[2] AE 8 SDQ[11] AF 20 SDQ[44] AE 12 SDQS[3] AF 5 SDQ[12] AH 19 SDQ[45] AH 17 SDQS[4] AH 4 SDQ[13] AH 21 SDQ[46] AE 21 SDQS[5] AF 7 SDQ[14] AG 22 SDQ[47] AH 24 SDQS[6] AH 6 SDQ[15] AE 23 SDQ[48] AH 27 SDQS[
Ballout and Package Information R Row Column Signal Name Row Column Signal Name Row Column Signal Name P 17 VCC E 6 VCCDVO AA 13 VCCSM U 16 VCC M 4 VCCDVO AF 12 VCCSM R 16 VCC J 4 VCCDVO AB 12 VCCSM N 16 VCC E 4 VCCDVO AA 11 VCCSM AA 15 VCC N 1 VCCDVO AB 10 VCCSM T 15 VCC J 1 VCCDVO AJ 9 VCCSM P 15 VCC E 1 VCCDVO AF 9 VCCSM J 15 VCC A 4 VCCGPIO Y 9 VCCSM U 14 VCC A 3 VCCGPIO AB 8 VCCSM R 14 VCC V 9 VCCHL AA 8 VCC
Ballout and Package Information R Row Column Datasheet Signal Name Row Column Signal Name Row Column Signal Name D 28 VSS U 22 VSS R 17 VSS AJ 27 VSS R 22 VSS N 17 VSS AG 27 VSS N 22 VSS H 17 VSS AC 27 VSS L 22 VSS D 17 VSS F 27 VSS J 22 VSS A 17 VSS A 27 VSS F 22 VSS AE 16 VSS AJ 26 VSS C 22 VSS AA 16 VSS AB 26 VSS AG 21 VSS T 16 VSS W 26 VSS AB 21 VSS P 16 VSS U 26 VSS AA 21 VSS J 16 VSS R 26 VSS Y 21 VS
Ballout and Package Information R Row Column Signal Name Row Column Signal Name Row Column Signal Name AJ 11 VSS M 7 VSS B 11 VSSALVDS AC 11 VSS J 7 VSS J 9 VSYNC AB 11 VSS G 7 VSS V 29 VTTHF H 11 VSS E 7 VSS M 29 VTTHF F 11 VSS C 7 VSS H 29 VTTHF D 11 VSS AG 6 VSS A 24 VTTHF AJ 10 VSS Y 6 VSS A 22 VTTHF AE 10 VSS L 6 VSS AB 29 VTTLF AA 10 VSS Y 5 VSS Y 29 VTTLF J 10 VSS U 5 VSS K 29 VTTLF C 10 VSS B 5 VSS
Ballout and Package Information R 11.1 Package Mechanical Information Figure 14 through Figure 16 provide detail on the package information and dimensions of the Intel 855GM/855GME GMCH. The Intel 855GM/855GME GMCH comes in a Micro-FCBGA package, which is similar to the mobile processors. The package consists of a silicon die mounted face down on an organic substrate populated with solder balls on the bottom side. Capacitors may be placed in the area surrounding the die.
Ballout and Package Information R Figure 15.
Ballout and Package Information R Figure 16.
