R Intel® 852GM Chipset Platform Design Guide For Use with the Mobile Intel® Pentium® 4 Processor-M, Mobile Intel® Celeron® Processor on .
R Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
R Contents 1. 2. 3. 4. Introduction .................................................................................................................................19 1.1. Terminology ...................................................................................................................19 1.2. Referenced Documents .................................................................................................20 System Overview...............................................................
R 4.5. 5. 6. 7. 4 Mobile Intel Pentium 4 Processor–M and Intel 852GM Chipset FSB Signal Package Lengths ......................................................................................................................... 46 4.5.1. Mobile Intel Pentium 4 Processor-M GTLREF Layout and Routing Recommendations......................................................................................... 50 4.5.2. AGTL+ I/O Buffer Compensation .................................................................
R Clock Package Length Table ..........................................................89 Clock Routing Example...................................................................89 7.3.3.4.1. Clock Routing Updates for “DDP Stacked” Memory Device Support .............................................................90 7.3.4. Data Signals – SDQ[64:0], SDM[7:0], SDQS[7:0]..........................................90 7.3.4.1. Data Bus Topology......................................................................
R 9. 10. 6 8.2.1.1. Package Length Compensation ................................................... 136 8.2.2. LVDS Routing Guidelines............................................................................ 136 8.3. Digital Video Out Port.................................................................................................. 138 8.3.1. DVO Interface Signal Groups ...................................................................... 138 8.3.1.1. DVOC Interface Signals .....................
R 10.5. 10.6. 10.7. 10.8. 10.9. 10.4.1.5. USB 2.0 Trace Length Pair Matching ...........................................166 10.4.1.6. USB 2.0 Trace Length Guidelines ................................................166 10.4.2. Plane Splits, Voids, and Cut-Outs (Anti-Etch)..............................................166 10.4.2.1. VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)......................167 10.4.2.2. GND Plane Splits, Voids, and Cut-Outs (Anti-Etch) .....................167 10.4.3.
R 11. 12. 8 10.9.2.5.1. Terminating Unused Connections.............................. 187 10.9.2.5.2. Termination Plane Capacitance ................................. 187 10.9.3. Intel 82562ET/EM Disable Guidelines......................................................... 187 10.9.4. General Intel 82562ET/82562EM Differential Pair Trace Routing Considerations............................................................................................. 188 10.9.4.1.1. Trace Geometry and Length ..............
R DDR Memory Power Delivery Design Guidelines........................................223 12.5.3.1. 2.5-V Power Delivery Guidelines ..................................................224 12.5.3.2. GMCH and DDR SMVREF Design Recommendations................224 12.5.3.3. DDR SMRCOMP Resistive Compensation ..................................225 12.5.3.4. DDR VTT Termination ..................................................................226 12.5.3.5. DDR SMRCOMP, SMVREF, and VTT 1.
R 15. 10 14.8.6. ICH4-M Power Management Interface ........................................................ 261 14.8.7. FWH/LPC Interface...................................................................................... 261 14.8.8. USB Interface .............................................................................................. 262 14.8.9. Hub Interface ............................................................................................... 262 14.8.10. RTC Circuitry ...............
R Figures Figure 1. Intel 852GM Chipset System Block Diagram........................................................... 22 Figure 2. Recommended Board Stack-Up Dimensions .......................................................... 28 Figure 3. Cross-Sectional View of 2:1 Ratio............................................................................ 32 Figure 4. Processor Topology ................................................................................................. 34 Figure 5.
R Figure 49. Data Signals Group Routing Example.................................................................. 100 Figure 50. Control Signal Routing Topology.......................................................................... 101 Figure 51. Control Signal to Clock Trace Length Matching Diagram .................................... 104 Figure 52. Control Signals Group Routing Example.............................................................. 105 Figure 53. Command Routing for Topology 1..........
R Figure 100. Termination Plane .............................................................................................. 187 Figure 101. Intel 82562ET/EM Disable Circuitry ................................................................... 188 Figure 102. Trace Routing..................................................................................................... 189 Figure 103. Ground Plane Separation...................................................................................
R Tables Table 1. Front Side Bus Routing Summary for the Processor................................................. 31 Table 2. Processor Front Side Bus Data Signal Routing Guidelines....................................... 35 Table 3. Processor Front Side Bus Address Signal Routing Guidelines................................. 35 Table 4. Processor Front Side Bus Control Signal Routing Guidelines .................................. 39 Table 5. Layout Recommendations for Topology 1A............................
R Table 47. CPC Group Package Lengths ............................................................................... 125 Table 48. Recommended GMCH RAMDAC Components.................................................... 133 Table 49. Signal Group and Signal Pair Names ................................................................... 135 Table 50. LVDS Signal Trace Length Matching Requirements ............................................ 135 Table 51. LVDS Signal Group Routing Guidelines ..................
R Table 99. GST[1:0] Configurations ........................................................................................ 255 Table 100. Intel 852GM GMCH Power-up Timing Specifications.......................................... 256 Equations Equation 1. Calculation to Determine Package Delta Addition to Motherboard Length for UP Systems ....................................................................................................................
R Revision History Rev Order No.
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Introduction R 1. Introduction This design guide organizes and provides Intel’s design recommendations for the Intel® 852GM chipset based systems. These design guidelines have been developed to ensure maximum flexibility for board designers while reducing the risk of board related issues. The following processors can be combined with the Intel 852GM GMCH chipset: • Mobile Intel® Pentium® 4 Processor-M • Mobile Intel® Celeron® processor • Intel® Celeron® M processor 1.1.
Introduction R 1.2. Term Definition SPD Serial Presence Detect STD Suspend-To-Disk STR Suspend-To-Ram TCO Total Cost of Ownership TDR Time Domain Reflectometry UBGA Micro Ball Grid Array USB Universal Serial Bus VRM Voltage Regulator Module Referenced Documents Contact your Intel Field Representative for the latest revsions. Document ® Mobile Intel Pentium (250686) ® ® 4 Processor –M Datasheet ® Mobile Intel Celeron Processor Datasheet (251308) ® ® http://developer.intel.
System Overview R 2. System Overview The Intel 852GM GMCH is a graphics memory controller hub (GMCH) component for mobile platforms. It provides the processor interface, system memory interface (DDR-SDRAM), Hub interface, CRT, LVDS, and one DVO port. An ACPI-compliant Intel 852GM chipset platform can support the Full-On (S0), Power On Suspend (S1-M), Suspend to RAM (S3), Suspend to Disk (S4), and Soft-Off (S5) power management states.
System Overview R Figure 1. Intel 852GM Chipset System Block Diagram Processor VR CK-408 400 MHz BPSB DVI DVOC CRT LFP LVDS 852GM GMCH 732 MicroFCBGA Hub Interface 1.5 LAN ATA100 IDE (2) USB2.0/1.1 (6) 200/266 MHz DDR ICH 4-M 421 BGA PCI Bus Wireless (802.11) Mini-PCI Cardbus Moon 2 PCI Docking AC'97 2.3 Audio Codec FWH Modem Codec 2.2. LPC I/F SIO KBC Processor Interface The 852GM GMCH supports a FSB frequency of 400 MHz (100-MHz HCLK respectively) using scaleable FSB VCC.
System Overview R • The execution trace cache is a first level cache that stores approximately 12-k decoded microoperations, which removes the decoder from the main execution path. 2.2.2. Mobile Intel Pentium 4 Processor-M The processor utilizes flip-chip pin grid array (FC-PGA2) package technology, which plugs into a 478pin surface mount, zero insertion force (ZIF) socket, referred to as the mPGA478B socket.
System Overview R • AGTL+ bus driver technology with integrated GTL termination resistors (gated AGTL+ receivers for reduced power) • Supports 32 bit • AGTL+ bus addressing (no support for 36-bit address extension) • Supports uniprocessor systems • 400-MHz, source-synchronous FSB • 2X Address, 4X data • High performance, low power core • Advanced Branch Prediction and Data Prefetch Logic • Advanced Power Management features 2.3. Intel 852GM Graphics Memory Controller Hub 2.3.1.
System Overview R • 3D Graphics Engine ⎯ 3D Setup and Render Engine ⎯ High quality performance Texture Engine • Analog Display Support ⎯ 350-MHz integrated 24-bit RAMDAC ⎯ Hardware color cursor support ⎯ Accompanying I2C and DDC channels provided through multiplexed interface ⎯ Hotplug and display support ⎯ Dual independent pipe for dual independent display • Digital Video Out Port (DVO) support ⎯ Single channel DVO Port with 165-MHz dot clock support for a 12-bit interface ⎯ Compliant with DVI Specificati
System Overview R • FWH Interface • LPC Interface • AC’97 2.3 Interface • Alert-On-LAN* • IRQ Controller • IPAA security 2.3.3.1. Packaging/Power • 421-pin, BGA package (31 mm x 31 mm) VCC1_5 (1.5 V main logic voltage); VCCSUS1_5 (1.5 V resume logic voltage); VCCLAN1_5 (1.5 V LAN logic voltage); VCC3_3 (3.3 V main I/O voltage); VCCSUS3_3 (3.3 V resume I/O voltage); VCCLAN3_3 (3.3 V LAN I/O voltage); V5REF (5 V); V5REF_SUS (5 V); VCCRTC; VCCHI (1.5 V); VCCP (1.2-1.
General Design Considerations R 3. General Design Considerations This section provides motherboard layout and routing guidelines. It does not discuss the functional aspects of any bus, or the layout guidelines for an add-in device. If the guidelines listed in this document are not followed, thorough signal integrity and timing simulations should be ompleted for each design.
General Design Considerations R Figure 2. Recommended Board Stack-Up Dimensions Stackup Dielectric Layer Layer Copper Trace Trace Thickness No. Type Weight Width Impedance (oz) (mils) (ohms) 5.0 55 4.0 55 4.0 55 5.0 55 (mils) S PREPREG => 5.0 CORE => 5.0 PREPREG => 12.0 CORE => 10.0 PREPREG => 12.0 CORE => 5.0 PREPREG => 5.
General Design Considerations R 3.2. Alternate Stack Ups OEMs may choose to use different stack-ups (number of layers, thickness, trace width, etc.) from the one example outlined in Figure 2. However, the following key elements should be observed: 1. Final post lamination, post etching, and post plating dimensions should be used for electrical model extractions. 2. Power plane layers should be 1 oz thick and signal layers should be ½ oz thick. External layers become 1 – 1.5 oz (1.
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Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines R 4. Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines The following layout guidelines support designs using the Mobile Intel Pentium 4 Processor–M / Mobile Intel Celeron Processor and the Intel 852GM chipset. Due to on-die Rtt resistors on both the processor and the chipset, additional resistors do not need to be placed on the motherboard for most FSB signals.
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines R Parameter ADSTBn/p[1:0]# Processor Routing Guidelines • An address strobe and its complement should be routed within ± 0.200 of the same Pad-toPad length. • The pad is defined as the attach point of the silicon die to the package substrate. • Length must be added to the system board to compensate for package length differences.
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines R 4.1.1. Return Path Evaluation The return path is the route current takes to return to its source. It may take a path through ground planes, power planes, other signals, integrated circuits, vias, VRMs, etc. Think of the return path as following a path of least impedance back to the original source.
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines R 4.3.1. Source Synchronous (SS) Signal Group Source synchronous groups and associated strobes should be routed on the same layer for the entire length of the bus. This results in a significant reduction of the flight time skew since the dielectric thickness, line width, and velocity of the signals will be uniform across a single layer of the stackup.
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines R Table 2. Processor Front Side Bus Data Signal Routing Guidelines Signal Names Total Trace Length Transmission Line Type Nominal Impedance (Ω) Width & Spacing (mils) Min (inches) Max (inches) Strip-line 0.5 5.5 55 ± 15% 4 & 12 HD[63:0]# Strip-line 0.5 5.5 55 ±15% 4 & 12 DSTBN[3:0]# HDSTBN[3:0]# Strip-line 0.5 5.5 55 ± 15% 4 & 12 DSTBP[3:0]# HDSTBP[3:0]# Strip-line 0.5 5.
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines R Figure 5. SS Topology for Address and Data Processor Vtt Vtt Pin Chip Set Pin Pad Pad L1 4.3.2. FSB Data and Address Routing Example Figure 6, Figure 7, Figure 8, and Figure 9 provide examples of a board routing for the Data signal group. The majority of the Data signal route is on an internal layer; both external layers can be used for parallel termination R-pack placement. Figure 6.
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines R Figure 7. FSB Host Address Routing Example Layer 3 Layer 3 FSB Address signals Figure 8.
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines R Figure 9.
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines R 4.3.3. Common Clock (CC) AGTL+ Signal Group Common clock signals should be routed to a minimum pin-to-pin motherboard length of 0.5 inches and a maximum motherboard length of 6.5 inches. Table 4.
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines R as either micro-strip or strip-lines using 55 Ω ± 15% characteristic trace impedance. The pull-up voltage for termination resistor Rtt is VCCP. Due to the dependencies on system design implementation, IERR# can be implemented in a number of ways to meet design goals. IERR# can be routed as a test point or to any optional system receiver.
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines R Figure 11. Routing Illustration for Topology 1B ICH4-M (or sys. receiver) CPU VCCP Rtt L2 L3 L1 Table 6. Layout Recommendations for Topology 1B 4.3.4.3. L1 L2 L3 Rtt Transmission Line Type 0.5” – 12.0” 0” – 3.0” 0” – 3.0” 56 Ω ± 5% Micro-strip 0.5” – 12.0” 0” – 3.0” 0” – 3.
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines R Figure 12. Routing Illustration for Topology 1C (System receiver) 3.3 V_IO_RCVR 3.3 CPU VCCP L2 L1 R2 R1 Rtt Q2 L3 L4 390 Q1 390 Rs Table 7. Layout Recommendations for Topology 1C 4.3.4.4. L1 L2 L3 L4 Rs R1 R2 Rtt Transmission Line Type 0.5 – 12.0” 03.0” 0– 3.0” 0.5 – 12.0” 330 Ω ± 5% 1.3 kΩ ± 5 % 330 Ω ± 5% 56 Ω ± 5% Micro-strip 0.5 – 12.0” 03.0” 0– 3.0” 0.5 – 12.
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines R Figure 13. Routing Illustration for Topology 2A VCCP Rtt CPU ICH4-M L1 L2 Table 8. Layout Recommendations for Topology 2A 4.3.4.5. L1 L2 Rtt Transmission Line Type 0.5” – 12.0” 0” – 3.0” 300 Ω ± 5% Micro-strip 0.5” – 12.0” 0” – 3.
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines R 4.3.4.6. Topology 2C: CMOS Signals Driven by ICH4-M – A20M#, IGNNE#, LINT0/INTR, LINT1/NMI, SLP#, SMI#, and STPCLK# The Topology 2C CMOS A20M#, IGNNE#, LINT0/INTR, LINT1/NMI, SLP#, SMI#, and STPCLK# signals should implement a point-to-point connection between the ICH4-M and the Mobile Intel Pentium 4 Processor–M.
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines R Figure 16. Routing Illustration for Topology 3 FWH 3.3V V_IO_FWH 3.3V CPU ICH4-M R2 R1 L4 Q2 L1 L2 L3 3904 Q1 3904 Rs Table 11. Layout Recommendations for Topology 3 L1 + L2 L3 L4 Rs R1 R2 Transmission Line Type 0.5” – 12.0” 0” – 3.0” 0.5” – 6.0” 300 Ω ± 5% 2kΩ ± 5% 300 Ω ± 5% Micro-strip 0.5” – 12.0” 0” – 3.0” 0.5” – 6.0” 300 Ω ± 5% 2kΩ ± 5% 300 Ω ± 5% Strip-line Figure 17.
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines R 4.4.1. Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging the Mobile Intel Pentium 4 Processor–M based system. Tektronix* and Agilent* should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature.
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines R Processor lengths GMCH Lengths A[5]# L6 0.155 HA[5]# T28 551 A[6]# K1 0.415 HA[6]# R27 523 A[7]# L3 0.304 HA[7]# U23 274 A[8]# M6 0.144 HA[8]# U24 333 A[9]# L2 0.372 HA[9]# R24 327 A[10]# M3 0.327 HA[10]# U28 560 A[11]# M4 0.246 HA[11]# V28 566 A[12]# N1 0.394 HA[12]# U27 522 A[13]# M1 0.408 HA[13]# T27 501 A[14]# N2 0.349 HA[14]# V27 562 A[15]# N4 0.
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines R Processor lengths GMCH Lengths D[0]# B21 0.414 HD[0]# K22 329 D[1]# B22 0.475 HD[1]# H27 620 D[2]# A23 0.538 HD[2]# K25 438 D[3]# A25 0.608 HD[3]# L24 387 D[4]# C21 0.386 HD[4]# J27 600 D[5]# D22 0.386 HD[5]# G28 693 D[6]# B24 0.535 HD[6]# L27 518 D[7]# C23 0.464 HD[7]# L23 329 D[8]# C24 0.515 HD[8]# L25 458 D[9]# B25 0.
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines R Processor lengths GMCH Lengths Data Group 2 DSTBN[2]# K22 0.252 HDSTBN[2]# E22 538 DSTBP[2]# J23 0.266 HDSTBP[2]# E21 502 D[32]# M23 0.300 HD[32]# B21 664 D[33]# N22 0.226 HD[33]# G21 501 D[34]# P21 0.178 HD[34]# C24 683 D[35]# M24 0.371 HD[35]# C23 675 D[36]# N23 0.271 HD[36]# D22 633 D[37]# M26 0.454 HD[37]# C25 747 D[38]# N26 0.
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines R Processor lengths 4.5.1. GMCH Lengths D[62]# AA22 0.268 HD[62]# D16 509 D[63]# AA24 0.394 HD[63]# C18 579 DBI[3]# V21 0.202 DINV[3]# G19 431 Mobile Intel Pentium 4 Processor-M GTLREF Layout and Routing Recommendations There are four AGTL+ GTLREF pins on the processor that are used to set the reference voltage level for the AGTL+ signals (GTLREF).
Mobile Intel Pentium 4 Processor–M and Mobile Intel Celeron Processor FSB Design Guidelines R same purpose described above. Refer to the Mobile Intel® Pentium® 4 Processor–M Datasheet and Intel® 852GM GMCH Chipset Datasheet for details on resistive compensation. 4.5.2.1. Mobile Intel Pentium 4 Processor–M AGTL+ I/O Buffer Compensation For the Mobile Intel Pentium 4 Processor–M, the COMP[1:0] pins (see Figure 19) must each be pulleddown to ground with 51.
Intel Celeron M Processor Front Side Bus Design Guidelines R 5. Intel Celeron M Processor Front Side Bus Design Guidelines The following layout guidelines support designs using the Intel Celeron M processor and the Intel 852GM GMCH chipset. Due to on-die Rtt resistors on both the processor and the chipset, additional resistors do not need to be placed on the motherboard for most FSB signals. A simple point-to-point interconnect topology is used in these cases. 5.1.
Intel Celeron M Processor Front Side Bus Design Guidelines R Figure 22. Trace Spacing vs. Trace to Reference Plane Example Reference Plane (VSS) X 2X Trace 5.2.2. Trace Trace Space to Trace Width Ratio Figure 20 illustrates the recommended relationship between the edge-to-edge trace spacing versus trace width ratio for the best signal quality results. In general, a 3:1 trace space to trace width ratio is preferred and highly recommended.
Intel Celeron M Processor Front Side Bus Design Guidelines R to maximize the signal spacing in these areas, it is allowable to have 1:1 trace spacing underneath the GMCH and the processor package outlines and up to 200 – 300 mils outside the package outline. Table 13 summarizes the list of common clock and key routing. RESET# (CPURST# of GMCH) is also a common clock signal but requires a special treatment for the case where an ITP700FLEX debug port is used. See Section 5.6 for further details. Table 13.
Intel Celeron M Processor Front Side Bus Design Guidelines R common clock nets on the system board in order to meet the same minimum requirement for trace lengths from the die-pad of the processor to the associated die-pad of the chipset. For example: ADS# = 997 mils board trace + 454 CPU PKG + 761 GMCH PKG = 2212 pad-to-pad length BR0# = X mils board trace + 336 CPU PKG + 465 GMCH PKG = 2212 pad-to-pad length Therefore: X = BR0# board trace = 2212 - 336 - 465 = 1411 pin to pin length. Figure 20.
Intel Celeron M Processor Front Side Bus Design Guidelines R 5.4. Source Synchronous Signals General Routing Guidelines All source synchronous signals use an AGTL+ bus driver technology with on-die GTL termination resistors connected in a point-to-point, Zo = 55 Ω controlled impedance topology between the processor and the GMCH. No external termination is needed on these signals.
Intel Celeron M Processor Front Side Bus Design Guidelines R Figure 21. Layer 6 FSB Source Synchronous Signals GND Referencing to Layer 5 In a similar way, Figure 22 illustrates a recommended layout and stack-up example of how another group of FSB source synchronous DATA and ADDRESS signals can reference ground planes on both Layer 2 and Layer 4. Note that in the socket cavity of the processor, Layer 3 is used for VCC core power delivery to reduce the I*R drop.
Intel Celeron M Processor Front Side Bus Design Guidelines R Figure 22. Layer 3 FSB Source Synchronous Signals 5.4.1. Source Synchronous Signal Length Matching Constraints The routing guidelines presented in the following subsections define the recommended routing topologies, trace width and spacing geometries, and absolute minimum and maximum routed lengths for each signal group, which are recommended to achieve optimal SI and timing.
Intel Celeron M Processor Front Side Bus Design Guidelines R Package length compensation should not be confused with length matching. Length matching refers to constraints on the min and max length bounds of a signal group based on clock length, whereas package length compensation refers to the process of compensating for package length variance across a signal group. There is some overlap in that both affect the target length of an individual signal.
Intel Celeron M Processor Front Side Bus Design Guidelines R Table 16. FSB Source Synchronous Data Signal Routing Guidelines Signal Names Transmission Line Type Total Trace Length Nominal Spacing Impedance & Width (Ω) (mils) Data Group #1 Data Group #2 Data Group #3 Data Group #4 D[15:0]# D[31:16]# D[47:32]# D[63:48]# Strip-line 0.5 5.5 55 ± 15% 3:1 DINV0# DINV1# DINV2# DINV3# Strip-line 0.5 5.5 55 ±15% 3:1 DSTBN[0]# DSTBN[1]# DSTBN[2]# DSTBN[3]# Strip-line 0.5 5.
Intel Celeron M Processor Front Side Bus Design Guidelines R Table 18. Processor FSB Source Synchronous Address Signal Routing Guidelines Signal Names Total Trace Length Transmission Line Type Address Group #1 Address Group #2 A[16:3]# A[31:17]# REQ[4:0]# ADSTB#[0] 5.4.5. ADSTB#[1] Nominal Impedance (Ω) Width & Spacing (mils) Min (inches) Max (inches) Strip-line 0.50 6.5 55 ± 15% 4&8 Strip-line 0.50 6.5 55 ± 15% 4&8 Strip-line 0.50 6.
Intel Celeron M Processor Front Side Bus Design Guidelines R Table 19.
Intel Celeron M Processor Front Side Bus Design Guidelines R Signal Group Addr Group 1 CPU Signal Name CPU GMCH Package GMCH Package Length Signal Name Length (mils) (mils) Signal Group CPU Signal Name DSTBN[3]# CPU GMCH Package GMCH Package Length Signal Name Length (mils) (mils) DSTBN[2]# 661 HDSTBN[2]# 538 758 H DSTBN[3]# 505 REQ4# 616 HREQ4# 276 A31# 773 HA31# 617 REQ3# 616 HREQ3# 383 A30# 773 HA30# 484 REQ2# 616 HREQ2# 247 A29# 773 HA29# 558 REQ1# 616 HREQ1# 3
Intel Celeron M Processor Front Side Bus Design Guidelines R 5.5. Asynchronous Signals The following sections describe the topologies and layout recommendations for the Asynchronous Open Drain and CMOS signals found on the platform. All Open Drain signals listed in the following sections must be pulled-up to VCCP (1.05 V). If any of these Open Drain signals are pulled-up to a voltage higher than VCCP, the reliability and power consumption of the processor may be affected.
Intel Celeron M Processor Front Side Bus Design Guidelines R 5.5.1. Topology 1A: Open Drain (OD) Signals Driven by the Processor – IERR# The Topology 1A OD signal IERR# should adhere to the following routing and layout recommendations. Table 21 lists the recommended routing requirements for the IERR# signal of the processor. The routing guidelines allow the signal to be routed as either micro-strip or strip-lines using 55 Ω ± 15% characteristic trace impedance.
Intel Celeron M Processor Front Side Bus Design Guidelines R If either FERR# or THERMTRIP# is routed to an optional system receiver rather than the ICH4-M and the interface voltage of the optional system receiver does not support a 1.05-V voltage swing, then a voltage translation circuit must be used. If the recommended voltage translation circuit described in Section 5.5.8 is used, the driver isolation resistor shown in Figure 30, Rs, should replace the series dampening resistor R1 in Topology 1B.
Intel Celeron M Processor Front Side Bus Design Guidelines R Figure 25. Routing Illustration for Topology 1C (System receiver) 3.3 V_IO_RCVR 3.3 CPU VCCP L2 L1 R2 R1 Rtt L4 Q2 L3 3904 Q1 3904 Rs Table 23. Layout Recommendations for Topology 1C L1 5.5.4. L2 L3 L4 Rs R1 R2- Rtt Transmission Line Type 0.5” – 12.0” 0” – 3.0” 0” – 3.0” 0.5” – 12.0” 330 Ω ± 5% 1.3 kΩ ± 5% 330 Ω ± 5% 56 Ω ± 5% Micro-strip 0.5” – 12.0” 0” – 3.0” 0” – 3.0” 0.5” – 12.0” 330 Ω ± 5% 1.
Intel Celeron M Processor Front Side Bus Design Guidelines R Table 24. Layout Recommendations for Topology 2A 5.5.5. L1 L2 Rtt Transmission Line Type 0.5” – 12.0” 0” – 3.0” 330 Ω ± 5% Micro-strip 0.5” – 12.0” 0” – 3.0” 330 Ω ±5% Strip-line Topology 2B: CMOS Signals Driven by ICH4-M – DPSLP# The Topology 2B CMOS DPSLP# signal, which is driven by the ICH4-M (CMOS signal input to the processor), should adhere to the routing and layout recommendations illustrated in Figure 27.
Intel Celeron M Processor Front Side Bus Design Guidelines R Figure 28. Routing Illustration for Topology 2C ICH4-M CPU L1 Table 26. Layout Recommendations for Topology 2C 5.5.7. L1 Transmission Line Type 0.5” – 12.0” Micro-strip 0.5” – 12.0” Strip-line Topology 3: CMOS Signals Driven by ICH4-M to CPU and FWH – INIT# The signal INIT# should adhere to the following routing and layout recommendations. Table 27 lists the recommended routing requirements for the INIT# signal of the ICH4-M.
Intel Celeron M Processor Front Side Bus Design Guidelines R Figure 29. Routing Illustration for Topology 3 FWH 3.3V V_IO_FWH 3.3V CPU ICH4-M R2 R1 L4 Q2 L1 L2 L3 3904 Q1 3904 Rs Table 27. Layout Recommendations for Topology 3 5.5.8. L1 + L2 L3 L4 Rs R1 R2 Transmission Line Type 0.5” – 12.0” 0” – 3.0” 0.5” – 6.0” 330 Ω ± 5% 1.3 kΩ ± 5% 330 Ω ± 5% Micro-strip 0.5” – 12.0” 0” – 3.0” 0.5” – 6.0” 330 Ω ± 5% 1.
Intel Celeron M Processor Front Side Bus Design Guidelines R Figure 30. Voltage Translation Circuit 3.3V 3.3V 1.3K ohm +/- 5% From Driver 330 ohm +/- 5% R2 Q2 To Receiver 3904 Q1 Rs 5.6. R1 330 ohm +/- 5% 3904 Processor RESET# Signal The RESET# signal is a common clock signal driven by the GMCH CPURST# pin.
Intel Celeron M Processor Front Side Bus Design Guidelines R Currently 1% tolerance resistors are recommended for Rs and Rtt. The use of 5% tolerant resistors for these resistors and whether it could provide adequate signal quality performance is under investigation. Figure 32. Processor RESET# Signal Routing Topology with ITP700FLEX Connector CPU L1 GMCH RESET# CPURESET# VCCP Rtt ITPFLEX CONNECTOR Rs L2 L3 RESET# Table 28.
Intel Celeron M Processor Front Side Bus Design Guidelines R Figure 33. Processor RESET# Signal Routing Example with ITP700FLEX Debug Port Secondary Side CPU Layer 6 GMCH Rtt GND VIA Rs CPU L1 MCH -M RESET# ITPFLEX Connector VCCP CPURESET# VCCP Rtt L2 5.7. Rs L3 ITPFLEX CONNECTOR RESET# Processor and GMCH Host Clock Signals Figure 34 illustrates processor and GMCH host clock signal routing.
Intel Celeron M Processor Front Side Bus Design Guidelines R Figure 34. Processor and GMCH Host Clock Layout Routing Example Secondary Side CPU GMCH GND VIA CPU BCLK[1:0] GMCH BCLK[1:0] Layer3 ITP Interposer BCLK[1:0] ITP BCLK[1:0] ITP FLEX FROM CK-408 5.8. Processor GTLREF Layout and Routing Recommendations There is one AGTL+ reference voltage pin on the Intel Celeron M Processor, GTLREF, which is used to set the reference voltage level for the AGTL+ signals (GTLREF).
Intel Celeron M Processor Front Side Bus Design Guidelines R Since the input buffer trip point is set by the 2/3*VCCP on GTLREF and to allow tracking of VCCP voltage fluctuations, no decoupling should be placed on the GTLREF pin. The node between R1 and R2 (GTLREF) should be connected to the GTLREF pin of the processor with Zo = 55 Ω trace shorter than 0.5 inches. Space any other switching signals away from GTLREF with a minimum separation of 25 mils.
Intel Celeron M Processor Front Side Bus Design Guidelines R Figure 36. Processor GTLREF Motherboard Layout Pin AG1 AG1 Pin R1 VCCP VCCP R2 R2 GTLREF Zo=55Ω <0.5” Banias CPU Pin E26 PRIMARY SIDE 5.9. PinG1 G1 Pin AGTL+ I/O Buffer Compensation The Intel Celeron M Processor has 4 pins, COMP[3:0], and the GMCH has 2 pins, HRCOMP[1:0], that require compensation resistors to adjust the AGTL+ I/O buffer characteristics to specific board and operating environment characteristics.
Intel Celeron M Processor Front Side Bus Design Guidelines R Figure 37. Processor COMP[2] & COMP[0] Resistive Compensation COMP[0] COMP[2] 27.4Ω +/- 1% 27.4Ω +/- 1% Figure 38. Processor COMP[3] & COMP[1] Resistive Compensation COMP[3] COMP[1] 54.9Ω +/- 1% 54.9Ω +/- 1% The recommended layout of the processor COMP[3:0] resistors is illustrated in Figure 39.
Intel Celeron M Processor Front Side Bus Design Guidelines R Figure 39. Processor COMP[3:0] Resistor Layout COMP[2] COMP[3] AA1 Y2 GND pins COMP[0] VCCP VCCP VCCP COMP[1] VCCA One GND Via VCCA=1.8 SECONDARY SIDE PRIMARY SIDE Figure 40. Processor COMP[1:0] Resistor Alternative Primary Side Layout PRIMARY SIDE VCCA=1.
Intel Celeron M Processor Front Side Bus Design Guidelines R Figure 41. COMP2 & COMP0 27.4-Ω Traces PRIMARY SIDE SECONDARY SIDE PRIMARY SIDE SECONDARY SIDE COMP0 COMP0 27.4 Ω 1% COMP0 COMP1 18-mil 18 -mil DogTrace Bone 18 - mil Trace SECONDARY SIDE COMP2 COMP3 COMP2 27.4 Ω 1% 5.10. Intel Celeron M Processor Front Side Bus Strapping and Debug Port The Intel Celeron M Processor and GMCH both have pins that require termination for proper component operation. 1. 2.
Intel Celeron M Processor Front Side Bus Design Guidelines R Table 29. ITP Signal Default Strapping When ITP Debug Port Not Used 5.11. Signal Resistor Value Connect To Resistor Placement TDI 150 Ω ± 5% VCCP Within 2.0” of the CPU TMS 39 Ω ± 5% VCCP Within 2.0” of the CPU TRST# 680 Ω ± 5% GND Within 2.0” of the CPU TCK 27 Ω ± 5% GND Within 2.
Processor Power Delivery Requirements R 6. Processor Power Delivery Requirements Please contact your Intel Field Representative for more information on the electrical requirements for the DC-to-DC Voltage Regulator for the Mobile Pentium 4 Processor-M featuring Intel® SpeedStep® technology.
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System Memory Design Guidelines (DDR-SDRAM) R 7. System Memory Design Guidelines (DDR-SDRAM) The Intel 852GM GMCH chipset Double Data Rate (DDR) SDRAM system memory interface consists of SSTL-2 compatible signals. These SSTL-2 compatible signals have been divided into several signal groups: Data, Control, Command, CPC, Clock, and Feedback signals. Table 30 summarizes the different signal grouping. Refer to the Intel® 852GM GMCH Chipset Datasheet for details on the signals listed. Table 30.
System Memory Design Guidelines (DDR-SDRAM) R 7.1. Length Matching and Length Formulas The routing guidelines presented in the following subsections define the recommended routing topologies, trace width and spacing geometries, and absolute minimum and maximum routed lengths for each signal group, which are recommended to achieve optimal SI and timing.
System Memory Design Guidelines (DDR-SDRAM) R 7.3. Topologies and Routing Guidelines The Intel 852GM GMCH chipset’s Double Data Rate (DDR) SDRAM system memory interface implements the low swing, high-speed, terminated SSTL_2 topology. This section contains information related to the recommended interconnect topologies and routing guidelines for each of the signal groups that comprise the DDR interface.
System Memory Design Guidelines (DDR-SDRAM) R 7.3.3. DDR Clock Routing Guidelines Table 33.
System Memory Design Guidelines (DDR-SDRAM) R 3. Exceptions to the trace width and spacing geometries are allowed in the breakout region in order to fan-out the interconnect pattern. Reduced spacing should be avoided as much as possible. 7.3.3.1. Clock Length Matching Requirements The GMCH chipset provides three differential clock pair for each SO-DIMM. A differential clock pair is made up of a SCK signal and its complement signal SCK#. Refer to Section 7.
System Memory Design Guidelines (DDR-SDRAM) R Figure 44. DDR Clock Trace Length Matching Diagram SO-DIMM0 Clock Reference Length X0 = _________ GMCH Package SCK0 SCK#0 SCK0 Length = X0 SCK#0 Length = X0 SCK1 Length = X0 SCK#1 Length = X0 SCK1 GMCH Die SCK#1 Length = X0 +/-25mils Note: All lengths are measured from GMCH die-pad to SO-DIMM0 connector pads.
System Memory Design Guidelines (DDR-SDRAM) R 7.3.3.3. Clock Package Length Table The package length data in the table below should be used to tune the motherboard length of each SCLK/SCLK# clock pair between the GMCH and the associated SO-DIMM socket. Intel recommends that die-pad to SO-DIMM pin length be tuned to within ± 25 mils in order to optimize timing margins on the interface. Table 34.
System Memory Design Guidelines (DDR-SDRAM) R Figure 45. Clock Signal Routing Example GMCH Clock SO-DIMM0 S0-DIMM1 7.3.3.4.1. Clock Routing Updates for “DDP Stacked” Memory Device Support Simulation results show that the current DDR layout and routing guidelines for Intel 852GM chipsetbased platforms can support “DDP stacked” SO-DIMM memory modules. 7.3.4.
System Memory Design Guidelines (DDR-SDRAM) R The data signals include SDQ[64:0], SDM[7:0], and SDQS[7:0]. • The data signals should transition from an external layer to an internal signal layer under the GMCH. • Keep to the same internal layer until transitioning back to an external layer at the series resistor. • After the series resistor, the signal should transition from the external layer to the same internal layer and route to SO-DIMM0.
System Memory Design Guidelines (DDR-SDRAM) R 7.3.4.1. Data Bus Topology Figure 46. Data Signal Routing Topology GM CH V tt Rt GM CH D ie P1 L1 SO -D IM M 0 PA D L2 L3 L4 SO -D IM M 1 PA D The data signals should be routed using a 2 to 1 trace spacing to trace width ratio for signals within the DDR group, except clocks and strobes. There should be a minimum of 20 mils of spacing to non-DDR related signals. Data signals should be routed on inner layers with minimized external trace lengths.
System Memory Design Guidelines (DDR-SDRAM) R Table 35.
System Memory Design Guidelines (DDR-SDRAM) R 7.3.4.2. SDQS to Clock Length Matching Requirements The first step in length matching is to determine the SDQS length range based on the SCK/SCK# reference length defined previously. The total length of the SDQS strobe signals, including package length, between the GMCH die-pad and the SO-DIMMs must fall within the range defined in the formulas below. See the clock Section for the definition of the clock reference length.
System Memory Design Guidelines (DDR-SDRAM) R Figure 47. SDQS to Clock Trace Length Matching Diagram SO-DIMM0 GMCH Package SDQS[7:0] SDQS Length = Y0 , where GMCH Die (X0 – 1.0") <= Y0 <= (X0 + 0.5) SCK[1:0] Clock Reference Length = X0 SCK#[1:0] Note: All lengths are measured from GMCH diepad to SO-DIMM connector pad. SO-DIMM0 GMCH Package GMCH Die SO-DIMM1 SDQS[4:0] SDQS Length = Y1 (X1-1.0" ) <= Y1 <= ( X1+0.5”) SCK[4:3] SCK#[4:3] Clock Ref.
System Memory Design Guidelines (DDR-SDRAM) R Length matching is not required from the SO-DIMM1 to the parallel termination resistors. Figure 48 on the following page depicts the length matching requirements between the SDQ, SDM, and SDQS signals within a byte lane. Byte lane mapping is defined in Table 36 below. 7.3.4.4. SDQ to SDQS Mapping Table 36 below defines the mapping between the nine byte lanes, nine mask bits, and the nine SDQS signals, as required to do the required length matching.
System Memory Design Guidelines (DDR-SDRAM) R Figure 48. SDQ/SDM to SDQS Trace Length Matching Diagram SO-DIMM0 GMCH Package SDQ[0] SDQ[1] SDQ Length (Y) = (X ±25 mils) SDQ[2] SDQ[3] GMCH Die SDQS[0] SDQS Length = X SDQ[4] SDQ[5] SDQ[6] SDQ Length (Y) = (X ±25 mils) SDQ[7] SDM[0] SDM Length (Y) = (X ±25 mils) Note: All lengths are measured from GMCH die pad to SO-DIMM connector pad. Note: Only one byte lane is shown for reference. Each byte lane is matched independently.
System Memory Design Guidelines (DDR-SDRAM) R 7.3.4.5. SDQ/SDQS Signal Package Lengths The package length data in Table 37 below should be used to tune the length of each SDQ, SDM, and SDQS motherboard trace as required to achieve the overall length matching requirements defined in the prior sections. Table 37.
System Memory Design Guidelines (DDR-SDRAM) R Signal Pin Number Pkg Length (mils) Signal Pin Number Pkg Length (mils) SDQ_27 AF14 655 SDQ_59 AF28 756 SDQ_28 AG11 599 SDQ_60 AG26 782 SDQ_29 AD12 460 SDQ_61 AF26 748 SDQ_30 AF13 536 SDQ_62 AE27 673 SDQ_31 AH13 642 SDQ_63 AD27 608 SDM_0 AE5 838 SDQS_0 AG2 925 SDM_1 AE6 693 SDQS_1 AH5 838 SDM_2 AE9 538 SDQS_2 AH8 756 SDM_3 AH12 606 SDQS_3 AE12 466 SDM_4 AD19 492 SDQS_4 AH17 678 SDM_5 AD21 470
System Memory Design Guidelines (DDR-SDRAM) R 7.3.4.6. DDR Data Routing Example Figure 49 is an example of a board routing for the Data signal group. The majority of the Data signal route is on an internal layer, both external layers can be used for parallel termination R-pack placement. Figure 49. Data Signals Group Routing Example From GMCH Data Signals 7.3.5.
System Memory Design Guidelines (DDR-SDRAM) R Table 38. Control Signal to SO-DIMM Mapping Signal Relative To SO-DIMM Pin SCS#[0] SO-DIMM0 AD23 SCS#[1] SO-DIMM0 AD26 SCS#[2] SO-DIMM1 AC22 SCS#[3] SO-DIMM1 AC25 SCKE[0] SO-DIMM0 AC7 SCKE[1] SO-DIMM0 AB7 SCKE[2] SO-DIMM1 AC9 SCKE[3] SO-DIMM1 AC10 The control signal routing should transition from an external layer to an internal signal layer under the GMCH.
System Memory Design Guidelines (DDR-SDRAM) R 7.3.5.2. Control Signal Routing Guidelines Table 39. Control Signal Routing Guidelines Parameter Routing Guidelines Signal Group SCKE[3:0], SCS#[3:0] Motherboard Topology Point-to-Point with Parallel Termination Reference Plane Ground Referenced Characteristic Trace Impedance (Zo) 55 Ω ±15% Inner layers: 4 mils Nominal Trace Width Outer layers: 5 mils Minimum Spacing to Trace Width Ratio 2 to 1 (e.g.
System Memory Design Guidelines (DDR-SDRAM) R 7.3.5.3. Control to Clock Length Matching Requirements The length of the control signals, between the GMCH die pad and the SO-DIMM must fall within the range defined below, with respect to the associated clock reference length. Refer to Figure 50 for a definition of the various trace segments that make up this path. The length of trace from the SO-DIMM to the termination resistor need not be length matched.
System Memory Design Guidelines (DDR-SDRAM) R Figure 51. Control Signal to Clock Trace Length Matching Diagram SO-DIMM0 GMCH Package SCS#[1:0] SCKE[1:0] CNTRL Length = Y0 GMCH Die (X0 – 1.0" ) <= Y0 <= (X0 + 0.5") SCK[1:0] SCK#[1:0] Clock Ref. Length = X0 Note: All lengths are measured from GMCH die pad to SO-DIMM connector pads. SO-DIMM0 GMCH Package SCS#[3:2] SCKE[3:2] GMCH Die SO-DIMM1 CNTRL Length = Y1 (X1 – 1.0") <= Y1 <= (X1+ 0.5") SCK[4:3] SCK#[4:3] Clock Ref.
System Memory Design Guidelines (DDR-SDRAM) R 7.3.5.4. DDR Control Routing Example Figure 52 is an example of a board routing for the Control signal group. Figure 52.
System Memory Design Guidelines (DDR-SDRAM) R 7.3.5.5. Control Group Package Length Table The package length data in Table 40 below should be used to match the overall length of each command signal to its associated clock reference length. Note that due to the relatively small variance in package length and adequate timing margins it is acceptable to use a fixed 500-mil nominal package length for all control signals, thereby reducing the complexity of the motherboard length calculations. Table 40.
System Memory Design Guidelines (DDR-SDRAM) R Resistor packs are acceptable for the series and parallel command termination resistors but command signals can not be placed within the same R-packs as data, strobe, or control signals. Figure 53 and Table 41 below depict the recommended topology and layout routing guidelines for the DDR-SDRAM command signals routing to SO-DIMM0 and SO-DIMM1. Figure 53.
System Memory Design Guidelines (DDR-SDRAM) R 7.3.6.2. Command Topology 1 Routing Guidelines Table 41. Command Topology 1 Routing Guidelines Parameter Routing Guidelines Signal Group SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE# Motherboard Topology Daisy Chain with Parallel Termination Reference Plane Ground Referenced Characteristic Trace Impedance (Zo) 55 Ω ± 15% Nominal Trace Width Inner layers: 4 mils Outer layers: 5 mils Minimum Spacing to Trace Width Ratio 2 to 1 (e.g.
System Memory Design Guidelines (DDR-SDRAM) R 7.3.6.3. Command Topology 1 Length Matching Requirements The routing length of the command signals, between the GMCH die pad and the SO-DIMM must be within the range defined below, with respect to the associated clock reference length. Refer to Figure 53 for a definition of the various motherboard trace segments. The length of trace from the SO-DIMM to the termination resistor need not be length matched.
System Memory Design Guidelines (DDR-SDRAM) R Figure 54. Topology 1 Command Signal to Clock Trace Length Matching Diagram SO-DIMM0 GMCH Package SMAA[12:6,3,0] SBA[1:0], RAS#, CAS#, WE# CMD Length = Y0 GMCH Die (X0 – 1.0") <= Y0 <= (X0 + 2.0") SCK[2:0] Clock Reference Length = X0 SCK#[2:0] Note: All lengths are measured from GMCH die pad to SO-DIMM connector pad. SO-DIMM0 GMCH Package SMAA[12:6,3,0] SBA[1:0], RAS#, CAS#, WE# GMCH Die SO-DIMM1 CMD Length = Y1 (X1 –1.0") <= Y1 <= (X1 +2.
System Memory Design Guidelines (DDR-SDRAM) R 7.3.6.4. Command Topology 2 The command signal routing should transition from an external layer to an internal signal layer under the GMCH. Keep to the same internal layer until transitioning back to an external layer at the series resistor Rs. At this point there is a T in the topology. One leg of the T will route through Rs and either transition back to the same internal layer or stay external and landing on the appropriate connector pad of SO-DIMM0.
System Memory Design Guidelines (DDR-SDRAM) R 7.3.6.5. Command Topology 2 Routing Guidelines Table 42. Command Topology 2 Routing Guidelines Parameter Routing Guidelines Signal Group SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE# Motherboard Topology Branched T with Parallel Termination Reference Plane Ground Referenced Characteristic Trace Impedance (Zo) 55 Ω ± 15% Nominal Trace Width Inner layers: 4 mils Outer layers: 5 mils Minimum Spacing to Trace Width Ratio 2 to 1 (e.g.
System Memory Design Guidelines (DDR-SDRAM) R 7.3.6.6. Command Topology 2 Length Matching Requirements The routed length of the command signals, between the GMCH package ball and the SO-DIMM must be within the range defined below, with respect to the associated clock reference length. Refer to Figure 55 for a definition of the various motherboard trace segments. The length of trace from the SO-DIMM to the termination resistor need not be length matched.
System Memory Design Guidelines (DDR-SDRAM) R Figure 56. Topology 2 Command Signal to Clock Trace Length Matching Diagram SO-DIMM0 GMCH Package SMAA[12:6,3,0] SBA[1:0], SRAS#, SCAS#, SWE# CMD Length = Y0 GMCH Die (X0 – 1.0") <= Y0 <= (X0 + 2.0") SCK[2:0] Clock Reference Length = X0 SCK#[2:0] Note: All lengths are measured from MCH die pad to SO-DIMM connector pad. SO-DIMM0 GMCH Package SO-DIMM1 SMAA[12:6,3,0] SBA[1:0], SRAS#, SCAS#, SWE# CMD Length = Y1 GMCH Die (X1 –1.0") <= Y1 <= (X1 +2.
System Memory Design Guidelines (DDR-SDRAM) R 7.3.6.7. Command Topology 2 Routing Example Figure 57 is an example of a board routing for the Command signal group. Figure 57.
System Memory Design Guidelines (DDR-SDRAM) R 7.3.6.8. Command Topology 3 This topology is recommended when the SO-DIMMS are too close together for the series resistor to be placed between connectors. In this topology the series resistors are placed behind the second SODIMM. External trace lengths should be minimized. It is suggested that the parallel termination be placed on both sides of the board to simplify routing and minimize trace lengths.
System Memory Design Guidelines (DDR-SDRAM) R 7.3.6.9. Command Topology 3 Routing Guidelines Table 43. Command Topology 3 Routing Guidelines Parameter Routing Guidelines Signal Group SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE# Motherboard Topology Branched T with Parallel Termination Reference Plane Ground Referenced Characteristic Trace Impedance (Zo) 55Ω ± 15% Nominal Trace Width Inner layers: 4 mils Outer layers: 5 mils Minimum Spacing to Trace Width Ratio 2 to 1 (e.g.
System Memory Design Guidelines (DDR-SDRAM) R 7.3.6.10. Command Topology 3 Length Matching Requirements The routed length of the command signals, between the GMCH package ball and the SO-DIMM must be within the range defined below, with respect to the associated clock reference length. Refer to Figure 55 for a definition of the various motherboard trace segments. The length of trace from the SO-DIMM to the termination resistor need not be length matched.
System Memory Design Guidelines (DDR-SDRAM) R Figure 59. Topology 3 Command Signal to Clock Trace Length Matching Diagram SO-DIMM0 GMCH Package SMAA[12:6,3,0] SBA[1:0], RAS#, CAS#, WE# CMD Length = Y0 GMCH (X0 – 1.0") <= Y0 <= (X0 + 2.0") Die SCK[2:0] Clock Reference Length = X0 SCK#[2:0] Note: All lengths are measured from GMCH die pad to SO-DIMM connector pad. SO-DIMM0 GMCH Package SMAA[12:6,3,0] SBA[1:0], RAS#, CAS#, WE# GMCH SO-DIMM1 to termination CMD Length = Y1 (X1 –1.
System Memory Design Guidelines (DDR-SDRAM) R 7.3.6.11. Command Group Package Length Table The package length data in Table 44 below should be used to match the overall length of each command signal to its associated clock reference length. Table 44.
System Memory Design Guidelines (DDR-SDRAM) R 7.3.7. CPC Signals – SMA[5,4,2,1], SMAB[5,4,2,1] The Intel 852GM GMCH chipset control signals, SCKE[3:0] and SCS#[3:0], are common clocked signals. They are “clocked” into the DDR SDRAM devices using clock signals SCK/SCK#[5:0]. The GMCH drives the CPC and clock signals together, with the clocks crossing in the valid control window. The GMCH provides one set of CPC signals per SO-DIMM slot. Refer to Table 38 for the CKE and CS# signal to SO-DIMM mapping.
System Memory Design Guidelines (DDR-SDRAM) R 7.3.7.1. CPC Signal Topology Figure 60. Command per Clock Signal Routing Topology Vtt GMCH Rt GMCH Pin P1 L2 L1 w SO-DIMM0,1 PIN The CPC signals should be routed using 2 to 1 trace space to width ratio for signals within the DDR group, except clocks and strobes. There should be a minimum of 20-mils of spacing to non-DDR related signals. CPC signals should be routed on inner layers with minimized external trace lengths. 7.3.7.2.
System Memory Design Guidelines (DDR-SDRAM) R 3. It is possible to route using 2 vias if one via is shared that connects to the SO-DIMM pad and parallel termination resistor. 4. The overall maximum and minimum length to the SO-DIMM must comply with clock length matching requirements. 7.3.7.3.
System Memory Design Guidelines (DDR-SDRAM) R Figure 61. CPC Signals to Clock Length Matching Diagram SO-DIMM0 GMCH Package SMA[5,4,2,1] CPC Length = Y0 GMCH Die (X0 – 1.0") <= Y0 <= (X0 + 0.5") SCK[1:0] SCK#[1:0] Clock Reference Length = X0 Note: All lengths are measured from GMCH die pad to SO-DIMM connector pad. SO-DIMM0 SO-DIMM1 GMCH Package SMAB[5,4,2,1] GMCH Die CPC Length = Y1 (X1–1.0") <= Y1 <= (X1+0.
System Memory Design Guidelines (DDR-SDRAM) R 7.3.7.4. CPC Group Package Length Table The package length data in the table below should be used to match the overall length of each CPC signal to its associated clock reference length. Table 47. CPC Group Package Lengths 7.3.8.
System Memory Design Guidelines (DDR-SDRAM) R 7.7. External Thermal Sensor Based Throttling (ETS#) The Intel 852GM chipset GMCH’s ETS# input pin is an active low input that can be used with an external thermal sensor to monitor the temperature of the DDR SO-DIMMs for a possible thermal condition. Assertion of ETS# will result in the limiting of DRAM bandwidth on the DDR memory interface to reduce the temperature in the vicinity of the system memory.
System Memory Design Guidelines (DDR-SDRAM) R 7.7.3. Thermal Sensor Placement Guidelines The many factors that can affect the accuracy of ambient temperature measurements by thermal sensors make the placement of them a very critical and especially challenging task. Ideally, one thermal sensor should be placed near each SO-DIMM in a system. The thermal sensor should be located in an area where the effects of airflow and effects of conduction from adjacent components are minimized.
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Integrated Graphics Display Port R 8. Integrated Graphics Display Port The GMCH contains four display ports: an analog CRT port, a dedicated LVDS port, and one 12-bit Digital Video Out (DVO) port. Section 8.1 will discuss the CRT and RAMDAC routing requirements. Section 8.2 will discuss the dedicated LVDS port. Section 8.3 will discuss DVOC design guideline. Section 8.4 provides recommendations for the GPIO signal group. 8.1. Analog RGB/CRT Guidelines 8.1.1.
Integrated Graphics Display Port R 8.1.3. RAMDAC Board Design Guidelines In order for the RAMDAC to successfully run at speeds up to 350 MHz, care should be taken when routing the analog RAMDAC signals. Intel recommends that each analog R, G, B signal be routed single-endedly. The analog RGB signals should be routed with an impedance of 37.5 Ω. Intel recommends that these routes be routed on an inner routing layer and that it be shielded with VSS planes, if possible.
Integrated Graphics Display Port R 8.1.4. RAMDAC Routing Guidelines Figure 63. GMCH RAMDAC Routing Guidelines with Docking Connector 1.5V Place C1 and C2 as C2 close to package as possible C1 VCCDACA1 VCCDACA2 Motherboard 1.5V 37.5 Ω impedance R1 D Switch RED Red DAC Channel D 75 Ω Routes FB C C FB C1 R1 C C RED# 1.5V 37.5 Ω impedance D R1 Switch GREEN Green DAC Channel FB D C Pin 1 Red 75 Ω Routes Pin 2 Green C Pin 3 Blue FB C1 R1 C VGA Connector C GREEN# 1.5V 37.
Integrated Graphics Display Port R The RAMDAC channel (red, green, blue) outputs are routed as single-ended (with 37.5 ohm trace impedance) shielded current output routes that are terminated prior to connecting to the video PI-filter and VGA/docking connector. Figure 64. RAMDAC Routing w/ Resistor and Analog Switch Layout Example for Docking Connector Complement Output DAC Output Intel 852GM (e.g. BLUE) (e.g. BLUE#) Via to ground plane 20 mil Space between channels 20 mil Space between channels 37.
Integrated Graphics Display Port R Table 48. Recommended GMCH RAMDAC Components Recommended DAC Board Components Component Value Tolerance Power Type R1 75.0 Ω 1% 1/16 W SMT, Metal Film Rset 128.0 Ω 1% 1/16 W SMT, Metal Film C1 0.1 µF 20% ----- SMT, Ceramic C2 0.01 µF 20% ----- SMT, Ceramic C 3.
Integrated Graphics Display Port R filtering and/or separate voltage rail may be needed to do so. On the Intel CRB, there is a place holder for a LC filter in case there is noise present in the VCCA power rail. Video DAC Power Supply DC Specification: 1.50 V ± 5% Video DAC Power Supply AC Specification: +/- 0.3% from 0.10 Hz to 10 MHz +/- 0.95% from 10 MHz to max pixel clock frequency Absolute minimum voltage at the VCCA package ball = 1.
Integrated Graphics Display Port R The following differential signal groups comprise the LVDS Interface. The topology rules for each group are defined in subsequent sections. Table 49. Signal Group and Signal Pair Names Channel Signal Group Signal Pair Names Channel A Clocks ICLKAM, ICLKAP Data Bus IYAM[3:0], IYAP[3:0] Channel B Clocks ICLKBM, ICLKBP Data Bus IYBM[3:0], IYBP[3:0] 8.2.1.
Integrated Graphics Display Port R 8.2.1.1. Package Length Compensation As mentioned in Section 8.2.1, all length matching is done from GMCH die-pad to LVDS connector pin. The reason for this is to compensate for the package length variation across each signal group in order to minimize timing variance. The GMCH does not equalize package lengths internally as some previous GMCH components have, and therefore, the GMCH requires a length matching process.
Integrated Graphics Display Port R The traces associated with the LVDS Transmitter timing domain signals are differential traces terminated across 100 ohms ± 15 % and should be routed as: • Strip-line only. • Isolate all other signals from the LVDS signals to prevent coupling from other sources onto the LVDS lines. • Use controlled impedance traces that match the differential impedance of your transmission medium (i.e.
Integrated Graphics Display Port R Signal Group 8.3. GMCH Signal Name Package Trace Length (mils) IYBP1 524.7 IYBM1 516.6 IYBP2 623.3 IYBM2 604.2 IYBP3 441.8 IYBM3 441.7 Board Length Total Trace Length Digital Video Out Port The GMCH DVO port interface supports a wide variety of third party DVO compliant devices (e.g. TV encoder, TMDS transmitter or integrated TV encoder and TMDS transmitter The Intel 852GM has a single dedicated Digital Video Out Port (DVOC). Intel’s DVO port is a 1.
Integrated Graphics Display Port R Voltage References, PLL Power Signals • DVORCOMP • GVREF 8.3.2. 8.3.2.1. DVO Port Interface Routing Guidelines Length Mismatch Requirements The routing guidelines presented in the following subsections define the recommended routing topologies, trace width and spacing geometries, and absolute minimum and maximum routed lengths for each signal group, which are recommended to achieve optimal SI and timing.
Integrated Graphics Display Port R 8.3.2.3. DVO Routing Guidelines Table 54 provides the DVOC routing guideline summary. Table 54. DVOC Routing Guideline Summary Parameter Definition Signal Group DVCBD [11:0] Motherboard Topology Point to point Reference Plane Ground Referenced Characteristic Trace Impedance (Zo) 55 Ω ± 15% Nominal Trace Width Inner layers: 4 mils Minimum Spacing to Trace Width Ratio 2 to 1 (e.g.
Integrated Graphics Display Port R Table 55. DVOC Interface Package Lengths Signal 8.3.2.4.
Integrated Graphics Display Port R Table 56. GMBUS Pair Mapping and Options Pair # 0 Signal Name DDCADATA Buffer Type LCLKCTRLA DDC for Analog monitor (CRT) connection. This cannot be shared with other DDC or I2C pairs due to legacy monitor issues. 3.3 V For control of SSC clock generator devices down on motherboard. If SSC is not supported then can be used for DVOC GMBUS. 3.3 V DDC for Digital Display connection via the integrated LVDS display port for support for EDID panel.
Integrated Graphics Display Port R • DVODETECT: Leave unconnected (NC) when using the DOVC port. • AGPBUSY#: Connect directly to ICH4-M. A 10-k, pullup resistor is required. • DVORCOMP is used to calibrate the DVO buffers. It should be connected to ground via a 40.2Ω, 1% resistor using a routing guideline of 10-mil trace and 20-mil spacing. • DPMS: connects to 1.5 V-version of the ICH4-M’s SUSCLK or a clock that runs during S1. • GVREF: Reference voltage for the DVOC input buffers.
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Hub Interface R 9. Hub Interface The GMCH and ICH4-M pin-map assignments have been optimized to simplify the hub interface routing between these devices. It is recommended that the hub interface signals be routed directly from the GMCH to the ICH4-M with all signals referenced to VSS. Layer transitions should be kept to a minimum. If a layer change is required, use only two vias per net and keep all data signals and associated strobe signals on the same layer.
Hub Interface R 9.2. Hub Interface Data HL[10:0] and Strobe Signals The Hub interface HL[10:0] data signals should be routed on the same layer as Hub interface strobe signals. 9.2.1. HL[10:0] and Strobe Signals Internal Layer Routing Traces should be routed 4 mils wide with 8 mils trace spacing (4 on 8) and 20 mils spacing from other signals. In order to break out of the GMCH and ICH4-M packages, the HL[10:0] signals can be routed 4 on 7.
Hub Interface R Table 59. Hub Interface Package Lengths for ICH4-M Signal Pin Number Package Length (mils) HUB_PD0 L19 551 HUB_PD1 L20 562 HUB_PD2 M19 552 HUB_PD3 M21 567 HUB_PD4 P19 599 HUB_PD5 R19 627 HUB_PD6 T20 623 HUB_PD7 R20 593 HUB_PD8 P23 668 HUB_PD9 L22 559 HUB_PD10 N22 682 HUB_PD11 K21 560 HUB_CLK T21 605 HUB_PSTRB P21 541 HUB_PSTRB# N20 565 Table 60.
Hub Interface R 9.2.2. Terminating HL[11] The HL[11] signal exists on the ICH4-M but not the GMCH and is not used on the platform. HL[11] must be pulled down to ground via a 56-Ω resistor. 9.3. Hub VREF/VSWING Generation/Distribution The Hub interface reference voltage (VREF) is used on both the GMCH (HLVREF) and the ICH4-M (HIREF).
Hub Interface R Figure 68. Single VREF/VSWING Voltage Generation Circuit for Hub Interface VCCHI R1 PSWING C1 GMCH HLVREF C2 C5 R2 C4 C6 C3 HI_VSWING ICH4-M HIREF R3 The resistor values, R1, R2, and R3 must be rated at 1% tolerance. See Table 62 for recommended resistor value. The selected resistor values ensure that the reference voltage tolerance is maintained over the input leakage specification. Two 0.1-µF capacitors (C1 and C3) should be placed close to the divider. In addition, the 0.
Hub Interface R Figure 69. ICH4-M Locally Generated Reference Voltage Divider Circuit VCCHI R1 C2 C1 R2 C3 9.3.2.2. HI_VSWING ICH4 C4 HIREF R3 GMCH Single Generated Voltage Reference Divider Circuit This option allows the GMCH to use one voltage divider circuit to generate both HLVREF and HLPSWING voltage references. The reference voltage for both HLVREF and HLPSWING must meet the voltage specification in Table 61. The resistor values R1, R2, and R3 must be rated at 1% tolerance (see Table 62).
Hub Interface R Figure 71. Individual HIVREF and HI_VSWING Voltage Reference Divider Circuits for ICH4-M VCCHI R4 R6 HI_VSWING HIVREF ICH4-M R5 C2 C4 R7 C3 C1 Table 63. Recommended Resistor Values for HIVREF and HI_VSWING Divider Circuits for ICH4-M Signal 9.3.3.2. Recommended Resistor Values HIVREF (350 mV) R4 = 487 Ω ± 1% HI_VSWING (800 mV) R6 = 130 Ω ± 1% VCCHI Capacitor value VCCHI=1.5 V R5 = 150 Ω ± 1%, C3 = 0.1 µF (near divider) C2 = 0.01 µF (near component) VCCHI=1.
Hub Interface R Table 64. Recommended Resistor Values for HLVREF and PSWING Divider Circuits for GMCH Signal Name 9.4. Recommended Resistor Values HLVREF (350 mV) R4 = 243 Ω ± 1% PSWING (800 mV) R6 = 49.9 Ω ± 1% VCCHI VCCHI=1.2 V R5 = 100 Ω ± 1% R7 = 100 Ω ± 1% Capacitor C3 = 0.1 µF (near divider) C6 = 0.01 µF (near component) VCCHI=1.2 V C1 = 0.1 µF (near divider) C5 = 0.01 µF (near component) Hub Interface Decoupling Guidelines To improve I/O power delivery, use two 0.
I/O Subsystem R 10. I/O Subsystem 10.1. IDE Interface This section contains guidelines for connecting and routing the ICH4-M IDE interface. The ICH4-M has two independent IDE channels. The ICH4-M has integrated the series resistors that have been typically required on the IDE data signals (PDD[15:0] and SDD[15:0]) running to the two ATA connectors.
I/O Subsystem R 10.1.2. Primary IDE Connector Requirements Figure 73. Connection Requirements for Primary IDE Connector 22 to 47 Ω † PCIRST# PDD[15:0] PDA[2:0] PDCS[3,1]# Primary IDE PDIOR# PDIOW# ICH4-M PDDREQ PDDACK# 3.3 V 3.3 V 4.7 k 8.2~10 k PIORDY (PRDSTB / PWDMARDY#) IRQ[14] PDIAG# / CBLID# GPIOx CSEL 10 k † Due to ringing, PCIRST# must be buffered • 22 Ω - 47 Ω series resistors are required on RESET#.
I/O Subsystem R 10.1.3. Secondary IDE Connector Requirements Figure 74. Connection Requirements for Secondary IDE Connector 22 – 47 Ω PCIRST# † SDD[15:0] SDA[2:0] Secondary ID SDCS[3,1]# SDIOR# SDIOW# ICH4-M SDDREQ SDDACK# 3.3 V 3.3 V 4.7 k 8.2~10 k SIORDY (SRDSTB / SWDMARDY# ) IRQ[15] SDIAG# / CBLID# GPIOy CSEL 10 k † Due to ringing, PCIRST# must be buffered • 22 Ω - 47 Ω series resistors are required on RESET#.
I/O Subsystem R additional control signal) driving its reset pin and a power supply that is isolated from the rest of the IDE interface. To isolate the power supplied to the IDE drive bay, a second additional control signal is needed to control the enabling/disabling of a FET that supplies a separate plane flood powering the IDE drive and its interface. Although actual hardware implementations may vary, the isolated reset signal and power plane are strict requirements.
I/O Subsystem R 10.1.4.2. S5/G3 to S0 Power-Up Procedures for IDE Swap Bay The procedures listed below summarize the steps that must be followed during power-up of an IDE sway bay drive: 1. ICH4-M powers up, IDE interface is tri-stated, disk drive is not powered up. IDE drive is recognized as being on a separate power plane and its reset is different from the ICH4-M. 2. BIOS powers on the IDE drive. e.g. GPIO is used to switch on a FET on the board. 3.
I/O Subsystem R 10.2. PCI The ICH4-M provides a PCI Bus interface that is compliant with the PCI Local Bus Specification Revision 2.2. The implementation is optimized for high performance data streaming when the ICH4-M is acting as either the target or the initiator in the PCI bus. The ICH4-M supports six PCI Bus masters (excluding the ICH4-M), by providing six REQ#/GNT# pairs. In addition, the ICH4-M supports two PC/PCI REQ#/GNT# pairs, one of which is multiplexed with a PCI REQ#/GNT# pair. Figure 75.
I/O Subsystem R Figure 76. ICH4-M AC’97 – Codec Connection AC / MC / AMC RESET# SDATA_OUT SYNC ICH4-M BIT_CLK SDATA_IN0 SDATA_IN1 Primary Codec SDATA_IN2 AC / MC / AMC Secondary Codec AC / MC / AMC Tertiary Codec Note: If a modem codec is configured as the primary AC-link Codec, there should not be any Audio Codecs residing on the AC-link. The primary codec may be connected to AC_SDIN0 as documented in the Intel® 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)I/O Controller Datasheet.
I/O Subsystem R Figure 77. ICH4-M AC’97 – AC_BIT_CLK Topology ICH4-M AC_BIT_CLK L1 R1 L3 L3 R2 L4 L2 C O N N Primary Codec Table 65. AC’97 AC_BIT_CLK Routing Summary AC’97 Routing Requirements Maximum Trace Length (inches) Series Termination Resistance AC_BIT_CLK Signal Length Matching 5 on 5 L1 = (1 to 8) – L3 R1 = 33 Ω - 47 Ω N/A L2 = 0.1 to 6 R2 = Option 0 Ω resistor for debugging purposes L3 = 0.1 to 0.4 L4 = (1 to 6) – L3 NOTES: 1.
I/O Subsystem R Table 66. AC’97 AC_SDOUT/AC_SYNC Routing Summary AC’97 Routing Requirements 5 on 5 Maximum Trace Length (inches) Series Termination Resistance L1 = (1 to 6) – L3 R1 = 33 Ω - 47 Ω L2 = 1 to 8 R2 = R1 if the connector card that will be used with the platform does not have a series termination on the card. Otherwise R2 = 0 Ω L3 = 0.1 to 0.4 L4 = (0.1 to 6) – L3 AC_SDOUT/AC_SYNC Signal Length Matching N/A NOTES: 1.
I/O Subsystem R 10.3.1. AC’97 Routing To ensure the maximum performance of the codec, proper component placement and routing techniques are required. These techniques include properly isolating the codec, associated audio circuitry, analog power supplies, and analog ground planes, from the rest of the motherboard. This includes plane splits and proper routing of signals not associated with the audio Section. Contact your vendor for devicespecific recommendations.
I/O Subsystem R 10.3.2. Motherboard Implementation The following design considerations are provided for the implementation of an ICH4-M platform using AC’97. These design guidelines have been developed to ensure maximum flexibility for board designers, while reducing the risk of board-related issues. These recommendations are not the only implementation or a complete checklist, but they are based on the ICH4-M platform.
I/O Subsystem R Figure 80. Example Speaker Circuit VCC3_3 R Value is Implementation Specific ICH4-M Integrated Pull-down SPKR 9 kΩ - 50 kΩ Stuff Jumper to Disable Timeout Feature (No Reboot) Effective Impedance Due to Speaker and Codec Circuit Reff 10.4. USB 2.0 Guidelines and Recommendations 10.4.1. Layout Guidelines 10.4.1.1. General Routing and Placement Use the following general routing and placement guidelines when laying out a new design.
I/O Subsystem R traces as much as practical. It is preferable to change layers to avoid crossing a plane split. Refer to Section 10.4.2. 8. Separate signal traces into similar categories and route similar signal traces together (such as routing differential pairs together). 9. Keep USB 2.0 USB signals clear of the core logic set. High current transients are produced during internal state transitions and can be very difficult to filter out. 10.
I/O Subsystem R Figure 82. USBRBIAS Connection ICH4-M USBRBIAS 22.6Ω+/- 1% USBRBIAS# Table 69. USBRBIAS/USBRBIAS# Routing Summary 10.4.1.4. USBRBIAS/ USBRBIAS# Routing Requirements Maximum Trace Length Signal Length Matching Signal Referencing 5 on 5 500 mils N/A N/A USB 2.0 Termination A common-mode choke should be used to terminate the USB 2.0 bus. Place the common-mode choke as close as possible to the connector pins. See Section 10.4.4 for details. 10.4.1.5. USB 2.
I/O Subsystem R 10.4.2.1. VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch) Use the following guidelines for the VCC plane. 1. Traces should not cross anti-etch, for it greatly increases the return path for those signal traces. This applies to USB 2.0 signals, high-speed clocks, and signal traces as well as slower signal traces that might be coupling to them. USB signaling is not purely differential in all speeds (i.e. the Full-speed Single Ended Zero is common mode). 2. Avoid routing of USB 2.
I/O Subsystem R Figure 83. Good Downstream Power Connection 5V 5V Thermister 5V Switc 100-150uF Vc c 1 470p Gnd Vc c Port1 4 1 470p Gnd 10.4.4. Port2 4 EMI Considerations The following guidelines apply to the selection and placement of common-mode chokes and ESD protection devices. 10.4.4.1. Common Mode Chokes Testing has shown that common-mode chokes can provide required noise attenuation.
I/O Subsystem R Finding a common mode choke that meets the designer’s needs is a two-step process. A part must be chosen with the impedance value that provides the required noise attenuation. This is a function of the electrical and mechanical characteristics of the part chosen and the frequency and strength of the noise present on the USB traces that you are trying to suppress. Once you have a part that gives passing EMI results, the second step is to test the effect this part has on signal quality.
I/O Subsystem R 10.5.1. IOAPIC Disabling Options 10.5.1.1. Recommended Implementation Intel recommends that IOAPIC be disabled in software while the connections to the board are as shown in Figure 85. Software can be used to turn off PICCLK from clock generator. To disable IOAPIC in BIOS: • ICH4-M: D31:F0; Offset: D1; bit 7:8 • Mobile Pentium 4 Processor-M Processor: MSR 1Bh bit 11 Figure 85. Minimum IOAPIC Disable Topology 33 Ω PCIF0 CK-408 10 kΩ APICD0 APICD1 APICLK ICH4-M 10.6. SMBus 2.
I/O Subsystem R Figure 86. SMBUS 2.0/SMLink Protocol SPD Data Host Controller and Slave Interface SMBus Temperature on Thermal Sensor Network Interface Card on PCI Bus SMBCLK Microcontroller SMBDATA Intel® ICH4 SMLink SMLink0 SMLink1 Wire OR (optional) Motherboard LAN Controller SMbus-SMlink_IF Note: Intel does not support external access of the ICH4-M’s Integrated LAN Controller via the SMLink interface.
I/O Subsystem R 10.6.1.2. General Design Issues and Notes Regardless of the architecture used, there are some general considerations. 1. The pull-up resistor size for the SMBus data and clock signals is dependent on the bus load (this includes all device leakage currents). Generally the SMBus device that can sink the least amount of current is the limiting agent on how small the resistor can be.
I/O Subsystem R Table 71.
I/O Subsystem R Figure 88. Voltage Translation Circuit for 3.3-V Receivers 3.3V 3.3V 1.3K ohm +/- 5% From Driver 330 ohm +/- 5% R2 Q2 To Receiver 3904 Q1 Rs 10.7.2. R1 330 ohm +/- 5% 3904 In Circuit FWH Programming All cycles destined for the FWH will appear on PCI. The ICH4-M hub interface to PCI Bridge will put all CPU boot cycles out on PCI (before sending them out on the FWH interface).
I/O Subsystem R 10.7.4. FWH VPP Design Guidelines The VPP pin on the FWH is used for programming the flash cells. The FWH supports VPP of 3.3 V or 12 V. If PP is 12 V, the flash cells will program about 50% faster than at 3.3 V. However, the FWH only supports 12 V VPP for 80 hours (3.3 V on Vpp does not affect the life of the device). The 12 V VPP would be useful in a programmer environment, which is typically an event that occurs very infrequently (much less than 80 hours). The VPP pin MUST be tied to 3.
I/O Subsystem R For further information on the RTC, please consult Application Note AP-728 ICH Family Real Time Clock (RTC) Accuracy and Considerations Under Test Conditions. This application note is valid for the ICH4-M. Even if the ICH4-M internal RTC is not used, it is still necessary to supply a clock input to RTCX1 of the ICH4-M because other signals are gated off that clock in suspend modes. However, in this case, the frequency accuracy (32.
I/O Subsystem R 5. VBIAS: RTC BIAS Voltage – This ball is used to provide a reference voltage and this DC voltage sets a current, which is mirrored throughout the oscillator and buffer circuitry. 6. VSS: Ground Table 73. RTC Routing Summary RTC Routing Requirements Maximum Trace Length To Crystal Signal Length Matching R1, R2, C1, and C2 tolerances Signal Referencing 5 mil trace width (results in ~2 pF per inch) 1 inch NA R1 = R2 = 10 MΩ ± 5% Ground C1 = C2 = (NPO class) See Section 10.8.
I/O Subsystem R Example 1: According to a required 12-pF load capacitance of a typical crystal that is used with the ICH4-M, the calculated values of C1 = C2 is 10 pF at room temperature (25°C) to yield a 32.768-kHz oscillation. At 0°C the frequency stability of crystal gives – 23 ppm (assumed that the circuit has 0 ppm at 25°C). This makes the RTC circuit oscillate at 32.767246 kHz instead of 32.768 kHz. If the values of C1, C2 are chosen to be 6.
I/O Subsystem R Figure 93. Diode Circuit to Connect RTC External Battery VCCSUS3_3 VccRTC 1.0uF 1K A standby power supply should be used in a mobile system to provide continuous power to the RTC when available, which will significantly increase the RTC battery life and thereby the RTC accuracy. 10.8.5. RTC External RTCRST# Circuit Figure 94. RTCRST# External Circuit for the ICH4-M RTC VCCSUS3_3 DIODE/ BATTERY CIRCUIT VccRTC 1.0 µF 1k 180 k RTCRST # 0.
I/O Subsystem R The ICH4-M RTC requires some additional external circuitry. The RTCRST# signal is used to reset the RTC well. The external capacitor and the external resistor between RTCRST# and the RTC battery (VBAT) were selected to create an RC time delay, such that RTCRST# will go high some time after the battery voltage is valid. The RC time delay should be in the range of 18 ms - 25 ms. Any resistor and capacitor combination that yields a time constant is acceptable.
I/O Subsystem R 10.9. Internal LAN Layout Guidelines The ICH4-M provides several options for LAN capability. The platform supports several components depending upon the target market. Available LAN components include the Intel® 82562ET, and Intel® 82562EM Platform LAN Connect components. Table 74.
I/O Subsystem R 10.9.1. ICH4-M – LAN Connect Interface Guidelines This Section contains guidelines on how to implement a Platform LAN Connect device on a system motherboard. It should not be treated as a specification and the system designer must ensure through simulations or other techniques that the system meets the specified timings. Special care must be given to matching the LAN_CLK traces to those of the other signals, as shown below.
I/O Subsystem R Table 76. LAN LOM Routing Summary 10.9.1.2. LAN Routing Requirements Maximum Trace Length Signal Referencing LAN Signal Length Matching 5 on 10 4.5 to 12 inches Ground Data signals must be equal to or no more than 0.5 inches (500 mils) shorter than the LAN clock trace. Signal Routing and Layout Platform LAN Connect Interface signals must be carefully routed on the motherboard to meet the timing and signal quality requirements of this interface specification.
I/O Subsystem R 10.9.1.5. Line Termination Line termination mechanisms are not specified for the LAN Connect Interface. Slew rate controlled output buffers achieve acceptable signal integrity by controlling signal reflection, over/undershoot, and ringback. A 0-Ω to 33-Ω series resistor can be installed at the driver side of the interface should the developer have concerns about over/undershoot.
I/O Subsystem R For a noise free and stable operation, place the crystal and associated discrete components as close as possible to the Intel 82562ET/EM, keeping the trace length as short as possible and do not route any noisy signals in this area. 10.9.2.3.
I/O Subsystem R Distance Priority Guideline A 1 < 1 inch B 2 < 1 inch 10.9.2.4.1. Distance from Magnetics Module to RJ-45 (Distance A) The distance A in Figure 99 above should be given the highest priority in board layout. The distance between the magnetics module and the RJ-45 connector should be kept to less than one inch of separation. The following trace characteristics are important and should be observed: • Differential Impedance: The differential impedance should be 100 Ω.
I/O Subsystem R together. This will result in a smaller loop area and reduce the likelihood of crosstalk. The effect of different configurations on the amount of crosstalk can be studied using electronics modeling software. 10.9.2.5.1. Terminating Unused Connections In Ethernet designs, it is common practice to terminate unused connections on the RJ-45 connector and the magnetics module to ground.
I/O Subsystem R Figure 101. Intel 82562ET/EM Disable Circuitry 3.3V Sus LAN_RST# GPIO_LAN_ENABLE MMBT3906 10K 5% Intel® 82562EM/ET Disable 10K 5% There are four pins which are used to put the Intel 82562ET/EM controller in different operating states: Test_En, Isol_Tck, Isol_Ti, and Isol_Tex. The table below describes the operational and disable features for this design.
I/O Subsystem R • Keep the total length of each differential pair under 4 inches. (Many customer designs with differential traces longer than 5 inches have had one or more of the following issues: IEEE phy conformance failures, excessive EMI (Electro Magnetic Interference), and/or degraded receive BER (Bit Error Rate).) • Do not route the transmit differential traces closer than 100 mils to the receive differential traces.
I/O Subsystem R decoupling capacitors should be sufficiently large in diameter to decrease series inductance. Additionally, the PLC should not be closer than one inch to the connector/magnetics/edge of the board. 10.9.4.1.2. Signal Isolation Some rules to follow for signal isolation: • Separate and group signals by function on separate layers if possible. Maintain a gap of 100 mils between all differential pairs (Ethernet) and other nets, but group associated differential pairs together.
I/O Subsystem R Figure 103. Ground Plane Separation 0.10 Inches Minimum Spacing Magnetics Module Void or Separate Ground Plane Separate Chassis Ground Plane Good grounding requires minimizing inductance levels in the interconnections and keeping ground returns short, signal loop areas small, and power inputs bypassed to signal return, will significantly reduce EMI radiation. Some rules to follow that will help reduce circuit inductance in both back planes and motherboards.
I/O Subsystem R 10.9.4.2. Common Physical Layout Issues Here is a list of common physical layer design and layout mistakes in LAN On Motherboard Designs. 1. Unequal length of the two traces within a differential pair. Inequalities create common-mode noise and will distort the transmit or receive waveforms. 2. Lack of symmetry between the two traces within a differential pair.
I/O Subsystem R at higher frequencies and will degrade the transmit BER performance. Caution should be exercised if a cap is put in either of these locations. If a cap is used, it should almost certainly be less than 22 pF. (6 pF to 12 pF values have been used on past designs with reasonably good success.) These caps are not necessary, unless there is some overshoot in 100-Mbps mode. Note: It is important to keep the two traces within a differential pair close† to each other.
I/O Subsystem R Figure 104. RTC Power Well Isolation Control No Stuff MMBT3906 RSMRST# generation from MB logic RSMRST# ICH4-M 10KΩ BAV99 BAV99 2.2KΩ No Stuff 10.11. CPU CMOS Considerations The Intel 82801DBM ICH4-M has been designed to be voltage compatible with the CMOS signals of the Intel Celeron M processor. For Intel Celeron M Processor based systems, the ICH4-M’s V_CPU_IO rail uses the same 1.05-V voltage as the VCCP rails for the processor the GMCH.
I/O Subsystem R Figure 105. ICH4-M CPU CMOS Signals with CPU and FWH V_CPU_IO @ 1.
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Platform Clock Routing Guidelines R 11. Platform Clock Routing Guidelines 11.1. System Clock Groups The system clocks are considered as a subsystem in themselves. At the center of this subsystem is the Clock Synthesizer/Driver component. Several vendors offer suitable products, as defined in the Intel CK408 Synthesizer/Driver Specification. This device provides the set of clocks required to implement a platform level motherboard solution.
Platform Clock Routing Guidelines R Figure 106 below depicts the system clock subsystem including the clock generator, major platform components, all the related clock interconnects. Figure 106. Clock Distribution Diagram 11.2. Clock Group Topologies and Routing Constraints The topology diagrams and routing constraint tables provided on the following pages define the recommended topology and routing rules for each of the platform level clocks.
Platform Clock Routing Guidelines R 11.2.1. Host Clock Group The clock synthesizer provides three pairs of 100-MHz differential clock outputs utilizing a 0.7-V voltage swing. The 100-MHz differential clocks are driven to the processor (Mobile Intel Pentium 4 Processor-M, Mobile Intel Celeron processor or Intel Celeron M processor) the GMCH, and the processor debug port with the topology shown in the figure below.
Platform Clock Routing Guidelines R Table 79. Host Clock Group Routing Constraints Parameter Definition Class Name HCLK Class Type Individual Differential Pairs Topology Differential Source Shunt Terminated Reference Plane Ground Referenced (contiguous over length) Single Ended Trace Impedance ( Zo ) 55 Ω ± 15% Differential Mode Impedance (Zdiff) 100 Ω ± 15% Nominal Inner Layer Trace Width 4.0 mils Nominal Inner Layer Pair Spacing (edge to edge)(except as allowed below) 7.
Platform Clock Routing Guidelines R 11.2.1.1. Host Clock Group General Routing Guidelines When routing the 100-MHz differential clocks, do not split up the two halves of a differential clock pair between layers, and route to all agents on the same physical routing layer referenced to ground. If a layer transition is required, make sure that the skew induced by the vias used to transition between routing layers is compensated in the traces to other agents.
Platform Clock Routing Guidelines R 11.2.2. CLK66 Clock Group The 66-MHz clocks are series terminated and routed point to point on the motherboard, with dedicated buffers for each of the loads. These clocks are all length tuned to match each other and the CLK33 clocks. Figure 108. CLK66 Clock Group Topology Rs L1 L2 GMCH ICH4 CK408 Table 81.
Platform Clock Routing Guidelines R 11.2.3. CLK33 Clock Group The 33-MHz clocks are series terminated and routed point to point on the motherboard with dedicated buffers for each of the loads. These clocks are length tuned to match the CLK66 clocks, however, they are out of phase due to an internal phase delay in the CK408. Figure 109. CLK33 Group Topology Rs L1 L2 ICH4 SIO, FWH CK408 Table 82.
Platform Clock Routing Guidelines R 11.2.4. PCI Clock Group The PCI clocks are series terminated and routed point to point as on the motherboard between the CK408 and the PCI connectors with dedicated buffers for of the three slots. These clocks are synchronous to the CLK33 clocks and are length tuned to compensate for the segment on the PCI daughter card. Figure 110. PCI Clock Group Topology Rs L1 L2 L3 Trace on Card PCI Connector CK408 PCI Device Table 83.
Platform Clock Routing Guidelines R 11.2.5. CLK14 Clock Group The 14-MHz clocks are series terminated and routed point to point on the motherboard. A single clock output is shared between the two loads. These clocks are length tuned to each other but are not synchronous with any other clocks. Figure 111. CLK14 Clock Group Topology Rs L1 L2 A C K 408 IC H 4 Rs L2B S IO Table 84.
Platform Clock Routing Guidelines R 11.2.6. DOTCLK Clock Group The 48-MHz DOTCLK is series terminated and routed point to point on the motherboard. This clock operates independently and is not length tuned to any other clock. Figure 112. DOTCLK Clock Topology Rs L1 L2 GMCH CK408 Table 85.
Platform Clock Routing Guidelines R 11.2.7. SSCCLK Clock Group The 48/66-MHz SSCCLK operates independently and is not length tuned to any other clock. This clock employs a spread-spectrum device in its path to reduce EMI. The overall clock path is divided into two segments as shown in Figure 113, with each segment series terminated and routed point to point. Figure 113. SSCCLK Clock Topology Rs L1 L2 SSC CK408 GMCH Rs L3 L4 Table 86.
Platform Clock Routing Guidelines R 11.2.8. USBCLK Clock Group The 48-MHz USBCLK is series terminated and routed point to point on the motherboard. This clock operates independently and is not length tuned to any other clock. Figure 114. USBCLK Clock Topology Rs L1 L2 GMCH CK408 Table 87.
Platform Clock Routing Guidelines R 11.3. CK-408 Clock Updates for Intel Celeron M Processor Platforms To maximize the power savings on Intel Celeron M processor / Intel 852GM Chipset based systems, additional control registers have been added to the CK-408 clock generator to allow option to tri-state the CPU[2:0] host clocks during CPU_STOP# or PWRDWN assertion. The option to have CPU[2:0] driven (default) or tri-stated can be programmed via the serial I2C bus interface to the CK-408 clock driver.
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Intel 852GM Platform Power Delivery Guidelines R 12. 12.1. Intel 852GM Platform Power Delivery Guidelines Definitions Table 88. Power Delivery Definitions Term S0/Full-On operation: In the S0 state, all components on the motherboard are powered and the system is fully functional. S1M/Power-On-Suspend (POS, Mobile): In the mobile implementation of the S1M state, the outputs of the clock chip are stopped in order to save power. All components remain powered but may or may not be in a low power state.
Intel 852GM Platform Power Delivery Guidelines R The solutions given in this document are only examples. There are many power distribution methods that achieve similar results. It is critical, when deviating from these examples, to consider the effect of the change. 12.2.1. Platform Power Delivery Architectural Block Diagram Figure 115. Platform Power Delivery Map Mobile Intel Pentium 4 Processor – M / Mobile Intel Celeron Processor VCC_CORE / VCCP = IMVP-III VCC_VID = 1.
Intel 852GM Platform Power Delivery Guidelines R Figure 116. Platform Power Delivery Map for Intel Celeron M Processor Intel® Celeron® M Processor VCC_CORE = IMVP-IV VCCP = IMVP-IV VCCA =+V1.8S 400MHz FSB DVO 852GM GMCH 200/266 MHz DDR VCC-GMCH = 1.35V / 1.2V VCCP = IMVP-IV LVDS +V1.5S +V 2.5 +V3.3S CRT +V1.25S +V2.5 Hub Interface 1.5 USB ICH4-M +V3.3 +V5Always PCI Bus Docking VCCP = IMVP-IV +V1.5S +V1.5Always +V1.5LAN +V3.3Always +V3.3S +V3.3LAN +V5Always +VCC_RTC ATA 66/100 IDE +V3.
Intel 852GM Platform Power Delivery Guidelines R 12.3. Voltage Supply 12.3.1. Power Management States Table 89. Power Management States on Intel Reference Board 12.3.2.
Intel 852GM Platform Power Delivery Guidelines R Signal Names Voltage (V) Current (A) Tolerance Enable Description +V5S 5 1.0 ± 5% SLP_S3# - HIGH ICH4-M VREF, MSE/KBD, FDD, IDE, PCI +V5ALWAYS 5 3.0 ± 5% +VDC ICH4-M VREFSUS, USB Supply +V12S 12 0.2 ± 5% SLP_S3# - HIGH PCI, IDE +VCC_VID -HIGH Mobile Intel Pentium 4 processor-M I/O core and I/O voltage by IMVP-III VR VID+ Intel Celeron M processor core voltage by IMVP – IV VR +VCC_CORE / +VCCP Mobile Intel Pentium 4 processor-M 1.
Intel 852GM Platform Power Delivery Guidelines R Figure 117. GMCH Power-Up Sequence CPURST# 1ms max RSTIN# 1ms min PWROK GMCH PWR Rails 12.4.3. ICH4-M Power Sequencing Requirements The following figure describes the power-up timing sequence for ICH4-M. The VGATE input should be connected to the processor voltage regulator PWRGD output. When both PWROK and VGATE are asserted, it indicates that core power and system power are stable and PCIRST# will be de-asserted a minimum of 1 ms later.
Intel 852GM Platform Power Delivery Guidelines R Figure 118.
Intel 852GM Platform Power Delivery Guidelines R Table 91. Timing Sequence Parameters for Figure 118 Sym Description Min Max Units T173 Notes VccSus supplies active to RSMRST# inactive 10 - ms T176 Vcc1.5, Vcc3.
Intel 852GM Platform Power Delivery Guidelines R Figure 119. Example V5REF / V5REFSUS Sequencing Circuitry 12.4.3.3. V5REFSUS Design Guidelines The same rule for V5REF also applies for V5REF_SUS. However, in most platforms, the VCCSUS3_3 rail is derived from the VCCSUS5 and therefore, the VCCSUS3_3 rail will always come up after the VCCSUS5 rail. As a result, V5REF_SUS will always be powered up before VCCSUS3_3.
Intel 852GM Platform Power Delivery Guidelines R Figure 121. V5REFSUS With +V3ALWAYS and +V5S or +V5 Connection Option +V5S or +V5 Customer specific or Intel recommended USB power circuit +V3ALWAYS D1* D2* V5REF_SUS2 V5REF_SUS1 USB Power (5 V) 0.1 µF ICH4-M ICH4-M Customer specific or Intel recommended USB interface circuits USB D+ USB D - USB D+ USB D- GND Note: D1 and D2 are BAT54 or Equivalent Schottky Diodes 12.4.4.
Intel 852GM Platform Power Delivery Guidelines R 12.5. Intel 852GM Platform Power Delivery Guidelines Each component is capable of generating large current swings when switching between logic high and logic low. This condition could cause the component voltage rails to drop below specified limits. To avoid this type of situation, ensure that the appropriate amount of bulk capacitance is added in parallel to the voltage input pins.
Intel 852GM Platform Power Delivery Guidelines R Table 93. GMCH Decoupling Recommendations Pin Name Configuration F Qty TYPE Notes VCC Connect to VCC1_2S 0.1 µF 4 XR7, 0603, 16 V, 10% 1 X 0.1 µF within 200 mils 10 µF 1 XR5, 1206, 6.3 V, 20% 3 X 0.1 µF on bottom side 150 µF 2 SPC, E, 6.3 V, 20% 0.1 µF 2 XR7, 0603, 16 V, 10% 10 µF 1 XR5, 1206, 6.3 V, 20% 150 µF 1 SPC, E, 6.3 V, 20% VTTLF 2 X 0.1 µF on bottom side VTTHF Connect to caps directly 0.
Intel 852GM Platform Power Delivery Guidelines R 12.5.2.2. DDR SDRAM VDD Decoupling Discontinuities in the DDR signal return paths will occur when the signals transition between the motherboard and the SO-DIMMs. To account for this ground to 2.5-V discontinuity, a minimum of nine 0603 form factor 0.1-µF high frequency bypass capacitors is required between the SO-DIMMs to help minimize any anticipated return path discontinuities that will be created.
Intel 852GM Platform Power Delivery Guidelines R Figure 123. DDR Power Delivery Block Diagram +V5 S w itc h in g R e g u la t o r V in +V 2_5 Vout S e n s e A d j. 10K 10K + SMVREF - +V5 S w itc h i n g R e g u la t o r V in +V1_25S Vout S e n s e A d j. Note: SMVREF and +V1.25 can optionally be on the switch rail and turned off in either S3 or S4. This is only a block diagram.
Intel 852GM Platform Power Delivery Guidelines R 12.5.3.3. DDR SMRCOMP Resistive Compensation The GMCH requires a system memory compensation resistor, SMRCOMP, to adjust buffer characteristics to specific board and operation environment characteristics. Refer to the RS – Intel® 852GM GMCH Chipset Datasheet and Figure 124 for details on resistive compensation. The SMRCOMP signal should be routed with as wide a trace as possible.
Intel 852GM Platform Power Delivery Guidelines R 12.5.3.4. DDR VTT Termination The recommended topology for DDR-SDRAM Data, Control, and Command signal groups requires that all these signals to be terminated to a 1.25-V source, VTT, at then end of the memory channel opposite the GMCH. Intel recommends that this VTT be generated from the same source as used for VCCSM, and not be used for GMCH and DDR SMVREF.
Intel 852GM Platform Power Delivery Guidelines R Figure 126. GMCH HDVREF[2:0] Reference Voltage Generation Circuit +VCCP R1 49.9 1% GMCH_HDVREF K21 J21 R2 100 1% C1 1uF C2 0.1uF J17 852GM HDVREF0 HDVREF1 HDVREF2 Figure 127. GMCH HAVREF Reference Voltage Generation Circuit +VCCP R1 49.9 1% GMCH_HAVREF R2 100 1% Y22 852GM HAVREF C3 C1 1uF 0.1uF Figure 128. GMCH HCCVREF Reference Voltage Generation Circuit +VCCP R1 49.9 1% GMCH_HCCVREF R2 100 1% C1 1uF Y28 852GM HCCVREF C3 0.
Intel 852GM Platform Power Delivery Guidelines R Figure 129. Primary Side of the Motherboard Layout Figure 130.
Intel 852GM Platform Power Delivery Guidelines R 12.5.4.2. GMCH AGTL+ I/O Buffer Compensation The HXRCOMP and HYRCOMP pins of the GMCH should each be pulled-down to ground with a 27.4 Ω ± 1% resistor. See Figure 131. The maximum trace length from pin to resistor should be less than 0.5 inches and should be 18-mil wide to achieve the Zo = 27.4 Ω target. Also, the routing for HRCOMP should be at least 25 mils away from any switching signal. Figure 131.
Intel 852GM Platform Power Delivery Guidelines R VCCALVDS. VCCADAC, VCCAGPLL, and VCCALVDS do not require an RLC filter but do require decoupling capacitors. Figure 133. Example Analog Supply Filter Low Pass Filtering *RDAMP L Filtered VCC VCC Noise CHIGH CBULK *RDAMP is not required for all filters *RDAMP Table 94. Analog Supply Filter Requirements 230 Required Intel 852GM Filters Rdamp Rdamp location L Cbulk Chigh VCCASM None N/A 1210 1.0 µH DCRmax 0.169 Ωs 100 µF 0603 0.
Intel 852GM Platform Power Delivery Guidelines R 12.5.5. 12.5.5.1. ICH4-M Decoupling / Power Delivery Guidelines ICH4-M Decoupling The ICH4-M is capable of generating large current swings when switching between logic high and logic low. This condition could cause the component voltage rails to drop below specified limits. To avoid this type of situation, ensure that the appropriate amount of decoupling capacitance is added in parallel to the voltage input pins.
Intel 852GM Platform Power Delivery Guidelines R 12.5.8. General LAN Decoupling The following are general LAN decoupling recommendations: • All VCC pins should be connected to the same power supply. • All VSS pins should be connected to the same ground plane. • Four to six decoupling capacitors, including two 4.7-µF capacitors are recommended • Place decoupling as close as possible to power pins.
Reserved, NC, and Test Signals R 13. Reserved, NC, and Test Signals The processor and Intel 852GM GMCH may have signals listed as “RSVD”, “NC”, or other name whose functionality is Intel reserved. The following section contains recommendations on how these Intel reserved signals on the processor or GMCH should be handled. The Mobile Intel Pentium 4 Processor–M has a total of eight NC and nine TESTHI signals that are Intel reserved in the pin-map.
Reserved, NC, and Test Signals R 13.1. Intel 852GM GMCH RSVD Signals Intel 852GM has a total of 32 RSVD and 12 NC signals that are Intel reserved in the pin-map. The recommendation is to provide test points for all RSVD signals. All NC signals should be left as no connects. The location of the Intel reserved signals in the GMCH pin-map is listed in Table 97. Table 97.
Reserved, NC, and Test Signals R Signal Name Ball Name RSVD T5 RSVD F12 RSVD D12 RSVD B12 RSVD AA5 RSVD L4 RSVD F3 RSVD D3 RSVD B3 RSVD F2 RSVD D2 RSVD C2 RSVD B2 RSVD D7 Intel® 852GM Chipset Platform Design Guide 235
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Platform Design Checklist R 14. Platform Design Checklist The following checklist provides design recommendations and guidance for the mobile Intel Pentium 4 Processor-M, mobile Intel Celeron processor or Intel Celeron M processor systems with the Intel 852GM chipset platform. It should be used to ensure that design recommendations in this design guide have been followed prior to schematic reviews. However, this is not a complete list and does not contain detailed layout information.
Platform Design Checklist R 14.3. Design Checklist Implementation The voltage rail designations in this checklist are as general as possible. The following table describes the equivalent voltage rails in the Intel reference board schematics. Checklist Rail Intel CRB Rail On S0-S1 Vcc1_2 +V1.2S_GMCH_CORE, +V1.2S_GMCH_HUB, +V1.2S_GMCH_HGPLL, +V1.2S_GMCH_DPLL, +V1.2S_GMCH_ASM X Vcc1_25 +V1.25S [DDR_Vtt] X Vcc1_5 +V1.5S_GMCH_DVO, +V1.5S_GMCH_ALVDS, +V1.5S_GMCH_ADAC, +V1.5S_GMCH_DLVDS, +V1.
Platform Design Checklist R 14.4. Mobile Intel Pentium 4 Processor-M and Mobile Intel Celeron Processor 14.4.1. Resistor Recommendations Pin Name System Pull-up/Pull-down Series Termination Voltage Translation A20M# Notes 9 Point-to-point connection to ICH4M. BR0# 220 Ω pull-up to VCCP Point-to-point connection to GMCH, with resistor placed by GMCH. COMP[1:0] 51.1 Ω ± 1% pulldown to gnd Resistor placed within 0.5” of processor pin. Trace should be at least 25 mils from other traces.
Platform Design Checklist R Pin Name System Pull-up/Pull-down Voltage Translation Notes PWRGOOD 300 Ω pull-up to VCCP Point-to-point connection to ICH4M, with resistor placed by the processor. RESET# 51 Ω pull-up to VCCP If ITP700FLEX is Used: RESET# connects from processor to GMCH and then forks out to ITP700 FLEX, with pull-up and series damping resistor placed next to ITP. Second pull-up may be required at ITP if there is noise issues on the signal. SLP# Point-to-point connection to ICH4M.
Platform Design Checklist R Figure 134. Routing Illustration for INIT# FWH 3.3V CPU V_IO_FWH 3.3V ICH4-M R2 R1 Q2 L1 L2 L3 L4 3904 Q1 3904 Rs Figure 135. Voltage Translation Circuit for PROCHOT# 3.3V 3.3V 1.3K +/-5% 330 From Driver 330 To Receiver Q2 3904 Q1 +/-5% R2 +/-5% R1 3904 Rs Figure 136. VCCIOPLL, VCCA and VSSA Power Distribution VCCA VCC_VID 4.7uH CA Mother board CIO 33uF 4.
Platform Design Checklist R 14.4.2. In Target Probe (ITP) Pin Name System Pull-up /Pull-down Series Termination Resistor (Ω) BPM[5:0]# 51 Ω pull-up to VCCP Connect to processor, with resistors placed by the processor. DBR# 150-240 Ω pull-up to V3ALWAYS If using ITP on interporser card, then DBR# should also be connected to DBRESET pin at the processor. RESET# 51 Ω pull-up to VCCP If USING ITP700FLEX 150 Ω from pullup to ITP700FLEX FBO Connect to TCK pin of processor. . 27.
Platform Design Checklist R 14.4.4. Power-up Sequence Please refer to processor datasheet for latest information. Table 98. Mobile Intel Pentium 4 Processor-M Power-up Timing Specifications Sym Ta Timing Parameters VccVID active to VID_GOOD Min Max 1 Unit Notes µs Please refer to the Mobile Intel Pentium 4 Processor-M Datasheet. 9 See Figure 137.
Platform Design Checklist R Figure 137. Mobile Intel Pentium 4 Processor-M Power Up Sequence Td R ESET# Tc PW RG O O D BC LK Vcc VID _G O O D Ta Tb VID [4:0], BSEL[1:0] VCC VID Ta= Tb= Tc= Td= 1us m inim um (VCC VID > 1V to VID _G O O D high) 50m s m axim um (VID _G O O D to Vcc valid m axim um tim e) T37 (PW R G O O D inactive pulse w idth) T36 (PW R G O O D to R ESET# de-assertion tim e) N ote: VID_G O O D is not a processor signal.
Platform Design Checklist R Pin Name System Series Termination Pull-up/Pulldown IERR# Voltage Translation 56 Ω pull-up to VCCP Notes IERR# is a 1.05 V signal. Voltage translation logic and/or series resistor may be required if used. R1 = 1.3 KΩ INIT# R2 = 330 Ω Rs = 330 Ω Point-to-point connection to ICH4-M. Voltage transition circuit is required if connecting to FWH. Signal is T-split from the ICH4-M to FWH. IGNNE# Point-to-point connection to ICH4-M.
Platform Design Checklist R Pin Name System Series Termination Pull-up/Pulldown VCCSENSE, VSSSENSE Voltage Translation 54.9 Ω ± 1% pull-down to gnd For each signal, stuffing option for pull-down should be provided for testing purposes. Also, a test point for differential probe ground should be placed between the two resistors. For normal operation, leave the resistors unpopulated. (default: no stuff) VSS[191:0] 9 Notes Connect to gnd Figure 138.
Platform Design Checklist R 14.6. CK-408 Clock Checklist 14.6.1. Resistor Recommendations Pin Name System Pull-up/Pull-down Series Resistor Notes 33 Ω If the signal is used, one 33-Ω series resistor is required. If the signal is NOT used, it should be left as NC (Not Connected) or connected to a test point. 33 Ω Use 66BUF[1] (pin 22) for GMCH. Use one of the other two signals for ICH4-M. 33 Ω Use one pair for the processor and another pair for GMCH.
Platform Design Checklist R Figure 140.
Platform Design Checklist R 14.7. Intel 852GM GMCH Checklist 14.7.1. System Memory 14.7.1.1. GMCH System Memory Interface Pin Name System Pull-up/Pull-down Series Resistor Notes RCVENIN# This signal should be routed to a via next to ball and left as a NC (No Connect). RCVENOUT# This signal should be routed to via next to ball and left as a NC (No Connect).
Platform Design Checklist R Pin Name System Series Resistor Pull-up/Pull-down VccSus2_5 9 Notes Need 0.1 µF cap by the voltage divider. 60.4 Ω 1% pull-down to gnd This signal may be optionally connected to Vcc2_5 and powered off in S3. Figure 141. Reference Voltage Level for SMVREF VccSus2_5 10k+/- 1% GMCH + - 10k+/-1 % 14.7.1.2. SMVREF_0 0.1 uF DDR SO-DIMM Interface Pin Name Configuration VREF[2:1] 250 SMVREF Notes 9 Signal voltage level = VCCSus2_5 / 2.
Platform Design Checklist R 14.7.1.3. SODIMM Decoupling Recommendation Pin Name F Vcc1_25 0.1 µF Qty 0.01 µF Vcc2_5Sus 14.7.2. 9 Notes Place one 0.1 µF cap and one 0.01 µF close to every 4 pull-up resistors terminated to Vcc1_25 (VTT for DDR signal termination). In S3, Vcc1_25 is powered OFF. 0.1 µF 9 100-150 µF 4 A minimum of 9 high frequency caps are recommeneded to be placed bewteen the SO-DIMMS. A minimum of 4 low frequency caps are required.
Platform Design Checklist R 14.7.3. Hub Interface Pin Name System Notes 9 Pull-up/Pull-down 14.7.4. 14.7.4.1. HLVREF See Section14.8.9. Signal voltage level = 0.35 V ± 8%. PSWING See Section14.8.9. Signal voltage level = 2/3 of VCC1_2 or 0.8 V ± 8%. HLZCOMP 27.4 Ω 1% pull-up to Vcc1_2 Graphics Interfaces LVDS Pin Name System Notes 9 Pull-up/Pull-down LIBG 1.5 kΩ 1% pull-down to gnd YAP[3:0]/YAM[3:0] If any of these LVDS data pairs are unused, they can be left as “no connect.
Platform Design Checklist R Pin Name System 9 Notes Pull-up/Pull-down DVOBD[11:0] Intel 852GM GMCH supports only one DVO port. So, these signals should be left as NC. DVOBCLK DVOBCLK# DVOBHSYNC DVOBVSYNC DVOBBLANK# DVOBFLDSTL (pin M2) 100 kΩ pull-down to gnd For Intel 852GM GMCH, pull-down resistor required on this signal (10 k-100 k). MI2CCLK, MI2CDATA 2.2 kΩ pull-up to Vcc1_5 Pull-up resistor required on each signal even if they are unused (2.2 k-100 k). This signal is 1.5 V tolerant.
Platform Design Checklist R 14.7.4.3. DAC Pin Name REFSET System Pull-up /Pull-down In Series 9 Notes 127 Ω 1% pull-down to gnd RED # Connect to gnd Need to connect to RED’s return path BLUE # Connect to gnd Need to connect to BLUE’s return path GREEN# Connect to gnd RED On GMCH side of ferrite bead: Need to connect to GREEN’s return path 75 Ω 1% pull-down to gnd, 3.
Platform Design Checklist R Table 99. GST[1:0] Configurations GMCH GST[1:0] Configuration 14.7.6. FSB DDR Gfx Core Clock Low Gfx Core Clock High 00 400 266 N/a 133 10 400 200 N/a 133 GMCH Decoupling Recommendations Pin Name VCC VTTLF Configuration Connect to Vcc1_2 Connect to VCCP VTTHF VCCHL VCCSM VCCQSM Connect to Vcc1_2 Connect to VccSus2_5 Connect to VccSus2_5 with filter network F Qty 0.1 µF 4 150 µF 2 10 µF 1 0.1 µF 2 150 µF 1 1 5 Connect pins directly to caps. 0.
Platform Design Checklist R Pin Name Configuration F Qty VCCAHPLL Connect to VCC1_2 0.1 µF 1 VCCAGPLL Connect to VCC1_2 0.1 µF 1 VCCADPLLA Connect to VCC1_2 with filter network 0.1 µF 1 220 µF 1 VCCADPLLB Connect to VCC1_2 with filter network 0.1 µF 1 220 µF 1 NOTE: 14.7.7. Notes 9 0.1 µH from power supply to GMCH pins, with caps on GMCH side of inductor. 0.1 µH from power supply to GMCH pins, with caps on GMCH side of inductor.
Platform Design Checklist R 14.8. ICH4-M Checklist Note: All inputs to the ICH4-M must not be left floating. Many GPIO signals are fixed inputs that must be pulled up to different sources. 14.8.1. PCI Interface and Interrupts Pin Name System Pull-up /Pull-down PCI_DEVSEL# 8.2 kΩ pull-up to Vcc3_3 PCI_FRAME# 8.2 kΩ pull-up to Vcc3_3 PCI_GPIO0 / REQA# 8.2 kΩ pull-up to Vcc3_3 Notes 9 Each signal requires a pull-up resistor.
Platform Design Checklist R 14.8.2. GPIO Note: Ensure ALL unconnected signals are OUTPUTS ONLY. Only GPIO[7:0] are 5-V tolerant. 9 Recommendations GPIO[7] & [5:0]: • These pins are in the Main Power Well. Pull-ups must use the VCC3_3 plane. • Unused core well inputs must be pulled up to VCC3_3. • GPIO[1:0] can be used as REQ[B:A]#. • GPIO[1] can be used as PCI REQ[5]#. • GPIO[5:2] can be used as PIRQ[H:E]#. • These signals are 5 V tolerant. • These pins are inputs.
Platform Design Checklist R 9 Recommendations • GPIO[25] can be used as AUDIO_PWRDN. GPIO[43:32]: • I/O pins. From main power well (VCC3_3). • Default as outputs when enabled as GPIOs. • These signals are NOT 5-V tolerant. • GPIO[32] can be used as AGP_SUSPEND#. • GPIO[33] can be used as KSC_VPPEN#. • GPIO[34] can be used as SER_EN. • GPIO[35] can be used as FWH_WP#. • GPIO[36] can be used as FWH_TBL#. • GPIO[40] can be used as IDE_PATADET. • GPIO[41] can be used as IDE_SATADET. 14.8.3.
Platform Design Checklist R 14.8.5. AC ’97 Interface Pin Name System Pull-up/Pull-down AC_BIT_CLK None Series Termination Resistor Notes 33-47 Ω The internal pull-down resistor is controlled by the AC’97 Global Control Register, ACLINK Shut Off bit: 9 1 = enabled; 0 = disabled When no AC'97 devices are connected to the link, BIOS must set the ACLINK Shut Off bit for the internal keeper resistors to be ENABLED. At that point, pull-ups/pull-downs are NOT needed on ANY of the link signals.
Platform Design Checklist R 14.8.6. ICH4-M Power Management Interface Pin Name System Notes 9 Pull-up/Pull-down PM_DPRSLPVR Signal has integrated pull-down in ICH4-M. PM_SLP_S1#/GPIO19 PM_SLP_S3#, PM_SLP_S4#, PM_SLP_S5# Signals driven by ICH4-M. PM_BATLOW# 10 kΩ pull-up to V3ALWAYS PM_CLKRUN# 10 kΩ pull-up to Vcc3_3 IF NOT USED Has integrated pull-up of 18 kΩ – 42 kΩ. PM_PWRBTN# PM_PWROK Pull up is not required if it is used.
Platform Design Checklist R 14.8.8. USB Interface Pin Name System Notes 9 Pull-up/Pull-down USB_OC[5:0]# 10 kΩ pull-up to V3ALWAYS USBRBIAS, USBRBIAS# 22.6 Ω ± 1% pull-down to gnd No pull-up is required if signalsl are driven.. Signals must NOT float if they are not being used. if not driven 14.8.9. Connect signals together and pull down through a common resistor, placed within 500 mils of the ICH4M. Avoid routing next to clock pin.
Platform Design Checklist R Figure 146. Single Generated GMCH & ICH4-M VSWING/VREF Reference Voltage/ Local Voltage Divider Circuit for VSWING/VREF VCCHI=1.5V R4 R4 = 43.2 Ω ± 1%, R5 = 49.9 Ω ± 1%, R6 = 78.7 Ω ± 1%, R7 = 24.2 Ω ± 1% R6 PVSWING C1 and C3 = 0.1 µF (near divider) HI_VSWING HLVREF HIREF GMCH R5 C6 C5 R7 Intel® ICH4 C2, C4, C5, C6 = 0.01µF (near component) C4 C3 C1 C2 14.8.10.
Platform Design Checklist R Figure 147. External Circuitry for the RTC VCCRTC 3.3V Sus 1uF RTCX2 1kΩ R1 10MΩ 32.768 kHz Xtal Vbatt RTCX1 C3 0.047uF C1 C2 R2 10MΩ VBIAS Notes Reference Designators Arbitrarily Assigned 3.3V Sus is Active Whenever System Plugged In Vbatt is Voltage Provided By Battery 14.8.11.
Platform Design Checklist R 14.8.12. Primary IDE Interface Pin Name System Pull-up/Pulldown Series Damping Notes IDE_PDD[15:0] These signals have integrated series resistors. IDE_PDA[2:0], IDE_PDCS1#, IDE_PDCS3#, IDE_PDDACK#, IDE_PDIOW#, IDE_PDIOR# These signals have integrated series resistors. Pads for series resistors can be implemented should the system designer have signal integrity concerns. IDE_PDDREQ These signals have integrated series resistors and pull-down resistors in ICH4-M.
Platform Design Checklist R 14.8.15. ICH4-M Decoupling Recommendations Pin Name Configuration Value Q VCC1.5 Connect to Vcc1_5 0.1 µF 2 Low frequency decoupling is dependent on layout and power supply design. CRB uses one 22 µF and one 100 µF. VCC3.3 Connect to Vcc3_3 0.1 µF 6 Low frequency decoupling is dependent on layout and power supply design. CRB uses two 22 µF. VCCSUS1.5 Connect to V1_5ALWAYS 0.1 µF 2 Low frequency decoupling is dependent on layout and power supply design.
Platform Design Checklist R 14.9. USB Power Checklist 14.9.1. Downstream Power Connection Pin Name USB_VCC[E:A] 9 Notes One 220 µF and two 470 pF are recommended for every two power lines. Either a thermister or a power distribution switch (with short circuit and thermal protection) is required. See Figure 148. Figure 148.
Platform Design Checklist R 14.10. FWH Checklist 14.10.1. Resistor Recommendations Pin Name System Pull-up/Pull-down FGPI[4:0] 100 Ω pull-down to gnd IC 10 kΩ pull-down to gnd RST# 268 Series Damping Notes 9 Each signal requires a 100 Ω pull-down resistor. 100 Ω ID[3:0] Signals are recommended to be connected to test points. RSVD[5:1] Signals are recommended to be connected to test points.
Platform Design Checklist R 14.11. LAN / HomePNA Checklist 14.11.1. Resistor Recommendations (for 82562ET / 82562EM) Pin Name System Term Resistor Pull-up/Pull-down ISOL_EX, ISOL_TCK, ISOL_TI 10 kΩ pull-up to VccSus3_3LAN RBIAS10 549 Ω ± 1%pull-down to gnd RBIAS100 619 Ω ± 1%pull-down to gnd Notes 9 If LAN is enabled, all three signals needs to be pulled up to VccSus3_3LAN through a common 10 KΩ pull-up resistor. See Figure 149.
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Schematics R 15. Schematics See the following pages for the reference board schematics.
A B C D E Mobile Intel Pentium 4 Processor-M / Intel 852GM Chipset CUSTOMER REFERENCE BOARD Fan Header CPU Thermal Sensor PG 5 PG 38 CK-408 PG 5 Clocking PG 11 PG 39,40,41 852GM LVDS PG 16 732 uFCBGA EVMC SLOT 421 BGA USB 2.
A B C D E Intel 852GM CUSTOMER REFERENCE PLATFORM SCHEMATIC ANNOTATIONS AND BOARD INFORMATION 2 Voltage Rails I C / SMB Addresses Default Jumper Settings 4 3 4 +VDC +VCC_IMVP +VCC_VID +V1.2S +V1.25S +V1.5S +V1.5ALWAYS +V1.5 +V2.5 +V3.3ALWAYS +V3.3 +V3.3S +V5ALWAYS +V5 +V5S +V12S -V12S Primary DC system power supply (10 to 21V) Core/VTT voltage for processor & VTT for Montara-GML 1.2V for processor PLL and VID circuitry 1.2V for Montara-GML core/hub interface 1.25V DDR Termination voltage 1.
B C TP_CPU_A35# AB1 TP_CPU_A34# Y1 TP_CPU_A33# W2 TP_CPU_A32# V3 H_A#[31:17] H_A#31 U4 H_A#30 T5 H_A#29 W1 H_A#28 R6 H_A#27 V2 H_A#26 T4 H_A#25 U3 H_A#24 P6 H_A#23 U1 H_A#22 T2 H_A#21 R3 H_A#20 P4 H_A#19 P3 H_A#18 R2 H_A#17 T1 R5 8 H_ADSTB#1 A35# A34# A33# A32# A31# A30# A29# A28# A27# A26# A25# A24# A23# A22# A21# A20# A19# A18# A17# ADSTB1# 4 3 8 H_ADSTB#0 H_REQ#4 H_REQ#3 H_REQ#2 H_REQ#1 H_REQ#0 G1 AC1 V5 AA3 G2 D2 DP3# DP2# DP1# DP0# DEFER# DRDY# DBSY# L25 K26 K25 J26 E2 H2 H5 TESTHI8 TESTHI9
A B 3 2 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 V
A B C D E CPU Thermal Sensor 6,8,9,11,15,16,18,20,21,23,26,31,33..36,38..40,42,44,48 +V3.3S 4 R2B1 R2B3 1K 1K RP2B1D 10K 3 C2B2 0.1UF 4 Address Select Straps Current Address: 1001 110x +V3.3S 2 6,8,9,11,15,16,18,20,21,23,26,31,33..36,38..
A B C D E 5,8,9,11,15,16,18,20,21,23,26,31,33..36,38..40,42,44,48 +V3.3S +V3.3S_CLKRC J3F1 XTAL_IN_D 1 3 4 +V3.3S_CLKVDD 1 5 2 C2U5 Place 0ohm near crystal. C2F4 22UF Place crystal within 500 mils of CK_408 1 2 U3F1 1 C3F4 NO_STUFF_10pF 2 +V3.3S_CLKRC FB2F2 300ohm@100MHz 1 2 C3F2 NO_STUFF_10pF C2U1 0.1UF C2F2 22UF 1 8 14 19 32 37 46 50 +V3.
A B C 13 M_CB[7:0] AD16 AC12 AF11 AD10 SCKE0 SCKE1 SCKE2 SCKE3 SCS0# SCS1# SCS2# SCS3# AC7 AB7 AC9 AC10 AD23 AD26 AC22 AC25 M_AB[5:4] M_CKE0 M_CKE1 M_CKE2 M_CKE3 M_CS0# M_CS1# M_CS2# M_CS3# 12,14 11,12,14 11,12,14 12,14 12,14 11,12,14 11,12,14 12,14 12,14 SBA0 SBA1 AD22 AD20 M_BS0# M_BS1# 12..14 12..14 SRAS# SCAS# SWE# AC21 AC24 AD25 M_RAS# M_CAS# M_WE# 12..14 12..14 12..
C 6,11,12,16,18,39 6,11,12,16,18,39 7 1 2 3 4 5 6 SMB_DATA_S SMB_CLK_S MCH_EXTTS0 6Pin_HDR Note: Host Clock terminations are at the source (CK408) CLK_MCH_BCLK# CLK_MCH_BCLK 3 H_REQ#[4:0] H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 3 R3F4 R3F3 49.9_1% 49.9_1% 3 3 H_ADSTB#0 H_ADSTB#1 6 CLK_MCH_BCLK# 6 CLK_MCH_BCLK 10 MCH_HYRCOMP 10,47 MCH_HYSWING 10 MCH_HXRCOMP 10,47 MCH_HXSWING 3 3 3 0.1UF 0.
B 2 1 VSS 3 VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83
A B C GMCH-GML Compensation & Reference Voltages 3..5,9,18,20,40,41,47,48 +VCC_IMVP 3..5,9,18,20,40,41,47,48 D E LAI Hub Interface 8,18 HUB_PD[10:0] J6U1 No_Stuff_HUBLINK +VCC_IMVP Host R5R9 301_1% R4T1 301_1% R5R10 4 8,47 MCH_HXSWING HUB_PD0 R4E2 8,47 MCH_HYSWING 150_1% HUB_PD2 150_1% R6E8 392_1% +VCC_IMVP R6F12 LAI_HUB_PIN18 392_1% R5D3 R5T2 49.9_1% R5T1 1 8 MCH_HXRCOMP 2 R6F10 8,18 HUB_PSTRB# 100_1% 1 8 MCH_HYRCOMP HUB_PD7 2 3..
A B C D E 5,6,8,9,15,16,18,20,21,23,26,31,33..36,38..40,42,44,48 +V3.3S 12 R4W1 +V3.3S_SPD 0.01_1% Power plane for Serial Presence Detect logic 12..14 M_DATA_R_[63:0] 4 13 M_AA_FR_0 7,14 M_AA[2:1] 13 M_AA_FR_3 7,14 M_AA[5:4] 13 M_AA_FR_[12:6] 13 M_BS0_FR# 13 M_BS1_FR# 12..
A B C D E 11,13,14 M_DATA_R_[63:0] M_AA0 M_AB1 M_AB2 7,13,14 M_AA0 4 7,14 M_AB[2:1] M_AA3 M_AB4 M_AB5 M_AA6 M_AA7 M_AA8 M_AA9 M_AA10 M_AA11 M_AA12 7,13,14 M_AA3 7,14 M_AB[5:4] 7,13,14 M_AA[12:6] 7,11,14 7,13,14 7,13,14 11,13,14 M_CS0# M_BS0# M_BS1# M_CB_R[7:0] M_CB_R0 M_CB_R1 M_CB_R2 M_CB_R3 M_CB_R4 M_CB_R5 M_CB_R6 M_CB_R7 M_CKE0, M_CKE1, M_CS0#, M_CS1# are only for LAI support. 3 11 +V3.
A B C D M_DATA_R_[63:0] 4 3 E 11,12,14 M_DATA0 4 RP6G3D 5 10 M_DATA_R_0 M_DATA32 4 RP5G11D5 10 M_DATA_R_32 M_DATA1 3 RP6G3C 6 10 M_DATA_R_1 M_DATA33 3 RP5G11C6 10 M_DATA_R_33 M_DATA2 1 RP6G3A 8 10 M_DATA_R_2 M_DATA34 1 RP5G11A8 10 M_DATA_R_34 M_AA12 7 RP5G14B2 10 M_AA_FR_12 M_DATA3 4 RP6G4D 5 10 M_DATA_R_3 M_DATA35 4 RP4G5D 5 10 M_DATA_R_35 M_AA11 6 RP5G14C3 10 M_AA_FR_11 M_DATA4 4 RP6G1D 5 10 M_DATA_R_4 M_DATA36 8 RP5G6A 1 10 M_DATA_R_36 M_AA10 6 RP5G1C 3 10 M
1 A B C5W26 0.1UF C5H2 0.01UF C6H4 0.01UF C4H4 0.1UF C4W9 0.01UF C5W10 0.01UF C4W13 0.01UF C5W31 0.1UF C6W9 0.1UF C4W12 0.1UF C5W33 0.01UF C5W22 0.01UF C5W37 0.1UF C5W36 0.01UF C5W25 0.01UF C5H1 0.1UF C6W11 0.1UF C6W10 0.01UF C5W39 0.1UF C5W20 0.01UF C5W35 0.1UF C5W13 0.1UF C5W24 0.01UF C4W14 0.1UF C5W38 0.01UF C5W30 0.01UF C4W15 0.01UF C4W11 0.01UF C5W18 0.01UF C6W12 0.1UF C5W23 0.1UF C4W8 0.1UF C4H2 0.1UF C5W27 0.01UF C5W8 0.1UF C5W17 0.1UF C4W7 0.01UF C5W12 0.01UF C5W34 0.01UF C4W5 0.01UF C5W32 0.
A B C D E +V1.5S_DVO 5,19..23,27..29,32,36..39,44,48 7 7 7 J6C1 DVOBD[11:0] DVOBD1 DVOBD0 DVOBD3 DVOBD2 DVOBD5 DVOBD4 DVOBD6 DVOBD9 DVOBD8 DVOBD11 DVOBD10 4 7 DVOBCCLKINT 7 DVOBFLDSTL 7 MDDCDATA 7 DVOCVSYNC 7 DVOCHSYNC 7 DVOCBLANK# DVOCD0 DVOCD1 DVOCD2 DVOCD3 DVOCD4 DVOCD7 DVOCD6 DVOCD9 DVOCD8 DVOCD11 DVOCD10 3 +V1.5S_DVO R7E4 R7E2 8.2K 8.
A B C +V3.3S D 5,6,8,9,11,15,18,20,21,23,26,31,33..36,38..40,42,44,48 +V3.3S_LVDSDDC LVDS Interface R6N5 5,6,8,9,11,15,18,20,21,23,26,31,33..36,38..40,42,44,48 +V3.3S_LVDS R5N6 0.01_1% Q5B2 2 3 LVDS_VDDEN# R5N4 1M 3 J6B1 2.2k 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 +V3.3S_LVDS_PANEL C5N1 C5B6 C5B7 1000PF 0.
A B C C6R2 C6R1 E +V12S +V5S_F_DAC C6R3 F3B1 0.1UF +1 0.1UF R3B1 1K CR3B1 I/O6 I/O5 I/O4 1N4148 R3N1 100K 4.7K U3A1 3 DDC_OE1# 100 1 2 3 4 7,24 DAC_DDCACLK OE1# 1A 1B GND VCC OE2# 2B 2A R3A7 2.2k 0.1UF R3A8 8 7 6 5 FB3A7 50OHM C3A9 DDC_VCC Vn DDC_SRC R3A9 4 1 R3A10 3 I/O1 I/O2 I/O3 8 6 5 3 4 1 2 4 Q3B1 1 DDC_GATE DAC_RED DAC_GREEN DAC_BLUE 2 1.1A 2 0.1UF ESD DIODE ARRAY 1 Vp CR6D1 D 15,23,27,37,44 8,15,16,18,20,23..25,27,34,35,38..40,42,44,47 +V5S +V1.
A B C D 3..5,9,10,20,40,41,47,48 +VCC_IMVP E 5,6,8,9,11,15,16,20,21,23,26,31,33..36,38..40,42,44,48 +V3.3S 21 21,22 21,22 21,23 21,24 2 6 21..24 21..24 22,23 24 19,22,23 24 21..24 22..24 21..23 21..
C 15,18,20,23,27,30,32,35,37..39,43,44 SLP_S1#_D 1 4 6,37,38,44 PM_SLP_S1# PM_SLP_S3# 74AHC1G08 2 3 4,37 +V3.
A B C D U7G2C R7G4 C7W6 C7W15 C7W18 10UF 0.1UF 0.1UF NO_STUFF_0.1UF No Stuff +V1.5_ICHLAN 4 0.01_1% +V3.3 C8G1 C7W7 C7W8 22UF 0.1UF 0.1UF 15,18,19,23,27,30,32,35,37..39,43,44 18 R7G5 VCCSUS1.5_0 VCCSUS1.5_1 VCCSUS1.5_2 VCCSUS1.5_3 VCCSUS1.5_4 VCCSUS1.5_5 VCCSUS1.5_6 VCCSUS1.5_7 F6 F7 VCCLAN1.5_0 VCCLAN1.5_1 E9 F9 VCCLAN3.3_0 VCCLAN3.3_1 E7 V6 VCC5REF1 VCC5REF2 +V3.3_ICHLAN VCC5REF 0.01_1% C7G7 C7W3 C7V3 C7G6 22UF 0.1UF 0.1UF 4.7UF +V5A_ICH 9,15,19,44,47,48 +V1.
B 6 10K 7 10K 19,20 18,37 SM_INTRUDER# R2J4 R8H2 +V5_ALWAYS Generation V5A_PWRGD 8 U4C2 V5A_COSC RUN_SS C4C9 3300pF COSC 2 RUN/SS TG 16 V5A_TG BOOST 15 V5A_BOOST C4C3 1 2 +V5_ALWAYS 1 L4B1 0.47uF 3 V5A_ITH 8 R4C6 37.4k_1% SW ITH VIN SGND 7 VOSENSE 5 6 14 V5A_SW 13 CR4C1 MBR0520LT1 INTVCC 12 SENSE- BG 11 SENSE+ PGND 10 1 C4C11 330pF 100K 2 1 V5A_BG C4P3 C4C6 C4P1 1UF 10UF 0.1UF 2 0.01_1% 5 Q4C1B Si4966DY C4C10 47pF 2 1 4.
A B 23 23,44 C +V12S_PCI 23,44 +V12S_PCI 23 +V5S_PCI 23 +V3.3S_PCI 4 18,21,23 INT_PIRQG# 18,21,23 INT_PIRQE# C7B10 0.01UF SLT1_PRSNT1# C7C1 0.
A B C D 5,15,19..22,27..29,32,36..39,44,48 +V5_PCI 15,17,27,37,44 +V12S Moon ISA support +V12S_PCI Default: 1-2 19 15,18..20,27,30,32,35,37..39,43,44 4 +V3.3S_PCI 3 18,22 PCI_REQA# 22,44 +V3.3PCISLT3 3 PCI_NOGO 22 +V3.3 1 2 1 2 R7B2 0.01_1% J9E4 Default: 1-2 -V12S 1 RP7B1A 8 0 PCI_RSV5 22 Moon ISA support 22 J9E2 E +V3.3ALWAYS CON3_HDR CON3_HDR 1 RP7F4A8 NO_STUFF_0 +V5PCISLT3 +V5PCISLT3 C7B4 C8B2 C7B5 R7C6 PCI_RSV1 0 22 0.1UF R7C3 NO_STUFF_0 0.
A B Qbuffers used for isolation during suspend as well as 5V->3.3V translation U9D2 1 18,22,23 PCI_AD[31:0] PCI_AD22 PCI_AD23 PCI_AD26 PCI_AD27 PCI_AD30 PCI_AD31 PCI_AD29 PCI_AD28 PCI_AD25 PCI_AD24 PCI_AD12 PCI_AD14 PCI_AD15 PCI_AD18 PCI_AD19 PCI_AD21 PCI_AD20 PCI_AD17 PCI_AD16 PCI_AD13 4 C 8,15..18,20,23,25,27,34,35,38..
A B C D J9E3A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 4 17 DOCK_RED 17 DOCK_VSYNC 17 DOCK_HSYNC 24 DOCK_SMBDATA 24 DOCK_CLKRUN# 24 DOCK_REQB# 24 DOCK_PIRQC# 24 DOCK_PIRQB# 24 DOCK_GNT4# GND0 V_DC0 V_DC1 GND1 GND2 RED_RTN RED VSYNC HSYNC GND3 GND4 NC0 SM_DATA SYSACT# CLKRUN# PC_REQ# GND5 CD2 NC1 NC2 CD3#/GND INTD# INTC# GND6 GNT# E J9E3C REQ# GND7 PERR# SERR# GND8 STOP# TRDY# GND9 LOCK# FRAME# GND10 C/BE1# C/BE0# GND11 AD29 AD28 GND12 AD25 AD24 GND13 AD21 AD20 GND14 V_ACD
A B C 19 IDE_PDD[15:0] 4 5,6,8,9,11,15,16,18,20,21,23,31,33..36,38..40,42,44,48 +V3.3S RP2J1C 3 47 BUF_PCI_RST# IDE_D_PRST# R4Y2 18,22..24,31,32,34,37 D PRIMARY HDD CONN J4J2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 IDE_PDD7 IDE_PDD6 IDE_PDD5 IDE_PDD4 IDE_PDD3 IDE_PDD2 IDE_PDD1 IDE_PDD0 6 19 IDE_PDDREQ 19 IDE_PDIOW# 19 IDE_PDIOR# 19 IDE_PIORDY 19 IDE_PDDACK# 18,21,37 INT_IRQ14 19 IDE_PDA1 19 IDE_PDA0 19 IDE_PDCS1# 27,44 IDE_PDACTIVE# 4.
A B C D Secondary IDE Power 8,15..18,20,23..25,34,35,38..40,42,44,47 E 8,15..18,20,23..25,34,35,38..40,42,44,47 +V5S +V5S C2H1 14 U3H1A 0.1UF 34,37 IDE_SPWR_EN# 2 4 IDE_SPWR_EN 74HC14 U3H1E 74HC14 10 IDE_SPWR2_D 11 C2H2 R2H6 390K IDE_SPWR2 2 Note: Primary IDE Power on Turner DC/DC Module 7 8,15..18,20,23..25,34,35,38..40,42,44,47 +V5S U3H1D SHMIDT4 9 SHMIDT2 8 3 IDE_SRST# 4 C2W1 7 5 6 +V5S_IDE_S R2H7 0.01_1% IDE_D_SRST# 26 47 74HC14 0.
A B +V5_ALWAYS C D E 20,21,29 R4B2 +V5_USB1 0.01_1% C4B3 5,15,19..23,27,29,32,36..39,44,48 +V3.3ALWAYS 0.
A B C D E 4 4 5,15,19..23,27,28,32,36..39,44,48 +V5_ALWAYS +V3.3ALWAYS 20,21,28 R6B2 10K R6N2 0.01_1% R6A7 10K USB_OC3# 19 U6B1 +V5_USB2 3 C6A12 R6B3 1K EN_U2 1 2 3 4 0.
A B C +V3.3 D 15,18..20,23,27,32,35,37..39,43,44 4 4 +V3.3_LAN R6A1 Bulk caps should be 4.7uF or higher. 0.01_1% Layout note: Place 100 Ohm resistor close to 82562EM L6A1 1 C6A5 C6A7 C6A10 C6A11 C6A3 C6A2 4.7UF 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 2 +V3.3_L_LAN +V3.3_LAN If LAN is enabled, PM_LANPWROK waits for PM_PWROK to go high and stays high in S3.
A B C D E 4 4 5,6,8,9,11,15,16,18,20,21,23,26,33..36,38..40,42,44,48 +V3.3S +V3.
C9N3 C9M3 0.1UF 0.1UF 0.1UF 3 44,48 SMC_MD CON3_HDR SMC_XTAL SMC_EXTAL +V3.3ALWAYS NO_STUFF_10K SMC_RES# SMC_STBY# R4B4 39 VR_SHUT_DOWN# 3 33 SMC_INITCLK R9A3 19,21,25,37,39 PM_PWROK 44,48 0 Stuff R9A4 only for in-ckt programming +V3.
A B C D E SMC SUSPEND TIMER 32 32 +V3.3ALWAYS_SMCRST R7A1 32 +V3.3ALWAYS_KBC 0 R8A4 1M SMC_INIT_CLK1 SMC_RST 1 7 6 7 U7A4C 74HC04 9 8 C8B1 7 4.7uF SMC_INITCLK 32 4 U7A4D 74HC04 SMC_INIT_CLK4 U7A4A 74HC04 J8A1 1 1 19 KSC_VPPEN# 2 SMC_RST# 32 R8B2 100K NMI Jumper: Shunt J8A1 for SMC Programming Q8A1 BSS138 1 MAX809 SMC_INIT_CLK3 2 2 14 5 U7A4B 74HC04 3 1 4.7K 7 Q8B1 BSS138 2 SMC_RST#_D 2 RST# SMC_INIT_CLK2 4 14 R7A2 14 3 3 0.
A B BUF_PCI_RST# C D E 18,22..24,26,31,32,37 +V5S PPT_PNF# 35 J9G2 8,15..18,20,23..25,27,35,38..40,42,44,47 1 2 SIO_RST# SIO Enable Disable 3 CON3_HDR +V3.3S_SIO J9G2 1-2 (Default) 2-3 1 +V3.
A B 7 9 11 13 15 17 19 21 23 25 27 29 31 33 +V5S J2A1A 7 5 8 7 60OHM@100MHZ FB2A2B PPT_L_PE FB2A2D PPT_L_BUSY/WAIT# FB2A1A PPT_L_ACK# FB2A1B PPT_L_PD7 3 4 1 2 6 5 8 7 60OHM@100MHZ FB2A1C FB2A1D FB3A6A FB3A6B 3 4 1 2 6 5 8 7 60OHM@100MHZ FB3A6C PPT_L_SLIN# FB3A6D PPT_L_PD2 FB3A5A PPT_L_INIT# FB3A5B PPT_L_PD1 6 5 8 5 60OHM@100MHZ FB3A5C PPT_L_ERR# FB3A5D PPT_L_PD0 FB3A4A PPT_L_AFD#/DSTRB# FB3A4D PPT_L_STB#/WRITE# 2 4 1 2 34 PPT_PE 34 PPT_BUSY/WAIT# 34 PPT_ACK# 34 PPT_PD7 PARALLEL PORT 60OHM@
A B C D E +V5_PS2 KBC_SCANOUT[15:0] 32 CBTD has integrated diode for 5V to 3.
A B 15,17,23,27,44 +V12S C D J3H1 LPC POWERED ON SUSPEND RAIL FOR ADD-IN H8 CARD LPC Debug Slot +V3.3_LPCSLOT +V3.3_LPCSLOT 15,17,23,27,44 +V12S J8F1 4 19,33 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 SUS_CLK 5,15,19..23,27..29,32,36,38,39,44,48 +V3.
A B C D E Fan Power Control +V5S Test CAPs C1E2 R1E2 100K U1E1 SI3457DV 0.1UF 22UF TP_220pf2 J1E1 FAN_ON_D TP_330pf1 CR1E1 1N4148 1 2 TP_0.1uf2 TP_0.082uf2 TP_0.082uf1 C8J4 0.082uF C9Y2 100pF TP_BS_0.01uf2 TP_BS_0.01uf1 TP_0.47uf1 2 C9Y4 0.01UF 1 TP_0.47uf2 2 C8J5 TP_BS_0.1uf2 C9Y5 0.1UF TP_BS_0.1uf1 TP_330pf2 2 C9J3 330PF C8J6 0.1UF TP_BS_100pf2 TP_BS_100pf1 1 TP_0.1uf1 Test CAPs backside CONN2_HDR 0.47uF TP_0.01uf1 TP_0.01uf2 C9J1 0.
B C +V3.3ALWAYS Step 2 - VR ON Step 1 - Power OK 2 0.1UF 74AHC1G08 MAIN2_PWROK 2 74AHC1G08 4 PM_PWROK 19,21,25,32,37 U4B4 2 3 1 4 4 2 ON_BOARD_VR_ON 40 74AHC1G08 4 3 OFF_BOARD_VR_ON 3 5 1 21 V5A_PWRGD 0.1UF U4B5 INTERPOSER_PRES# 74AHC1G08 2 32 VR_SHUT_DOWN# U7B1 4 74AHC1G08 +V3.3S Step 3 - Power Good 15,18..20,23,27,30,32,35,37,38,43,44 3 43 DDR_VR_PWRGD C4B4 1 32,37,42 VR_ON +V3.3ALWAYS +V3.3S R4N2 2.2k 0.1UF 3 5,15,19..23,27..29,32,36..38,44,48 C7B2 0.
A B C D E 4 4 20,21,22,23,27,36,37,43,44 +V5 8,15,16,17,18,20,23,24,27,34,35,38,39,44,47 5,6,8,9,11,15,16,18,20,21,23,26,31,33,34,35,36,38,39,44,48 +V5S +V3.3S +VDC 16,21,39,44 +VCC_VID 3 ,093 ,,, 34,39 VR_VID[4:0] 6,19,37,39 PM_STPCPU# 19,37,39 4,39 3 +VCC_IMVP 3,4,5,9,10,18,20,47,48 PM_DPRSLPVR ON_BOARD_VR_PWRGD 39 39 ON_BOARD_VR_ON 9,10,47,48 +V1.2S_GMCH 32,37,39 VR_ON 47 GMCH_VCORE_PWRGD 39 1.2V_EV 2 2 5,6,8,9,11,15,16,18,20,21,23,26,31,33..
A B C D E Processor Decoupling 3..5,9,10,18,20,40,47,48 4 V_CORE Mid and High Frequency Decoupling 3..5,9,10,18,20,40,47,48 3 V_CORE Bulk and Mid Frequency Decoupling Bulk decoupling values are tuned to Intel’s IMVP III 2 phase VR design. Circuits using other converter topologies may have different requirements.
A B C D E 4 4 3 3 %/$1.
A B 20..23,27,36,37,42,44 C D E +V5 BOOT_1 C3G9 C3G8 150uF C3G10 150uF 0.1UF 4 C3G5 47pF VSENSE_1 2 COMP_1 3 C3V2 R3V4 2 COMP_1_D 1 U3G1 24 23 22 21 20 1 4 2 5 25.5k_1% 5600pF RT_1 R3U3 28 27 2 NO_STUFF_10K_1% SS/ENA_1 R3F22 3 R4G1 5.49k_1% V2.5_DDR_D 1 2 VBIAS_1 C3G1 1 CON3_HDR 0.01UF NO_STUFF_10K PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PH8 VSENSE NC/Comp PWRGD 9,11,12 +V2.5 Single point sense near load L4G1 PH_1 1 BOOT RT AGND 4 2 4.7uH C4F1 0.
A B C D E 22,23 HDM conn. is a modulized conn. design in 2 parts. 3 pin power recepticle and a 72 pin recepticle. The 2 parts will be arranged as shown on this schematic page. HDM Connector Assembly (base board) J1B1 A1 A2 A3 A4 16,21,39,40 C8A2 22UF 35V +VDC 15,17,23,27,37 D1 D2 D3 D4 4 -V12S +V12S C2B1 22UF 35V F1 F2 F3 F4 8,15..18,20,23..25,27,34,35,38..40,42,47 3Pin_RECEPTICLE 5,6,8,9,11,15,16,18,20,21,23,26,31,33..36,38..40,42,48 +V5S +V3.3S C7E7 CON3,RCPTL,TH,700000-667.
A B C D E Power On Sequence PM_SLP_S4# 4 +V3.3 5 PM_SLP_S3# 4 +V3.3S 5 +V5S 5 +V5 5 3 2 +V3A PG 20 +V1.5A MAIN_PWROK MAIN2_PWROK PG 39 U7A6 8 PM_PWROK 17 U7B1 3 3 CPU PG 38 SMC PG 3 PG 32 2 +V3A VR_PWRGD_CK408# 9 SMC_PROG_RST# 2 U8A2 SMC_RST# MAX809 PG 33 RST_HDR VR_ON +V2.5 +V1.
A B PS_ON_SW# C SW7J1 4 SMC_SHUTDOWN PCI_RST# BUF_PCI_RST# PWR_PWROK PG 44 SW6 E Reset Map PG 44 DC/DC Turner D U7A3 MASTER_RESET# PCI SLOTS 4 ICH4 PM_PWROK PG22 PG 39 PG 18 PM_RSMRST# PG 40 Core VR PG 39 Q9B3 PG32 R=0 R=0 DOCKING 3 PCI_GATED_RST# LPC SLOT PG 37 3 PG 22 ITP ADD SLOT PG 15 PG 5 U7A4 PG 33 SMC 2 MAX809 PG 33 SMC_RST# U8A2 PG 32 2 SMC_RES# FWH PG 31 PG 32 SMC_PROG_RST# H_CPURST# SIO PG 34 MCH H_PWRGD CPU PG 7 1 1 PG 3 Title Size A A B C Reset Ma
A B C D E REV 4.403 Fab 4 INTEL(R) CELERON(R) M PROCESSOR / INTEL(R) 852GM CHIPSET CUSTOMER REFERENCE BOARD 4 4 Fan Header CPU Thermal Sensor PG 5 PG 38 INTEL(R) CELERON(R) M PROCESSOR 478 uFCPGA ITP CK-408 PG 5 Clocking PG 6 852GM VR IMVP-IV VR PG 43 PG 39,40,41 PG 11 PG 16 732 uFCBGA USB4 PG 22 PG 22 PG 23 ATA 100 33MHz PCI 421 BGA USB 2.
A B C D E CUSTOMER REFERENCE PLATFORM SCHEMATIC ANNOTATIONS AND BOARD INFORMATION 2 Voltage Rails I C / SMB Addresses Default Jumper Settings 4 3 4 +VDC +VCC_CORE +VCCP +V1.8S +V1.25S +V1.35S +V1.5S +V1.5ALWAYS +V1.5 +V2.5 +V3.3ALWAYS +V3.3 +V3.3S +V5ALWAYS +V5 +V5S +V12S -V12S Primary DC system power supply (10 to 21V) Core voltage for processor 1.05V rail for processor PSB, 852GM PSB 1.8V for processor PLL and VID circuitry 1.25V DDR Termination voltage 1.35V for 852GM core 1.
A H_ADS# H_BNR# H_BPRI# DEFER# DRDY# DBSY# L4 H2 M2 H_DEFER# 8 H_DRDY# 8 H_DBSY# 8 BR0# N4 IERR# INIT# A4 B5 LOCK# J2 H_ADSTB#1 AF4 AC4 AC7 AC3 AD3 AE4 AD2 AB4 AC6 AD5 AE2 AD6 AF3 AE1 AF1 AE5 H_A20M# H_FERR# H_IGNNE# C2 D3 A3 A20M# FERR# IGNNE# H_STPCLK# H_INTR H_NMI H_SMI# C6 D1 D4 B4 STPCLK# LINT0 LINT1 SMI# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# ADSTB#1 HIT# HITM# H_BR0# 8 8 8 +VCCP 4,5,9,18..
A B C D E One 0.01uF & 10uF cap for each VCCA pin. NO_STUFF 3 resistors of VCCA pins for CeleronM B0 support and no stuff 6caps of those 3 pins 40..42,46,51 +VCC_CORE 40..42,46,51 +VCC_CORE C3E1 C3E2 10UF 0.
A B C D E CPU Thermal Sensor +V3.3S 4 R2B4 R2B5 1K 1K 4 C2B2 0.1UF +V3.3S 2 3,6,8,9,11,15..18,20,21,23,26,31,33..36,38..40,43,45,51 Address Select Straps Current Address: 1001 110x RP2B1D 10K 3 3,6,8,9,11,15..18,20,21,23,26,31,33..36,38..
A B J3F1 NO_STUFF_SMA CON 4 Place crystal within 500 mils of CK_408 R3F18 NO_STUFF_0 Place 0ohm near crystal. 14.318MHZ Y3F1 C3F2 NO_STUFF_10pF NO_STUFF_10pF 1UF R3F3 C2U4 0.1UF C2U6 0.1UF C2U1 0.1UF C2F2 22UF 1 8 14 19 32 37 46 50 +V3.
A B C 13 M_CB[7:0] M_AA0 M_AA1 M_AA2 M_AA3 M_AA4 M_AA5 M_AA6 M_AA7 M_AA8 M_AA9 M_AA10 M_AA11 M_AA12 M_AA0 12..14 8,9,51 M_AA[2:1] 11,14 AD16 AC12 AF11 AD10 M_AB1 M_AB2 M_AB4 M_AB5 M_AA[12:6] 12..14 SMA_B1 SMA_B2 SMA_B4 SMA_B5 SCKE0 SCKE1 SCKE2 SCKE3 SCS0# SCS1# SCS2# SCS3# AC7 AB7 AC9 AC10 AD23 AD26 AC22 AC25 M_AB[5:4] M_CKE0 M_CKE1 M_CKE2 M_CKE3 M_CS0# M_CS1# M_CS2# M_CS3# 12,14 11,12,14 11,12,14 12,14 12,14 11,12,14 11,12,14 12,14 12,14 SBA0 SBA1 AD22 AD20 M_BS0# M_BS1# 12..14 12..
C 3 H_REQ#[4:0] H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 3 Layout Note: MCH_HXSWING and MCH_HYSWING should be 10mil traces with 20mil spacing 3 3 H_ADSTB#0 H_ADSTB#1 6 CLK_MCH_BCLK# 6 CLK_MCH_BCLK 10 MCH_HYRCOMP 10,46 MCH_HYSWING 10 MCH_HXRCOMP 10,46 MCH_HXSWING 3 3 3 0.1UF 0.
A B 2 1 VSS 3 VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS8
A B C D E LAI Hub Interface GMCH Compensation & Reference Voltages 8,18 HUB_PD[10:0] NO_STUFF_HUBLINK Layout Note: Route MCH_HXSWING & MCH_HYSWING w/ 10 mil trace & 20 mil space 9 +VCCP_VTTLF Host 4 J6U1 HUB_PD0 HUB_PD2 R5R9 301_1% 9 +VCCP_VTTLF HUB_PD4 R4T1 301_1% 150_1% 392_1% LAI_HUB_PIN6 LAI_HUB_PIN10 R6F1 392_1% R5R10 8,46 MCH_HXSWING R6E8 R6F12 LAI_HUB_PIN18 392_1% R4E2 8,46 MCH_HYSWING R6F10 150_1% 9 +VCCP_VTTLF 8,18 HUB_PSTRB# R5D2 R5T2 49.
A B C D E 3,5,6,8,9,15..18,20,21,23,26,31,33..36,38..40,43,45,51 +V3.3S 12 R4W1 +V3.3S_SPD 0.01_1% Power plane for Serial Presence Detect logic 12..14 M_DATA_R_[63:0] 4 13 M_AA_FR_0 7,14 M_AA[2:1] 13 M_AA_FR_3 7,14 M_AA[5:4] 13 M_AA_FR_[12:6] 13 M_BS0_FR# 13 M_BS1_FR# 12..
A B C D E 11,13,14 M_DATA_R_[63:0] M_AA0 M_AB1 M_AB2 7,13,14 M_AA0 4 7,14 M_AB[2:1] M_AA3 M_AB4 M_AB5 M_AA6 M_AA7 M_AA8 M_AA9 M_AA10 M_AA11 M_AA12 7,13,14 M_AA3 7,14 M_AB[5:4] 7,13,14 M_AA[12:6] 7,11,14 7,13,14 7,13,14 11,13,14 M_CS0# M_BS0# M_BS1# M_CB_R[7:0] M_CB_R0 M_CB_R1 M_CB_R2 M_CB_R3 M_CB_R4 M_CB_R5 M_CB_R6 M_CB_R7 M_CKE0, M_CKE1, M_CS0#, M_CS1# are only for LAI support. 3 11 +V3.
A B C D E M_DATA_R_[63:0] 11,12,14 4 3 M_DATA_R_0 M_DATA32 4 RP5G11D 5 10 M_DATA_R_32 3 RP6G3C 6 10 M_DATA_R_1 M_DATA33 3 RP5G11C 6 10 M_DATA_R_33 1 RP6G3A 8 10 M_DATA_R_2 M_DATA34 1 RP5G11A8 10 M_DATA_R_34 4 RP6G4D 5 10 M_DATA_R_3 M_DATA35 4 RP4G5D 5 10 4 RP6G1D 5 10 M_DATA_R_4 M_DATA36 8 RP5G6A 1 10 M_DATA5 3 RP6G1C 6 10 M_DATA_R_5 M_DATA37 7 RP5G6B 2 10 M_DATA6 1 RP6G1A 8 10 M_DATA_R_6 M_DATA38 M_DATA7 4 RP6G2D 5 10 M_DATA_R_7 M_DATA39 M_DATA8 3 RP6G4C 6 10 M_
1 A B 56 C5W26 0.1UF C5H2 0.01UF C6H4 0.01UF C4H4 0.1UF C4W9 0.01UF C5W10 0.01UF C4W13 0.01UF C5W37 0.1UF C6W9 0.1UF C4W12 0.1UF C5W39 0.01UF C5W22 0.01UF C5W33 0.1UF C5W32 0.01UF C5W25 0.01UF C5H1 0.1UF C6W11 0.1UF C6W10 0.01UF C5W35 0.1UF C5W20 0.01UF C5W31 0.1UF C5W13 0.1UF C5W24 0.01UF C4W14 0.1UF C5W34 0.01UF C5W36 0.01UF C4W15 0.01UF C4W11 0.01UF C5W18 0.01UF C6W12 0.1UF C5W23 0.1UF C4W8 0.1UF C4H2 0.1UF C5W27 0.01UF C5W7 0.1UF C5W17 0.1UF C4W7 0.01UF C5W12 0.01UF C5W30 0.01UF C4W5 0.
A B C D E +V1.5S_DVO 5,19..23,27..29,32,36..39,45,51 7 DVOBD[11:0] J6C1 DVOBD1 DVOBD0 DVOBD3 DVOBD2 DVOBD5 DVOBD4 DVOBD6 DVOBD9 DVOBD8 DVOBD11 DVOBD10 4 7 DVOBCCLKINT 7 DVOBFLDSTL 7 MDDCDATA 7 DVOCVSYNC 7 DVOCHSYNC 7 DVOCBLANK# DVOCD0 DVOCD1 DVOCD2 DVOCD3 DVOCD4 DVOCD7 DVOCD6 DVOCD9 DVOCD8 DVOCD11 DVOCD10 3 +V1.5S_DVO R7E4 R7E2 8.2K 8.
A B C +V3.3S D 3,5,6,8,9,11,15,17,18,20,21,23,26,31,33..36,38..40,43,45,51 +V3.3S_LVDSDDC LVDS Interface R6N5 3,5,6,8,9,11,15,17,18,20,21,23,26,31,33..36,38..40,43,45,51 +V3.3S_LVDS R5N6 0.01_1% Q5B2 2 3 LVDS_VDDEN# R5N4 1M 3 C5N1 C5B6 C5B7 1000PF 0.
A B C6R2 C6R1 E +V12S +V5S_F_DAC C6R3 F3A1 I/O6 I/O5 I/O4 8 6 5 R4A1 1K 1N4148 DDC_GATE C3A9 0.1UF 3 DDC_OE1# 100 1 2 3 4 7,24 DAC_DDCACLK OE1# 1A 1B GND Q3B1 VCC OE2# 2B 2A 4 1 DDC_SRC R3A7 2.2k R3A8 8 7 6 5 2 1.1A 1 R3A10 4.7K U3A1 R3A9 +1 R4A2 100K 3 I/O1 I/O2 I/O3 CR4B1 2 0.1UF FB3A7 50OHM 3 0.1UF 1 0.1UF ESD DIODE ARRAY Vn 4 1 2 4 D 15,23,27,37,45 8,15,16,18,20,23..25,27,34,35,38..41,43,45,46 +V5S DDC_VCC Vp CR6D1 DAC_RED DAC_GREEN DAC_BLUE C +V1.
B C D 3..5,9,19,20,40,42,43,46 22..24 22..24 22..24 22..
PM_SLP_S3# PM_SLP_S4# PM_SLP_S5# PM_STPCPU# PM_STPPCI# SUS_CLK PM_SUS_STAT# PM_THRM# SLP_S1#_D 5 1 4 6,37,38,45 PM_SLP_S1# PM_SLP_S3# 74AHC1G08 2 R6H11 4 37 +V3.3S_ICH 3 SLP_S1# R6V2 NO_STUFF_1K AC_SPKR R7V7 NO_STUFF_10K AC_SDATAOUT R7V8 NO_STUFF_1K Board Default Optional Override R6V2 No Reboot NO STUFF STUFF for No Reboot R7V7 Safe Mode Boot NO STUFF 3 R7V8 A16 swap override NO STUFF R7V9 Reserved NO STUFF STUFF for safe mode STUFF for A16 swap override 0.
A B C D U7G2C +V1.5 R7G4 C6G1 C7W6 C7W15 C7W18 10UF 0.1UF 0.1UF NO_STUFF_0.1UF No Stuff +V1.5_ICHLAN 4 0.01_1% +V3.3 C8G1 C7W7 C7W8 22UF 0.1UF 0.1UF E12 E13 E20 F14 G18 R6 T6 U6 VCCSUS1.5_0 VCCSUS1.5_1 VCCSUS1.5_2 VCCSUS1.5_3 VCCSUS1.5_4 VCCSUS1.5_5 VCCSUS1.5_6 VCCSUS1.5_7 F6 F7 VCCLAN1.5_0 VCCLAN1.5_1 E9 F9 VCCLAN3.3_0 VCCLAN3.3_1 E7 V6 VCC5REF1 VCC5REF2 15,18,19,23,27,30,32,35,37,38,44,45 18 R7G5 +V3.3_ICHLAN VCC5REF 0.01_1% C7G7 C7W3 C7V3 C7G6 22UF 0.1UF 0.1UF 4.
B C 20,37 +V3.3ALWAYS_ICH 6 10K 7 10K +V3.3ALWAYS 19,20,22,24,37 +V3.3S_ICH V5A_PWRGD 8 RUN_SS C4C10 47pF C4C11 3300pF 1 COSC 2 RUN/SS TG 16 V5A_TG BOOST 15 V5A_BOOST Q4C1A SI4966DY 2 Layout: CR4B2 needs to be placed close to U4C1 & Q4C1 C4C5 V5A_ITH R4C6 37.4k_1% 14 V5A_SW VIN 13 CR4C1 MBR0520LT1 INTVCC 12 V5A_INTVCC SW ITH 8 SGND 7 VOSENSE L4B1 5 SENSE- BG 11 6 SENSE+ PGND 10 1 6 R4C1 2 4.7uH Q4C1B SI4966DY 1 V5A_BG C4P3 C4C8 C4P1 1UF 10UF 0.1UF 0.
A B 23 23,45 C +V12S_PCI 23,45 23 23 +V5_PCI 4 18,21,23 INT_PIRQG# 18,21,23 INT_PIRQE# C7B10 0.01UF SLT1_PRSNT1# C7C1 0.
A B C D 5,15,19..22,27..29,32,36..39,45,51 +V5_PCI 15,17,27,37,45 +V12S Moon ISA support Default: 1-2 19 15,18..20,27,30,32,35,37,38,44,45 4 +V3.3S_PCI 3 18,22 PCI_REQA# 22,45 +V3.3PCISLT3 3 PCI_NOGO 22 1 2 1 2 R7B2 0.01_1% J9E4 Default: 1-2 -V12S CON3_HDR CON3_HDR +V3.3 1 RP7B1A 8 0 PCI_RSV5 22 +V12S_PCI Moon ISA support 22 J9E2 E +V3.3ALWAYS 1 RP7F4A8 NO_STUFF_0 +V5PCISLT3 +V5PCISLT3 C7B4 C8B2 C7B5 10UF 0.1UF 0.1UF R7C6 PCI_RSV1 0 +V3.
A B C Qbuffers used for isolation during suspend 8,15..18,20,23,25,27,34,35,38..
A B C D J9E3A 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 17 DOCK_RED 17 DOCK_VSYNC 17 DOCK_HSYNC 24 DOCK_SMBDATA 24 DOCK_CLKRUN# 24 DOCK_REQB# 24 DOCK_PIRQC# 24 DOCK_PIRQB# 24 DOCK_GNT4# GND0 V_DC0 V_DC1 GND1 GND2 RED_RTN RED VSYNC HSYNC GND3 GND4 NC0 SM_DATA SYSACT# CLKRUN# PC_REQ# GND5 CD2 NC1 NC2 CD3#/GND INTD# INTC# GND6 GNT# E J9E3C REQ# GND7 PERR# SERR# GND8 STOP# TRDY# GND9 LOCK# FRAME# GND10 C/BE1# C/BE0# GND11 AD29 AD28 GND12 AD25 AD24 GND13 AD21 AD20 GND14 V_AC
A B C R4Y2 BUF_PCI_RST# 19 IDE_PDD[15:0] 4 3,5,6,8,9,11,15..18,20,21,23,31,33..36,38..40,43,45,51 +V3.3S RP2J1C 3 E 47 IDE_D_PRST# 18,22..24,31,32,34,37 D PRIMARY HDD CONN J4J2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 IDE_PDD7 IDE_PDD6 IDE_PDD5 IDE_PDD4 IDE_PDD3 IDE_PDD2 IDE_PDD1 IDE_PDD0 6 19 IDE_PDDREQ 19 IDE_PDIOW# 19 IDE_PDIOR# 19 IDE_PIORDY 19 IDE_PDDACK# 18,21,37 INT_IRQ14 19 IDE_PDA1 19 IDE_PDA0 19 IDE_PDCS1# 27,45 IDE_PDACTIVE# 4.
A B C D Secondary IDE Power 8,15..18,20,23..25,34,35,38..41,43,45,46 E 8,15..18,20,23..25,34,35,38..41,43,45,46 +V5S +V5S C2H1 14 U3H1A 0.1UF 2 4 R2H5 1M 14 1 34,37 IDE_SPWR_EN# IDE_SPWR_EN 11 C2H2 R2H6 390K IDE_SPWR2 1 1000PF 3 U2H1A SI4925DY 2 U2H1B SI4925DY 4 R2H1 NO_STUFF_0 4 7 74HC14 U3H1E 74HC14 10 IDE_SPWR2_D Note: Primary IDE Power on Turner DC/DC Module 7 +V5S_IDE_S 8,15..18,20,23..25,34,35,38..
A B +V5_ALWAYS C D E 20,21,29 R4B2 +V5_USB1 0.01_1% C4B3 5,15,19..23,27,29,32,36..39,45,51 +V3.3ALWAYS 0.
A B C D E 4 4 5,15,19..23,27,28,32,36..39,45,51 +V5_ALWAYS +V3.3ALWAYS 20,21,28 R6B2 10K R6N2 0.01_1% R6A7 10K USB_OC3# 19 U6B1 +V5_USB2 C6A12 3 R6B3 1K EN_U2 0.
A B +V3.3 C D 15,18..20,23,27,32,35,37,38,44,45 4 4 +V3.3_LAN R6A1 0.01_1% Bulk caps should be 4.7uF or higher. Layout note: Place 100 Ohm resistor close to 82562EM L6A1 +V3.3_L_LAN C6A5 C6A7 C6A10 C6A11 C6A3 C6A2 4.7UF 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF +V3.3_LAN 3 R6A6 10K If LAN is enabled, PM_LANPWROK waits for PM_PWROK to go high and stays high in S3.
A B C D E 4 4 3,5,6,8,9,11,15..18,20,21,23,26,33..36,38..40,43,45,51 +V3.3S +V3.
3 SMC_XTAL SMC_EXTAL +V3.3ALWAYS 5,15,19..23,27..29,36..39,45,51 NO_STUFF_10K SMC_RES# SMC_STBY# R4B5 3 39 VR_SHUT_DOWN# 33 SMC_INITCLK R9A3 19,21,25,37,39 PM_PWROK 0 Stuff R9A4 only for in-ckt programming 5,15,19..23,27..29,36..39,45,51 +V3.
A B C D E SMC SUSPEND TIMER 32 +V3.3ALWAYS_KBC +V3.3ALWAYS_SMCRST R7A1 +V3.3ALWAYS_KBC 0 14 R8A4 1M R7A2 7 7 U7A4C 74HC04 8 C8B1 7 4.7uF SMC_INITCLK 32 4 U7A4D 74HC04 SMC_INIT_CLK4 U7A4A 74HC04 2 4.7K J8A1 Q8A1 BSS138 1 MAX809 Q8B1 BSS138 SMC_RST 1 2 SMC_INIT_CLK3 9 6 U7A4B 74HC04 3 1 2 SMC_RST#_D 2 7 14 SMC_INIT_CLK2 5 4 14 RST# 14 SMC_INIT_CLK1 3 3 0.1UF 3 GND 32 C8A5 U7A2 VCC 4 +V3.
A B C D E BUF_PCI_RST# 18,22..24,26,31,32,37 SIO Enable Disable 1 +V3.3S_SIO RP8G1A 1 8 10K GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 85 84 83 82 5 NC 65 3,5,6,8,9,11,15..18,20,21,23,26,31,33,35,36,38..40,43,45,51 PC87393 +V3.3S +V3.3S_SIO +V3.3S_SIO +V3.3S_SIO EV GPIO Strapping options R8G6 0.01_1% C8U6 C8U5 C8F2 0.1UF 0.1UF 22UF R8G3 NO_STUFF_4.
A B 7 9 11 13 15 17 19 21 23 25 27 29 31 33 +V5S J2A1A 7 5 8 7 60OHM@100MHZ PPT_L_PE FB2A2B PPT_L_BUSY/WAIT# FB2A2D FB2A1A PPT_L_ACK# FB2A1B PPT_L_PD7 3 4 1 2 6 5 8 7 60OHM@100MHZ FB2A1C FB2A1D FB3A6A FB3A6B 3 4 1 2 6 5 8 7 60OHM@100MHZ FB3A6C PPT_L_SLIN# FB3A6D PPT_L_PD2 FB3A5A PPT_L_INIT# FB3A5B PPT_L_PD1 6 5 1 4 60OHM@100MHZ FB3A5C PPT_L_ERR# FB3A5D PPT_L_PD0 FB3A4A PPT_L_AFD#/DSTRB# FB3A4D PPT_L_STB#/WRITE# 2 4 1 2 34 PPT_PE 34 PPT_BUSY/WAIT# 34 PPT_ACK# 34 PPT_PD7 PARALLEL PORT 60OHM@
A B C D E +V5_PS2 KBC_SCANOUT[15:0] 32 CBTD has integrated diode for 5V to 3.
A B 15,17,23,27,45 +V12S C D J3H1 +V3.3_LPCSLOT 15,17,23,27,45 +V12S J8F1 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 19,33 SUS_CLK 5,15,19..23,27..29,32,36,38,39,45,51 +V3.
A B C D E Fan Power Control 8,15..18,20,23..25,27,34,35,39..41,43,45,46 +V5S Test CAPs 0.1UF 22UF TP_220pf2 J1E1 FAN_ON_D TP_330pf1 CR1E1 1N4148 1 2 4 C8J7 220PF TP_330pf2 C9J3 330PF TP_0.1uf1 Test CAPs backside CONN2_HDR TP_BS_100pf1 Q1E1 BSS138 1 FAN_ON U1E1 SI3457DV C1E2 TP_0.1uf2 C8J6 0.1UF TP_BS_100pf2 TP_BS_0.01uf1 C8J4 0.082uF TP_BS_0.01uf2 TP_0.47uf1 C9Y4 0.01UF 0.47uF TP_0.01uf2 TP_0.01uf1 C9J1 0.01UF TP_BS_220pf2 TP_BS_220pf1 3 TP_0.47uf2 C8J5 TP_BS_0.
B 20 V1.5_PWRGD 2 U7A5 4 0.1UF MAIN2_PWROK 2 74AHC1G08 4 PM_PWROK 19,21,25,32,37 U4B4 C7B1 3 +V3.3ALWAYS 0.1UF 2.2k U4B5 INTERPOSER_PRES# 4 2 4 OFF_BOARD_VR_ON 3 3 4 2 ON_BOARD_VR_ON 40,41 74AHC1G08 74AHC1G08 5 U7B1 1 74AHC1G08 3,5,6,8,9,11,15..18,20,21,23,26,31,33..36,38,40,43,45,51 +V3.3S Step 3 - Power Good 3 21 V5A_PWRGD 0.1UF 1 4 2 32 VR_SHUT_DOWN# 0.1UF 44 DDR_VR_PWRGD C4B6 1 43 CORE_VR_ON 3 5,15,19..23,27..29,32,36..
A B C D 3..5,9,18..20,42,46 E +VCCP R1F13 1K 5,6,8,9,11,15..18,20,21,23,26,31,33..36,38,39,45 4 +V3.3S 4 VR_VID_N 8,15..18,20,23..25,27,33..35,38,39,45,46 R1F14 1K 39 C1F4 0.
5 4 3 2 1 D D C C Blank B B A A Title Size Project: Document Number B Intel Celeron M / 852GM CRB C26116 of Wednesday, January 12, 2005 41 Date: Sheet 5 4 3 2 1 Rev 4.
5 4 3 2 1 VCore HF and Bulk Decoupling D 4,40,41,46,51 C3R12 10UF 20% 4,40,41,46,51 This solution will allow any of the decoupling options. caps should NOT be stuffed at the same time.
5 4 3 2 1 +VDC 16,21,39,41,45 VDC_VTTVR R5C1 .002 5% R6C5 .002 +VDC_MCHVR 5% C6C8 C5C6 10UF D 5..18,20,23..25,27,34,35,38..41,45,46 10UF +V5S D +V5S_VTTMCH 1 .002 5% 1 R6C3 CR5C1 CR6C1 C5C5 4.7UF 3 BAT54WT1 3 BAT54WT1 0 C5C4 0.15UF 6225_LG1 3 4 NO_STUFF_102276-100 C 6225_PH1 TP5C1 6225_UG1 Q5C1B SI4966DY 3..5,9,18..20,40,42,46 +VCCP 5 L5C2 1 4.7uH 6225_BOOT1 6 R5P11 2K_1% 2 32,37 R5P5 1.
A B 20..23,27,36,37,45 C D E +V5 BOOT_1 C3G9 C3G8 C3G10 150uF 150uF 0.1UF 4 24 23 22 21 20 VSENSE_1 2 COMP_1 C3G5 47pF C3V2 R3V4 COMP_1_D 5600pF 25.5k_1% RT_1 R3U2 2 NO_STUFF_10K_1% SS/ENA_1 J3G2 R3F22 C3G1 3 R4G1 5.49k_1% V2.5_DDR_D VBIAS_1 CON3_HDR 1 0.022uF U3G1 0.01UF NO_STUFF_10K VIN0 VIN1 VIN2 VIN3 TPS54610 VIN4 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PH8 VSENSE 3 NC/Comp 4 PWRGD 5 BOOT 28 RT 27 FSEL 6 7 8 9 10 11 12 13 14 9,11,12 +V2.
A B C D HDM Connector Assembly (base board) E 22,23 HDM conn. is a modulized conn. design in 2 parts. 3 pin power recepticle and a 72 pin recepticle. The 2 parts will be arranged as shown on this schematic page. J1B1 A1 A2 A3 A4 16,21,39,41,43 C8A2 22UF 35V +VDC 15,17,23,27,37 D1 D2 D3 D4 4 +V12S C7B3 22UF 35V F1 F2 F3 F4 8,15..18,20,23..25,27,34,35,38..41,43,46 3,5,6,8,9,11,15..18,20,21,23,26,31,33..36,38..40,43,51 3Pin_RECEPTICLE 4 -V12S +V5S +V3.3S C7E7 CON3,RCPTL,TH,700000-667.
A B 3..5,9,18..20,40,42,43 C +VCCP D 9 +V2.5_GMCH_TXLVDS F8H1 2 R8J14 R8H3 10K PSMI# J8J1 4 R8J16 SMA_CONN 5 2 3 4 3 1K SMA_CONN_D 1 1 1 R8J15 J8J3 NO_STUFF_SMA CON Q8J5 2N3904 2 0 J8H1 +2.5V_EVMC_IN +2.5V_EVMC_SENSE 18 GND_DDR R8J12 Layout Note: Resistors: R3G4,R6T6,R6P4,R4D1,R6R1, R5T3,R5R11,R5P8,R4G2,R3G8,R4E3,R6W11, R3G1,R1C2 should be placed by the risistor divider networks not near the EVMC slot. +2.
A B C D E Power On Sequence PM_SLP_S4# 4 +V3.3 5 PM_SLP_S3# 4 +V3.3S 5 +V5S 5 +V5 5 PG 45 3 2 +V3A PG 20 +V1.5A 7 MAIN_PWROK MAIN2_PWROK PG 39 U7A5 8 PM_PWROK GMCH PG 7 17 PG 39 U7B1 3 3 CPU PG 39 SMC PG 3 PG 32 2 +V3A VR_PWRGD_CK408# 9 SMC_PROG_RST# SMC_RST# MAX809 PG 33 2 U8A2 RST_HDR PG 32 +V5A VR PG 21 +V5_ALWAYS CK-408 PG 6 16 VR_ON +V2.5 +V1.
A B PS_ON_SW# C SW8J1 4 SMC_SHUTDOWN PCI_RST_SLOTS# PCI_RST# PWR_PWROK PG 45 U7A5 MASTER_RESET# SW7J1 E Reset Map PG 45 DC/DC Turner D PCI SLOTS 4 ICH4 PM_PWROK PG 22 PG 39 PG 19 PM_RSMRST# PG 45 Core VR PG 41 Q9B3 PCI_GATED_RST# PG32 R=0 DOCKING 3 ITP R=0 LPC SLOT PG 37 3 U9C1 QSW PG 24 PG 25 ADD CONN PG 5 PG 15 U87A4A PG 33 SMC 2 MAX809 PG 33 SMC_RST# U8A2 PG 32 2 SMC_RES# FWH PG 31 PG 32 SMC_PROG_RST# H_CPURST# SIO PG 34 MCH H_PWRGD CPU PG 8 1 1 PG 3 Titl
