Design Guide

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Intel

855GM/855GME Chipset Platform

Design Guide

May 2004

Document Number: 252616-004

Summary of content (362 pages)

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R ® Intel 855GM/855GME Chipset Platform Design Guide May 2004 Document Number: 252616-004
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R Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
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R Contents 1. 2. 3. 4. Introduction .................................................................................................................................21 1.1. Referenced Documents .................................................................................................23 System Overview........................................................................................................................25 2.1. Platform Component Features............................................
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R 4.1.4.8. Voltage Translation Logic ............................................................... 55 Processor RESET# Signal ............................................................................ 55 4.1.5.1. Processor RESET# Routing Example............................................ 57 4.1.6. Processor and GMCH Host Clock Signals .................................................... 57 4.1.7. Processor GTLREF Layout and Routing Recommendations........................ 58 4.1.8.
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R 7. 6.3.5.2. Control Signal Routing Guidelines ..................................................93 6.3.5.3. Control to Clock Length Matching Requirements ...........................94 6.3.5.4. Memory Control Routing Example ..................................................96 6.3.5.5. Control Group Package Length Table ............................................97 6.3.6. Command Signals – SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE#.......97 6.3.6.1. Command Topology 1...................................
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R 8. 9. 6 7.3.5.3. Control to Clock Length Matching Requirements......................... 143 7.3.5.4. Control Group Package Length Table.......................................... 144 7.3.6. Command Signals – SMAA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE#.. 145 7.3.6.1. Command Topology ..................................................................... 145 7.3.6.2. Command Topology Routing Guidelines...................................... 148 7.3.6.3. Command Topology Length Matching Requirements.......
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R 9.2.5. 9.2.6. 9.2.7. 9.2.8. 9.2.9. 10. 11. AGP Interface Package Lengths..................................................................183 AGP Routing Ground Reference .................................................................184 Pull-ups ........................................................................................................184 AGP VDDQ and VCC...................................................................................186 VREF Generation for AGP 2.0 (2X and 4X).......
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R 11.5. 11.6. 11.7. 11.8. 11.9. 8 11.4.6. USB Selective Suspend............................................................................... 211 I/O APIC (I/O Advanced Programmable Interrupt Controller) ..................................... 212 SMBus 2.0/SMLink Interface....................................................................................... 212 11.6.1. SMBus Architecture and Design Considerations ........................................ 214 11.6.1.1. SMBus Design Considerations......
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R 11.9.6.1.3. 12. 13. Magnetics Module General Power and Ground Plane Considerations ............................................................234 11.9.6.2. Common Physical Layout Issues..................................................236 11.10. Power Management Interface......................................................................................237 11.10.1. SYS_RESET# Usage Model........................................................................237 11.10.2. PWRBTN# Usage Model .......
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R 13.5.2.5. 14. 15. 16. 10 DDR SMRCOMP and VTT 1.25-V Supply Disable in S3/Suspend .................................................................................. 269 13.5.3. Other GMCH Reference Voltage and Analog Power Delivery .................... 269 13.5.3.1. GMCH GTLVREF ......................................................................... 269 13.5.3.2. GMCH AGTL+ I/O Buffer Compensation ..................................... 270 13.5.3.3. GMCH AGTL+ Reference Voltage .....................
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R 17. 16.7.3. AGP_BUSY# Design Requirement..............................................................303 16.7.4. (SMBus) System Management Interface .....................................................303 16.7.5. AC ’97 Interface ...........................................................................................304 16.7.6. ICH4-M Power Management Interface ........................................................305 16.7.7. FWH/LPC Interface .....................................................
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R Figures Figure 1. Intel Pentium M Processor and Intel 855GM Chipset Block Diagram...................... 26 Figure 2. Intel Pentium M, Intel Pentium M Processor on 90 nm Process with 2 MB L2 Cache, Intel Celeron M Processor and 855GME Chipset System Block Diagram .............. 30 Figure 3. Recommended Board Stack-Up Dimensions........................................................... 34 Figure 4. Trace Spacing vs. Trace to Reference Plane Example............................................ 38 Figure 5.
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R Figure 50. Command per Clock Signal Routing Topology .................................................... 112 Figure 51. CPC Signals to Clock Length Matching Diagram ................................................ 114 Figure 52. DDR Memory Thermal Sensor Placement........................................................... 118 Figure 53. Recommended Device Order for Micro-DIMM/Memory Down Combination...... 120 Figure 54. DDR Clock Routing to Micro-DIMM ....................................................
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R Figure 101. USBRBIAS Connection ...................................................................................... 208 Figure 102. Good Downstream Power Connection ............................................................... 210 Figure 103. Common Mode Choke Schematic...................................................................... 210 Figure 104. SMBUS 2.0/SMLink Protocol.............................................................................. 213 Figure 105.
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R Figure 154. DPMS Clock Implementation ............................................................................. 297 Figure 155. Single or Locally Generated GMCH and ICH4-M HIVREF/HI_VSWING Circuit 307 Figure 156. Single Generated GMCH and ICH4-M VSWING/VREF Reference Voltage/ Local Voltage Divider Circuit for VSWING/VREF............................................................ 307 Figure 157. External Circuitry for the RTC ...........................................................................
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R Tables Table 1. Conventions and Terminology ................................................................................... 21 Table 2. Processor System Bus Common Clock Signal Internal Layer Routing Guidelines... 39 Table 3. Processor and GMCH PSB Common Clock Signal Package Lengths and Minimum Board Trace Lengths ................................................................................................ 40 Table 4.
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R Table 46. Data Signal Group Routing Guidelines ................................................................. 132 Table 47. SDQ/SDM to SDQS Mapping................................................................................ 135 Table 48. DDR SDQ/SDM/SDQS Package Lengths............................................................. 137 Table 49. Control Signal to Micro-DIMM/Memory Down Mapping........................................ 139 Table 50. Control Signal Routing Guidelines ...................
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R Table 97. Intel 82562ET/EM Control Signals......................................................................... 232 Table 98. Individual Clock Breakdown................................................................................... 239 Table 99. Host Clock Group Routing Constraints.................................................................. 242 Table 100. Clock Package Length ......................................................................................... 243 Table 101.
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R Revision History Revision Number Description Revision Date 001 Initial Release March 2003 002 Updates Include: September 2003 • Added 855GME design guidelines 003 Updates Include: January 2004 • Added Intel Celeron M processor support 004 Updates include: May 2004 • Added section 7 Memory Down/Micro-DIMM design guidelines • Added section 9 AGP Port Design guidelines ® ® • Added support for Intel Pentium M on 90 nm Process with 2 MB L2 Cache Intel® 855GM/855GME Chipset Platform Design Gu
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R This page intentionally left blank 20 Intel® 855GM/855GME Chipset Platform Design Guide
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Introduction R 1. Introduction This design guide provides Intel’s design recommendations for the Intel 855GM/855GME chipset based systems. The guidelines have been developed to ensure maximum flexibility for board designers while reducing the risk of board related issues. Table 1.
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Introduction R Convention/Terminology Definition components can communicate 22 SPD Serial Presence Detect STD Suspend-To-Disk STR Suspend-To-Ram TCO Total Cost of Ownership TDM Time Division Multiplexed UBGA Micro Ball Grid Array USB Universal Serial Bus VRM Voltage Regulator Module Intel® 855GM/855GME Chipset Platform Design Guide
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Introduction R 1.1. Referenced Documents Document Location ® ® http://developer.intel.com/design/mobile/datashts ® ® http://developer.intel.com ® ® http://developer.intel.com/design/mobile/datashts Intel Pentium M Processor Datasheet (252612) Intel Pentium M Processor on 90 nm Process with 2-MB L2 Cache Datasheet Intel Celeron M Processor Datasheet (300302) ® http://developer.intel.com ® Intel 82801DBM I/O Controller Hub 4-Mobile (ICH4-M) Datasheet and Spec Update http://developer.intel.
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Introduction R This page intentionally left blank.
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System Overview R 2. System Overview 2.1. Platform Component Features The technologies represented by the Intel Centrino brand will include the Intel Pentium M processor, related chipsets, and 802.11 (Wi-Fi) wireless networking capability. The Intel Pentium M processor is a higher performance, lower power mobile processor with several micro-architectural enhancements over existing Intel mobile processors.
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System Overview R 2.2. Intel 855GM Platform Component Features Figure 1. Intel Pentium M Processor and Intel 855GM Chipset Block Diagram Intel® Pentium® M Processor or Intel Celeron® M Processor CK-408 DVI Device LVDS IMVP-IV VR 400 MHz BPSB DVOB & DVOC 1.5 V CRT Intel® 855GM GMCH 732 MicroFCBGA 200/266 MHz DDR Hub Interface 1.5 Mini-PCI ATA100 IDE (2) USB2.0/1.1 (6) Intel® 82801DBM 421 BGA (ICH4-M) Intel® PRO/ Wireless Network Connection PCI Bus Cardbus LAN AC'97 2.2/2.3 Modem Codec 2.2.
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System Overview R     Intel Celeron M processor: 1.356 V (Standard Voltage core version), 1.004 V (UltraLow Voltage core version) VCCA (1.8 V): VCCP (1.05 V) 2.2.2. Intel® 855GM Chipset Graphics Memory Controller Hub (GMCH) 2.2.2.1.
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System Overview R  Accompanying I2C and DDC channels provided through multiplexed interface  Dual independent pipe for dual independent display  Simultaneous display: same images and native display timings on each display device • Digital Video Out Port (DVOB and DVOC) support  DVOB & DVOC with 165-MHz dot clock support for each 12-bit interface  Compliant with DVI Specification 1.
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System Overview R       2.2.4. VCCSUS1_5 (1.5 V resume logic voltage), VCCSUS3_3 (3.3 V resume I/O voltage) VCCLAN1_5 (1.5 V LAN logic voltage), VCCLAN3_3 (3.3 V LAN I/O voltage) V5REF (5 V) , V5REF_SUS (5 V) VCCRTC (2.0V – 3.3V) VCCHI (1.5 V) VCCP (1.05 V) Intel® Pro/Wireless Network Connection • Ability to connect to 802.11 Wi-Fi Certified networks • Industry standard and extended wireless security support (WEP, 802.
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System Overview R 2.3. Intel 855GME Platform Component Features The Intel 855GME chipset based system supports the Intel® Pentium® M processor in the 90 nm process.. This section lists only additional features supported on the Intel 855GME chipset based system. All features in Intel 855GM chipset based system are supported in the Intel 855GME chipset based system as well. Figure 2.
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System Overview R 2.3.2. Intel 855GME Chipset Graphics Memory Controller Hub (GMCH) All chipset and graphics features of Intel 855GM chipset GMCH is supported in Intel 855GME chipset GMCH. This section lists the additional enhancements.
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General Design Considerations R 3. General Design Considerations This section documents motherboard layout and routing guidelines for the Intel 855GM/GME chipset based systems. It does not discuss the functional aspects of any bus, or the layout guidelines for an addin device. If the guidelines listed in this document are not followed, it is important that thorough signal integrity and timing simulations are completed for each design.
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General Design Considerations R Figure 3. Recommended Board Stack-Up Dimensions Stackup Dielectric Layer Layer Copper Trace Trace Thickness No. Type Weight Width Impedance (oz) (mils) (ohms) 5.0 55 4.0 55 4.0 55 5.0 55 (mils) S PREPREG => 5.0 CORE => 5.0 PREPREG => 12.0 CORE => 10.0 PREPREG => 12.0 CORE => 5.0 PREPREG => 5.
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General Design Considerations R 6. 7. of the motherboard. Due to the arrangement of the processor and the GMCH pin-maps, GND vias placed near all GND land pads will also be very close to high-speed signals that may be transitioning to an internal layer. Thus, no additional ground stitching vias (besides the GND pin vias) are required in the immediate vicinity of the processor and the GMCH packages to accompany the signal transitions from the component side into an internal layer.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R 4. Intel Pentium M/Celeron M Front Side Bus Design Guidelines The following layout guidelines support designs using the Intel Pentium M processor or Intel Celeron processor and the Intel 855GM/GME GMCH chipset. Due to on-die Rtt resistors on both the processor and the chipset, additional resistors do not need to be placed on the motherboard for most PSB signals. A simple point-to-point interconnect topology is used in these cases. 4.1.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R Figure 4. Trace Spacing vs. Trace to Reference Plane Example R e fe r e n c e P la n e ( V S S ) X 2X T ra c e 4.1.1.2. T ra c e Trace Space to Trace Width Ratio Figure 5 illustrates the recommended relationship between the edge-to-edge trace spacing versus trace width ratio for the best signal quality results. In general, a 3:1 trace space to trace width ratio is preferred and highly recommended.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R Table 2 summarizes the list of common clock and key routing. RESET# (CPURST# of GMCH) is also a common clock signal but requires a special treatment for the case where an ITP700FLEX debug port is used. See Section 4.1.5 for further details. Table 2.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R BR0# = X mils board trace + 336 CPU PKG + 465 GMCH PKG = 2212 pad-to-pad length Therefore: X = BR0# board trace = 2212 - 336 - 465 = 1411 pin to pin length. Figure 6. Common Clock Topology Length L1 Processor GMCH Pad Pad Package trace Motherboard PCB trace Table 3. Processor and GMCH PSB Common Clock Signal Package Lengths and Minimum Board Trace Lengths Signal Names 4.1.3. Package Length Min.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R requires careful attention to their routing considerations. The following guidelines should be strictly adhered to, to guarantee robust high frequency operation of these signals. Source synchronous data and address signals and their associated strobes are partitioned into groups of signals. Flight time skew minimization within the same group of source synchronous signals is a key parameter that allows their high frequency (400 MHz) operation.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R Figure 7. Layer 6 PSB Source Synchronous Signals GND Referencing to Layer 5 In a similar way, Figure 8 illustrates a recommended layout and stack-up example of how another group of PSB source synchronous DATA and ADDRESS signals can reference ground planes on both Layer 2 and Layer 4. Note that in the socket cavity of the processor, Layer 3 is used for VCC core power delivery to reduce the I*R drop.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R Figure 8. Layer 3 PSB Source Synchronous Signals 4.1.3.1. Source Synchronous Signal Length Matching Constraints The routing guidelines presented in the following subsections define the recommended routing topologies, trace width and spacing geometries, and absolute minimum and maximum routed lengths for each signal group, which are recommended to achieve optimal SI and timing.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R with nominal package lengths and that package length compensation be performed as secondary operation. 4.1.3.3. Source Synchronous – Data Group Robust operation of the 400-MHz, source synchronous data signals require tight skew control. For this reason, these signals are split into matched groups as outlined in Table 4.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R Table 5. Processor System Bus Source Synchronous Data Signal Routing Guidelines Signal Names Transmission Line Type Total Trace Length Spacing Nominal Impedance & Width (mils) (Ω) Data Group #1 Data Group #2 Data Group #3 Data Group #4 D[15:0]# D[31:16]# D[47:32]# D[63:48]# Strip-line 0.5 5.5 55 ± 15% 3:1 DINV0# DINV1# DINV2# DINV3# Strip-line 0.5 5.5 55 ±15% 3:1 DSTBN[0]# DSTBN[1]# DSTBN[2]# DSTBN[3]# Strip-line 0.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R Table 7. Processor PSB Source Synchronous Address Signal Routing Guidelines Signal Names Address Group #1 Address Group #2 A[16:3]# A[31:17]# REQ[4:0]# ADSTB#[0] 4.1.3.5. ADSTB#[1] Transmission Line Type Total Trace Length Nominal Impedance (Ω) Width & Spacing (mils) Min (inches) Max (inches) Strip-line 0.50 6.5 55 ± 15% 4&8 Strip-line 0.50 6.5 55 ± 15% 4&8 Strip-line 0.50 6.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R Table 8.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R Signal Group Addr Group 1 48 CPU Signal Name CPU GMCH Package GMCH Package Length Signal Name Length (mils) (mils) Signal Group CPU Signal Name CPU GMCH Package GMCH Package Length Signal Name Length (mils) (mils) DSTBP[2]# 661 HDSTBP[2]# 502 DSTBP[3]# 758 HDSTBP[3]# 463 DSTBN[2]# 661 HDSTBN[2]# 538 DSTBN[3]# 758 H DSTBN[3]# 505 REQ4# 616 HREQ4# 276 A31# 773 HA31# 617 REQ3# 616 HREQ3# 383 A30# 773 HA30# 484
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R 4.1.4. Asynchronous Signals The following sections describe the topologies and layout recommendations for the Asynchronous Open Drain and CMOS signals found on the platform. All Open Drain signals listed in the following sections must be pulled-up to VCCP (1.05 V). If any of these Open Drain signals are pulled-up to a voltage higher than VCCP, the reliability and power consumption of the processor may be affected.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R 4.1.4.1. Topology 1A: Open Drain (OD) Signals Driven by the Processor – IERR# The Topology 1A OD signal IERR# should adhere to the following routing and layout recommendations. Table 10 lists the recommended routing requirements for the IERR# signal of the processor. The routing guidelines allow the signal to be routed as either micro-strip or strip-lines using 55 Ω ± 15% characteristic trace impedance.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R dampening resistor R1 in Topology 1B. Thus, it is important to note that R1 will no longer be required in such a topology. Figure 10. Routing Illustration for Topology 1B VCCP ICH4-M (or sys. receiver) CPU Rtt L2 R1 L1 L3 Table 11. Layout Recommendations for Topology 1B 4.1.4.3. L1 L2 L3 R1 Rtt Transmission Line 0.5” – 12.0” 0” – 3.0” 0” – 3.0” 56 Ω ± 5% 56 Ω ± 5% Micro-strip 0.5” – 12.0” 0” – 3.0” 0” – 3.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R Figure 11. Routing Illustration for Topology 1C (System receiver) 3.3 V_IO_RCVR 3.3 CPU VCCP L2 L1 R2 R1 Rtt L4 Q2 3904 Q1 L3 3904 Rs Table 12. Layout Recommendations for Topology 1C L1 4.1.4.4. L2 L3 L4 Rs R1 R2- Rtt Transmission 0.5” – 12.0” 0” – 3.0” 0” – 3.0” 0.5” – 12.0” 330 Ω ± 5% 1.3 kΩ ± 5% 330 Ω ± 5% 56 Ω ± 5% Micro-strip 0.5” – 12.0” 0” – 3.0” 0” – 3.0” 0.5” – 12.0” 330 Ω ± 5% 1.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R Table 13. Layout Recommendations for Topology 2A L1 4.1.4.5. L2 Rtt Transmission Line Type 0.5” – 12.0” 0” – 3.0” 330 Ω ± 5% Micro-strip 0.5” – 12.0” 0” – 3.0” 330 Ω ±5% Strip-line Topology 2B: CMOS Signals Driven by ICH4-M – DPSLP# The Topology 2B CMOS DPSLP# signal, which is driven by the ICH4-M (CMOS signal input to the processor), should adhere to the routing and layout recommendations illustrated in Figure 13.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R Figure 14. Routing Illustration for Topology 2C ICH4-M CPU L1 Table 15. Layout Recommendations for Topology 2C 4.1.4.7. L1 Transmission Line Type 0.5” – 12.0” Micro-strip 0.5” – 12.0” Strip-line Topology 3: CMOS Signals Driven by ICH4-M to CPU and FWH – INIT# The signal INIT# should adhere to the following routing and layout recommendations. Table 16 lists the recommended routing requirements for the INIT# signal of the ICH4-M.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R Table 16. Layout Recommendations for Topology 3 4.1.4.8. L1 + L2 L3 L4 Rs R1 R2 Transmission Line 0.5” – 12.0” 0” – 3.0” 0.5” – 6.0” 330 Ω ± 5% 1.3 kΩ ± 5% 330 Ω ± 5% Micro-strip 0.5” – 12.0” 0” – 3.0” 0.5” – 6.0” 330 Ω ± 5% 1.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R termination of the AGTL+ buffers on both the processor and the GMCH provide proper signal quality for this connection. This is the same case as for the other common clock signals listed Section 4.1.2. Length L1 of this interconnect should be limited to minimum of 1 inch and maximum of 6.5 inches. Figure 17.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R Table 17. Processor RESET# Signal Routing Guidelines with ITP700FLEX Connector 4.1.5.1. L1 L2 + L3 L3 Rs Rtt 1.0” – 6.0” 6.0” max 0.5” max Rs = 22.6 Ω ± 1% Rtt = 220 Ω ± 5% Processor RESET# Routing Example Figure 19 illustrates a board routing example for the RESET# signal with an ITP700FLEX debug port implemented. It illustrates how the CPURST# pin of GMCH forks out into two branches on Layer 6 of the motherboard.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R BCLK[1:0] layer transition vias are accompanied by GND stitching vias. For similar reasons, routing for the ITP interposer’s BCLK[1:0] signals also transition from Layer 3 to the secondary side layer and have 507-mil long traces on this layer. Throughout the routing length on Layer 3, BCLK[1:0] signals should reference a solid GND plane on Layer 2 and Layer 4 as shown in Figure 8.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R (MCH_GTLREF) to be supplied to its HVREF[4:0] pins. The GTLREF voltage divider for both the processor and GMCH cannot be shared. Thus, both the processor and GMCH must have their own locally generated GTLREF networks. Figure 21 shows the recommended topology for generating GTLREF for the processor using a R1 = 1 kΩ ± 1% and R2 = 2 kΩ ± 1% resistive divider.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R Figure 22. Processor GTLREF Motherboard Layout Pin AG1 AG1 Pin R1 VCCP VCCP R2 R2 GTLREF Zo=55Ω <0.5” Banias CPU Pin E26 PRIMARY SIDE 4.1.8. PinG1 G1 Pin AGTL+ I/O Buffer Compensation The Intel Pentium M / Intel Celeron M processor has 4 pins, COMP[3:0], and the GMCH has 2 pins, HRCOMP[1:0], that require compensation resistors to adjust the AGTL+ I/O buffer characteristics to specific board and operating environment characteristics.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R Figure 23. Processor COMP[2] & COMP[0] Resistive Compensation COMP[0] COMP[2] 27.4Ω +/- 1% 27.4Ω +/- 1% Figure 24. Processor COMP[3] & COMP[1] Resistive Compensation COMP[3] COMP[1] 54.9Ω +/- 1% 54.9Ω +/- 1% The recommended layout of the processor COMP[3:0] resistors is illustrated in Figure 25.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R compensation resistors on the secondary side. The use of 18-mil wide dog bones and traces is used to achieve the Zo = 27.4-Ω target to ensure proper operation of the PSB. See Figure 27 for more details. Figure 25. Processor COMP[3:0] Resistor Layout COMP[2] COMP[3] AA1 Y2 GND pins COMP[0] VCCP VCCP VCCP COMP[1] VCCA One GND Via VCCA=1.8 SECONDARY SIDE PRIMARY SIDE Figure 26.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R Figure 27. COMP2 & COMP0 27.4-Ω Traces PRIMARY SIDE SECONDARY SIDE PRIMARY SIDE SECONDARY SIDE COMP0 COMP0 27.4 Ω 1% COMP0 COMP1 18-mil 18 -mil DogTrace Bone 18 - mil Trace SECONDARY SIDE COMP2 COMP3 COMP2 27.4 Ω 1% 4.1.9. Intel Pentium M / Intel Celeron M Front Side Bus Strapping and Debug Port The Intel Pentium M / Intel Celeron M processor and GMCH both have pins that require termination for proper component operation. 1. 2.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R Table 18. ITP Signal Default Strapping When ITP Debug Port Not Used 4.1.10. Signal Resistor Value Connect To Resistor Placement TDI 150 Ω ± 5% VCCP Within 2.0” of the CPU TMS 39 Ω ± 5% VCCP Within 2.0” of the CPU TRST# 680 Ω ± 5% GND Within 2.0” of the CPU TCK 27 Ω ± 5% GND Within 2.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R 4.2.1. 4.2.1.1. ITP Support Background/Justification One key tool that is needed to debug BIOS, logic, signal integrity, general software, and general hardware issues involving CPUs, chipsets, SIOs, PCI devices, and other hardware in a platform design is the In Target Probe (ITP). The ITP is widely used by various validation, test, and debug groups within Intel (as well as by third party BIOS vendors, OEMs, and other developers).
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R 4.2.2.2. 1. Provide a motherboard with a CPU socket. The FSB LAI is an interposer that plugs into the CPU socket, and the CPU then plugs into the LAI. The use of non-standard sockets may also prohibit the LAI from working as the locking mechanism may become inaccessible. It is important to check the LAI design guidelines to ensure a particular socket will work.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R Figure 29. ITP700FLEX Debug Port Signals L8 BCLKp 1.05v CK408 Processor150Ω ITPCLK[1:0] L6 BaniasCLK[1:0] TDI BCLK[1:0] TMS TRST# BCLKn 1.05v 39.2Ω 1% 5% TDI TDI TMS TMS TRST# GMCHCLK[1:0] TMS TRST# 1.05v 680Ω 5% FBO TCK FBO TCK TCK 54.9Ω 22.6Ω 1% 1% TDOITP TDO BPM[3:0]# PRDY# PREQ# RESET# CPURESET# TCK L1 TDO BCLK[1:0] FBO 27.4Ω 1% 1.05v GMCH TRST# VTT VTT VTAP 0.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R termination guarantee proper signal quality for the BPM[4:0]# signals. Due to the length of the ITP700FLEX cable, the length L2 of the BPM[4:0]# signals on the motherboard should be limited to be shorter than 6.0 inches. The BPM[4:0]# signals’ length L2 should be length matched to each other within ± 250 mils.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R DBA# is an optional system signal that can be used to indicate to the system that the ITP/TAP port is being used. If not implemented, this signal can be left as no connect. If implemented, it should be routed with a 150 Ω to 240 Ω pull-up resistor placed within 5.5” of the ITP700FLEX connector. See the ITP700 Debug Port Design Guide for more details on DBA# usage.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R Note that the VCCP (1.05 V) power delivery continues from the processor socket cavity on the secondary side of the motherboard through the pin field as shown on the right side of Figure 30. Three VCCP vias in conjunction with three ground stitching vias allow a transition to the primary side to connect to the VTT and VTAP pins of the ITP700FLEX connector and also a transition back to the secondary side of the motherboard.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R Figure 30. ITP700FLEX Signals Layout Example Primary Side Secondary Side 1.05v 150Ω VCCA=1.8v 1.05v TDI TMS TRST# TCK TDO FBO 1.05v 27.4Ω BPM[5:0]# VTT, VTAP 680Ω DBR# 39.2Ω 0.1uF 22.6Ω 220 Ω 54.9Ω 1.05v 22.6Ω TDO RESET# Figure 31. ITP_CLK to ITP700FLEX Connector Layout Example ITP700FLEX Connect Connector PRIMARY SIDE Ω 49.9Ω 49.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R 4.3.1.3. ITP700FLEX Design Guidelines for Production Systems For production systems that do not populate the onboard ITP700FLEX debug port connector, the following guidelines should be followed to ensure that all necessary signals are terminated properly. Table 18 summarizes all the signals that require termination when a system does not populate the ITP700FLEX connector but still implements the routing for all the signals.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R also requires the use of a pair of 33-Ω ± 5% series resistors placed within 0.5 inches of the clock chip output pins and followed by a pair of 49.9-Ω ± 1% termination resistors to ground. The majority of the ITP_CLK differential serpentine routing takes place on internal Layer 6 below the PSB address signal routing. Completion of ITP+CLK routing on Layer 6 is not possible due to PSB routing on Layer 6.
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Intel Pentium M/Celeron M Front Side Bus Design Guidelines R not required and can be left as no connect. However, it is the responsibility of the system designer to determine whether termination for DBA# is required or not. 4.3.3. Logic Analyzer Interface (LAI) Intel is working with Agilent Corporation to provide logic analyzer interfaces (LAIs) for use in debugging Intel Pentium M processor / Intel Celeron M processor based systems.
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Intel® Mobile Voltage Positioning IV General Description R 5. Intel® Mobile Voltage Positioning IV General Description Please contact your Intel Field Representative for more information on the electrical requirements for the DC-to-DC Voltage Regulator for the Intel Pentium M processor / Intel Celeron M processor.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R 6. System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration The Intel 855GM/GME chipset GMCH Double Data Rate (DDR) SDRAM system memory interface consists of SSTL-2 compatible signals. These SSTL-2 compatible signals have been divided into several signal groups: Data, Control, Command, CPC, Clock, and Feedback signals. Table 20 summarizes the different signal grouping.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R 6.1. Length Matching and Length Formulas The routing guidelines presented in the following subsections define the recommended routing topologies, trace width and spacing geometries, and absolute minimum and maximum routed lengths for each signal group, which are recommended to achieve optimal SI and timing.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R 6.2. Package Length Compensation As mentioned in Section 6.1, all length matching is done GMCH die-pad to memory device pin. The reason for this is to compensate for the package length variation across each signal group. The GMCH does not equalize package lengths internally as some previous GMCH components have, and therefore, the GMCH requires length matching.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R Figure 33. Memory Clock Routing Topology SCK/SCK#[5:0] GM CH S O -D IM M P A D S P1 L1 L2 GM CH P in R1 P1 L1 L2 D iffe r e n tia l P a irs 6.3.3. Memory Clock Routing Guidelines Table 24.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R Parameter Breakout Exceptions (Reduced geometries for GMCH breakout region) Definition Inner Layers: 4 mil trace, 4 mil pair space allowed Outer Layers: 5 mil trace, 5 mil pair space allowed Pair to pair spacing of 5 mils allowed Spacing to other DDR signals of 5 mils allowed Maximum breakout length is 0.3” NOTES: 1. Pad to Pin length tuning is utilized on clocks in order to achieve minimal variance.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R X1, in Figure 34. These are the lengths to which all clocks within the corresponding group will be matched and the reference length values used to calculate the length ranges for the other signal groups. 6.3.3.2. Clock Reference Lengths The clock reference length for each SO-DIMM clock group is determined by first determining the longest total clock length required to complete the clock routing.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R 6.3.3.3. Clock Package Length Table The package length data in the table below should be used to tune the motherboard length of each SCK/SCK# clock pair between the GMCH and the associated SO-DIMM socket. It is recommended that die-pad to SO-DIMM pin length be tuned to within ± 25 mils in order to optimize timing margins on the interface. Table 25.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R Figure 35. Clock Signal Routing Example GMCH Clocks SODIMM0 SODIMM1 6.3.4. Data Signals – SDQ[71:0], SDM[8:0], SDQS[8:0] The GMCH data signals are source synchronous signals that include a 72-bit wide data bus, which includes 8 check bits for Error Checking and Correction (ECC), a set of 9 Data Mask bits, and a set of 9 data strobe signals.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R To facilitate routing, swapping of the byte lanes is allowed for SDQ[63:0] only. Bit swapping within the byte lane is also allowed for SDQ[63:0] only. The check bits, SDQ[71:64], cannot be byte lane swapped with another SDQ byte lane. Also, bit swapping within the SDQ[71:64] byte lane is not allowed. It is suggested that the parallel termination be placed on both sides of SO-DIMM1 to simplify routing and minimize trace lengths.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R Table 26. Memory Data Signal Group Routing Guidelines Parameter Definition Signal Group SDQ[71:0], SDQS[8:0], SDM[8:0] Motherboard Topology Daisy Chain with Parallel Termination Reference Plane Ground Referenced Characteristic Trace Impedance (Zo) 55 Ω +/- 15% Nominal Trace Width Minimum Spacing to Trace Width Ratio Inner layers: 4 mils Outer layers: 5 mils SDQ/SDM: 2 to 1 (e.g. 8 mil space to 4 mil trace) SDQS: 3 to 1 (e.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R 36 for the definition of the various trace segments. The length tuning requirements are also depicted in Figure 37. Refer to Section 6.1 for more details on length matching and length formula requirements. Length range formula for SO-DIMM0: X0 = SCK/SCK#[2:0] total reference length, including package length Y0 = SDQS[8:0] total length = GMCH package + L1 + L2 + S0, as shown in Figure 37, where: ( X0 – 1.0” ) ≤ Y0 ≤ ( X0 + 0.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R Figure 37. SDQS to Clock Trace Length Matching Diagram S O -D IM M 0 G MCH Package S D Q S [8:0 ] S D Q S Length = Y 0 , w here GM CH D ie S C K [2:0 ] S C K # [2 :0] C lock R eference Length = X0 N ote: A ll lengths are m easured from G M C H diepad to S O -D IM M connector pad. S O -D IM M 0 G M C H P a c ka g e GM CH D ie S O -D IM M 1 S D Q S [8:0 ] S D Q S Length = Y 1 S C K [5:3 ] S C K #[5 :3] C lock R ef.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R Length matching is not required from the SO-DIMM1 to the parallel termination resistors. Figure 38 on the following page depicts the length matching requirements between the SDQ, SDM, and SDQS signals within a byte lane. Byte lane mapping is defined in Table 27 below. 6.3.4.4.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R Figure 38. SDQ/SDM to SDQS Trace Length Matching Diagram SO-DIMM0 SDQ[0] GMCH Package SDQ[1] SDQ Length (Y) = (X ±25 mils) SDQ[2] SDQ[3] GMCH Die SDQS[0] SDQS Length = X SDQ[4] SDQ[5] SDQ[6] SDQ Length (Y) = (X ±25 mils) SDQ[7] SDM[0] SDM Length (Y) = (X ±25 mils) Note: All lengths are measured from GMCH die pad to SO-DIMM connector pad. SO-DIMM0 Note: Only one byte lane is shown for reference.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R 90 Signal Pin Number Pkg Length (mils) Signal Pin Number Pkg Length (mils) Signal Pin Number Pkg Length (mils) SDQ_01 AE3 751 SDQ_25 AH11 622 SDQ_49 AH23 752 SDQ_02 AF4 690 SDQ_26 AG13 572 SDQ_50 AE24 666 SDQ_03 AH2 903 SDQ_27 AF14 655 SDQ_51 AH25 817 SDQ_04 AD3 682 SDQ_28 AG11 599 SDQ_52 AG23 639 SDQ_05 AE2 739 SDQ_29 AD12 460 SDQ_53 AF23 667 SDQ_06 AG4 741 SDQ_30 AF13 536 S
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R 6.3.4.6. Memory Data Routing Example Figure 39 is an example of a board routing for the Data signal group. The majority of the Data signal route is on an internal layer, both external layers can be used for parallel termination R-pack placement. Figure 39. Data Signals Group Routing Example From GMCH Data Signals 6.3.5.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R Table 29.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R 6.3.5.2. Control Signal Routing Guidelines Table 30. Control Signal Routing Guidelines Parameter Routing Guidelines Signal Group SCKE[3:0], SCS#[3:0] Motherboard Topology Point-to-Point with Parallel Termination Reference Plane Ground Referenced Characteristic Trace Impedance (Zo) 55 Ω ±15% Nominal Trace Width Inner layers: 4 mils Outer layers: 5 mils Minimum Spacing to Trace Width Ratio 2 to 1 (e.g.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R 6.3.5.3. Control to Clock Length Matching Requirements The length of the control signals, between the GMCH die pad and the SO-DIMM must fall within the range defined below, with respect to the associated clock reference length. Refer to Figure 40 for a definition of the various trace segments that make up this path. The length of trace from the SO-DIMM to the termination resistor need not be length matched.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R Figure 41. Control Signal to Clock Trace Length Matching Diagram SO-DIMM0 GMCH Package SCS#[1:0] SCKE[1:0] CNTRL Length = Y0 GMCH Die SCK[2:0] SCK#[2:0] Clock Ref. Length = X0 Note: All lengths are measured from GMCH die pad to SO-DIMM connector pads. SO-DIMM0 GMCH Package SO-DIMM1 SCS#[3:2] SCKE[3:2] CNTRL Length = Y1 GMCH Die SCK[5:3] SCK#[5:3] Clock Ref.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R 6.3.5.4. Memory Control Routing Example Figure 42 is an example of a board routing for the Control signal group. Figure 42.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R 6.3.5.5. Control Group Package Length Table The package length data in Table 31 below should be used to match the overall length of each command signal to it’s associated clock reference length.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R Figure 43. Command Routing for Topology 1 GMCH GMCH Pin Vtt Rs P1 L1 L2 w L3 S0 L4 w S1 SO-DIMM0 PAD Rt SO-DIMM1 PAD The command signals should be routed using a 2 to 1 trace spacing to trace width ratio for signals within the DDR group, except clocks and strobes. There should be a minimum of 20 mils spacing to non-DDR related signals. Command signals should be routed on inner layers with minimized external traces. 6.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R Maximum Recommended Motherboard Via Count Per Signal 6 CMD to SCK/SCK# [5:0] Length Matching Requirements See length matching Section 6.3.6.3 and Figure 44 for details. NOTES: 1. Recommended resistor values and trace lengths may change in a later revision of the design guide. 2. Power distribution vias from Rt to Vtt are not included in this count. 3.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R Figure 44. Topology 1 Command Signal to Clock Trace Length Matching Diagram SO-DIMM0 GMCH Package SMAA[12:6,3,0] SBA[1:0], RAS#, CAS#, WE# CMD Length = Y0 GMCH Die SCK[2:0] Clock Reference Length = X0 SCK#[2:0] Note: All lengths are measured from GMCH die pad to SO-DIMM connector pad.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R 6.3.6.4. Command Topology 2 The command signal routing should transition from an external layer to an internal signal layer under the GMCH. Keep to the same internal layer until transitioning back to an external layer at the series resistor Rs. At this point there is a T in the topology.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R 6.3.6.5. Command Topology 2 Routing Guidelines Table 33.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R 6.3.6.6. Command Topology 2 Length Matching Requirements The routed length of the command signals, between the GMCH package ball and the SO-DIMM must be within the range defined below, with respect to the associated clock reference length. Refer to Figure 45 for a definition of the various motherboard trace segments. The length of trace from the SO-DIMM to the termination resistor need not be length matched.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R Figure 46. Topology 2 Command Signal to Clock Trace Length Matching Diagram SO-DIMM0 GMCH Package SMAA[12:6,3,0] SBA[1:0], SRAS#, SCAS#, SWE CMD Length = Y0 GMCH Die SCK[2:0] Clock Reference Length = X0 SCK#[2:0] Note: All lengths are measured from MCH die pad to SO-DIMM connector pad.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R 6.3.6.7. Command Topology 2 Routing Example Figure 47 is an example of a board routing for the Command signal group. Figure 47.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R 6.3.6.8. Command Topology 3 This topology is recommended when the SO-DIMMS are too close together for the series resistor to be placed between connectors. In this topology the series resistors are placed behind the second SODIMM. External trace lengths should be minimized. It is suggested that the parallel termination be placed on both sides of the board to simplify routing and minimize trace lengths.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R 6.3.6.9. Command Topology 3 Routing Guidelines Table 34.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R 6.3.6.10. Command Topology 3 Length Matching Requirements The routed length of the command signals, between the GMCH package ball and the SO-DIMM must be within the range defined below, with respect to the associated clock reference length. Refer to Figure 45 for a definition of the various motherboard trace segments. The length of trace from the SO-DIMM to the termination resistor need not be length matched.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R Figure 49. Topology 3 Command Signal to Clock Trace Length Matching Diagram SO-DIMM0 GMCH Package SMAA[12:6,3,0] SBA[1:0], RAS#, CAS#, WE# CMD Length = Y0 GMCH Die SCK[2:0] Clock Reference Length = X0 SCK#[2:0] Note: All lengths are measured from GMCH die pad to SO-DIMM connector pad.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R 6.3.6.11. Command Group Package Length Table The package length data in Table 35 below should be used to match the overall length of each command signal to its associated clock reference length. Table 35.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R 6.3.7. CPC Signals – SMA[5,4,2,1], SMAB[5,4,2,1] The GMCH chipset CPC (clock-per-command) signals, SMA[5,4,2,1] and SMAB[5,4,2,1]are “clocked” into the DDR SDRAM devices using clock signals SCK/SCK#[5:0]. The GMCH drives the CPC and clock signals together, with the clocks crossing in the valid command window. The GMCH provides one set of CPC signals per SO-DIMM slot. Refer to Table 29 for the CKE and CS# signal to SO-DIMM mapping.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R 6.3.7.1. CPC Signal Topology Figure 50. Command per Clock Signal Routing Topology V tt GM CH GM CH P in Rt P1 L2 L1 w S1 SO -D IM M 0,1 P A D The CPC signals should be routed using 2 to 1 trace space to width ratio for signals within the DDR group, except clocks and strobes. There should be a minimum of 20-mils of spacing to non-DDR related signals.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R CPC to SCK/SCK# [5:0] Length Matching Requirements See length matching Section 6.3.7.3 and Figure 51 for details. NOTES: 1. Recommended resistor values and trace lengths may change in a later revision of the design guide. 2. Power distribution vias from Rt to Vtt are not included in this count. 3. It is possible to route using 2 vias if one via is shared that connects to the SO-DIMM pad and parallel termination resistor. 4.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R Figure 51. CPC Signals to Clock Length Matching Diagram SO-DIMM0 GMCH Package SMA[5,4,2,1] CPC Length = Y0 GMCH Die SCK[2:0] SCK#[2:0] Clock Reference Length = X0 Note: All lengths are measured from GMCH die pad to SO-DIMM connector pad. SO-DIMM0 SO-DIMM1 GMCH Package CPC Length = Y1 SMAB[5,4,2,1] GMCH Die SCK[5:3] Clock Ref Length = X1 SCK#[5:3] Note: All lengths are measured from GMCH die pad to SO-DIMM connector pad.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R 6.3.8. Feedback – RCVENOUT#, RCVENIN# The Intel 855GM/GME chipset GMCH provides a feedback signal called “receive enable” (RCVEN#), which is used to measure timing for the read data. The RCVENOUT# signal is shunted directly to RCVENIN# inside the package in order to reduce timing variance. With this change it is no longer necessary to provide an external connection.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R Example 1 Example 2 SO-DIMM0 SO-DIMM1 SO-DIMM0 SO-DIMM1 SCK0,1,2 SCK3,4,5 SCK0,1,2 SCK3,4,5 SMAA[1,2,4,5] SMAB[1,2,4,5] SMAB[1,2,4,5] SMAA[1,2,4,5] SCKE0,1; SCS#0,1 SCKE2,3; SCS#2,3 SCKE0,1; SCS#0,1 SCKE2,3; SCS#2,3 On platforms where ECC memory is supported, it is important that all relevant SDQ, SDQS, and SCK signals to the SO-DIMMs be disabled when the system is populated with only non-ECC or a combination of ECC an
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R By default, the functionality and input buffer associated with ETS# are disabled. Also, the GMCH can be programmed to send an SERR, SCI, or SMI message to the ICH4-M upon the assertion of this signal. External thermal sensors that are suitable for the purpose described above would need to have a small form factor and be able to accurately monitor the ambient temperature in the vicinity of the DDR system memory.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R allows for the best correlation of thermal sensor temperature to chassis or notebook surface temperature. See Figure 52 for details. Assuming airflow is negligible within a system, the optimal placement of the thermal sensor is on the surface of the motherboard directly beneath the shadow of an SO-DIMM module centered longitudinally and laterally in relation to the outline of the SO-DIMM.
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System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration R This page intentionally left blank.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R 7. System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration This section contains routing guidelines for a Micro-DIMM and memory soldered onto the motherboard (Memory Down) configuration. The order of routing for this configuration is specific. It is recommended the designer route to the Micro-DIMM first and the Memory Down devices second (See Figure 53.) Figure 53.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R Table 40. Supported Memory Configurations - Memory Down Device Type Bus Width Device Width #Devices Physical Banks Max Capacity TSOP x64 x16 4 1 256 MB BGA x64 x16 4 1 256 MB BGA x64 x16 8 2 512 MB BGA x64 x8 8 1 512 MB These guidelines support standard TSOP and BGA packages in 64Mb, 128Mb, 256Mb, and 512Mb memory densities. Stacked memory technologies are not supported (i.e. Stacked TSOP, DDP).
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R 7.1. Length Matching and Length Formulas The routing guidelines presented in the following subsections define the recommended routing topologies, trace width, spacing geometries, and absolute minimum and maximum routed lengths for each signal group. These parameters are recommended to achieve optimal SI and timing.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R length matching formulas in conjunction with nominal package lengths and that package length compensation be performed as a secondary operation. 7.3. Topologies and Routing Guidelines The 855GM/GME GMCH chipset’s Double Data Rate (DDR) SDRAM system memory interface implements the low swing, high-speed, terminated SSTL_2 topology.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R Figure 55. DDR Clock Routing to Memory Down Two Load BGA Figure 56. DDR Clock Routing to Memory Down Two Load TSOP Figure 57. DDR Clock Routing to Memory Down 4 Load BGA The clock signals should be routed as closely coupled differential pairs over the entire length. Spacing to other DDR signals should not be less than 20 mils. Isolation spacing to non-DDR signals should be 25 mils.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R 7.3.3. DDR Clock Routing Guidelines Table 44.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R Parameter Definition Inner Layers: 4 mil trace, 4 mil pair space allowed Outer Layers: 5 mil trace, 5 mil pair space allowed Breakout Exceptions Pair to pair spacing of 5 mils allowed (Reduced geometries for GMCH breakout region) Spacing to other DDR signals of 5 mils allowed Maximum breakout length is 0.3” NOTES: 1. Pad to Pin length tuning is utilized on clocks in order to achieve minimal variance.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R X0 = SCK/SCK#[1:0] P1 + L1 + L2 + L3 (see Figure 54) Length Range Formulas for Memory Down: X1 = SCK/SCK#[4:3] P1 + L1 + L2 + L3 + L4 (see Figure 55) = SCK/SCK#[4:3] P1 + L1 + L2 + L3 + L4 + L5 (see Figure 56 and Figure 57) This may result in a clock length variance of as much as 700 mils on the motherboard.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R Figure 58.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R 7.3.3.3. Clock Package Length Table The package length data in the table below should be used to tune the motherboard length of each SCK/SCK# clock pair between the GMCH and the Micro-DIMM connector or memory down component. It is recommended that die-pad to Micro-DIMM or memory down component pad length be tuned to within ± 25 mils in order to optimize timing margins on the interface. Table 45.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R • After the series resistor, the signal should transition from the external layer to the same internal layer and route to the SDRAM device. • Transition back out to an external layer and connect to the appropriate SDRAM pad. • Connection to the termination resistor should be via the same internal layer with a transition back to the external layer near the resistor. External trace lengths should be minimized.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R 7.3.4.1. Data Bus Topology Figure 59. Data Signal Routing GMCH to 1x16 TSOP/BGA & /1x8 BGA Configuration Figure 60. Data Signal Routing GMCH to 2x16 BGA Configuration The data signals should be routed using a 2 to 1 trace spacing to trace width ratio for signals within the DDR group, except clocks and strobes. There should be a minimum of 20 mils of spacing to non-DDR related signals.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R Table 46.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R 7.3.4.2. SDQS to Clock Length Matching Requirements The first step in length matching is to determine the SDQS length range based on the SCK/SCK# reference length defined previously. The total length of the SDQS strobe signals, including package length, between the GMCH die-pad and the Micro-DIMM/Memory Down device must fall within the range defined in the formulas below.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R Figure 61. SDQS to Clock Trace Length Matching Diagram 7.3.4.3. Data to Strobe Length Matching Requirements The data bit signals, SDQ[63:0] are grouped by byte lanes and associated with a data mask signal SDM[8:0], and a data strobe, SDQS[8:0]. • The data and mask signals must be length matched to their associated strobe within ± 25 mils, including package.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R where: ( X – 25 mils ) ≤ Y ≤ ( X + 25 mils ) Length matching is not required for length L3 to the parallel termination resistors. Figure 62 on the following page depicts the length matching requirements between the SDQ, SDM, and SDQS signals within a byte lane. Byte lane mapping is defined in Table 47 below. 7.3.4.4.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R Figure 62.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R 7.3.4.5. SDQ/SDQS Signal Package Lengths The package length data in Table 48 below should be used to tune the length of each SDQ, SDM, and SDQS motherboard trace as required to achieve the overall length matching requirements defined in the prior Sections. Table 48.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R 7.3.5.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R Table 49.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R 7.3.5.1. Control Signal Topology Figure 63. Control Signal Routing GMCH to Micro-DIMM Pad Figure 64.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R Figure 65. Control Signal Routing GMCH to Memory Down 1x16/2x16 4 Load BGA Figure 66. Control Signal Routing GMCH to Memory Down 1x8 8 Loads BGA The control signals should be routed using 2 to 1 trace spacing to trace width ratio for signals within the DDR group, except clocks and strobes. There should be a minimum of 20-mils of spacing to non-DDR related signals.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R 7.3.5.2. Control Signal Routing Guidelines Table 50. Control Signal Routing Guidelines Parameter Routing Guidelines Signal Group SCKE[3:0], SCS#[3:0] Motherboard Topology Point-to-Point with Parallel Termination Reference Plane Ground Referenced Characteristic Trace Impedance (Zo) 55 Ω ± 15% Inner layers: 4 mils Nominal Trace Width Outer layers: 5 mils Minimum Spacing to Trace Width Ratio 2 to 1 (e.g.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R 7.3.5.3. Control to Clock Length Matching Requirements The length of the control signals, between the GMCH die pad and the Micro-DIMM/Memory Down device must fall within the range defined below, with respect to the associated clock reference length. . Refer to Figure 63, Figure 64, Figure 65, and Figure 66 for a definition of the various trace segments that make up this path.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R Figure 67. Control Signal to Clock Trace Length Matching Diagram 7.3.5.4. Control Group Package Length Table The package length data in Table 51 should be used to match the overall length of each command control signal to its associated clock reference length.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R 7.3.6. Command Signals – SMAA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE# The Intel 855GM GMCH chipset command signals, SMA[12:0], SBA[1:0], SRAS#, SCAS#, and SWE# clocked into the DDR SDRAMs using the clock signals SCK/SCK#[5:0]. The GMCH drives the command and clock signals together, with the clocks crossing in the valid command window.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R Figure 68. CMD Signal Routing GMCH to Micro-DIMM and Mem Down TSOP 4 Load Figure 69.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R Figure 70. CMD Signal Routing GMCH to Micro-DIMM and Memory Down BGA 8-Load The command signals should be routed using a 2 to 1 trace spacing to trace width ratio for signals within the DDR group, except clocks and strobes. There should be a minimum of 20 mils spacing to non-DDR related signals. Command signals should be routed on inner layers with minimized external traces.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R 7.3.6.2. Command Topology Routing Guidelines Table 52.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R 7.3.6.3. Command Topology Length Matching Requirements The routing length of the command signals between the GMCH die pad and Micro-DIMM/Memory Down must be within the range defined below. This is with respect to the associated clock reference length. Refer to Figure 43 for a definition of the various motherboard trace segments. The length of trace from the Micro-DIMM to the termination resistor need not be length matched.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R Figure 71.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R 7.3.6.4. Command Group Package Length Table The package length data in Table 53 below should be used to match the overall length of each command signal to its associated clock reference length. Table 53.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R 7.3.7. CPC Signals – SMA[5,4,2,1], SMAB[5,4,2,1] The GMCH drives the CPC and clock signals together, with the clocks crossing in the valid control window. The GMCH provides one set of CPC signals for the Micro-DIMM slot and one set for the Memory Down configuration. Refer to Table 49 for the CKE and CS# signal to Micro-DIMM mapping. Table 54.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R 7.3.7.1. CPC Signal Topology Figure 72. Command Per Clock Signal Routing Topology 4 Load BGA Figure 73.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R Figure 74. CPC Signal Routing 8 Load BGA Topology Figure 75. CPC Signal Routing Micro-DIMM The CPC signals should be routed using 2 to 1 trace space to width ratio for signals within the DDR group, except clocks and strobes. There should be a minimum of 20-mils of spacing to non-DDR related signals. CPC signals should be routed on inner layers with minimized external trace lengths.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R 7.3.7.2. CPC Signal Routing Guidelines Table 55. CPC Signal Routing Guidelines Parameter Routing Guidelines Signal Group SMA[5,4,2,1], SMAB[5,4,2,1] Motherboard Topology Point-to-Point with Parallel Termination Reference Plane Ground Referenced Characteristic Trace Impedance (Zo) 55 Ω ±15% Nominal Trace Width Inner layers: 4 mils Outer layers: 5 mils Minimum Spacing to Trace Width Ratio 2 to 1 (e.g.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R 7.3.7.3. CPC to Clock Length Matching Requirements The total length of the CPC signals, between the GMCH die pad and the Micro-DIMM/Memory Down device must fall within the range defined below, with respect to the associated clock reference length. Refer to Figure 72, Figure 73, Figure 74, and Figure 75 for a definition of the various trace segments.
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System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration R Figure 76. CPC Signals to Clock Length Matching Diagram 7.3.7.4. CPC Group Package Length Table The package length data in the table below should be used to match the overall length of each CPC signal to its associated clock reference length. Table 56.
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Integrated Graphics Display Port R 8. Integrated Graphics Display Port The GMCH contains four display ports: an analog CRT port, a dedicated LVDS port, and two 12-bit Digital Video Out (DVO) ports. Section 8.1 will discuss the CRT and RAMDAC routing requirements. Section 8.2 will discuss the dedicated LVDS port. Section 0 will discuss the DVOB and DVOC design guideline. Section 8.3.4 provides recommendations for a flexible modular design guideline for DVOB and DVOC muxed interfaces. Section 8.
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Integrated Graphics Display Port R Equation 1. REFSET = Vreference (Vbg / 4) = Ireference 32 * (73.2uA) A 127 Ω 1% precision resistor value is the recommend value to use. See Figure 77 for the recommended Rset placement. Note: When using 855GME platform with external graphics only, Rset resistor is not needed. Figure 77.
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Integrated Graphics Display Port R The RGB signals also require protection diodes between 1.5 V and ground. These diodes should have low C ratings (~5 pF max) and small leakage current (~ 10 µA at 120˚C) and should be properly decoupled with a 0.1-µF cap. These diodes and decoupling should be placed to minimize power rail inductance. The choice between diodes (or diode packs) should comprehend the recommended electrical characteristics in addition to cost.
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Integrated Graphics Display Port R The analog switch should exhibit a low “on” resistance (< 8 Ω) and low parasitic capacitance (<10 pF). The output routing from the analog switch should be routed as single-ended, 37.5-Ω impedance to the 75-Ω termination resistors that are located near the VGA connector on the motherboard and the VGA connector on the docking station. The single-ended routing after these 75-Ω termination resistors to the pi-filter and then to the VGA connector should be ideally 75-Ω.
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Integrated Graphics Display Port R Figure 79. DAC R, G, B Routing and Resistor Layout example Complement Output Intel 855GM DAC Output Chipset (e.g. BLUE) (e.g. BLUE#) Via to ground plane 20 mil Space between channels 20 mil Space between channels 37.5Ω Trace Impedance 37.5Ω Trace Impedance 75Ω Trace Impedance 75Ω Trace Impedance VGA Π-Filter ANALOG SWITCH VGA Π-Filter 75.0Ω, 1%, 1/16W, 75.0down to ground 75.0 75.
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Integrated Graphics Display Port R 8.1.6. HSYNC and VSYNC Design Considerations HSYNC and VSYNC signals are connected to the analog display attached to the VGA connector. These are 3.3-V outputs from the GMCH. Some monitors have been found to drive HSYNC and VSYNC signals during reset. Because these signals are used as straps on the 852GM/GME and 855GM/GME chipsets, the GMCH can enter an illegal state under these conditions.
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Integrated Graphics Display Port R kept minimal. LIBG pin is a current reference on the LVDS interface. A 1.5-kΩ pulldown is required unless 855GME platform is being used with external graphics only option. The following differential signal groups comprise the LVDS Interface. The topology rules for each group are defined in subsequent sections. Table 58.
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Integrated Graphics Display Port R Table 59.
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Integrated Graphics Display Port R • Use controlled impedance media. The differential impedance of cable LVDS uses should be 100 Ω ± 15%. Cables should not introduce major impedance discontinuities that cause signal reflection. • Balanced cables (twisted pair) are usually better than unbalanced cables (ribbon cable, multiconductor) for noise reduction and signal quality. • Cable length must be less than 16 inches. Table 60. LVDS Package Lengths GMCH Signal Name Package Trace Length (mils) 503.
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Integrated Graphics Display Port R 8.3. Digital Video Out Port The GMCH DVO port interface supports a wide variety of third party DVO compliant devices (e.g. TV encoder, TMDS transmitter or integrated TV encoder and TMDS transmitter). The GMCH has two dedicated Digital Video Out Ports, DVOB and DVOC. Intel’s DVO port is a 1.5-V only interface that can support transactions up to 165 MHz. Some of the DVO port command signals may require voltage translation circuit depending on the third party device.
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Integrated Graphics Display Port R Table 62. DVO Interface Trace Length Mismatch Requirements Data Group Signal Matching to Clock Strobe DVO Clock Strobes Associated With the Group Clock Strobe Matching Notes DVOBD [11:0] ± 100 mils DVOBCLK[1:0] ± 10 mils 1,2 DVOCD [11:0] ± 100 mils DVOCCLK[1:0] ± 10 mils 1,2 NOTES: 1. Data signals of the same group should be trace length matched to the clock within ±100 mil including package lengths. 2.
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Integrated Graphics Display Port R Table 63. DVOB and DVOC Routing Guideline Summary Parameter Definition Signal Group DVOBD [11:0], DVCBD [11:0] Motherboard Topology Point to point Reference Plane Ground Referenced Characteristic Trace Impedance (Zo) 55 Ω ±15% Nominal Trace Width Inner layers: 4 mils Minimum Spacing to Trace Width Ratio 2 to 1 (e.g.
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Integrated Graphics Display Port R Table 64. DVO Interface Package Lengths 8.3.4.
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Integrated Graphics Display Port R 8.3.5. DVOB and DVOC Simulation Method A model for simulation purposes is shown in Figure 80. The DVO component is a third party-chip. Figure 80. DVOB and DVOC Simulations Model tDVb, tDVa tDSu, tDh DVO (Device) DVO I/F GMCH DVOB/DVOC Control, Data Figure 81.
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Integrated Graphics Display Port R All numbers in this table are from the GMCH specification for DVO interface at 165MHz. For third party receiver devices, please refer to appropriate third party vendor specifications. 8.4. DVOB and DVOC port Flexible (Modular) Design The GMCH supports flexible design interfaces described in this section. 8.4.1. DVOB and DVOC Module Design The GMCH supports a DVO module design connected to the GMCH through a generic connector.
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Integrated Graphics Display Port R Figure 83. Generic Module Connector Parasitic Model Motherboard C1 8.5. R L 20mΩ 2.5nH Module C2 2.21 pF 2.21 pF DVO GMBUS and DDC Interface Considerations The GMCH DVOB and/or DVOC port controls the video front-end devices via the GMBUS (I2C) interface. DDCADATA and DDCACLK should be connected to the CRT connector. The GMBUS should be connected to the DVO device, as required by the specifications for those devices.
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Integrated Graphics Display Port R LCLKCTRLA/LCLKCTRLB GMBUS pair. LCLKCTRLA/LCLKCTRLB are used as bootup straps. Please refer to the Intel 855GM/GME (Montara-GM/GM+) Chipset GMCH External Design Specification for details on strapping option. This will prevent the GMCH from confusing noise on these lines for false cycles. 8.5.1.
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Integrated Graphics Display Port R Figure 84. GVREF Reference Voltage +V1.5S 1 KΩ 1% GVREF (to DVO device) 0.1 µF 176 GVREF(to GMCH) 1 KΩ 1% 0.
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AGP Port Design Guidelines R 9. AGP Port Design Guidelines For detailed AGP interface functionality (e.g., protocols, rules, signaling mechanisms), refer to the latest AGP Interface Specification, Revision 2.0, which can be obtained from http://www.agpforum.org. This section focuses only on specific Intel 855GME chipset platform recommendations. 9.1. AGP Interface The AGP Interface Specification Revision 2.0 enhances the functionality of the original AGP Interface Specification (revision 1.
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AGP Port Design Guidelines R All signals in the 2X/4X timing domain must meet minimum and maximum trace length requirements as well as trace width and spacing requirements. Because of the multiplexed AGP/DVO interface, there are trace length matching requirements within each set of 2X/4X signals, as well as between sets of 2X/4X signals. The signal groups are documented in Table 68. Table 68. AGP 2.0 Signal Groups 1X Signals 2X Signals 4X Signals CLK (3.
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AGP Port Design Guidelines R 9.2. AGP Routing Guidelines 9.2.1. 1x Timing Domain Routing Guidelines 9.2.1.1. Trace Length Requirements for AGP 1X This section contains information on the 1X timing domain routing guidelines. The AGP 1X timing domain signals have a maximum trace length of 10 inches (pin to pin). The target impedance is 55-Ω ± 15%. This maximum applies to ALL of the signals listed as 1X timing domain signals in Table 68.
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AGP Port Design Guidelines R 9.2.2. 2x/4x Timing Domain Routing Guidelines 9.2.2.1. Trace Length Requirements for AGP 2X/4X These trace length guidelines apply to ALL of the signals listed as 2X/4X timing domain signals in Table 68. In addition to these maximum trace length requirements, these signals must meet the trace spacing and trace length mismatch requirements in Sections 9.2.2.2 and 9.2.2.3.
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AGP Port Design Guidelines R Table 71. Layout Routing Guidelines for AGP 2X/4X Signals Signal 9.2.2.3. Maximum Length (inch) Trace Space (mils) (4 mil traces) Length Mismatch (inch) Relative To Notes 2X/4X Timing Domain Set#1 6 8 ± 0.1 AGP_ADSTB0 and AGP_ADSTB0# AGP_ADSTB0, AGP_ADSTB0# must be the same length (±10 mils) 2X/4X Timing Domain Set#2 6 8 ± 0.1 AGP_ADSTB1 and AGP_ADSTB1# AGP_ADSTB1, AGP_ADSTB1# must be the same length (±10 mils) 2X/4X Timing Domain Set#3 6 8 ± 0.
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AGP Port Design Guidelines R Table 73. AGP 2.0 Routing Guideline Summary Signal 9.2.3. Maximum Length Trace Spacing (4 mil traces) Length Mismatch 1X Timing Domain 10 in 4 mils No Requirement 2X/4X Timing Domain Set#1 6 in 8 mils 2X/4X Timing Domain Set#2 6 in 2X/4X Timing Domain Set#3 6 in Relative To Notes N/A None ± 0.1 in AD_STB0 and AD_STB0# AD_STB0, AD_STB0# must be the same length 8 mils ± 0.1 in AD_STB1 and AD_STB1# AD_STB1, AD_STB1# must be the same length 8 mils ± 0.
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AGP Port Design Guidelines R 9.2.5. AGP Interface Package Lengths Table 74.
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AGP Port Design Guidelines R 9.2.6. AGP Routing Ground Reference Intel strongly recommends that at least the following critical signals be referenced to ground from the GMCH to an AGP controller connector using a minimum number of vias on each net: AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, SB_STB#, G_TRDY#, G_IRDY#, G_GNT#, and ST[2:0]. 9.2.7. Pull-ups The AGP 2.
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AGP Port Design Guidelines R Table 75. AGP Pull-Up/Pull-Down Requirements and Straps Signal AGP 2.
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AGP Port Design Guidelines R 9.2.8. AGP VDDQ and VCC AGP specifies two separate power planes: VCC and VDDQ. VCC is the core power for the graphics controller. VDDQ is the interface voltage. 9.2.9. VREF Generation for AGP 2.0 (2X and 4X) 9.2.9.1. 1.5-V AGP Interface (2X/4X) The voltage divider networks consist of AC and DC elements. The reference voltage that should be supplied to the Vref pins of the graphics controller is ½ * VDDQ.
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Hub Interface R 10. Hub Interface The GMCH and ICH4-M pin-map assignments have been optimized to simplify the hub interface routing between these devices. It is recommended that the hub interface signals be routed directly from the GMCH to the ICH4-M with all signals referenced to VSS. Layer transitions should be kept to a minimum. If a layer change is required, use only two vias per net and keep all data signals and associated strobe signals on the same layer.
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Hub Interface R 10.2. Hub Interface Data HL[10:0] and Strobe Signals The hub interface HL[10:0] data signals should be routed on the same layer as hub interface Strobe signals. 10.2.1. HL[10:0] and Strobe Signals Internal Layer Routing Traces should be routed 4 mils wide with 8 mils trace spacing (4 on 8) and 20 mils spacing from other signals. In order to break out of the GMCH and ICH4-M packages, the HL[10:0] signals can be routed 4 on 7.
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Hub Interface R Table 79. Hub Interface Package Lengths for ICH4-M Signal Pin Number Package Length (mils) HUB_PD0 L19 551 HUB_PD1 L20 562 HUB_PD2 M19 552 HUB_PD3 M21 567 HUB_PD4 P19 599 HUB_PD5 R19 627 HUB_PD6 T20 623 HUB_PD7 R20 593 HUB_PD8 P23 668 HUB_PD9 L22 559 HUB_PD10 N22 682 HUB_PD11 K21 560 HUB_CLK T21 605 HUB_PSTRB P21 541 HUB_PSTRB# N20 565 Table 80.
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Hub Interface R 10.2.2. Terminating HL[11] The HL[11] signal exists on the ICH4-M but not the GMCH and is not used on the platform. HL[11] must be pulled down to ground via a 56-Ω resistor. 10.3. Hub VREF/VSWING Generation/Distribution The hub interface reference voltage (VREF) is used on both the GMCH (HLVREF) and the ICH4-M (HIREF).
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Hub Interface R Figure 88. Single VREF/VSWING Voltage Generation Circuit for Hub Interface VCCHI R1 PSW ING C1 GMCH HLVREF C2 C5 R2 C4 C6 C3 HI_VSW ING ICH4-M HIREF R3 The resistor values, R1, R2, and R3 must be rated at 1% tolerance. See Table 82 for recommended resistor value. The selected resistor values ensure that the reference voltage tolerance is maintained over the input leakage specification. Two, 0.1-µF capacitors (C1 and C3) should be placed close to the divider. In addition, the 0.
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Hub Interface R Figure 89. ICH4-M and GMCH Locally Generated Reference Voltage Divider Circuit VCCHI VCCHI R1 R1 C5 C1 R2 R2 HLVREF HI_VSWING ICH4 C4 C3 R3 10.3.3. C2 C1 GMCH C6 C3 PSWING HIREF R3 Single GMCH and ICH4-M Voltage Generation / Separate Divider Circuit for VSWING/VREF This section describes the option to use one voltage divider circuit for VREF, shared by both ICH4-M and GMCH, while using another voltage divider circuit for VSWING.
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Hub Interface R 10.3.4. Separate GMCH and ICH4-M Voltage Generation / Separate Divider Circuits for VREF and VSWING This option allows for tuning the voltage references HIVREF and HI_VSWING individually, for both ICH4-M and GMCH. The reference voltage for both HIVREF and HI_VSWING must meet the voltage specification in Table 81. Normal care needs to be taken to minimize crosstalk to other signals (< 10-15 mV).
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I/O Subsystem R 11. I/O Subsystem 11.1. IDE Interface This section contains guidelines for connecting and routing the Intel 82801DBM ICH4-M IDE interface. The ICH4-M has two independent IDE channels. This section provides guidelines for IDE connector cabling and motherboard design, including component and resistor placement, and signal termination for both IDE channels.
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I/O Subsystem R 11.1.2. Primary IDE Connector Requirements Figure 92. Connection Requirements for Primary IDE Connector 22 to 47Ω † PCIRST# PDD[15:0] PDA[2:0] PDIOR# ® Intel ICH4-M PDIOW# PDDREQ PDDACK# 3.3V 3.3V 4.7K 8.2~10K PIORDY (PRDSTB / PWDMARDY#) IRQ[14] Primary IDE Connector PDCS[3,1]# PDIAG# / CBLID# GPIOx CSEL 10K † Due to ringing, PCIRST# must be buffered Follow these connection requirements for Primary IDE connector: • 22 Ω - 47 Ω series resistors are required on RESET#.
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I/O Subsystem R 11.1.3. Secondary IDE Connector Requirements Figure 93. Connection Requirements for Secondary IDE Connector 22 - 47Ω PCIRST# † SDA[2:0] SDCS[3,1]# SDIOR# ® Intel ICH4-M SDIOW# SDDREQ SDDACK# 3.3V 3.3V 4.7K 8.2~10K SIORDY (SRDSTB / SWDMARDY# ) Secondary IDE Connector SDD[15:0] IRQ[15] PDIAG# / CBLID# GPIOy CSEL 10K † Due to ringing, PCIRST# must be buffered Follow these requirements for Secondary IDE Connector: • 22 Ω - 47 Ω series resistors are required on RESET#.
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I/O Subsystem R 11.1.4. Mobile IDE Swap Bay Support Systems that require the support for an IDE “hot” swap drive bay can be designed to utilize the ICH4M’s IDE interface disable feature to achieve this functionality. To support a mobile “hot” swap bay, the ICH4-M allows the IDE output signals to be tri-stated or driven low and input buffers to be turned off. This requires certain hardware and software requirements to be met for proper operation.
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I/O Subsystem R 11.1.4.2. S5/G3 to S0 Boot Up Procedures for IDE Swap Bay The procedures listed below summarize the steps that must be followed during power up of an IDE swap bay drive: 1. ICH4-M powers up, IDE interface is tri-stated, disk drive is not powered up. IDE drive is recognized as being on a separate power plane and its reset is different from the ICH4-M. 2. BIOS powers on the IDE drive. e.g. GPIO is used to switch on a FET on the board. 3.
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I/O Subsystem R 11.2. PCI The Intel 82801DBM ICH4-M provides a PCI Bus interface that is compliant with the PCI Local Bus Specification Revision 2.2. The implementation is optimized for high performance data streaming when the ICH4-M is acting as either the target or the initiator in the PCI bus. The ICH4-M supports six PCI Bus masters (excluding the ICH4-M), by providing six REQ#/GNT# pairs.
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I/O Subsystem R Figure 95. Intel 82801DBM ICH4-M AC’97 – Codec Connection AC / MC / AMC RESET# SDATA_OUT SYNC Intel® ICH4 BIT_CLK SDATA_IN0 SDATA_IN1 Primary Codec SDATA_IN2 AC / MC / AMC Secondary Codec AC / MC / AMC Tertiary Codec NOTE: If a modem codec is configured as the primary AC-link Codec, there should not be any Audio Codecs residing on the AC-link. The primary codec may be connected to AC_SDIN0 as documented in the Intel ICH4-M Datasheet.
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I/O Subsystem R AC_SDIN1, and AC_SDIN2 may not be driven. If the link is enabled, the assumption can be made that there is at least one codec. Figure 96. Intel 82801DBM ICH4-M AC’97 – AC_BIT_CLK Topology Intel® ICH4 AC_BIT_CLK L1 R1 L3 L3 R2 L4 L2 C O N N Primary Codec Table 85. AC’97 AC_BIT_CLK Routing Summary AC’97 Routing Requirements Maximum Trace Length (inches) Series Termination Resistance AC_BIT_CLK Signal Length Matching 5 on 5 L1 = (1 to 8) – L3 R1 = 33 Ω - 47 Ω N/A L2 = 0.
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I/O Subsystem R Table 86. AC’97 AC_SDOUT/AC_SYNC Routing Summary AC’97 Routing Requirements Maximum Trace Length (inches) Series Termination Resistance AC_SDOUT/AC_SYNC Signal Length Matching 5 on 5 L1 = (1 to 6) – L3 R1 = 33Ω - 47 Ω N/A L2 = 1 to 8 R2 = R1 if the connector card that will be used with the platform does not have a series termination on the card. Otherwise R2 = 0 Ω L3 = 0.1 to 0.4 L4 = (0.1 to 6) – L3 NOTES: 1.
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I/O Subsystem R 11.3.1. AC’97 Routing To ensure the maximum performance of the codec, proper component placement and routing techniques are required. These techniques include properly isolating the codec, associated audio circuitry, analog power supplies, and analog ground plane, from the rest of the motherboard. This includes plane splits and proper routing of signals not associated with the audio section. Contact your vendor for devicespecific recommendations.
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I/O Subsystem R 11.3.2. Motherboard Implementation The following design considerations are provided for the implementation of an ICH4-M platform using AC’97. These design guidelines have been developed to ensure maximum flexibility for board designers, while reducing the risk of board-related issues. These recommendations are not the only implementation or a complete checklist, but they are based on the ICH4-M platform.
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I/O Subsystem R Figure 99. Example Speaker Circuit VCC3_3 R Value is Implementation Specific Intel® ICH4-M Integrated Pull-down SPKR 9KΩ - 50KΩ Stuff Jumper to Disable Timeout Feature (No Reboot) Effective Impedance Due to Speaker and Codec Circuit Reff 11.4. USB 2.0 Guidelines and Recommendations 11.4.1. Layout Guidelines 11.4.1.1. General Routing and Placement Use the following general routing and placement guidelines when laying out a new design.
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I/O Subsystem R traces as much as practical. It is preferable to change layers to avoid crossing a plane split. Refer to Section 11.4.2. 8. Separate signal traces into similar categories and route similar signal traces together (such as routing differential pairs together). 9. Keep USB 2.0 USB signals clear of the core logic set. High current transients are produced during internal state transitions and can be very difficult to filter out. 10.
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I/O Subsystem R Figure 101. USBRBIAS Connection Intel® ICH4-M USBRBIAS 22.6Ω+/- 1% USBRBIAS# Table 89. USBRBIAS/USBRBIAS# Routing Summary 11.4.1.4. USBRBIAS/ USBRBIAS# Routing Requirements Maximum Trace Length Signal Length Matching Signal Referencing 5 on 5 500 mils N/A N/A USB 2.0 Termination A common-mode choke should be used to terminate the USB 2.0 bus. Place the common-mode choke as close as possible to the connector pins. See Section 11.4.4 for details. 11.4.1.5. USB 2.
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I/O Subsystem R 11.4.2.1. VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch) Use the following guidelines for the VCC plane. 1. Traces should not cross anti-etch, for it greatly increases the return path for those signal traces. This applies to USB 2.0 signals, high-speed clocks, and signal traces as well as slower signal traces that might be coupling to them. USB signaling is not purely differential in all speeds (i.e. the Full-speed Single Ended Zero is common mode). 2. Avoid routing of USB 2.
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I/O Subsystem R Figure 102. Good Downstream Power Connection 5V 5V Sus 5V Switch Thermister Vcc 1 470pF 220uF Gnd Vcc Port1 4 1 470pF Gnd 11.4.4. Port2 4 EMI Considerations The following guidelines apply to the selection and placement of common-mode chokes and ESD protection devices. 11.4.4.1. Common Mode Chokes Testing has shown that common-mode chokes can provide required noise attenuation.
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I/O Subsystem R 1. 2. 11.4.5. A part must be chosen with the impedance value that provides the required noise attenuation. This is a function of the electrical and mechanical characteristics of the part chosen and the frequency and strength of the noise present on the USB traces that you are trying to suppress. Once you have a part that gives passing EMI results the second step is to test the effect this part has on signal quality.
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I/O Subsystem R 11.5. I/O APIC (I/O Advanced Programmable Interrupt Controller) The Intel ICH4-M is designed to be backwards compatible with a number of the legacy interrupt handling mechanisms as well as to be compliant with the latest I/O (x) APIC architecture. In addition to implementing two 8259 interrupt controllers (PIC), the ICH4-M also incorporates an Advanced Programmable Interrupt Controller (APIC) that is implemented via the 3-wire serial APIC bus that connects all I/O and local APICs.
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I/O Subsystem R micro-controller to perform various functions. For example, the slave write interface can reset or wake a system, generate SMI# or interrupts, and send a message. The slave read interface can read the system power state, read the watchdog timer status, and read system status bits. Both the SMBus Host Controller and the SMBus Slave Interface obey the SMBus 1.
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I/O Subsystem R 11.6.1. 11.6.1.1. SMBus Architecture and Design Considerations SMBus Design Considerations There is not a single SMBus design solution that will work for all platforms. One must consider the total bus capacitance and device capabilities when designing SMBus segments. Routing SMBus to the PCI slots makes the design process even more challenging since they add so much capacitance to the bus.
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I/O Subsystem R Added Considerations for Mixed Architecture 1. The bus switch must be powered by VCC_SUSPEND. 2. Devices that are powered by the VCC_ SUSPEND well must not drive into other devices that are powered off. This is accomplished with the “bus switch”. 3. The bus bridge can be a device like the Phillips PCA9515. 11.6.1.4.
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I/O Subsystem R 11.7. FWH The following provides general guidelines for compatibility and design recommendations for supporting the FWH device. The majority of the changes will be incorporated in the BIOS. Refer to the FWH BIOS Specification or equivalent. 11.7.1. FWH Decoupling Refer to section 13.5.6 for more details. 11.7.2. In Circuit FWH Programming All cycles destined for the FWH will appear on PCI.
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I/O Subsystem R 11.7.4. FWH VPP Design Guidelines The VPP pin on the FWH is used for programming the flash cells. The FWH supports VPP of 3.3 V or 12 V. If VPP is 12 V, the flash cells will program about 50% faster than at 3.3 V. However, the FWH only supports 12-V VPP for 80 hours (3.3 V on Vpp does not affect the life of the device). The 12 V VPP would be useful in a programmer environment, which is typically an event that occurs very infrequently (much less than 80 hours).
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I/O Subsystem R 11.8. RTC The Intel 82801DBM ICH4-M contains a real time clock (RTC) with 256 bytes of battery backed SRAM. The internal RTC module provides two key functions: keeping date and time and storing system data in its RAM when the system is powered down. The ICH4-M uses a crystal circuit to generate a low-swing 32 kHz input sine wave. This input is amplified and driven back to the crystal circuit via the RTCX2 signal.
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I/O Subsystem R 11.8.1. RTC Crystal The Intel 82801DBM ICH4-M RTC module requires an external oscillating source of 32.768 kHz connected on the RTCX1 and RTCX2 balls. Figure 109 documents the external circuitry that comprises the oscillator of the ICH4-M RTC. Figure 109. External Circuitry for the ICH4-M RTC VCCRTC 3.3V Sus 1uF RTCX2 1kΩ R1 10MΩ 32.768 kHz Xtal Vbatt RTCX1 C3 0.
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I/O Subsystem R 11.8.2. External Capacitors To maintain the RTC accuracy, the external capacitor C3 needs to be 0.047 µF and capacitor values C1 and C2 should be chosen to provide the manufacturer’s specified load capacitance (Cload) for the crystal when combined with the parasitic capacitance of the trace, socket (if used), and package.
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I/O Subsystem R Note that the temperature dependency of crystal frequency is a parabolic relationship (ppm / degree square). The effect of changing the crystal’s frequency when operating at 0°C (25°C below room temperature) is the same when operating at 50°C (25°C above room temperature). 11.8.3. RTC Layout Considerations Since the RTC circuit is very sensitive and requires high accuracy oscillation, reasonable care must be taken during layout and routing of the RTC circuit.
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I/O Subsystem R Figure 110. Diode Circuit to Connect RTC External Battery V CCSUS 3_3 VccRTC 1.0uF 1K A standby power supply should be used in a mobile system to provide continuous power to the RTC when available, which will significantly increase the RTC battery life and thereby the RTC accuracy. 11.8.5. RTC External RTCRST# Circuit Figure 111. RTCRST# External Circuit for the ICH4-M RTC VCCSUS3_3 DIODE/ BATTERY CIRCUIT VccRTC 1.0uF 1K 180K RTCRST # 0.
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I/O Subsystem R remains set until software clears it. As a result, when the system boots, the BIOS knows that the RTC battery has been removed. This RTCRST# circuit is combined with the diode circuit (shown in Figure 110) whose purpose is to allow the RTC well to be powered by the battery when the system power is not available. Figure 111 is an example of this circuitry that is used in conjunction with the external diode circuit. 11.8.6.
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I/O Subsystem R 82540EP Gigabit Ethernet Controller, Intel® 82551QM Fast Ethernet Controller, Intel® 82562ET, and Intel® 82562EM Platform LAN Connect components. Table 94. LAN Component Connections/Features LAN Component Interface to ICH4-M Connection Features ® PCI Gigabit Ethernet (1000BASE-T) with Alert Standard Format (ASF) alerting Gigabit Ethernet, ASF 1.0 alerting, PCI 2.2 compatible ® PCI Performance 10/100 Ethernet with ASF alerting Ethernet 10/100 connection, ASF 1.0 alerting, PCI 2.
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I/O Subsystem R Table 95. LAN Design Guide Section Reference Layout Section 11.9.2. Figure 112 Reference Design Guide Section Intel ICH4-M – LAN Connect Interface (LCI) A Reference Section 11.9.2 Intel 82562ET / Intel 82562EM B Reference Section 11.9.3 Intel 82551QM / Intel 82540EP C Reference Section 11.9.5 Intel® 82801DBM ICH4-M – LAN Connect Interface Guidelines This section contains guidelines on how to implement a Platform LAN Connect device on a system motherboard.
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I/O Subsystem R 11.9.2.1. Bus Topologies The Platform LAN Connect Interface can be configured in several topologies: • Direct point-to-point connection between the ICH4-M and the LAN component • LOM Implementation 11.9.2.1.1. LAN On Motherboard Point-To-Point Interconnect The following are guidelines for a single solution motherboard. Either Intel 82562EM or Intel 82562ET is uniquely installed. Figure 113.
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I/O Subsystem R Figure 114. LAN_CLK Routing Example LAN_CLK LAN_RXD0 11.9.2.3. Crosstalk Consideration Noise due to crosstalk must be carefully controlled to a minimum. Crosstalk is the key cause of timing skews and is the largest part of the tRMATCH skew parameter. tRMATCH is the sum of the trace length mismatch between LAN_CLK and the LAN data signals. To meet this requirement on the board, the length of each data trace is either equal to or up to 0.5 inches shorter than the LAN_CLK trace.
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I/O Subsystem R 11.9.3.1. Guidelines for Intel 82562ET / Intel 82562EM Component Placement Component placement can affect signal quality, emissions, and temperature of a board design. This section will provide guidelines for component placement. Careful component placement can: • Decrease potential problems directly related to electromagnetic interference (EMI), which could cause failure to meet FCC and IEEE test specifications. • Simplify the task of routing traces.
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I/O Subsystem R 11.9.3.4. Critical Dimensions There are two dimensions to consider during layout. Distance ‘A’ from the line RJ-45 connector to the magnetics module and distance ‘B’ from the Intel 82562ET or Intel 82562EM to the magnetics module. The combined total distances A and B must not exceed 4 inches (preferably, less than 2 inches). (See Figure 116.) Figure 116.
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I/O Subsystem R Note: Measured trace impedance for layout designs targeting 100 Ω often result in lower actual impedance. OEMs should verify actual trace impedance and adjust their layout accordingly. If the actual impedance is consistently low, a target of 105 Ω to 110 Ω should compensate for second order effects. 11.9.3.4.2. Distance from Intel 82562ET / 82562ET to Magnetics Module (Distance B) Distance B should also be designed to be less than one inch between devices.
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I/O Subsystem R Figure 117. Termination Plane TDP N/C TDN RDP RJ-45 RDN Magnetics Module Termination Plane Addition Capacitance that may need to be added for EFT testing 11.9.4. Intel 82562ET/EM Disable Guidelines To disable the Intel 82562ET/EM, the device must be isolated (disabled) prior to reset (RSM_PWROK) asserting. Using a GPIO, such as GPO28 to be LAN_Enable (enabled high), LAN will default to enabled on initial power-up and after an AC power loss.
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I/O Subsystem R The four control signals shown in the below table should be configured as follows: Test_En should be pulled-down thru a 100-Ω resistor. The remaining 3 control signals should each be connected thru 100Ω series resistors to the common node “Intel 82562ET/EM _Disable” of the disable circuit. Table 97.
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I/O Subsystem R • Maintain constant symmetry and spacing between the traces within a differential pair. • Keep the signal trace lengths of a differential pair equal to each other. • Keep the total length of each differential pair under 4 inches. [Many customer designs with differential traces longer than 5 inches have had one or more of the following issues: IEEE phy conformance failures, excessive EMI (Electro Magnetic Interference), and/or degraded receive BER (Bit Error Rate).
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I/O Subsystem R 11.9.6.1.1. Trace Geometry and Length The key factors in controlling trace EMI radiation are the trace length and the ratio of trace-width to trace-height above the ground plane. To minimize trace inductance, high-speed signals and signal layers that are close to a ground or power plane should be as short and wide as practical. Ideally, this trace width to height above the ground plane ratio is between 1:1 and 3:1.
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I/O Subsystem R Figure 120. Ground Plane Separation 0.10 Inches Minimum Spacing Magnetics Module Void or Separate Ground Plane Separate Chassis Ground Plane Good grounding requires minimizing inductance levels in the interconnections and keeping ground returns short, signal loop areas small, and power inputs bypassed to signal return, will significantly reduce EMI radiation. Some rules to follow that will help reduce circuit inductance in both back planes and motherboards.
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I/O Subsystem R 11.9.6.2. Common Physical Layout Issues Here is a list of common physical layer design and layout mistakes in LAN On Motherboard Designs. 1. Unequal length of the two traces within a differential pair. Inequalities create common-mode noise and will distort the transmit or receive waveforms. 2. Lack of symmetry between the two traces within a differential pair.
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I/O Subsystem R at higher frequencies and will degrade the transmit BER performance. Caution should be exercised if a cap is put in either of these locations. If a cap is used, it should almost certainly be less than 22 pF. (6 pF to 12 pF values have been used on past designs with reasonably good success.) These caps are not necessary, unless there is some overshoot in 100 Mbps mode. Note: It is important to keep the two traces within a differential pair close† to each other.
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I/O Subsystem R 11.11. CPU I/O Signal Considerations The Intel 82801DBM ICH4-Mhas been designed to be voltage compatible with the CMOS signals of the Intel Pentium M / Intel Celeron M processor. For Intel Pentium M / Intel Celeron M processor -based systems, the ICH4-M’s V_CPU_IO rail uses the same 1.05-V voltage as the VCCP rails for the processor the GMCH. It is important to verify that the voltage requirements of all CPU and ICH4-M signals are compatible with the FWH as well. See Section 11.
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Platform Clock Routing Guidelines R 12. Platform Clock Routing Guidelines 12.1. System Clock Groups The system clocks are considered as a subsystem in themselves. At the center of this subsystem is the Clock Synthesizer/Driver component. Several vendors offer suitable products, as defined in the Intel CK-408 Synthesizer/Driver Specification. This device provides the set of clocks required to implement a platform level motherboard solution.
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Platform Clock Routing Guidelines R Figure 122 below depicts the system clock subsystem including the clock generator, major platform components, and all the related clock interconnects. Figure 122.
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Platform Clock Routing Guidelines R 12.2.1. Host Clock Group The clock synthesizer provides three pairs of 100-MHz differential clock outputs utilizing a 0.7-V voltage swing. The 100-MHz differential clocks are driven to the processor, the GMCH, and the processor debug port with the topology shown in the figure below. The host clocks are routed point to point as closely coupled differential pairs on the motherboard, with dedicated buffers for each of the three loads.
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Platform Clock Routing Guidelines R Table 99. Host Clock Group Routing Constraints Parameter Definition Class Name HOST_CLK Class Type Individual Differential Pairs Topology Differential Source Shunt Terminated Reference Plane Ground Referenced (contiguous over length) Single Ended Trace Impedance ( Zo ) 55 Ω +/-15% Differential Mode Impedance (Zdiff) 100 Ω +/- 15% Nominal Inner Layer Trace Width 4.0 mils Nominal Inner Layer Pair Spacing (edge to edge) 7.
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Platform Clock Routing Guidelines R 3. To minimize skew it is recommended that all clock pairs be length matched from CK408 pin to CPU and GMCH die-pad, and length compensated on the motherboard for differences in package length and for socket/interposer effective length. A table of package lengths and equivalent socket lengths are provided. 4. The motherboard length of the ITP connector clock pair should be matched to the sum of the motherboard length of the CPU clock pair and the BPM[3:0]# signals. 5.
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Platform Clock Routing Guidelines R Figure 124. BCLK to GCLKIN Timing Requirement When assessing whether a system design meets the required BCLK/GCLKIN phase relationship, the following factors should be taken into account: • Selected clock synthesizer chip’s worst case (minimum) phase relationship between CLK66 (GCLKIN) and HCLKx (BCLK) rising edges. This includes the following clock timing parameters:  Min phase offset.
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Platform Clock Routing Guidelines R 12.2.2. CLK66 Clock Group The 66-MHz clocks are series terminated and are routed point to point on the motherboard, with dedicated buffers for each of the loads. These clocks are all length tuned to match each other and as well as to the CLK33 clocks. Figure 125.
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Platform Clock Routing Guidelines R Table 101. CLK66 Clock Group Routing Constraints Parameter Definition Class Name CLK66 Class Type Individual Nets Topology Series Terminated Point to Point Reference Plane Ground Referenced Single Ended Trace Impedance ( Zo ) 55 Ω+/-15% Nominal Inner Layer Trace Width 4.0 mils Nominal Outer Layer Trace Width 5.
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Platform Clock Routing Guidelines R 12.2.3. CLK33 Clock Group The 33-MHz clocks are series terminated and routed point to point on the motherboard with dedicated buffers for each of the loads. These clocks are length tuned to match the CLK66 clocks, however, they are out of phase due to an internal phase delay in the CK408. Figure 126. CLK33 Group Topology Rs L1 L2 ICH4-M SIO, FWH CK408 Table 102.
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Platform Clock Routing Guidelines R 12.2.4. PCI Clock Group The PCI clocks are series terminated and routed point to point as on the Inter reference motherboard between the CK408 and the PCI connectors, with a dedicated buffer for each slot. These clocks are synchronous to the CLK33 clocks and are length tuned to compensate for the segment on the PCI daughter card. Figure 127. PCI Clock Group Topology Rs L1 L2 L3 Trace on Card PCI Connector CK408 PCI Device Table 103.
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Platform Clock Routing Guidelines R 12.2.5. CLK14 Clock Group The 14-MHz clocks are series terminated and routed point to point on the motherboard. A single clock output is shared between the two loads. These clocks are length tuned to each other but are not synchronous with any other clocks. Figure 128. CLK14 Clock Group Topology Rs L1 L2 A C K 408 IC H 4-M Rs L2B S IO Table 104.
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Platform Clock Routing Guidelines R 12.2.6. DOTCLK Clock Group The 48-MHz DOTCLK is series terminated and routed point to point on the motherboard. This clock operates independently and is not length tuned to any other clock. Figure 129. DOTCLK Clock Topology Rs L1 L2 GMCH CK408 Table 105.
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Platform Clock Routing Guidelines R 12.2.7. SSCCLK Clock Group The 48/66-MHz SSCCLK operates independently and is not length tuned to any other clock. This clock employs a spread-spectrum device in its path to reduce EMI. The overall clock path is divided into two segments as shown in Figure 130, with each segment series terminated and routed point to point. Figure 130. SSCCLK Clock Topology Rs L1 L2 SSC CK408 GMCH Rs L3 L4 Table 106.
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Platform Clock Routing Guidelines R 12.2.8. USBCLK Clock Group The 48-MHz USBCLK is series terminated and routed point to point on the motherboard. This clock operates independently and is not length tuned to any other clock. Figure 131. USBCLK Clock Topology Rs L1 L2 GMCH CK408 Table 107.
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Platform Clock Routing Guidelines R 12.3. CK-408 Clock Updates for Intel Pentium M Processor and Intel Celeron M Processor Platforms To maximize the power savings on 855GM chipset based systems, additional control registers have been added to the CK-408clock generator to allow option to tri-state the CPU[2:0] host clocks during CPU_STOP# or PWRDWN assertion. The option to have CPU[2:0] driven (default) or tri-stated can be programmed via the serial I2C bus interface to the CK-408 clock driver.
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Intel 855GM/GME Chipset Based System Power Delivery Guidelines R 13. Intel 855GM/GME Chipset Based System Power Delivery Guidelines 13.1. Definitions Table 108. Power Delivery Definitions Term Definition S0/Full-On operation: During S0 operation, all components on the motherboard are powered and the system is fully functional. S1-M/Power-OnSuspend (POS, Mobile): In the mobile implementation of the Power-On-Suspend state, the outputs of the clock chip are stopped in order to save power.
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Intel 855GM/GME Chipset Based System Power Delivery Guidelines R The solutions given in this document are only examples. There are many power distribution methods that achieve similar results. It is critical, when deviating from these examples, to consider the effect of the change. 13.2.1. Platform Power Delivery Architectural Block Diagram Figure 132. Platform Power Delivery Map Intel® Pentium® M Processor / Dothan Processor VCC_CORE = IMVP-IV VCCP = IMVP-IV VCCA =+V1.
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Intel 855GM/GME Chipset Based System Power Delivery Guidelines R 13.3. Voltage Supply 13.3.1. Power Management States Table 109. Power Management States on Intel Reference Board 13.3.2.
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Intel 855GM/GME Chipset Based System Power Delivery Guidelines R Signal Names Voltage (V) Current (A) Tolerance Enable Description +V3ALWAYS 3.3 0.4 +/- 5% +VDC_ON ICH4-M Resume, SMC/KBC, AC’97 +V3 3.3 0.9 +/- 5% SLP_S5# - HIGH ICH4-M LAN I/O, AC’97, RS232 +V3S 3.3 7.0 +/- 5% SLP_S3# - HIGH GMCH GPIO, ICH4-M I/O, CK-408, FWH, SIO,PCI +V5 5 9.0 +/- 5% SLP_S5# - HIGH AC’97, +V5S 5 1.0 +/- 5% SLP_S3# - HIGH ICH4-M VREF, MSE/KBD, FDD, IDE, PCI +V5ALWAYS 5 3.
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Intel 855GM/GME Chipset Based System Power Delivery Guidelines R Figure 133. GMCH Power-Up Sequence CPURST# 1ms max RSTIN# 1ms min PWROK GMCH PWR Rails 13.4.3. ICH4-M Power Sequencing Requirements The following figure describes the power-on timing sequence for ICH4-M. The VGATE input should be connected to the processor voltage regulator PWRGD output. When both PWROK and VGATE are asserted, it indicates that core power and system power are stable and PCIRST# will be de-asserted a minimum of 1 ms later.
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Intel 855GM/GME Chipset Based System Power Delivery Guidelines R Figure 134.
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Intel 855GM/GME Chipset Based System Power Delivery Guidelines R Table 111. Timing Sequence Parameters ICH4-M Sym Description Min Max Units T173 Notes VccSus supplies active to RSMRST# inactive 10 - ms T176 Vcc1.5, Vcc3.
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Intel 855GM/GME Chipset Based System Power Delivery Guidelines R Figure 135. Example V5REF / V5REFSUS Sequencing Circuitry 13.4.3.3. V5REFSUS Design Guidelines The aforementioned rule for V5REF also applies to the V5REF_SUS input pin. However, in some platforms, the VCCSUS3_3 rail is derived from the VCCSUS5 and therefore, the VCCSUS3_3 rail will always come up after the VCCSUS5 rail. As a result, V5REF_SUS will always be powered up before VCCSUS3_3.
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Intel 855GM/GME Chipset Based System Power Delivery Guidelines R Figure 137. V5REFSUS With +V3ALWAYS and +V5S or +V5 Connection Option +V5S or +V5 Customer specific or Intel recommended USB power circuit +V3ALWAYS D1 D2 V5REF_SUS1 V5REF_SUS2 USB Power (5V) 0.1uF ICH4-M Customer specific or Intel recommended USB interface circuits USB D+ USB D- USB D+ USB D- GND Note: D1 and D2 are BAT54 or Equivalent Schottky Diodes 13.4.4.
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Intel 855GM/GME Chipset Based System Power Delivery Guidelines R 13.5. Intel 855GM/GME Chipset Based System Power Delivery Guidelines Each component is capable of generating large current swings when switching between logic high and logic low. This condition could cause the component voltage rails to drop below specified limits. To avoid this type of situation, ensure that the appropriate amount of bulk capacitance is added in parallel to the voltage input pins.
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Intel 855GM/GME Chipset Based System Power Delivery Guidelines R 13.5.1. 855GM/GME Chipset GMCH Decoupling Guidelines Decoupling in Table 15 is based on voltage regulator solution used on the customer reference board design. Table 113. GMCH Decoupling Recommendations Pin Name Configuration F Qty TYPE Notes VCC Connect to VCC1_2S for 855GM 0.1 µF 4 XR7, 0603, 16 V, 10% 1 X 0.1 µF within 200 mils 10 µF 1 XR5, 1206, 6.3 V, 20% 3 X 0.1 µF on bottom side 150 µF 2 SPC, E, 6.3 V, 20% 0.
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Intel 855GM/GME Chipset Based System Power Delivery Guidelines R 13.5.1.1. GMCH VCCSM Decoupling For the VCCSM pins of the GMCH, a minimum of eleven, 0603 form factor, 0.1-µF, high frequency capacitors is required and must be placed within 150 mils of the GMCH package. The capacitors should be evenly distributed along the GMCH DDR system memory interface and must be placed perpendicular to the GMCH with the power (2.5 V) side of the capacitors facing the GMCH.
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Intel 855GM/GME Chipset Based System Power Delivery Guidelines R • JEDEC Standard, JESD79 (release 2), Double Data Rate (DDR) SDRAM Specification • Intel DDR 266 JEDEC Spec Addendum Rev 1.0 or later Figure 139. DDR Power Delivery Block Diagram +V5 S w itc h in g R e g u la t o r V in +V 2_5 Vout S e n s e A d j. 10K 10K + SMVREF - +V5 S w itc h i n g R e g u la t o r V in Vout +V1_25S S e n s e A d j. NOTE: 13.5.2.1. +V1.
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Intel 855GM/GME Chipset Based System Power Delivery Guidelines R 13.5.2.3. DDR SMRCOMP Resistive Compensation The GMCH requires a system memory compensation resistor, SMRCOMP, to adjust buffer characteristics to specific board and operation environment characteristics. Refer to the RS – Intel® 855GM/GME (Montara-GM/GM+) Chipset GMCH External Design Specification and Figure 140 for details on resistive compensation. The SMRCOMP signal should be routed with as wide a trace as possible.
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Intel 855GM/GME Chipset Based System Power Delivery Guidelines R tolerance and VTT can vary more easily depending on signal states. A solid 1.25V termination island should be used to for this purpose and be placed on the surface signal layer, just beyond the last SODIMM connector and must be at least 50 mils wide. The Data and Command signals should be terminated using one resistor per signal. Resistor packs and ± 5% tolerant resistors are acceptable for this application.
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Intel 855GM/GME Chipset Based System Power Delivery Guidelines R Figure 143. GMCH HAVREF Reference Voltage Generation Circuit +VCCP R1 49.9 1% GMCH Y22 GMCH_HAVREF R2 100 1% C1 1uF HAVREF C3 0.1uF Figure 144. GMCH HCCVREF Reference Voltage Generation Circuit +VCCP R1 49.9 1% GMCH Y28 GMCH_HCCVREF R2 100 1% 13.5.3.2. C1 1uF HCCVREF C3 0.1uF GMCH AGTL+ I/O Buffer Compensation The HXRCOMP and HYRCOMP pins of the GMCH should each be pulled-down to ground with a 27.4 Ω ± 1% resistor.
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Intel 855GM/GME Chipset Based System Power Delivery Guidelines R 13.5.3.3. GMCH AGTL+ Reference Voltage The GMCH’s AGTL+ I/O buffer resistive compensation mechanism also requires the generation of reference voltages to the HXSWING and HYSWING pins with a value of 1/3*VCCP. Implementations for HXSWING and HYSWING voltage generation are illustrated in Figure 146. Two resistive dividers with R1a = R1b = 301 Ω ± 1% and R2a = R2b = 150 Ω ± 1% generate the HXSWING and HYSWING voltages. C1a = C1b = 0.
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Intel 855GM/GME Chipset Based System Power Delivery Guidelines R Table 114. Analog Supply Filter Requirements Required GMCH Filters Config Rdamp Rdamp location L Cbulk Chigh VCCASM V1.5S None N/A 1210 1.0 µH DCRmax 0.169 Ωs 100 µF 0603 0.1 µF X5R VCCQSM V2.5S 1Ω In series with Cbulk 0805 0.68 µH DCRmax 0.80 Ωs 1206 4.7 µF X5R 0603 0.1 µF X5R VCCAHPLL V_1.2S None N/A None 1Ω In series with inductor 0805 0.10 µH 220uF 0603 0.1 µF X5R 1Ω In series with inductor 0805 0.
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Intel 855GM/GME Chipset Based System Power Delivery Guidelines R Table 115. ICH4-M Decoupling Requirements Pin Name Configuration F Qty VCC3_3 Connect to Vcc3_3S 0.1 µF 6 VCCSUS3_3 Connect to Vcc3_3A 0.1 µF 2 VCCLAN3_3 Connect to Vcc3_3 0.1 µF 2 V_CPU_IO Connect to Vccp IMVP-IV 1 µF 1 1 µF 1 VCC1_5 Connect to Vcc1_5S 0.1 µF 2 VCCSUS1_5 Connect to Vcc1_5A 0.1 µF 2 VCCLAN1_5 Connect to Vcc1_5 0.1 µF 2 V5REF Connect to Vcc5_Ref 0.1 µF 1 V5REF_SUS Connect to Vcc5A 0.
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Intel Pro/Wireless 2100/2100A – Bluetooth Coexistence Interface Design Requirements R 14. Intel Pro/Wireless 2100/2100A – Bluetooth Coexistence Interface Design Requirements This section describes the design requirements needed to support the Intel PRO/Wireless 2100/2100A wireless component, a critical component of the latest Intel Centrino mobile technology. The following discussion provides guidelines on the interface design between the Intel PRO/Wireless 2100/2100A 802.
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Intel Pro/Wireless 2100/2100A – Bluetooth Coexistence Interface Design Requirements R Figure 148. Recommended Topology for Coexistence Traces Intel® PRO/Wireless 2100/2100A 14.2. DC Power Requirements for Bluetooth The Bluetooth* module requires a 3.3-V power supply that can be regulated within a tolerance of ±2%. This source may be derived from any power rail available on the platform. 14.3.
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Intel Pro/Wireless 2100/2100A – Bluetooth Coexistence Interface Design Requirements R This concern exists for any condition in which the power provided to either component has been disabled through any number of means. The solution illustrated in Figure 148 will adequately prevent any of these possible conditions from affecting system performance or damaging the hardware. 14.4. USB Selective Suspend See section 11.4.6 for information regarding Bluetooth power requirements during selective suspend.
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Reserved, NC, and Test Signals R 15. Reserved, NC, and Test Signals The Intel Pentium M processor, Intel Pentium M Processor on 90 nm Process with 2 MB L2 Cache, 855GM/GME chipset GMCH may have signals listed as “RSVD”, “NC”, or other name whose functionality is Intel reserved. The following section contains recommendations on how these Intel reserved signals on the processor or GMCH should be handled. 15.1.
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Reserved, NC, and Test Signals R 15.3. Intel 855GM/GME Chipset GMCH RSVD Signals The Intel 855GM/GME chipset GMCH has a total of 13 RSVD and 12 NC signals that are Intel reserved in the pin-map. The recommendation is to provide test points for all RSVD signals for possible future use. All NC signals should be left as no connects. The location of the Intel reserved signals in the GMCH pin-map is listed in Table 117. Table 117.
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Platform Design Checklist R 16. Platform Design Checklist The following checklist provides design recommendations and guidance for the Intel Pentium M processor and Intel Celeron M processor systems with the Intel 855GM/855GME chipset. It should be used to ensure that design recommendations in the design guide have been followed prior to schematic reviews. However, this is not a complete list and does not contain detailed layout information.
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Platform Design Checklist R 16.2. Customer Implementation of Voltage Rails Fill in schematic name of voltage rails and mark boxes of when rails are powered on. Name of Rail 16.3. On S0-S1 On S3 On S4 On S5 Design Checklist Implementation The voltage rail designations in this Design Checklist are intended to be as general as possible. The following table describes the equivalent voltage rails in the Intel CRB Schematics. Checklist Rail Intel CRB Rail On S0-S1 Vcc1_2 +V1.
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Platform Design Checklist R Checklist Rail Intel CRB Rail On S0-S1 Vcc3_3 +V3.3S_ICH, X On S3 On S4 On S5 Notes +V3.3S_GMCH_GPIO, +V3.3S_CLKRC, +V3.3S_SPD, +V3.3S_LVDS, +V3.3S_FWH VccSus3_3 +V3.3_ICHLAN, X 1,2,3 +V3.3_LAN V3ALWAYS +V3.3ALWAYS_ICH X Vcc5 +V5S_DAC X VccSus5 +V5_USB X X V5ALWAYS +V5A_ICH X Vcc12 +V12S X VccRTC +V_RTC X VCCP +VCC_IMVP X VCCA +V1.8S_PROC X VccCORE +VCC_CORE X NOTES: 1. 2. 3. 4. 5.
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Platform Design Checklist R 16.4. Intel Pentium M Processor / Intel Celeron M Processor 16.4.1. Resistor Recommendations Pin Name System Pull-up/Pull-down Series Termination Voltage Translation A20M# Notes 9 Point-to-point connection to ICH4-M. BR0# Point-to-point connection to GMCH. COMP0, COMP2 27.4 Ω ± 1% pulldown to gnd Resistor placed within 0.5” of processor pin. Trace should be 27.4 Ω ± 15%. COMP1, COMP3 54.9 Ω ± 1% pulldown to gnd Resistor placed within 0.5” of processor pin.
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Platform Design Checklist R Pin Name System Pull-up/Pull-down RESET# 54.9 Ω ± 1% pull-up to VCCP If USING ITP700FLEX Series Termination 22.6 Ω ± 1% from pull-up to ITP700FLEX Voltage Translation Notes If ITP700FLEX is Not Used: Point-topoint connection to GMCH. If ITP700FLEX is Used: RESET# connects from processor to GMCH and then forks out to ITP700 FLEX, with pullup and series damping resistor placed next to ITP. RSVD (pin AC1, AF7, C3, C14, E26, G1) Route to test points.
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Platform Design Checklist R Figure 149. Routing Illustration for INIT# FWH 3.3V CPU V_IO_FWH 3.3V ICH4-M R2 R1 Q2 L1 L2 L3 L4 3904 Q1 3904 Rs Figure 150. Voltage Translation Circuit for PROCHOT# 3.3V 3.3V 1.
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Platform Design Checklist R 16.4.2. In Target Probe (ITP) Pin Name System Pull-up /Pull-down Series Termination Resistor (Ω) BPM[5:0]# 9 Notes Connect to processor directly. DBR# 150-240 Ω pull-up to V3ALWAYS RESET# 54.9 Ω ± 1% pull-up to VCCP If using ITP on interporser card, then DBR# should also be connected to DBRESET pin at the processor. The 150-240 Ω pull-up resistor should be placed within 1 ns of the ITP700FLEX connector. The CPU should not be power cycled when DBR# is asserted.
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Platform Design Checklist R 16.4.3.2. VCCA (PLL) Description C, µF 9 Notes Mid Frequency Decoupling (Polymer Covered Tantalum POSCAP, Neocap, KO Cap) 4 x 10 µF Place one 10 µF and one 0.01 µF for each VCCA pin. High Frequency Decoupling (0603 MLCC, >= X7R) Place next to the processor 4 x 0.01 µF Place one 10 µF and one 0.01 µF for each VCCA pin. 16.4.3.3.
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Platform Design Checklist R 16.5. CK-408 Clock Checklist 16.5.1. Resistor Recommendations Pin Name System Series Resistor Notes 9 Pull-up/Pull-down 33 Ω If the signal is used, one 33-ohm series resistor is required. If the signal is NOT used, it should be left as NC (Not Connected) or connected to a test point. 33 Ω Use 66BUF[1] (pin 22) for GMCH. Use one of the other two signals for ICH4-M. 33 Ω Use one pair for the processor and another pair for GMCH.
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Platform Design Checklist R Figure 151.
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Platform Design Checklist R 16.6. Intel 855GM/855GME Checklist 16.6.1. System Memory 16.6.1.1. GMCH System Memory Interface Pin Name System Pull-up/Pull-down Series Resistor Notes RCVENIN# This signal should be routed to a via next to ball and left as a NC (No Connect). RCVENOUT# This signal should be routed to via next to ball and left as a NC (No Connect).
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Platform Design Checklist R Pin Name System Pull-up/Pull-down SMRCOMP 60.4 Ω 1% pull-up to VccSus2_5 60.4 Ω 1% pull-down to gnd 292 Series Resistor Notes 9 Signal voltage level = 1/2 * VccSus2_5. Need 0.1 µF cap by the voltage divider. This signal may be optionally connected to Vcc2_5 and powered off in S3.
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Platform Design Checklist R Figure 152. Reference Voltage Level for SMVREF VccSus2_5 10k+/- 1% GMCH + - 10k+/-1 % 16.6.1.2. Pin Name SMVREF 0.1 uF DDR SO-DIMM Interface Configuration Notes VREF[2:1] Connect to VccSus2_5 VDDSPD Connect to Vcc3_3 SA[2:0] Connect to either VC3_3 or gnd VSS[31:1] Connect to gnd Power must be provided during S3. These lines are used for strapping the SPD address for each SO-DIMM.
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Platform Design Checklist R 16.6.2. Pin Name FSB System 9 Notes Pull-up/Pull-down HXSWING, HYSWING 301 Ω 1% pull-up to VCCP 150 Ω 1% pull-down to gnd Signal voltage level = 1/3 of VCCP. C1a=0.1 µF. C1b=0.1 µF. Trace should be 10-mil wide with 20-mil spacing. See Figure 153. HXRCOMP, HYRCOMP 27.4 Ω 1% pull down to gnd One pulled-down resistor per pin. Trace should be 10-mil wide with 20-mil spacing. HDVREF[2:0] 49.9 Ω 1% pull-up to VCCP Signal voltage level = 2/3 of VCCP. Need one 0.
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Platform Design Checklist R 16.6.3. Hub Interface Pin Name System Notes 9 Pull-up/Pull-down HLVREF See Section16.7.9. Signal voltage level = 0.35 V ± 8%. PSWING See Section16.7.9. Signal voltage level = 2/3 of VCC1_2 or 0.8 V ± 8%. HLZCOMP 27.4 Ω 1% pull-up to Vcc1_2 16.6.4. Graphics Interfaces 16.6.4.1. LVDS Pin Name System Notes 9 Pull-up/Pull-down LIBG YAP[3:0]/YAM[3:0] YBP[3:0]/YBM[3:0] CLKAP/CLKAM CLKBP/CLKBM LVREFH, LVREFL, LVBG 1.
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Platform Design Checklist R 16.6.4.2. DVO Pin Name System Notes 9 Pull-up/Pull-down DVORCOMP GVREF 40.2 Ω 1% pull-down to gnd Trace should be 10-mil wide with 20-mil spacing. 1 kΩ 1% pull-up to Vcc1_5 Signal voltage level = 1/2 of Vcc1_5. Need 0.1 µF cap at pin. 1 kΩ 1% pull-down to gnd DVOCD[11:0] If unused, these signals can be left as NC. DVOCCLK DVOCCLK# DVOCHSYNC DVOCVSYNC DVOCBLANK# DVOCFLDSTL 100 kΩ pull-down to gnd Pull-down resistor required only if signal is unused (10 k-100 k).
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Platform Design Checklist R Figure 154. DPMS Clock Implementation Vcc1_5 1K To GMCH PM_SUS_CLK DPMS pin 3 From ICH4-M BSS138 SUS_CLK 1 2 SUSCLK 16.6.4.3. Pin Name DAC System Pull-up /Pull-down In Series Notes REFSET 127 Ω 1% pull-down to gnd RED # Connect to gnd Need to connect to RED’s return path BLUE # Connect to gnd Need to connect to BLUE’s return path GREEN# Connect to gnd Need to connect to GREEN’s return path RED On GMCH side of ferrite bead: 75 Ω 1% pull-down to gnd, 3.
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Platform Design Checklist R 16.6.5. Pin Name Miscellaneous System Notes 9 Pull-up/Pull-down EXTTS 10 kΩ 1% pull-up to Vcc3_3 DPWR# (pin AA22) Connect to the processor. LCLKCTLB Leave as NC if not used. LCLKCTLA Leave as NC if not used. GST[2:0] 298 Leave as NC or 1 kΩ pull-up to Vcc1_5 These pins have internal pull-down.
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Platform Design Checklist R 16.6.6. Pin Name VCC VTTLF GMCH Decoupling Recommendations Configuration Connect to Vcc1_2 Connect to VCCP VTTHF VCCHL VCCSM VCCQSM VCCASM VCCDVO VCCADAC VCCALVDS VCCDLVDS VCCTXLVDS VCCGPIO VCCAHPLL Connect to Vcc1_2 Connect to VccSus2_5 Connect to VccSus2_5 with filter network Connect to Vcc1_2 with network filter Connect to Vcc1_5 Connect to Vcc1_5 Connect to Vcc1_5 Connect to Vcc1_5 Connect to VccSus2_5 Connect to Vcc3_3 Connect to Vcc1_2 F Qty 0.
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Platform Design Checklist R Pin Name Configuration F Qty VCCAGPLL Connect to Vcc1_2 0.1 µF 1 VCCADPLLA Connect to Vcc1_2 with network filter 0.1 µF 1 220 µF 1 0.1 µF 1 220 µF 1 VCCADPLLB NOTE: 300 Connect to Vcc1_2 with network filter Notes 9 0.1 uH from power supply to GMCH pins, with caps on GMCH side of inductor. 0.1 uH from power supply to GMCH pins, with caps on GMCH side of inductor. Decoupling guidelines are recommendations based on our reference board design.
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Platform Design Checklist R 16.7. Note: ICH4-M Checklist All inputs to the ICH4-M must not be left floating. Many GPIO signals are fixed inputs that must be pulled up to different sources. 16.7.1. PCI Interface and Interrupts Pin Name System Pull-up /Pull-down PCI_DEVSEL# 8.2 kΩ pull-up to Vcc3_3 PCI_FRAME# 8.2 kΩ pull-up to Vcc3_3 PCI_GPIO0 / REQA# 8.2 kΩ pull-up to Vcc3_3 Notes 9 Each signal requires a pull-up resistor.
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Platform Design Checklist R 16.7.2. GPIO Note: Ensure ALL unconnected signals are OUTPUTS ONLY. Only GPIO[7:0] are 5 V tolerant. Recommendations 9 GPIO[7] & [5:0]: • • • • • • • These pins are in the Main Power Well. Pull-ups must use the VCC3_3 plane. Unused core well inputs must be pulled up to VCC3_3. GPIO[1:0] can be used as REQ[B:A]#. GPIO[1] can be used as PCI REQ[5]#. GPIO[5:2] can be used as PIRQ[H:E]#. These signals are 5 V tolerant. These pins are inputs.
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Platform Design Checklist R 16.7.3. AGP_BUSY# Design Requirement Signal System Notes 9 Pull-up/Pull-down AGPBUSY# 10 KΩ pull-up to Vcc3_3 This ICH4-M signal requires a pull-up to the switched 3.3-V rail (powered OFF during S3). This ICH4-M signal must be connected to the AGP_BUSY# output of GMCH. NOTE: Please also consult Intel for the latest AGP Busy and Stop signal implementation. 16.7.4.
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Platform Design Checklist R 16.7.5. AC ’97 Interface Pin Name System Pull-up/Pull-down AC_BIT_CLK None Series Termination Resistor Notes 33-47 Ω The internal pull-down resistor is controlled by the AC’97 Global Control Register, ACLINK Shut Off bit: 9 1 = enabled; 0 = disabled When no AC'97 devices are connected to the link, BIOS must set the ACLINK Shut Off bit for the internal keeper resistors to be ENABLED. At that point, pull-ups/pulldowns are NOT needed on ANY of the link signals.
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Platform Design Checklist R 16.7.6. ICH4-M Power Management Interface Pin Name System Notes 9 Pull-up/Pull-down PM_DPRSLPVR Signal has integrated pull-down in ICH4-M. PM_SLP_S1#/GPIO19 PM_SLP_S3#, PM_SLP_S4#, PM_SLP_S5# Signals driven by ICH4-M. 10 kΩ pull-up to V3ALWAYS PM_BATLOW# IF NOT USED Pull up is not required if it is used. However, signal must not float if it is NOT being used 10 kΩ pull-up to Vcc3_3 PM_CLKRUN# Has integrated pull-up of 18 kΩ – 42 kΩ.
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Platform Design Checklist R 16.7.8. USB Interface Pin Name System Notes 9 Pull-up/Pull-down 10 kΩ pull-up to V3ALWAYS USB_OC[5:0]# if not driven 22.6 Ω ± 1% pull-down to gnd USBRBIAS, USBRBIAS# 16.7.9. No pull-up is required if signalsl are driven.. Signals must NOT float if they are not being used. Connect signals together and pull down through a common resistor, placed within 500 mils of the ICH4-M. Avoid routing next to clock pin.
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Platform Design Checklist R Figure 155. Single or Locally Generated GMCH and ICH4-M HIVREF/HI_VSWING Circuit VCCHI=1.5V R1 PVSWING C5 C1 GMCH HLVREF HI_VSWING C2 C3 R1 = 226 Ω ± 1%, R2 = 147 Ω ± 1%, R3 = 113 Ω ± 1% HIREF C4 C6 Option 1 ICH4-M R2 Option 2 R1 = 80.6 Ω ± 1%, R2 = 51.1 Ω ± 1%, R3 = 40.2 Ω ± 1% R3 Option 3 VCCHI=1.5V R1 = 255 Ω ± 1%, R2 = 162 Ω ± 1%, R3 = 127 Ω ± 1% VCCHI=1.5V R1 C1 and C3 = 0.
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Platform Design Checklist R 16.7.10. RTC Circuitry Pin Name System In Series 9 Notes Pull-up/Pull-down RTCRST# 180 kΩ pull-up to VccRTC RTCRST# requires 18-25 ms delay. Use a 0.1 µF cap to ground Pull up with 180 kΩ resistor. Any resistor or capacitor combination that yields a time constant is acceptable. CLK_RTCX1, CLK_RTCX2 Connect a 32.768 kHZ crystal oscillator across these pins with a 10 MΩ resistor and a decoupling cap at each signal. Values for C1 and C2 are dependent on crystal.
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Platform Design Checklist R 16.7.11. LAN Interface Pin Name System 9 Notes Pull-up/Pull-down LAN_JCLK Connect to LAN_CLK on the platform LAN Connect Device. If LAN interface is not used, leave the signal unconnected (NC). 10 kΩ pull-down to gnd LAN_RST# If ICH4-M LAN not used Timing Requirement: Signal should be connected to power monitoring logic, and should go high no sooner than 10 ms after both VccSus3_3 and VccSus1_5 have reached their nominal voltages.
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Platform Design Checklist R 16.7.13. Secondary IDE Interface Pin Name System Pull-up/Pulldown Series Damping Notes IDE_SDD[15:0] These signals have integrated series resistors. IDE_SDA[2:0], IDE_SDCS1#, IDE_SDCS3#, IDE_SDDACK#, IDE_SDIOW#, IDE_SDIOR# These signals have integrated series resistors. Pads for series resistors can be implemented should the system designer have signal integrity concerns. IDE_SDDREQ These signals have integrated series resistors and pull-down resistors in ICH4-M.
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Platform Design Checklist R 16.7.15. ICH4-M Decoupling Recommendations Pin Name Configuration Value Q VCC1.5 Connect to Vcc1_5 0.1 µF 2 Low frequency decoupling is dependent on layout and power supply design. CRB uses one 22 µF and one 100 µF. VCC3.3 Connect to Vcc3_3 0.1 µF 6 Low frequency decoupling is dependent on layout and power supply design. CRB uses two 22 µF. VCCSUS1.5 Connect to V1_5ALWAYS 0.1 µF 2 Low frequency decoupling is dependent on layout and power supply design.
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Platform Design Checklist R Figure 158. Good Downstream Power Connection 5V 5V Sus Thermister 5V Switch Vc Vcc 220uF 1 470pF Port 4 Gnd Vcccc 1 470pF 4 G Gnd Port Ferrite Bead 5V Sus PWR Distribution Switch Vc Vc c 100-150uF 1 470pF Port 4 Gnd Ferrite Bead Vcccc 470pF 100-150uF G Gnd 16.9. FWH Checklist 16.9.1.
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Platform Design Checklist R 16.10. LAN / HomePNA Checklist 16.10.1. Resistor Recommendations (for 82562ET / 82562EM) Pin Name System Pull-up/Pull-down ISOL_EX, ISOL_TCK, ISOL_TI Term Resistor 10 kΩ pull-up to VccSus3_3LAN Notes 9 If LAN is enabled, all three signals needs to be pulled up to VccSus3_3LAN through a common 10 kΩ pull-up resistor. See Figure 159.
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Platform Design Checklist R 16.10.2. Signal Name Decoupling Recommendations Configuration F Qty VCC[2:1], VCCP[2:1], VCCA[2:1], VCCT[4:1] Connect to VccSus3_3LAN 0.1 µF 4.7 µF 4 2 VCCR[2:1] Connect to VccSus3_3LAN via filter 0.1 µF 4.7 µF 1 1 314 Notes 9 4.7 uH from power supply to VCCR pins. Caps on VCCR side of the inductor.
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Schematics R 17. Schematics Refer to the following page for schematics.
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A B C D E 4 4 Clocking PG 3,4 PG 11 3 855GM/GME GMCH LVDS PG 16 DAC (CRT) 732 uFCBGA PG 7,8,9,10 PG 17 Hub Interface 66MHz PG 10 USB2 USB4 PG 28 PG 28 USB1 PG 29 USB0 PG 29 USB5 (Docking) IDE0 IDE1 PG 26,27 PG 29 DDR VR 33MHz PCI ICH4-M 421 BGA LAN CONNECT PG 18,19,20,21 PG 14 3 PG 46 EVMC SLOT PG 22 PG 22 PG 23 PG 44 ATA 100 USB 2.
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A B C D E Intel 855GM/GME CUSTOMER REFERENCE PLATFORM SCHEMATIC ANNOTATIONS AND BOARD INFORMATION 2 Voltage Rails I C / SMB Addresses Default Jumper Settings 4 3 4 +VDC +VCC_CORE +VCCP +V1.8S +V1.25S +V1.35S +V1.5S +V1.5ALWAYS +V1.5 +V2.5 +V3.3ALWAYS +V3.3 +V3.3S +V5ALWAYS +V5 +V5S +V12S -V12S Primary DC system power supply (10 to 21V) Core voltage for processor 1.05V rail for processor PSB, 855GME PSB 1.8V for processor PLL and VID circuitry 1.25V DDR Termination voltage 1.
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A 8 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#[31:3] H_A20M# H_FERR# H_IGNNE# C2 D3 A3 A20M# FERR# IGNNE# H_STPCLK# H_INTR H_NMI H_SMI# C6 D1 D4 B4 18,37 18,37 18,37 18,37 STPCLK# LINT0 LINT1 SMI# ADDR GROUP 1 18 18 18 CONTROL H_ADS# H_BNR# H_BPRI# DEFER# DRDY# DBSY# L4 H2 M2 H_DEFER# 8 H_DRDY# 8 H_DBSY# 8 BR0# N4 IERR# INIT# A4 B5 LOCK# J2 HIT# HITM# H_BR0# 8 8 8 +VCCP 4,5,9,18..20,40,42,46 R2E1 56 4 8 H_IERR# H_INIT# Place testpoint on H_IERR# with a GND 0.
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A B C D E One 0.01uF & 10uF cap for each VCCA pin. Coupon TP +V1.8S_PROC 42,46 +VCC_CORE 42,46 +VCC_CORE C3E1 C3E2 10UF 0.
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A B C D E CPU Thermal Sensor RP2B1D 10K U2A1 H_THERMDA C2A1 2200PF 3 ADD0 ADD1 2 3 4 10 6 H_THERMDC 7 8 NO_STUFF_3Pin_Recepticle J4A1 Layout Note: Route H_THERMDA and H_THERMDC on same layer. 10 mil trace on 10 mil spacing. 2 THERMDP VCC DXP DXN ADD0 ADD1 STBY# 15 SMBDATA SMBCLK ALERT# 12 14 11 GND1 GND2 NC1 NC2 NC3 NC4 NC5 1 5 9 13 16 3 RP2B1B 10K RP2B1C 10K 4 STBY# 5 3 2 R2B4 R2B5 1K 1K +V3.3S 6 4 C2B2 0.1UF 6,8,9,11,15..18,20,21,23,26,31,33..36,38..
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A B J3F1 NO_STUFF_SMA CON 4 Place crystal within 500 mils of CK_408 R2F1 49.9_1% R3F4 R3F18 NO_STUFF_0 Place 0ohm near crystal. 14.318MHZ Y3F1 C3F2 NO_STUFF_10pF NO_STUFF_10pF R3F11 NO_STUFF_330 R3F3 C2U1 0.1UF C2F2 22UF +V3.3S_CLKVDD5 R2U2 +V3.
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C 2 13 M_CB[7:0] 44 SM_VREF_MCH C5F13 0.1UF SMVREF M_DQS0 M_DQS1 M_DQS2 M_DQS3 M_DQS4 M_DQS5 M_DQS6 M_DQS7 M_DQS8 SMA_A0 SMA_A1 SMA_A2 SMA_A3 SMA_A4 SMA_A5 SMA_A6 SMA_A7 SMA_A8 SMA_A9 SMA_A10 SMA_A11 SMA_A12 AC18 AD14 AD13 AD17 AD11 AC13 AD8 AD7 AC6 AC5 AC19 AD5 AB5 M_AA0 M_AA1 M_AA2 M_AA3 M_AA4 M_AA5 M_AA6 M_AA7 M_AA8 M_AA9 M_AA10 M_AA11 M_AA12 M_AA0 12..14 M_AA[2:1] 11,14 AD16 AC12 AF11 AD10 M_AB1 M_AB2 M_AB4 M_AB5 M_AA[12:6] 12..
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C 3 H_REQ#[4:0] H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 3 Layout Note: MCH_HXSWING and MCH_HYSWING should be 10mil traces with 20mil spacing 10,46 MCH_HYSWING 3 3 6 CLK_MCH_BCLK# 6 CLK_MCH_BCLK 10 MCH_HYRCOMP 10 MCH_HXRCOMP 10,46 MCH_HXSWING 3 3 3 0.1UF 0.
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B 2 1 VSS 3 VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83
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A B C GMCH Compensation & Reference Voltages 9 +VCCP_VTTLF 4 R5R9 301_1% NO_STUFF_HUBLINK J6U1 HUB_PD0 HUB_PD2 9 +VCCP_VTTLF HUB_PD4 R4T1 301_1% 150_1% 150_1% 9 +VCCP_VTTLF 8,18 HUB_PSTRB# LAI_HUB_PIN10 LAI_HUB_PIN18 LAI_HUB_PIN26 392_1% HUB_PD6 8 MCH_HXRCOMP HUB_PD7 27.4_1% 8,46 MCH_HDVREF R6F12 R6F10 R5D2 R5T2 49.
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A B C D E 5,6,8,9,15..18,20,21,23,26,31,33..36,38..40,45 +V3.3S 12 R4W1 +V3.3S_SPD 0.01_1% Power plane for Serial Presence Detect logic 12..14 M_DATA_R_[63:0] 4 13 M_AA_FR_0 7,14 M_AA[2:1] 13 M_AA_FR_3 7,14 M_AA[5:4] 13 M_AA_FR_[12:6] 13 M_BS0_FR# 13 M_BS1_FR# 12..
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A B C D E 11,13,14 M_DATA_R_[63:0] M_AA0 M_AB1 M_AB2 7,13,14 M_AA0 4 7,14 M_AB[2:1] M_AA3 M_AB4 M_AB5 M_AA6 M_AA7 M_AA8 M_AA9 M_AA10 M_AA11 M_AA12 7,13,14 M_AA3 7,14 M_AB[5:4] 7,13,14 M_AA[12:6] 7,11,14 7,13,14 7,13,14 11,13,14 M_CS0# M_BS0# M_BS1# M_CB_R[7:0] M_CB_R0 M_CB_R1 M_CB_R2 M_CB_R3 M_CB_R4 M_CB_R5 M_CB_R6 M_CB_R7 M_CKE0, M_CKE1, M_CS0#, M_CS1# are only for LAI support. 3 11 +V3.
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A B C D E M_DATA_R_[63:0] 11,12,14 4 3 M_DATA0 4 RP6G3D 5 10 M_DATA_R_0 M_DATA32 4 RP5G11D 5 10 M_DATA_R_32 M_DATA1 3 RP6G3C 6 10 M_DATA_R_1 M_DATA33 3 RP5G11C 6 10 M_DATA_R_33 M_DATA2 1 RP6G3A 8 10 M_DATA_R_2 M_DATA34 1 RP5G11A8 10 M_DATA_R_34 M_DATA3 4 RP6G4D 5 10 M_DATA_R_3 M_DATA35 4 RP4G5D 5 10 M_DATA4 4 RP6G1D 5 10 M_DATA_R_4 M_DATA36 8 RP5G6A 1 10 M_DATA5 3 RP6G1C 6 10 M_DATA_R_5 M_DATA37 M_DATA6 1 RP6G1A 8 10 M_DATA_R_6 M_DATA7 4 RP6G2D 5 10 M_DATA_R_7 M
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1 A B C5W26 0.1UF C5H2 0.01UF C6H4 0.01UF C4H4 0.1UF C4W9 0.01UF C5W10 0.01UF C4W13 0.01UF C5W37 0.1UF C6W9 0.1UF C4W12 0.1UF C5W39 0.01UF C5W22 0.01UF C5W33 0.1UF C5W32 0.01UF C5W25 0.01UF C5H1 0.1UF C6W11 0.1UF C6W10 0.01UF C5W35 0.1UF C5W20 0.01UF C5W31 0.1UF C5W13 0.1UF C5W24 0.01UF C4W14 0.1UF C5W34 0.01UF C5W36 0.01UF C4W15 0.01UF C4W11 0.01UF C5W18 0.01UF C6W12 0.1UF C5W23 0.1UF C4W8 0.1UF C4H2 0.1UF C5W27 0.01UF C5W7 0.1UF C5W17 0.1UF C4W7 0.01UF C5W12 0.01UF C5W30 0.01UF C4W5 0.01UF C5W38 0.
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B C DVOBHSYNC DVOBVSYNC 7 DVOBD[11:0] J6C1 DVOBD1 DVOBD0 DVOBD3 DVOBD2 DVOBD5 DVOBD4 DVOBD6 DVOBD9 DVOBD8 DVOBD11 DVOBD10 4 7 DVOBCCLKINT 7 DVOBFLDSTL 7 MDDCDATA 7 DVOCVSYNC 7 DVOCHSYNC 7 DVOCBLANK# DVOCD0 DVOCD1 DVOCD2 DVOCD3 DVOCD4 DVOCD7 DVOCD6 DVOCD9 DVOCD8 DVOCD11 DVOCD10 3 +V1.5S_DVO R7E4 R7E2 8.2K 8.
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A B C +V3.3S D 5,6,8,9,11,15,17,18,20,21,23,26,31,33..36,38..40,45 +V3.3S_LVDSDDC LVDS Interface 5,6,8,9,11,15,17,18,20,21,23,26,31,33..36,38..40,45 +V3.3S_LVDS R5N6 0.01_1% Q5B2 2 3 LVDS_VDDEN# R5N4 1M 3 C5N1 C5B6 C5B7 1000PF 0.
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I/O6 I/O5 I/O4 0.1UF 0.1UF 0.1UF 8 6 5 +V5S_F_DAC CR4B1 R4A1 1K 1N4148 DDC_GATE C3A9 0.1UF 3 R3A9 1 2 3 4 7,24 DAC_DDCACLK OE1# 1A 1B GND VCC OE2# 2B 2A 8 7 6 5 F3A1 +1 2 1.1A Q3B1 1 R4A2 100K DDC_SRC R3A8 4 1 R3A10 4.7K U3A1 DDC_OE1# 100 E +V12S 3 I/O1 I/O2 I/O3 C6R3 DDC_VCC 1 2 4 C6R1 Vn 4 DAC_RED DAC_GREEN DAC_BLUE ESD DIODE ARRAY C6R2 D 15,23,27,37,45 8,15,16,18,20,23..25,27,33..35,38..40,45,46 +V5S 1 7 Vp CR6D1 C +V1.5S_GMCH_ADAC 2 B 9 R3A7 2.
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B 22..24 22..24 22..24 22..
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68 25,32,37,38,44,45 20,32,37,38,44,45 37,38 6,37,39 6,37 33,37 32,34,37 5,21,32,37 PM_SLP_S3# PM_SLP_S4# PM_SLP_S5# PM_STPCPU# PM_STPPCI# SUS_CLK PM_SUS_STAT# PM_THRM# PM_SLP_S3# 5 R6H11 3 4 37 +V3.3S_ICH NO_STUFF_1K AC_SPKR R7V7 NO_STUFF_10K AC_SDATAOUT R7V8 NO_STUFF_1K PCI_GNTA# 18,22,23 5,15,20..23,27..29,32,36..39,45 +V3.
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A B +V1.5 R7G4 U7G2C C6G1 C7W6 C7W15 10UF 0.1UF 0.1UF NO_STUFF_0.1UF C7W18 No Stuff +V1.5_ICHLAN 4 0.01_1% +V3.3 C8G1 C7W7 C7W8 22UF 0.1UF 0.1UF 15,18,19,23,27,30,32,35,37,38,44,45 18 R7G5 C7G7 C7W3 C7V3 C7G6 22UF 0.1UF 0.1UF 4.7UF 4,9,15,19,45,46 VCCSUS1.5_0 VCCSUS1.5_1 VCCSUS1.5_2 VCCSUS1.5_3 VCCSUS1.5_4 VCCSUS1.5_5 VCCSUS1.5_6 VCCSUS1.5_7 F6 F7 VCCLAN1.5_0 VCCLAN1.5_1 E9 F9 VCCLAN3.3_0 VCCLAN3.3_1 E7 V6 VCC5REF1 VCC5REF2 +V3.3_ICHLAN +V5A_ICH +V1.5S 18 R6G5 0.
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B C 20,37 +V3.3ALWAYS_ICH 6 10K 7 10K +V3.3ALWAYS 19,20,22,24,37 +V3.3S_ICH 8 U4C1 V5A_COSC RUN_SS C4C10 47pF C4C11 3300pF 1 COSC 2 RUN/SS 3 V5A_ITH R4C6 37.4k_1% R4P1 NO_STUFF_680K 4 Place these caps near U4C1 TG 16 V5A_TG BOOST 15 V5A_BOOST VIN 13 CR4C1 MBR0520LT1 INTVCC 12 V5A_INTVCC 8 SGND 7 VOSENSE 5 SENSE- BG 11 6 SENSE+ PGND 10 C4C5 1 1 6 1 V5A_BG C4P3 C4C8 C4P1 1UF 10UF 0.1UF +V5_ALWAYS 20,28,29 R4C1 2 4.7uH 0.
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A B 23,45 23 23 4 +V5_PCI 23 18,21,23 INT_PIRQG# 18,21,23 INT_PIRQE# C7B10 0.01UF SLT1_PRSNT1# C7C1 0.
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A B C D 5,15,19..22,27..29,32,36..39,45 15,17,27,37,45 +V5_PCI +V12S Moon ISA support 19 R7B2 0.01_1% 15,18..20,27,30,32,35,37,38,44,45 4 C7B4 C8B2 C7B5 10UF 0.1UF 0.1UF +V3.3S_PCI R7C3 NO_STUFF_0 18,21,24 INT_PIRQD# 3 RP7F4C 6 NO_STUFF_0 15,18,21,24 INT_PIRQA# 18,21,22,37 INT_PIRQH# 22 3 +V5S_PCI 20..22,27,36,37,44,45 +V5 R8B6 Place close to slot 3 C8C3 C8E5 C8B4 C8E6 C8B5 22UF 0.1UF 0.1UF 0.1UF 0.1UF +V3.
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A B C Qbuffers used for isolation during suspend 8,15..18,20,23,25,27,33..35,38..
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A B C D J9E3A 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 17 DOCK_RED 17 DOCK_VSYNC 17 DOCK_HSYNC 24 DOCK_SMBDATA 24 DOCK_CLKRUN# 24 DOCK_REQB# 24 DOCK_PIRQC# 24 DOCK_PIRQB# 24 DOCK_GNT4# GND0 V_DC0 V_DC1 GND1 GND2 RED_RTN RED VSYNC HSYNC GND3 GND4 NC0 SM_DATA SYSACT# CLKRUN# PC_REQ# GND5 CD2 NC1 NC2 CD3#/GND INTD# INTC# GND6 GNT# E J9E3C REQ# GND7 PERR# SERR# GND8 STOP# TRDY# GND9 LOCK# FRAME# GND10 C/BE1# C/BE0# GND11 AD29 AD28 GND12 AD25 AD24 GND13 AD21 AD20 GND14 V_AC
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A B C R4Y2 BUF_PCI_RST# 19 IDE_PDD[15:0] 4 5,6,8,9,11,15..18,20,21,23,31,33..36,38..40,45 +V3.3S RP2J1C 3 E 47 IDE_D_PRST# 18,22..24,31,32,34,37 D PRIMARY HDD CONN J4J2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 IDE_PDD7 IDE_PDD6 IDE_PDD5 IDE_PDD4 IDE_PDD3 IDE_PDD2 IDE_PDD1 IDE_PDD0 6 19 IDE_PDDREQ 19 IDE_PDIOW# 19 IDE_PDIOR# 19 IDE_PIORDY 19 IDE_PDDACK# 18,21,37 INT_IRQ14 19 IDE_PDA1 19 IDE_PDA0 19 IDE_PDCS1# 27,45 IDE_PDACTIVE# 4.
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A B C D Secondary IDE Power 8,15..18,20,23..25,33..35,38..40,45,46 E 8,15..18,20,23..25,33..35,38..40,45,46 +V5S +V5S C2H1 14 U3H1A 2 4 14 1 34,37 IDE_SPWR_EN# 0.1UF IDE_SPWR_EN 11 R2H5 1M C2H2 R2H6 390K IDE_SPWR2 1 1000PF 3 U2H1A SI4925DY 2 U2H1B SI4925DY 4 R2H1 NO_STUFF_0 4 7 74HC14 U3H1E 74HC14 10 IDE_SPWR2_D Note: Primary IDE Power on Turner DC/DC Module 7 +V5S_IDE_S 8,15..18,20,23..25,33..35,38..40,45,46 +V5S 7 R2H8 SHMIDT4 1M 0.
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A B +V5_ALWAYS C D E 20,21,29 R4B2 +V5_USB1 0.01_1% C4B3 5,15,19..23,27,29,32,36..39,45 +V3.3ALWAYS 0.
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A B C D E 4 4 +V5_ALWAYS 5,15,19..23,27,28,32,36..39,45 20,21,28 +V3.3ALWAYS R6B2 10K R6N2 0.01_1% R6A7 10K USB_OC3# 19 U6B1 +V5_USB2 C6A12 3 0.
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A B +V3.3 C D 15,18..20,23,27,32,35,37,38,44,45 4 4 +V3.3_LAN R6A1 0.01_1% Bulk caps should be 4.7uF or higher. Layout note: Place 100 Ohm resistor close to 82562EM L6A1 C6A7 C6A10 C6A11 C6A3 C6A2 4.7UF 4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 4.7UH 18 18 18 18 18 18 18 +V3.3_LAN 3 R6A6 10K If LAN is enabled, PM_LANPWROK waits for PM_PWROK to go high and stays high in S3.
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A B C D E 4 4 5,6,8,9,11,15..18,20,21,23,26,33..36,38..40,45 +V3.3S +V3.
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2 3 SMC_MD CON3_HDR SMC_XTAL SMC_EXTAL +V3.3ALWAYS 5,15,19..23,27..29,36..39,45 NO_STUFF_10K SMC_RES# SMC_STBY# R4B5 3 39 VR_SHUT_DOWN# 33 SMC_INITCLK R9A3 19,21,25,37,39 PM_PWROK 0 Stuff R9A4 only for in-ckt programming 5,15,19..23,27..29,36..39,45 +V3.
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A B C D E SMC SUSPEND TIMER 32 32 R7A1 +V3.3ALWAYS_KBC 14 R8A4 1M R7A2 1 4.7K 7 U7A4A 74HC04 7 8 C8B1 7 4.7uF SMC_INITCLK 32 4 U7A4D 74HC04 1 NMI Jumper NOTE: Shunt J8A1 for SMC Programming R8B2 100K 1 19 KSC_VPPEN# J8A1 Q8A1 BSS138 2 SMC_RST# 32 SMC_INIT_CLK3 9 6 U7A4C 74HC04 SMC_INIT_CLK4 1 MAX809 Q8B1 BSS138 SMC_RST 1 2 7 14 SMC_INIT_CLK2 5 4 U7A4B 74HC04 3 SMC_RST#_D 2 RST# 14 SMC_INIT_CLK1 3 3 0.1UF 14 2 GND 32 C8A5 U7A2 VCC 4 3 0 +V3.
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B C D BUF_PCI_RST# 18,22..24,26,31,32,37 +V3.3S_SIO 1 8 10K GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 85 84 83 82 5 NC 65 5,6,8,9,11,15..18,20,21,23,26,31,33,35,36,38..40,45 PC87393 +V3.3S +V3.3S_SIO +V3.3S_SIO +V3.3S_SIO EV GPIO Strapping options R8G6 0.01_1% C8U6 C8U5 C8F2 0.1UF 0.1UF 22UF R8G3 NO_STUFF_4.
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A B 7 9 11 13 15 17 19 21 23 25 27 29 31 33 J2A1A 7 5 8 7 60OHM@100MHZ PPT_L_PE FB2A2B PPT_L_BUSY/WAIT# FB2A2D FB2A1A PPT_L_ACK# FB2A1B PPT_L_PD7 3 4 1 2 6 5 8 7 60OHM@100MHZ FB2A1C FB2A1D FB3A6A FB3A6B 3 4 1 2 6 5 8 7 60OHM@100MHZ FB3A6C PPT_L_SLIN# FB3A6D PPT_L_PD2 FB3A5A PPT_L_INIT# FB3A5B PPT_L_PD1 6 5 1 4 60OHM@100MHZ FB3A5C PPT_L_ERR# FB3A5D PPT_L_PD0 FB3A4A PPT_L_AFD#/DSTRB# FB3A4D PPT_L_STB#/WRITE# 2 4 1 2 34 PPT_PE 34 PPT_BUSY/WAIT# 34 PPT_ACK# 34 PPT_PD7 PARALLEL PORT 60OHM@100MHZ
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A B C D E +V5_PS2 KBC_SCANOUT[15:0] 4 CBTD has integrated diode for 5V to 3.
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A B 15,17,23,27,45 +V12S C D J3H1 +V3.3_LPCSLOT 15,17,23,27,45 +V12S J8F1 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 19,33 SUS_CLK 5,15,19..23,27..29,32,36,38,39,45 +V3.
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A B C D E Fan Power Control 8,15..18,20,23..25,27,33..35,39,40,45,46 +V5S Test CAPs 4 3 U1E1 SI3457DV C1E2 0.1UF 22UF TP_220pf2 J1E1 FAN_ON_D TP_330pf1 CR1E1 1N4148 1 2 4 C8J7 220PF TP_330pf2 C9J3 330PF TP_0.1uf1 Test CAPs backside CONN2_HDR TP_BS_100pf1 Q1E1 BSS138 1 FAN_ON 1000PF R1E2 100K TP_220pf1 C1E3 TP_0.1uf2 C8J6 0.1UF TP_BS_100pf2 TP_BS_0.01uf1 C8J4 0.082uF TP_0.47uf1 TP_BS_0.01uf2 C9Y4 0.01UF 0.47uF TP_0.01uf2 TP_0.01uf1 C9J1 0.
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B C 5 C7A4 20 V1.5_PWRGD 2 0.1UF 4 74AHC1G08 MAIN_PWROK 1 MAIN2_PWROK 2 74AHC1G08 4 PM_PWROK 19,21,25,32,37 C7B1 +V3.3ALWAYS 0.1UF U4B5 1 4 2 4 74AHC1G08 ON_BOARD_VR_ON 4 3 OFF_BOARD_VR_ON 3 4 74AHC1G08 2 C4B6 2.2k INTERPOSER_PRES# 74AHC1G08 5 U7B1 1 Step 3 - Power Good 5,6,8,9,11,15..18,20,21,23,26,31,33..36,38,40,45 +V3.3S 3 21 V5A_PWRGD 2 32 VR_SHUT_DOWN# 0.1UF 44 DDR_VR_PWRGD 0.1UF U4B4 3 5,15,19..23,27..29,32,36..38,45 4 C4B5 1 CORE_VR_ON E +V3.
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A B C D 3..5,9,18..20,42,46 E +VCCP R1F13 1K 5,6,8,9,11,15..18,20,21,23,26,31,33..36,38,39,45 +V3.3S VR_VID_N 8,15..18,20,23..25,27,33..35,38,39,45,46 4 R1F14 1K 39 C1F4 0.1UF VR_VID_D0 VR_VID0 5 + 4 - 2 SIO_VR_VID0 34 U2F1A LM339 12 3 R2G1 VR_VID_D1 VR_VID1 1K 7 + 6 - C1F3 0.
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5 4 3 2 1 D D C C Blank B B A A Title IMVP-IV VR Controller Size Project: B Intel 855GM/GME CRB Monday, September 15, 2003 Date: 5 4 3 2 Document Number of 41 Sheet 1 Rev 4.
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5 4 3 2 1 VCore HF and Bulk Decoupling D 4,46 C3R12 10UF 20% 4,46 This solution will allow any of the decoupling options. caps should NOT be stuffed at the same time.
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5 4 3 2 1 D D C C Blank B B A A Title 855GME VR and VCCP Size Project: B Intel 855GM/GME CRB Monday, September 15, 2003 Date: 5 4 3 2 Document Number of 43 Sheet 1 Rev 4.
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A B 20..23,27,36,37,45 C D E +V5 BOOT_1 C3G9 C3G8 C3G10 150uF 150uF 0.1UF 4 24 23 22 21 20 VSENSE_1 R3V4 C3V2 COMP_1_D 5600pF 25.5k_1% R3U2 RT_1 NO_STUFF_10K_1% 2 2 COMP_1 C3G5 47pF SS/ENA_1 J3G2 R3F22 C3G1 3 R4G1 5.49k_1% V2.5_DDR_D 0.01UF NO_STUFF_10K VBIAS_1 CON3_HDR 1 0.022uF U3G1 VIN0 VIN1 VIN2 VIN3 TPS54610 VIN4 VSENSE 3 NC/Comp 4 PWRGD 5 BOOT 28 RT 27 FSEL 6 7 8 9 10 11 12 13 14 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PH8 9,11,12 +V2.
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A B C D HDM Connector Assembly (base board) J1B1 A1 A2 A3 A4 16,21,39 F1 F2 F3 F4 15,17,23,27,37 8,15..18,20,23..25,27,33..35,38..40,46 5,6,8,9,11,15..18,20,21,23,26,31,33..36,38..40 3 4 8,15..18,20,23..25,27,33..35,38..40,46 3Pin_RECEPTICLE -V12S_TURNER 0.01_1% R1D2 0.002 1% +V3.3A_TURNER C1D1 22UF 72Pin_RECEPTICLE(male) PS_ON_SW# -V12S 2 2 IN F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 +V5S 0.01_1% 8,15..
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A B C D E Power On Sequence +V3.3 5 PM_SLP_S3# 4 +V3.3S 5 +V5S 5 +V5 5 +V12S 5 -V12S 5 PG 45 PWR_PWROK U7A3 6 +V3A PG 20 +V1.
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A B E SMC_SHUTDOWN PCI_RST_SLOTS# PCI_RST# MASTER_RESET# U7A5 ICH4 PM_PWROK PG 39 Core VR PG 41 DOCKING 3 ITP Q9B3 PCI_GATED_RST# PG32 PG 15 SMC_RST# U8A2 PG 32 SMC 2 SMC_RES# FWH PG 31 PG 32 H_CPURST# SIO PG 34 GMCH H_PWRGD CPU PG 8 1 PG 3 Title Reset Map Size Project: A Intel 855GM/GME CRB Monday, September 15, 2003 Date: A 3 ADD CONN SMC_PROG_RST# 1 LPC SLOT PG 37 U9C1 QSW PG 24 PG 25 U87A4A PG 33 PG 33 R=0 R=0 PG 5 MAX809 4 PG 19 PG 45 2 PCI SLOTS PG 22