Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium Desktop Processor 6000 Series Specification Update November 2014 Document Number: 322911-021US
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Contents Revision History ...............................................................................................................5 Preface ..............................................................................................................................6 Summary Tables of Changes ..........................................................................................8 Identification Information .........................................................................................
§§ Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium Desktop Processor 6000 Series Specification Update 4 November 2014 Document Number: 322911-021US
Revision History Revision Description Date 001 Initial Release January 2010 002 Added Errata AAU85-AAU87. Corrected Extended Model and Model Number register values in Component Identification table. February 2010 003 Added Errata AAU88-AAU91. Added Documentation Changes AAU1-AAU3. March 2010 004 Added Errataum AAU92. April 2010 ® 005 Updated Processor Identification table to include the SKU information for the Intel i5-680 processor. Added processor K-0 stepping information.
Preface This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents.
Nomenclature Errata are design defects or errors. These may cause the processor behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics such as, core speed, L2 cache size, package type, etc.
Summary Tables of Changes The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations: Codes Used in Summary Tables Stepping X: Errata exists in the stepping indicated.
Errata (Sheet 1 of 5) Steppings Number Status ERRATA C-2 K-0 AAU1 X X No Fix The Processor May Report a #TS Instead of a #GP Fault AAU2 X X No Fix REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering Violations AAU3 X X No Fix Code Segment Limit/Canonical Faults on RSM May Be Serviced before Higher Priority Interrupts/Exceptions and May Push the Wrong Address onto the Stac
Errata (Sheet 2 of 5) Steppings Number Status ERRATA C-2 K-0 AAU26 X X No Fix Synchronous Reset of IA32_APERF/IA32_MPERF Counters on Overflow Does Not Work AAU27 X X No Fix Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May Result in Stuck Core Operating Ratio AAU28 X X No Fix Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt AAU29 X X No Fix xAPIC Timer May Decrement Too Quickly Following an Automatic Reload Whil
Errata (Sheet 3 of 5) Steppings Number Status ERRATA C-2 K-0 AAU51 X X No Fix Corrected Errors With a Yellow Error Indication May be Overwritten by Other Corrected Errors AAU52 X X No Fix Performance Monitor Events DCACHE_CACHE_LD and DCACHE_CACHE_ST May Overcount AAU53 X X No Fix Rapid Core C3/C6 Transitions May Cause Unpredictable System Behavior AAU54 X X No Fix APIC Timer CCR May Report 0 in Periodic Mode AAU55 X X No Fix Performance Monitor Events INSTR_RETIRED and MEM_I
Errata (Sheet 4 of 5) Steppings Number Status ERRATA No Fix If the APIC timer Divide Configuration Register (Offset 03E0H) is written at the same time that the APIC timer Current Count Register (Offset 0390H) reads 1H, it is possible that the APIC timer will deliver two interrupts. X Fixed TXT.PUBLIC.
Errata (Sheet 5 of 5) Steppings Number Status ERRATA X No Fix PCIe Ports May Not Enter Slave Loopback Mode From the Configuration LTSSM State X X No Fix USB Devices May Not Function Properly With Integrated Graphics While Running Targeted Stress Graphics Workloads With Non-Matching Memory Configurations X X No Fix VM Entry May Omit Consistency Checks Related to Bit 14 (BS) of the Pending Debug Exception Field in Guest-State Area of the VMCS X No Fix Intel Turbo Boost Technology Ratio Chan
Identification Information Component Identification using Programming Interface The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series stepping can be identified by the following register contents: Extended Family1 Extended Model2 Reserved Processor Type3 27:20 19:16 15:14 13:12 11:8 7:4 3:0 00000000b 0010b 00b 0110 0101b xxxxb Reserved 31:28 Note: 1. 2. 3. 4. 5. 6.
Component Marking Information The processor stepping can be identified by the following component markings. Figure 1. Processor Production Top-side Markings (Example) INTEL M ©'08 PROC# BRAND SLxxx [COO] SPEED/CACHE/FMB [FPO] e4 LOT NO S/N Table 1.
Table 1. Processor Identification (Sheet 2 of 2) S-Spec Number Processor Number Stepping Processor Signature Core Frequency (GHz) / DDR3 (MHz) / Integrated Graphics Frequency SLBLR i3-530 C-2 20652h 2.93 / 1333 / 733 N/A 4 1, 3, 5, 8, 10 SLBMS G6950 C-2 20652h 2.80 / 1066 / 533 N/A 3 1, 5, 10 SLBT6 G6960 C-2 20652h 2.93 / 1066 / 533 N/A 3 1, 5, 10 Max Intel® Turbo Boost Technology Frequency (GHz)2 Shared L3 Cache Size (MB) Notes Notes: 1. This processor has TDP of 73 W. 2.
Errata AAU1. The Processor May Report a #TS Instead of a #GP Fault Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception) instead of a #GP fault (general protection exception). Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP fault. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AAU2.
AAU3. Code Segment Limit/Canonical Faults on RSM May Be Serviced before Higher Priority Interrupts/Exceptions and May Push the Wrong Address onto the Stack Problem: Normally, when the processor encounters a Segment Limit or Canonical Fault due to code execution, a #GP (General Protection Exception) fault is generated after all higher priority Interrupts and exceptions are serviced.
AAU5. Premature Execution of a Load Operation Prior to Exception Handler Invocation Problem: If any of the below circumstances occur, it is possible that the load portion of the instruction will have executed before the exception handler is entered. • If an instruction that performs a memory load causes a code segment limit violation. • If a waiting X87 floating-point (FP) instruction or MMX™ technology (MMX) instruction that performs a memory load has a floating-point exception pending.
AAU7. Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update Problem: A partial memory state save of the 512-byte FXSAVE image or a partial memory state restore of the FXRSTOR image may occur if a memory address exceeds the 64KB limit while the processor is operating in 16-bit mode or if a memory address exceeds the 4GB limit while the processor is operating in 32-bit mode.
AAU10. Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame Problem: The ENTER instruction is used to create a procedure stack frame. Due to this erratum, if execution of the ENTER instruction results in a fault, the dynamic storage area of the resultant stack frame may contain unexpected values (i.e., residual stack data as a result of processing the fault). Implication: Data in the created stack frame may be altered following a fault on the ENTER instruction.
AAU13. General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit Violation above 4-G Limit Problem: In 32-bit mode, memory accesses to flat data segments (base = 00000000h) that occur above the 4-G limit (0ffffffffh) may not signal a #GP fault. Implication: When such memory accesses occur in 32-bit mode, the system may not issue a #GP fault. Workaround: Software should ensure that memory accesses in 32-bit mode do not occur above the 4-G limit (0ffffffffh).
AAU17. MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang Problem: If the target linear address range for a MONITOR or CLFLUSH is mapped to the local xAPIC's address space, the processor will hang. Implication: When this erratum occurs, the processor will hang. The local xAPIC's address space must be uncached. The MONITOR instruction only functions correctly if the specified linear address range is of the type write-back. CLFLUSH flushes data from the cache.
AAU20. A VM Exit on MWAIT May Incorrectly Report the Monitoring Hardware as Armed Problem: A processor write to the address range armed by the MONITOR instruction may not immediately trigger the monitoring hardware. Consequently, a VM exit on a later MWAIT may incorrectly report the monitoring hardware as armed, when it should be reported as unarmed due to the write occurring prior to the MWAIT.
AAU24. An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception Problem: A MOV SS/POP SS instruction should inhibit all interrupts including debug breakpoints until after execution of the following instruction. This is intended to allow the sequential execution of MOV SS/POP SS and MOV [r/e]SP, [r/e]BP instructions without having an invalid stack during interrupt handling.
AAU27. Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May Result in Stuck Core Operating Ratio Problem: If a processor is at its TCC (Thermal Control Circuit) activation temperature and then Thermal Monitor is disabled by a write to IA32_MISC_ENABLES MSR (1A0H) bit [3], a subsequent re-enable of Thermal Monitor will result in an artificial ceiling on the maximum core P-state. The ceiling is based on the core frequency at the time of Thermal Monitor disable.
AAU30. Reported Memory Type May Not Be Used to Access the VMCS and Referenced Data Structures Problem: Bits 53:50 of the IA32_VMX_BASIC MSR report the memory type that the processor uses to access the VMCS and data structures referenced by pointers in the VMCS. Due to this erratum, a VMX access to the VMCS or referenced data structures will instead use the memory type that the MTRRs (memory-type range registers) specify for the physical address of the access.
AAU34. Infinite Stream of Interrupts May Occur if an ExtINT Delivery Mode Interrupt is Received while All Cores in C6 Problem: If all logical processors in a core are in C6, an ExtINT delivery mode interrupt is pending in the xAPIC and interrupts are blocked with EFLAGS.IF=0, the interrupt will be processed after C6 wakeup and after interrupts are re-enabled (EFLAGS.IF=1). However, the pending interrupt event will not be cleared.
AAU37. FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM Problem: In general, a PEBS record should be generated on the first count of the event after the counter has overflowed. However, IA32_DEBUGCTL_MSR.FREEZE_WHILE_SMM (MSR 1D9H, bit [14]) prevents performance counters from counting during SMM (System Management Mode). Due to this erratum, if 1. A performance counter overflowed before an SMI 2.
AAU40. An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May Also Result in a System Hang Problem: Uncorrectable errors logged in IA32_CR_MC2_STATUS MSR (409H) may also result in a system hang causing an Internal Timer Error (MCACOD = 0x0400h) to be logged in another machine check bank (IA32_MCi_STATUS). Implication: Uncorrectable errors logged in IA32_CR_MC2_STATUS can further cause a system hang and an Internal Timer Error to be logged. Workaround: None identified.
AAU44. Faulting Executions of FXRSTOR May Update State Inconsistently Problem: The state updated by a faulting FXRSTOR instruction may vary from one execution to another. Implication: Software that relies on x87 state or SSE state following a faulting execution of FXRSTOR may behave inconsistently. Workaround: Software handling a fault on an execution of FXRSTOR can compensate for execution variability by correcting the cause of the fault and executing FXRSTOR again.
AAU47. Performance Monitor Counters May Count Incorrectly Problem: Under certain circumstances, a general purpose performance counter, IA32_PMC0-4 (C1H - C4H), may count at core frequency or not count at all instead of counting the programmed event. Implication: The Performance Monitor Counter IA32_PMCx may not properly count the programmed event.
AAU49. EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation Change Problem: This erratum is regarding the case where paging structures are modified to change a linear address from writable to non-writable without software performing an appropriate TLB invalidation.
AAU52. Performance Monitor Events DCACHE_CACHE_LD and DCACHE_CACHE_ST May Overcount Problem: The performance monitor events DCACHE_CACHE_LD (Event 40H) and DCACHE_CACHE_ST (Event 41H) count cacheable loads and stores that hit the L1 cache. Due to this erratum, in addition to counting the completed loads and stores, the counter will incorrectly count speculative loads and stores that were aborted prior to completion.
AAU56. A Page Fault May Not be Generated When the PS bit is set to "1" in a PML4E or PDPTE Problem: On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7) is reserved in PML4Es and PDPTEs. If the translation of the linear address of a memory access encounters a PML4E or a PDPTE with PS set to 1, a page fault should occur. Due to this erratum, PS of such an entry is ignored and no page fault will occur due to its being set.
AAU59. VM Exits Due to "NMI-Window Exiting" May Be Delayed by One Instruction Problem: If VM entry is executed with the "NMI-window exiting" VM-execution control set to 1, a VM exit with exit reason "NMI window" should occur before execution of any instruction if there is no virtual-NMI blocking, no blocking of events by MOV SS, and no blocking of events by STI.
AAU63. LBRs May Not be Initialized During Power-On Reset of the Processor Problem: If a second reset is initiated during the power-on processor reset cycle, the LBRs (Last Branch Records) may not be properly initialized. Implication: Due to this erratum, debug software may not be able to rely on the LBRs out of poweron reset. Workaround: Ensure that the processor has completed its power-on reset cycle prior to initiating a second reset.
AAU66. Multiple Performance Monitor Interrupts are Possible on Overflow of Fixed Counter 0 Problem: The processor can be configured to issue a PMI (performance monitor interrupt) upon overflow of the IA32_FIXED_CTR0 MSR (309H). A single PMI should be observed on overflow of IA32_FIXED_CTR0, however multiple PMIs are observed when this erratum occurs.
AAU69. Storage of PEBS Record Delayed Following Execution of MOV SS or STI Problem: When a performance monitoring counter is configured for PEBS (Precise Event Based Sampling), overflow of the counter results in storage of a PEBS record in the PEBS buffer. The information in the PEBS record represents the state of the next instruction to be executed following the counter overflow.
AAU72. Logical Processor May Use Incorrect VPID after VM Entry That Returns From SMM Problem: A logical processor in VMX root operation should use VPID 0000H. Due to this erratum, a logical processor may instead use VPID 1FB3H if VMX root operation was entered using a VM entry that returns from SMM. Implication: After a VM entry that sets the "enable VPID" VM-execution control and that establishes VPID 1FB3H, the logical processor may erroneously use TLB entries that were cached in VMX root operation.
AAU76. PMIs during Core C6 Transitions May Cause the System to Hang Problem: If a performance monitoring counter overflows and causes a PMI (Performance Monitoring Interrupt) at the same time that the core enters C6, then this may cause the system to hang. Implication: Due to this erratum, the processor may hang when a PMI coincides with core C6 entry. Workaround: It is possible for the BIOS to contain a workaround for this erratum.
AAU80. 8259 Virtual Wire B Mode Interrupt May Be Dropped When it Collides With Interrupt Acknowledge Cycle From the Preceding Interrupt Problem: If an un-serviced 8259 Virtual Wire B Mode (8259 connected to IOAPIC) External Interrupt is pending in the APIC and a second 8259 Virtual Wire B Mode External Interrupt arrives, the processor may incorrectly drop the second 8259 Virtual Wire B Mode External Interrupt request.
AAU85. The Combination of a Page-Split Lock Access And Data Accesses That Are Split Across Cacheline Boundaries May Lead to Processor Livelock Problem: Under certain complex micro-architectural conditions, the simultaneous occurrence of a page-split lock and several data accesses that are split across cacheline boundaries may lead to processor livelock. Implication: Due to this erratum, a livelock may occur that can only be terminated by a processor reset.
AAU89. PCI Express x16 Port Links May Fail to Dynamically Switch From 5.0GT/s to 2.5GT/s Problem: If an endpoint device initiates a PCI Express speed change from 5.0 GT/s to 2.5 GT/s, the link may incorrectly go into Recovery.Idle rather than the expected Recovery.Speed state. This may cause the link to lose sync, eventually resulting in a link down. The link will recover and re-train to the L0 state, however any outstanding packets queued during the speed change may be lost.
AAU93. VM Entry to 64-Bit Mode May Fail if Bits 48 And 47 of Guest RIP Are Different Problem: VM entry to 64-bit mode should allow any value for bits [47:0] of the RIP field in the guest-state area as long as bits 63:48 are identical. Due to this erratum, such a VM entry may fail if bit 47 of the field has a value different from that of bit 48. Implication: It is not possible to perform VM entry to a 64-bit guest that has made a transition to a non-canonical instruction pointer.
AAU96. Under Certain Low Temperature Conditions, Some Uncore Performance Monitoring Events May Report Incorrect Results Problem: Due to this erratum, under certain low operating temperatures, a small number of Last Level Cache and external bus performance monitoring events in the uncore report incorrect counts. This erratum may affect event codes in the ranges 00H to 0CH and 40H to 43H. Implication: Due to this erratum, the count value for some uncore Performance Monitoring Events may be inaccurate.
AAU100. VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32] Problem: If the “load IA32_PERF_GLOBAL_CTRL” VM-exit control is 1, a VM exit should load the IA32_PERF_GLOBAL_CTRL MSR (38FH) from the IA32_PERF_GLOBAL_CTRL field in the guest-state area of the VMCS. Due to this erratum, such a VM exit may instead clear bits 34:32 of the MSR, loading only bits 31:0 from the VMCS.
AAU103. PCIe Port’s LTSSM May Not Transition Properly in the Presence of TS1 or TS2 Ordered Sets That Have Unexpected Symbols Within those Sets Problem: When a PCIe port receives TS1 and/or TS2 ordered sets with unexpected symbols (per the PCIe Base Specification), the port’s LTSSM (Link Training State Machine) might not transition according to the PCIe Base Specification requirements. The LTSSM may incorrectly stay in its current state, or transition to an incorrect state.
AAU106. USB Devices May Not Function Properly With Integrated Graphics While Running Targeted Stress Graphics Workloads With NonMatching Memory Configurations Problem: When the integrated graphics engine continuously generates a large stream of writes to system memory, and Intel Flex Memory Technology is enabled, with a different amount of memory in each channel, the memory arbiter may temporarily stop servicing other device-initiated traffic.
AAU109. Execution of VMPTRLD May Corrupt Memory If Current-VMCS Pointer is Invalid Problem: If the VMCLEAR instruction is executed with a pointer to the current-VMCS (virtualmachine control structure), the current-VMCS pointer becomes invalid as expected. A subsequent execution of the VMPTRLD (Load Pointer to Virtual-Machine Control Structure) instruction may erroneously overwrite the four bytes at physical address 0000008FH.
AAU113. The Upper 32 Bits of CR3 May be Incorrectly Used With 32-Bit Paging Problem: When 32-bit paging is in use, the processor should use a page directory located at the 32-bit physical address specified in bits 31:12 of CR3; the upper 32 bits of CR3 should be ignored. Due to this erratum, the processor will use a page directory located at the 64-bit physical address specified in bits 63:12 of CR3.
AAU116. Virtual-APIC Page Accesses With 32-Bit PAE Paging May Cause a System Crash Problem: If a logical processor has EPT (Extended Page Tables) enabled, is using 32-bit PAE paging, and accesses the virtual-APIC page then a complex sequence of internal processor micro-architectural events may cause an incorrect address translation or machine check on either logical processor. Implication: This erratum may result in unexpected faults, an uncorrectable TLB error logged in IA32_MCi_STATUS.
Specification Changes The Specification Changes listed in this section apply to the following documents: • Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 Datasheet - Volumes 1 and 2 • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B: In
Specification Clarifications The Specification Clarifications listed in this section may apply to the following documents: • Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 Datasheet - Volumes 1 and 2 • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M • Intel® 64 and IA-32 Architectures Software Developer’s Manual
Documentation Changes The Documentation Changes listed in this section apply to the following documents: • Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 Datasheet - Volumes 1 and 2 • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B: In
§§ Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium Desktop Processor 6000 Series Specification Update 56 November 2014 Document Number: 322911-021US
