R Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH) Specification Update November 2007 Notice: The Intel® 855GM/855GME chipset may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
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R Contents Revision History ............................................................................................................. 4 Preface .......................................................................................................................... 5 Summary Table of Changes........................................................................................... 6 Errata .................................................................................................................
R Revision History Revision Description Date -001 Initial Release July 2003 -002 Added the Intel 855GME chipset October 2003 -003 Document Change #1 added September 2004 -004 Document Changes #2 & #3 added October 2004 -005 Errata Change #5 added November 2004 Specification Change #1 added Document Change #4 added -006 Errata Change #6 and #7 added March 2005 Specification Change #2 added Document Change #5 added -007 Errata Change #8 added November 2007 Errata Change #4 Updated §
R Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
R Summary Table of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes that apply to the listed Intel 855GM/855GME chipset GMCH steppings. Intel intends to fix some of the errata in a future stepping of the component and to account for the other outstanding issues through documentation or Specification Changes as noted.
R Errata Stepping NO. PLANS A2 ERRATA 855GM 855GME 1 X X No Fix VGA Panning Test Issue 2 X X No Fix VGA Timing issue 3 X X No Fix Intermittent System hangs during power cycle test. 4 X X No Fix Display may flicker when integrated graphics and ECC support are enabled UPDATED 5 X No Fix Anomalous System Behavior May Occur When AGP GART Size is 64 MB and APBASE bit 27 is Set 6 X No Fix AGP PCI Write to system memory may be corrupted.
R Documentation Changes Stepping NO. 855GM 855GME 1 X X Ball definition for RSTIN# incorrectly shown in table 44 2 X X DVODETECT internal resistor incorrectly defined in Section 3.6.3 X Section 8.4 and Section 10 incorrectly shows some signal pins as reserved 3 8 DOCUMENTATION CHANGES A2 4 X X LVDS Panel Clock Frequency Range Is Incorrect 5 X X Electrical Characteristics Chapter added to the Public Datasheets.
R Identification Information Component Identification via Programming Interface The Intel 855GM/855GME chipset GMCH may be identified by the following register contents. 1 2 Component Stepping Vendor ID Device ID Revision Number 855GM A2 8086h 3580h (Device #0) 02h 855GME A2 8086h 3580h (Device #0) 02h 3 NOTES: 1. The Vendor ID corresponds to bits 15-0 of the Vendor ID Register located at offset 00-01h in the PCI function 0 configuration space. 2.
R Errata 1. VGA Panning Problem: VGA text mode diagnostic and stress test applications that use pixel panning can experience temporary visual anomalies under certain memory configurations. This issue was seen in two test configurations. 1. Test applications using a single VGA font table with a 32-kB font buffer range could fail. The failure can occur using 64-MB technology products that use 2-kB and 4-kB page sizes. This failure was seen in a diagnostic utility. 2.
R 3. Intermittent System Hangs during BIOS Memory Testing When Power Cycle Testing Problem: Systems may intermittently hang during BIOS memory testing as a result of the internal RCOMP state machine colliding with BIOS induced RCOMP cycle. Implication: System hang may occur during boot-up or resume from S3. No other failures have been identified or reported. Issues are resolved with a BIOS workaround. Workaround: Please refer to Intel 855GM Memory BIOS Specification and BIOS Spec Update for details.
R 7. A4, B4 – AGP PCI Write to System Memory May Be Corrupted Problem: Display corruption or a system hang may result if an upstream AGP FRAME#-based PCI write crosses a 32-byte aligned boundary. Note that upstream AGP FRAME#-based PCI writes which cross a 32-byte aligned boundary are expected to be rare. Implication: The issue may cause display corruption or a system hang. With the workaround implemented, Intel has done extensive validation and expects less than 3% impact on system performance.
R Specification Changes 1. 24-Bit LVDS Will Not Be Supported on 855GM/855GME Platforms 24-bit LVDS support has been dropped from 855GM/855GME platforms. This change affects Section 6.5.2.1 paragraph 4. Text stating 24-bit LVDS should be ignored. 2. ECC Is Not a Validated or Supported Feature on 855GM/GME Mobile Platforms ECC is not a validated or supported feature on 855GM/GME mobile platforms. All text stating support for ECC is not applicable for mobile platforms.
R Specification Clarifications 1. Graphics Limitations Using ECC DIMM Memory Memory with ECC enabled requires more system memory resources. This will cause the Integrated graphics engine to have less memory bandwidth for accesses to the graphics frame buffer. A system BIOS workaround is required to allow integrated graphics more access time to memory. (contact your BIOS vendor for latest updates). SO-DIMM memory with ECC enabled is not supported.
R Documentation Changes 1. Ball Definition for RSTIN# Incorrectly shown in Table 51 Table 51, “XOR Chain Exclusion List of Pins” incorrectly shows the ball definition for RSTIN# to be D28. Actual ball definition is AD28. D28 is a VSS ball. This is the only reference where RSTIN# is incorrectly defined. Ballout diagram in Section 11 is correct. 2. DVODETECT Internal Resistor Is Improperly Defined in Section 3.6.3 The text in Section 3.6.
R 4. LVDS Panel Clock Range Is Incorrect LVDS Flat Panel Clock Speed is shown as a range of 35 MHz – 112 MHz throughout the document. The lower end should be changed to 25 MHz. The correct range is from 25 MHz – 112 MHz. This correction will apply to Table 2 Intel 855GM/855GME GMCH Interface Clocks, Section 6.5.2.1 paragraph 1, and Section 6.5.2.2 paragraph 2. 5.
