Datasheet

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Intel

852GME Chipset GMCH

and Intel

852PM Chipset MCH

Datasheet

April 2005

Document Number: 253027-004

Summary of content (279 pages)

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R Intel® 852GME Chipset GMCH and Intel® 852PM Chipset MCH Datasheet April 2005 Document Number: 253027-004
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R INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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R Contents 1 Overview ........................................................................................................................... 17 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 2 Signal Description ............................................................................................................. 27 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Datasheet Terminology..........................................................................................................
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R 3 Register Description.......................................................................................................... 63 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 4 Conceptual Overview of the Platform Configuration Structure ............................ 63 Nomenclature for Access Attributes..................................................................... 64 Standard PCI Bus Configuration Mechanism....................................................... 65 Routing Configuration Accesses ........
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R 3.8.1 3.8.2 3.8.3 3.8.4 3.8.5 3.8.6 3.8.7 3.8.8 3.8.9 3.9 3.10 Datasheet VID – Vendor Identification Register (Device #0, Function #1) .......... 105 DID – Device Identification Register (Device #0, Function #1) .......... 105 PCICMD – PCI Command Register (Device #0, Function #1) ........... 106 PCISTS – PCI Status Register (Device #0, Function #1)................... 107 RID – Revision Identification Register (Device #0, Function #1) .......
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R 3.11 4 System Address Map ...................................................................................................... 161 4.1 4.2 4.3 4.4 5 System Memory Address Ranges...................................................................... 161 MS-DOS* Compatibility Area ............................................................................. 163 Extended System Memory Area.........................................................................
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R 5.5 5.6 5.7 5.8 5.9 5.10 5.11 6 Electrical Characteristics................................................................................................. 209 6.1 6.2 6.3 6.4 6.5 7 Strapping Configuration Table............................................................................ 241 Ballout and Package Information .................................................................................... 243 9.1 Datasheet XOR Chain Differential Pairs..............................................
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R Figures Figure 1. Intel® 852PM GMCH Chipset System Block Diagram....................................... 13 Figure 2. Intel® 852GME GMCH Chipset System Block Diagram .................................... 16 Figure 3 . Full and Warm Reset Waveforms..................................................................... 53 Figure 4. Configuration Address Register......................................................................... 68 Figure 5. Configuration Data Register ....................................
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R Tables Table 1. SDRAM Memory Capacity .................................................................................. 22 Table 2. Intel® 852GME GMCH Interface Clocks ............................................................. 25 Table 3. Host Interface Signal Descriptions...................................................................... 28 Table 4. DDR SDRAM Interface Descriptions .................................................................. 31 Table 5. AGP Addressing Signal Descriptions ..
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R Table 49. Intel® 852GM/852GME/852GMV GMCH and Intel® 852PM MCH Package Thermal Resistance................................................................................................. 210 Table 50. Power Characteristics ..................................................................................... 211 Table 51. Signal Groups ................................................................................................. 213 Table 52. DC Characteristics .........................................
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R Revision History Revision Number Description -001 Initial release -002 Updates include: Revision Date June 2003 May 2004 ® ® • Added support for Mobile Intel Pentium 4 processor supporting Hyper-Threading Technology on 90-nm process technology • Updated Reference Documents table -003 June 2004 Updates include: ® ® • Added support for Intel Celeron D processor on 90 nm process and in the 478-pin package -004 Updates include: April 2005 • Added Electrical Characteristics as Chapter 6 • Test
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R Intel® 852PM Chipset MCH Features Processor/Host Bus Support ⎯ Mobile Intel® Pentium® 4 processor supporting Hyper-Threading Technology† on 90-nm process technology ⎯ Mobile Intel® Pentium® 4 processor ⎯ Intel® Celeron® processor ⎯ Intel® Celeron® D processor on 90 nm process and in the 478-pin package ⎯ Source synchronous double pumped Address (2X) ⎯ Source synchronous quad pumped Data (4X) ⎯ Supports a subset of the Enhanced Mode Scalable Bus Protocol ⎯ Intel Pentium 4 processor system bus interrupt
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R Figure 1. Intel® 852PM GMCH Chipset System Block Diagram Intel Processor 400/533MHz PC2100/PC2700 AGP 2.0 AGP Controller 852PM MCH 732 Micro-FCBGA 266/333MHz DDR 266 MHz HUB Interface ATA100 IDE (2) LAN Intel 82801DBM USB 2.0/1.1 (6) ICH4-M 421 BGA PCI 33MHz Audio Codec Moon2 AC’97 2.
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R Intel® 852GME Chipset GMCH Features Note: The Intel® 852GME chipset GMCH shares the same chipset features as the Intel 852PM chipset MCH along with the following additional integrated graphics features.
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R supported • Max 165 MHz dot clock • Variety of DVO devices supported • Compliant with DVI Specification 1.0 ⎯ Dedicated LFP LVDS interface • Single or dual channel LVDS panel support up UXGA panel resolution with frequency range from 25 MHz to 112 MHz (single channel/dual channel) • Supports data format of 18-bpp • Compliant with ANSI/TIA/EIA –6441995 specification • SSC support of 0.5%, 1.0%, and 2.
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R Figure 2. Intel® 852GME GMCH Chipset System Block Diagram Intel Processor RGB CRT 400/533 MHz FSB LVDS Panel 852GME GMCH 732 Micro-FCBGA DVO Device/ AGP Graphic Controller DVO/AGP PC2100/PC2700 266/333 MHz DDR 266 MHz Hub Interface ATA100 IDE (2) LAN Intel 82801DB ICH4-M 421 BGA USB 2.0/1.1 (6) Audio Codec PCI 33MHz AC’97 2.
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Overview R 1 Overview This datasheet provides Intel’s specifications for the Intel® 852PM and Intel® 852GME chipset based systems. The Intel® 852PM chipset MCH is designed for use with the Mobile Intel® Pentium® 4 processor, Mobile Intel® Pentium® 4 Processor supporting Hyper-Threading Technology on 90-nm process technology, Intel® Celeron® processor or the Intel® Celeron® D processor on 90 nm process and in the 478-pin package.
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Overview R Term DBL Display Brightness Link DVO Digital Video Out DVI* Digital Visual Interface is the interface specified by the DDWG (Digital Display Working Group) DVI Spec. Rev. 1.
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Overview R Term 1.2 Description System Bus Processor-to-GMCH interface. The Enhanced mode of the Scalable bus is the P6 Bus plus enhancements, consisting of source synchronous transfers for address and data, and system bus interrupt delivery. The Mobile Intel Pentium 4 processor and Intel Celeron processor implement a subset of Enhanced mode.
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Overview R Document Document No./Location Advanced Configuration and Power Management(ACPI) Specification 1.0b & 2.0 http://www.teleport.com/~acpi/ Advanced Power Management (APM) Specification 1.2 http://www.microsoft.com/hwdev/busbios/amp_12.ht m ® IA-32 Intel Architecture Software Developer Manual Volume 3: System Programming Guide http://developer.intel.com/design/Pentium4/manuals/ 24547203.pdf 1.3 System Architecture Overview 1.3.
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Overview R 1.4 Processor Host Interface Intel 852GME GMCH and 852PM MCH are optimized for the Mobile Intel Pentium 4 processor.
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Overview R Table 1. SDRAM Memory Capacity Technology Width System Memory Capacity System Memory Capacity with High Density 128 Mb 16 256 MB - 256 Mb 16 512 MB - 512 Mb 16 1 GB - 128 Mb 8 256 MB 512 MB 256 Mb 8 512 MB 1 GB 512 Mb 8 1 GB 2 GB The Intel 852PM MCH and Intel 852GME system memory interface supports a thermal throttling scheme to selectively throttle reads and/or writes. Throttling can be triggered either by on-die thermal sensor, or by preset write bandwidth limits.
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Overview R The GMCH has four display ports, one analog and three digital. These provide support for a progressive scan analog monitor, a dedicated dual channel LVDS panel and two DVO devices. The data that is sent out to the display port is selected from one of the two possible sources, pipe A or pipe B. 1.6.
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Overview R within the Graphics Aperture address range pass through an address translation mechanism with a fully associative 20 entry TLB. Accesses between AGP and hub interface are limited to memory writes originating from the hub interface destined for AGP. The AGP interface is clocked from a dedicated 66 MHz clock (GLCKIN). The AGP-to-host/core interface is asynchronous. The AGP interface should be powered-off or tri-stated without voltage on the interface during ACPI S3 or APM Suspend to RAM state.
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Overview R AGP and hub interface run at a constant 66 MHz base frequency. The hub interface runs at 4X, while AGP transfers may be at 1X, 2X, or 4X. The following table indicates the frequency ratios between the various interfaces that the GMCH/MCH supports: Table 2.
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Overview R 26 Datasheet
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Signal Description R 2 Signal Description This section describes the GMCH/MCH signals. These signals are arranged in functional groups according to their associated interface. The following notations are used to describe the signal type: I Input pin O Output pin I/O Bi-directional Input/Output pin The signal description also includes the type of buffer used for the particular signal: AGTL+ Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for complete details.
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Signal Description R 2.1 Host Interface Signals Table 3. Host Interface Signal Descriptions Signal Name Type Description ADS# I/O AGTL+ Address Strobe: The system bus owner asserts ADS# to indicate the first of two cycles of a request phase. The GMCH/MCH can assert this signal for snoop cycles and interrupt messages. BNR# I/O AGTL+ Block Next Request: Used to block the current request bus owner from issuing a new request. This signal is used to dynamically control the CPU bus pipeline depth.
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Signal Description R Signal Name DPSLP# Type I CMOS Description Deep Sleep #: This signal comes from the ICH4-M device, providing an indication of C3 and C4 state control to the CPU. Deassertion of this signal is used as an early indication for C3 and C4 wake up (to active HPLL). Note that this is a low Voltage CMOS buffer operating on the FSB VTT power plane. DRDY# I/O Data Ready: Asserted for each cycle that data is transferred.
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Signal Description R Signal Name HREQ[4:0]# Type Description I/O AGTL+ Host Request Command: Defines the attributes of the request. HREQ[4:0]# are transferred at 2X rate. Asserted by the requesting agent during both halves of the Request Phase. In the first half the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. In the second half the signals carry additional information to define the complete transaction type.
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Signal Description R 2.2 DDR SDRAM Interface Table 4. DDR SDRAM Interface Descriptions Signal Name SCS[3:0]# Type O SSTL_2 Description Chip Select: These pins select the particular DDR SDRAM components during the active state. NOTE: There is one SCS# per DDR-SDRAM Physical SO-DIMM device row. These signals can be toggled on every rising system memory clock edge (SCMDCLK).
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Signal Description R Signal Name SDQS[8:0] Type I/O SSTL_2 Description Data Strobes: Data strobes are used for capturing data. During writes, SDQS is centered on data. During reads, SDQS is edge aligned with data. The following list matches the data strobe with the data bytes. There is an associated data strobe (DQS) for each data signal (DQ) and check bit (CB) group.
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Signal Description R 2.3 AGP Interface Signals Unless otherwise specified, the voltage level for all signals in this interface is 1.5 volts. 2.3.1 AGP Addressing Signals Table 5. AGP Addressing Signal Descriptions Signal Name GPIPE# Type Description I AGP Pipelined Read: This signal is asserted by the AGP master to indicate a full width address is to be enqueued on by the target using the AD bus. One address is placed in the AGP request queue on each rising clock edge while PIPE# is asserted.
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Signal Description R 2.3.2 AGP Flow Control Signals Table 6. AGP Flow Control Signals Signal Name GRBF# Type I AGP Description Read Buffer Full: Read buffer full indicates if the master is ready to accept previously requested low priority read data. When RBF# is asserted the GMCH/MCH is not allowed to initiate the return low priority read data. That is, the GMCH/MCH can finish returning the data for the request currently being serviced. RBF# is only sampled at the beginning of a cycle.
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Signal Description R 2.3.3 AGP Status Signals Table 7. AGP Status Signal Descriptions Datasheet Signal Name Type GST[2:0] O AGP Description Status: Provides information from the arbiter to an AGP Master on what it may do. ST[2:0] only have meaning to the master when its GNT# is asserted. When GNT# is deasserted these signals have no meaning and must be ignored.
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Signal Description R 2.3.4 AGP Strobes Table 8. AGP Strobe Descriptions Signal Name 36 Type Description GADSTB[0] I/O AGP Address/Data Bus Strobe-0: provides timing for 2X and 4X data on AD[15:0] and C/BE[1:0]# signals. The agent that is providing the data will drive this signal. GADSTB#[0] I/O AGP Address/Data Bus Strobe-0 Complement: With AD STB0, forms a differential strobe pair that provides timing information for the AD[15:0] and C/BE[1:0]# signals in 4X mode.
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Signal Description R 2.3.5 AGP/PCI Signals-Semantics For transactions on the AGP interface carried using AGP FRAME# protocol these signals operate similarly to their semantics in the PCI 2.1 specification, as defined below. Table 9. AGP/PCI Signals-Semantics Descriptions Signal Name GFRAME# Type I/O AGP Description G_FRAME: Frame. During PIPE# and SBA Operation: Not used by AGP SBA and PIPE# operations. During Fast Write Operation: Used to frame transactions as an output during Fast Writes.
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Signal Description R Signal Name GSTOP# Type I/O AGP Description G_STOP#: Stop. During PIPE# and SBA Operation: This signal is not used during PIPE# or SBA operation. During FRAME# Operation: G_STOP# is an input when the GMCH/MCH acts as a FRAME#-based AGP initiator and is an output when the GMCH/MCH acts as a FRAME#-based AGP target. G_STOP# is used for disconnect, retry, and abort sequences on the AGP interface. GDEVSEL# I/O AGP G_ DEVSEL#: Device Select.
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Signal Description R Signal Name GPAR Type I/O AGP Description Parity. During FRAME# Operation: G_PAR is driven by the GMCH/MCH when it acts as a FRAME#-based AGP initiator during address and data phases for a write cycle, and during the address phase for a read cycle. G_PAR is driven by the GMCH/MCH when it acts as a FRAME#-based AGP target during each data phase of a FRAME#-based AGP memory read cycle. Even parity is generated across G_AD[31:0] and G_CBE[3:0]#.
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Signal Description R 2.5 Clocks Table 11. Clock Signals Signal Name Type Description Host Processor Clocking BCLK I BCLK# CMOS Differential Host Clock In: These pins receive a buffered host clock from the external clock synthesizer. This clock is used by all of the GMCH/MCH logic that is in the Host clock domain (host, hub and system memory). The clock is also the reference clock for the graphics core PLL. This is a low voltage differential input.
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Signal Description R Signal Name Type DVOBCCLKINT I DVO Description DVOBC Pixel Clock Input/Interrupt: This input can be programmed to be either a TV reference clock input from a TV encoder or an Interrupt input pin for LFP display Hot Plug support. DVOBC Pixel Clock Input: This signal may be configured as the reference clock input from a TV-OUT device. The maximum input frequency for this signal is 85 MHz. DVOBC Interrupt: This signal may be configured as an interrupt input for Hot plug support.
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Signal Description R 2.6 GMCH Internal Graphics Display Signals The Intel 852GME internal graphics device has support for four display ports: a dedicated LVDS panel interface, two DVO ports, and an analog VGA port. 2.6.1 Dedicated LVDS Panel Interface Table 12. Dedicated LVDS Panel Interface Signal Descriptions Name ICLKAP Type O Voltage 1.25 V± 225 mV LVDS ICLKAM O O 1.25 V±225 mV O 1.25 V±225 mV O 1.25 V±225 mV Channel A differential data pair 3:0 output (compliment): 245-800 MHz. 1.
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Signal Description R 2.6.2 Digital Video Port B (DVOB) Table 13. Digital Video Port B Signal Descriptions Signal Name DVOBD[11:0] Type Description O DVOB Data: This data bus is used to drive 12-bit RGB data on each edge of the differential clock signals, DVOBCLK and DVOBCLK#. This provides 24-bits of data per clock period. In dual channel mode, this provides the lower 12-bits of pixel data. DVO DVOBD[11:0] should be left as left as NC (“Not Connected”) if not used.
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Signal Description R 2.6.3 Digital Video Port C (DVOC) Table 14. Digital Video Port C Signal Descriptions Signal Name DVOCD[11:0] Type Description O DVOC Data: This data bus is used to drive 12-bit RGB data on each edge of the differential clock signals, DVOCCLK and DVOCCLK#. This provides 24-bits of data per clock period. In dual channel mode, this provides the upper 12-bits of pixel data. DVO DVOCD[11:0] should be left as left as NC (“Not Connected”) if not used.
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Signal Description R Table 15. DVOB and DVOC Port Common Signal Descriptions Signal Name Type DVOBCINTR# I DVO ADDID[7:0] I DVO Description DVOBC Interrupt: This pin is used to signal an interrupt, typically used to indicate a hot plug or unplug of a digital display. ADDID[7:0]: These pins are used to communicate to the video BIOS when an external device is interfaced to the DVO port. NOTE: Bit[7] needs to be strapped low when an on-board DVO device is present. The other pins should be left as NC.
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Signal Description R 2.6.4 GMCH DVO & I2C to AGP Pin Mapping The GMCH will mux a DVODETECT signal with the GPAR signal on the AGP bus. This signal will act as a strap and indicate whether the interface is in AGP or DVO mode. The GMCH/MCH has an internal pull-down on DVODETECT signal that will by default pull it low.
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Signal Description R 2.6.5 Analog Display Table 17. Analog Display Signal Descriptions Signal Name VSYNC Type O CMOS HSYNC O CMOS RED O Analog RED# O Description CRT Vertical Synchronization: This signal is used as the vertical sync signal. CRT Horizontal Synchronization: This signal is used as the horizontal sync signal. Red (Analog Video Output): This signal is a CRT Analog video output from the internal color palette DAC. The DAC is designed for a 37.5-Ω equivalent load on each pin (e.g.
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Signal Description R 2.6.6 Graphics General Purpose Input/Output Signals Table 18. Graphics GPIO Signal Descriptions GPIO I/F Total AGPBUSY# Type Comments O AGPBUSY: Output of the GMCH IGD to the ICH4-M, which indicates that certain graphics activity is taking place. It will indicate to the ACPI software not to enter the C3 state. It will also cause a C3/C4 exit if C3/C4 was being entered, or was already entered when AGPBUSY# went active. Not active when the IGD is in any ACPI state other than D0.
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Signal Description R GPIO I/F Total MI2CDATA Type Comments I/O DVO I2C Data: This signal is used as the I2C_DATA for a digital display (i.e. TV-Out Encoder, TMDS transmitter). This signal is tri-stated during a hard reset. DVO MDVICLK I/O DVO MDVIDATA I/O DVO MDDCDATA I/O DVO MDDCCLK I/O DVO 2.7 DVI DDC Clock: This signal is used as the DDC clock for a digital display connector (i.e. primary digital monitor). This signal is tri-stated during a hard reset.
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Signal Description R 2.8 Voltage References, PLL Power Table 19. Voltage References, PLL Power GPIO I/F Total Type Comments Host Processor HXRCOMP Analog Host RCOMP: Used to calibrate the Host AGTL+ I/O buffers. HYRCOMP Analog Host RCOMP: Used to calibrate the Host AGTL+ I/O buffers. HXSWING Analog Host Voltage Swing (RCOMP reference voltage): These signals provide a reference voltage used by the FSB RCOMP circuit.
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Signal Description R VCCASM Power Power supply for system memory logic running at the core voltage (isolated supply, not connected to the core). Hub Interface HLRCOMP Analog Hub Interface RCOMP: This signal is connected to a reference resistor in order to calibrate the buffers. PSWING Analog RCOMP reference voltage: This is connected to the RCOMP buffer differential amplifier and is used to calibrate the buffers.
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Signal Description R 2.9 Reset States and Pull-up/Pull-downs This section describes the expected states of the Intel 852GME GMCH and 852PM MCH I/O buffers. These tables refer only to the contributions on the interface from the GMCH/MCH and do NOT reflect any external influence (such as external pullup/pulldown resistors or external drivers).
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Signal Description R 2.9.1 Full and Warm Reset State Figure 3 . Full and Warm Reset Waveforms ICH4-M Power ICH4-M PWROK In 1 ms min write to CF9h 1 ms min ICH4-M PCIRST# Out GMCH/MCH RSTIN# In 1 ms 1 ms GMCH/MCH CPURST# Out GMCH/MCH Power GMCH/MCH PWROK In GMCH/MCH Reset State Unknown Full Reset Running Warm Reset Warm Reset Running All register bits assume their default values during full reset.
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Signal Description R Table 21.
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Signal Description R Table 22. System Memory Signal Reset and Power Managed States Host I/F Total Before CPURST# Deassertion Just out of CPURST# C3 S1 S3 S4/S5 SDQ[63:0] Hi-Z Hi-Z Intern: IG Hi-Z Hi-Z Pwrdn SDM[8:0] Hi-Z Hi-Z Intern: IG Hi-Z Hi-Z Pwrdn SDQS[7:0] Hi-Z Hi-Z Intern: IG Hi-Z Hi-Z Pwrdn Hi-Z Hi-Z Pwrdn Hi-Z Hi-Z Pwrdn If ECC not enabled, ECC clocks are Hi-Z.
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Signal Description R Table 23.
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Signal Description R Table 24.
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Signal Description R Host I/F Total DVOBFLDSTL MDDCDATA DVOCVSYNC DVOCHSYNC DVOCBLANK# DVOCD[0] DVOCD[1] DVOCD[2] DVOCD[3] DVOCD[4] DVOCD[7] DVOCD[6] DVOCD[8] DVOCD[11] 58 Before CPURST# Deassertion Just out of CPURST# C3 S1 S3 S4/S5 Input Input Normal Operation Input Pwrdn Pwrdn Hi-Z External PU Hi-Z External PU Hi-Z External PU Hi-Z External PU Pwrdn Pwrdn Hi-Z Normal Operation Hi-Z if port not enabled Pwrdn Pwrdn Hi-Z Normal Operation Hi-Z if port not enabled Pw
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Signal Description R Host I/F Total Just out of CPURST# C3 S1 S3 S4/S5 Input Normal Operation Input Pwrdn Pwrdn Hi-Z Normal Operation Hi-Z if port not enabled Pwrdn Pwrdn Hi-Z Normal Operation Hi-Z if port not enabled Pwrdn Pwrdn Hi-Z Hi-Z Normal Operation Hi-Z if port not enabled Pwrdn Pwrdn Hi-Z External PU Hi-Z External PU Hi-Z External PU Hi-Z External PU Pwrdn Pwrdn Hi-Z External PU Hi-Z External PU Hi-Z External PU Hi-Z External PU Pwrdn Pwrdn Hi-Z External PU
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Signal Description R Table 25.
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Signal Description R Table 26.
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Signal Description R 62 Datasheet
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Register Description R 3 Register Description 3.1 Conceptual Overview of the Platform Configuration Structure The Intel 852GME GMCH, Intel 852PM MCH and ICH4-M are physically connected by hub interface. From a configuration standpoint, the hub interface is logically PCI bus #0. As a result, all devices internal to the GMCH/MCH and ICH4-M appear to be on PCI bus #0.
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Register Description R Table 27. Device Number Assignment GMCH/MCH Function 3.2 Bus #0, Device# Host-Hub Interface, DDR SDRAM I/F, Legacy control Device #0 (Intel 852GME GMCH and Intel 852PM MCH) Host-to-AGP Bridge(Virtual PCI-to-PCI) Device #1 (Intel 852GME GMCH and Intel 852PM MCH) Integrated Graphics Controller (IGD) Device #2 (Intel 852GME GMCH) Nomenclature for Access Attributes Table 28 provides the nomenclature for the access attributes. Table 28.
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Register Description R A physical PCI Bus #0 does not exist. The hub interface and the internal devices in the GMCH/MCH and ICH4-M logically constitute PCI Bus #0 to configuration software. 3.3 Standard PCI Bus Configuration Mechanism The PCI bus defines a slot based “configuration space” that allows each device to contain up to eight functions with each function containing up to 256, 8-bit configuration registers.
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Register Description R The Host-Hub Interface Bridge entity within the GMCH/MCH is hardwired as Device #0 on PCI Bus #0. The Host-AGP/PCI_B Bridge entity within the GMCH/MCH is hardwired as Device #1 on PCI Bus #0. Configuration cycles to any of the GMCH/MCH’s internal devices are confined to the GMCH/MCH and not sent over hub interface. Accesses to disabled GMCH/MCH internal devices will be forwarded over the hub interface as Type 0 Configuration cycles. 3.4.
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Register Description R Note: Although initial AGP platform implementations will not support hierarchical buses residing below AGP, this specification still must define this capability in order to support PCI-66 compatibility. Note also that future implementations of the AGP devices may support hierarchical PCI or AGP-like buses coming out of the root AGP device. 3.
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Register Description R DDR SDRAM configurations, operating parameters, and optional system features that are applicable and to program the GMCH/MCH registers accordingly. 3.6 I/O Mapped Registers The GMCH/MCH contains two registers that reside in the CPU I/O Address Space: the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register.
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Register Description R Bit Description 31 Configuration Enable (CFGE): When this bit is set to 1, accesses to PCI Configuration Space are enabled. If this bit is Reset to 0, accesses to PCI Configuration Space are disabled. 30:24 Reserved 23:16 Bus Number: When the Bus Number is programmed to 00h, the target of the Configuration Cycle is a hub interface agent (GMCH, ICH4-M, etc.).
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Register Description R 3.6.2 CONFIG_DATA – Configuration Data Register I/O Address: Default Value: Access: Size: 0CFCh 00000000h Read/Write 32 bits CONFIG_DATA is a 32-bit Read/Write window into Configuration Space. The portion of Configuration Space that is referenced by CONFIG_DATA is determined by the contents of CONFIG_ADDRESS. Figure 5. Configuration Data Register 31 0 0 Bit Default Configuration Data Window Bit 31:0 70 Description Configuration Data Window (CDW).
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Register Description R 3.7 Host-Hub Interface Bridge Device Registers (Device #0, Function #0) Table 29 summarizes the configuration space for Device #0, Function#0. Table 29.
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Register Description R Register Name 72 Register Symbol Register Start Register End Default Value Access System Management RAM Control SMRAM 60 60 02h R/W/L Extended System Management RAM Control ESMRAMC 61 61 38h R/W/L Error Status ERRSTS 62 63 0000h R/WC Error Command ERRCMD 64 65 0000h R/W SMI Command SMICMD 66 66 00h R/W SCI Command SCICMD 67 67 00h R/W Secondary Host Interface Control Register SHIC 74 77 00006010h RO, R/W AGP Capability Identifier ACAP
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Register Description R 3.7.1 VID – Vendor Identification Register (Device #0) Address Offset: Default Value: Access: Size: 00-01h 8086h Read Only 16 bits The VID register contains the vendor identification number. This 16-bit register, combined with the Device Identification Register, uniquely identifies any PCI device. Writes to this register have no effect. Bit Description 15:0 3.7.
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Register Description R 3.7.3 PCICMD – PCI Command Register (Device #0) Address Offset: Default Value: Access: Size: 04-05h 0006h Read Only, Read/Write 16 bits Since GMCH/MCH Device #0 does not physically reside on PCI_A many of the bits are not implemented. Bit Description 15:10 Reserved 9 Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast back-to-back Write. Since Device #0 is strictly a target, this bit is not implemented and is hardwired to 0.
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Register Description R 3.7.4 PCI Status Register (Device #0) Address Offset: Default Value: Access: Size: 06-07h 0090h Read Only, Read/WriteClear 16 bits PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0’s PCI Interface. Bit 14 is Read/Write Clear. All other bits are Read Only. Since GMCH/MCH Device #0 does not physically reside on PCI_A many of the bits are not implemented.
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Register Description R 3.7.5 RID – Revision Identification (Device #0) Address Offset: Default Value: Access: Size: 08h 02h Read Only 8 bits This register contains the revision number of the GMCH/MCH Device #0. These bits are read only and writes to this register have no effect. Bit 7:0 Description Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification number for the GMCH/MCH Device #0. Intel 852GME = 02 Intel 852PM = 02 3.7.
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Register Description R 3.7.7 BCC – Base Class Code Register (Device #0) Address Offset: Default Value: Access: Size: 0Bh 06h Read Only 8 bits This register contains the Base Class code of the GMCH/MCH Device #0. This code is 06h indicating a bridge device. Bit Description 7:0 3.7.8 Base Class Code (BASEC): This is an 8-bit value that indicates the Base Class Code for the GMCH/MCH. This code has the value 06h, indicating a Bridge device.
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Register Description R 3.7.9 APBASE – Aperture Base Configuration (Device #0) Address Offset: Default Value: Access: Size: 10h 00000008h Read Only, Read/Write 32 bits The APBASE is a standard PCI Base Address register that is used to set the base of the Graphics Aperture. The standard PCI Configuration mechanism defines the base address configuration register such that only a fixed amount of space can be requested (dependent on which bits are hardwired to “0” or behave as hardwired to “0”).
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Register Description R 3.7.10 SVID – Subsystem Vendor Identification Register (Device #0) Address Offset: Default Value: Access: Size: 2C-2Dh 0000h Read/Write Once 16 bits This value is used to identify the vendor of the subsystem. Bit 15:0 3.7.11 Description Subsystem Vendor ID (SUBVID): This field should be programmed during boot-up to indicate the vendor of the system board. After it has been written once, it becomes Read Only.
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Register Description R 3.7.13 CAPID⎯Capability Identification Register (Device #0) Address Offset: Default: Access: Size 40 – 44h Chipset Dependent Read Only 40 bits The Capability Identification Register uniquely identifies chipset capabilities as defined in the table below. The bits in this register are intended to define a capability ceiling for each feature, not a capability select.
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Register Description R 3.7.14 RRBAR – Register Range Base Address Register (Device #0) Address Offset: Default Value: Access: Size: 48−4Bh 00000000h Read/Write, Read Only 32 bits This register requests a 64-kB allocation for the Device registers. The base address is defined by bits 31 to 16 and can be used to access device configuration registers. Only Dword aligned writes are allowed to this space. See Table below for address map within the 64-kB space.
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Register Description R 3.7.15 GMC – GMCH Miscellaneous Control Register (Device #0) Address Offset: Default Value: Access: Size: 50–51h 0000h Read/Write 16 bits Bit Description 15:10 Reserved 9 Aperture Access Global Enable—R/W. This bit is used to prevent access to the aperture from any port (CPU, PCI0 or AGP/PCI1) before the aperture range is established and appropriate translation table in the main DDR SDRAM has been initialized. Default is 0.
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Register Description R 3.7.16 GGC – GMCH Graphics Control Register (Device 0) Address Offset: Default Value: Access: Size: Bit 52–53h 0030h Read/Write 16 bits Description 15:7 Reserved 6:4 Graphics Mode Select (GMS): This field is used to select the amount of main system memory that is pre-allocated to support the Internal Graphics Device in VGA (non-linear) and Native (linear) modes. The BIOS ensures that system memory is pre-allocated only when Internal Graphics is enabled.
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Register Description R 3.7.17 DAFC – Device and Function Control Register (Device 0) Address Offset: Default Value: Access: Size: 54–55h 0000h Read/Write 16 bits This 16-bit register controls the visibility of devices and functions within the GMCH/MCH to configuration software. Bit Description 15:8 Reserved 7 Device #2 Disable: 1 = Disabled. 0 = Enabled. 6:3 Reserved 2 Device #0 Function #3 Disable: 1 = Disable Function #3 registers within Device #0 and all associated DDR SDRAM and I/O ranges.
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Register Description R 3.7.18 FDHC – Fixed DRAM Hole Control Register (Device #0) Address Offset: Default Value: Access: Size: 58h 00h Read/Write 8 bits This 8-bit register controls a single fixed DDR SDRAM hole: 15–16 MB. Bit 7 Description Hole Enable (HEN): This field enables a memory hole in DDR SDRAM space. Host cycles matching an enabled hole are passed onto ICH4-M through hub interface. The GMCH/MCH will ignore hub interface cycles matching an enabled hole.
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Register Description R Table 30. Attribute Bit Assignment Bits [7, 3] Reserved Bits [6, 2] Reserved Bits [5, 1] WE Bits [4, 0] RE Description X X 0 0 Disabled. DDR SDRAM is disabled and all accesses are directed to hub interface. The GMCH/MCH does not respond as a hub interface target for any Read or Write access to this area. X X 0 1 Read Only. Reads are forwarded to DDR SDRAM and Writes are forwarded to hub interface for termination. This Write protects the corresponding DDR SDRAM segment.
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Register Description R Figure 6.
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Register Description R Table 31.
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Register Description R Video Buffer Area (A0000h–BFFFFh) Attribute Bits do not control this 128-kB area. The Host-initiated cycles in this region are always forwarded to either PCI0 or PCI2 unless this range is accessed in SMM mode. Routing of accesses is controlled by the Legacy VGA Control Mechanism of the “Virtual” PCI-PCI Bridge Device embedded within the GMCH. This area can be programmed as SMM area via the SMRAM register.
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Register Description R 3.7.20 SMRAM – System Management RAM Control Register (Device #0) Address Offset: Default Value: Access: Size: 60h 02h Read/Write/Lock, Read Only 8 bits The SMRAM register controls how accesses to Compatible and Extended SMRAM spaces are treated. The Open, Close, and Lock Bits function only when G_SMRAME Bit is set to a 1. Also, the Open Bit must be Reset before the LOCK Bit is set.
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Register Description R 3.7.21 ESMRAMC – Extended System Management RAM Control (Device #0) Address Offset: Default Value: Access: Size: 61h 38h Read/Write/Lock 8 bits The Extended SMRAM register controls the configuration of Extended SMRAM Space. The Extended SMRAM (E_SMRAM) Memory provides a Write-Back cacheable SMRAM Memory Space that is above 1 MB. Bit 7 Description H_SMRAM_EN (H_SMRAME): Controls the SMM Memory Space location (i.e., above 1 MB or below 1 MB).
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Register Description R 3.7.22 ERRSTS – Error Status Register (Device #0) Address Offset: Default Value: Access: Size: 62–63h 0000h Read/Write Clear 16 bits This register is used to report various error conditions. A SERR or SMI cycle may be generated on a zero to one transition of any of these flags when enabled in the PCICMD/ERRCMD, SMICMD, or SCICMD registers respectively.
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Register Description R 3.7.23 ERRCMD – Error Command Register (Device #0) Address Offset: Default Value: Access: Size: 64–65h 0000h Read/Write 16 bits This register enables various errors to generate. The actual generation of the SERR message is globally enabled for Device #0 via the PCI Command register. It is software’s responsibility to make sure that when an SERR error message is enabled for an error condition, SMI and SCI error messages are disabled for that same error condition.
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Register Description R Bit Description 4:2 Reserved 1 SERR on Multiple-bit ECC Error: 1 = For systems that support ECC, this field must be set to 1. 0 = Reserved 0 SERR on Single-bit ECC Error: 1 = For systems that support ECC, this field must be set to 1. 0 = Reserved 3.7.24 SMICMD – SMI Error Command Register (Device #0) Address Offset: Default Value: Access: Size: 66h 00h Read/Write 8 bits This register enables various errors to generate an SMI cycle.
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Register Description R 3.7.25 SCICMD – SCI Error Command Register (Device #0) Address Offset: Default Value: Access: Size: 67h 00h Read/Write 8 bits This register enables various errors to generate a SCI cycle. When an Error Flag is set in the ERRSTS register, it can generate a SERR or SMI cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers respectively. An error can generate one and only one Error Special cycle.
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Register Description R 3.7.26 SHIC - Secondary Host Interface Control Register (Device #0) Address Offset: Default Value: Access: Size: 74-77h 00006010h Read Only, Read/Write 32 bits Bit Description 31:2 Reserved 1 AGP/DVO Mux Strap (Read only): Specifies the use of AGP bus muxed with DVO. This bit is defined at Reset by a strap on the G_PAR/DVO_DETECT signal. By default the AGP bus pulls this signal high.
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Register Description R 3.7.28 AGPSTAT – AGP Status Register (Device #0) Address Offset: Default Value: Access: Size: A4–A7h 1F000217h Read Only 32 bits This register reports AGP device capability/status. Bit 31:24 Description Request (RQ). Indicates a maximum of 32 outstanding AGP command requests can be handled by the GMCH/MCH. Default =1Fh to allow a maximum of 32 outstanding AGP command requests. 23:10 Reserved 9 Side Band Addressing (SBA).
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Register Description R 3.7.29 AGPCMD – AGP Command Register (Device #0) Address Offset: Default Value: Access: Size: A8–ABh 00000000h Read/Write 32 bits This register provides control of the AGP operational parameters. Bit Description 31:10 Reserved 9 Side Band Addressing Enable (SBA_EN). When this bit is set to 1, the side band addressing mechanism is enabled. 8 AGP Enable. 0 = Disable. When this bit is reset to 0, the GMCH/MCH will ignore all AGP operations, including the sync cycle.
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Register Description R 3.7.30 AGPCTRL – AGP Control Register (Device #0) Address Offset: Default Value: Access: Size: B0–B1h 0000h Read/Write 16 bits This register provides for additional control of the AGP interface. Note: Bit 7 is visible to the operating system and must be retained in this position. Bit Description 15:8 Reserved 7 GTLB Enable (and GTLB Flush Control). NOTE: This bit can be changed dynamically (i.e., while an access to GTLB occurs).
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Register Description R 3.7.32 APSIZE – Aperture Size (Device #0) Address Offset: Default Value: Access: Size: B4h 00h Read/Write 8 bits This register determines the effective size of the Graphics Aperture used for a particular GMCH/MCH configuration. This register can be updated by the GMCH/MCH-specific BIOS configuration sequence before the PCI standard bus enumeration sequence. If the register is not updated then a default value will select an aperture of maximum size (i.e., 256 MB).
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Register Description R 3.7.33 ATTBASE – Aperture Translation Table Base Register (Device #0) Address Offset: Default Value: Access: Size: B8–BBh 00000000h Read/Write 32 bits This register provides the starting address of the Graphics Aperture Translation Table Base located in the main DDR SDRAM.
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Register Description R 3.7.34 AMTT – AGP Interface Multi-Transaction Timer Register (Device #0) Address Offset: Default Value: Access: Size: BCh 00h Read/Write 8 bits AMTT is an 8-bit register that controls the amount of time that the GMCH/MCH’s arbiter allows AGP/PCI master to perform multiple back-to-back transactions.
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Register Description R 3.7.35 LPTT – Low Priority Transaction Timer Register (Device #0) Address Offset: Default Value: Access: Size: BDh 00h Read/Write 8 bits LPTT is an 8-bit register similar in a function to AMTT. This register is used to control the minimum tenure on the AGP for low priority data transaction (both reads and writes) issued using PIPE# or SB mechanisms.
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Register Description R 3.8 Main Memory Control, Memory I/O Control Registers (Device #0, Function #1) The following table shows the GMCH/MCH Configuration Space for Device #0, Function #1. Table 32.
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Register Description R 3.8.1 VID – Vendor Identification Register (Device #0, Function #1) Address Offset: Default Value: Access: Size: 00-01h 8086h Read Only 16 bits The VID register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identifies any PCI device. Writes to this register have no effect. Bit 15:0 3.8.2 Description Vendor Identification (VID): This register field contains the PCI standard identification for Intel.
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Register Description R 3.8.3 PCICMD – PCI Command Register (Device #0, Function #1) Address Offset: Default Value: Access: Size: 04-05h 0006h Read Only, Read/Write 16 bits Since GMCH/MCH Device #0 does not physically reside on PCI_A, many of the bits are not implemented. Bit 106 Description 15:10 Reserved 9 Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast back-to-back Write.
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Register Description R 3.8.4 PCISTS – PCI Status Register (Device #0, Function #1) Address Offset: Default Value: Access: Size: 06-07h 0080h Read Only, Read/WriteClear 16 bits PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0’s PCI Interface. Bit 14 is Read/Write Clear. All other bits are Read Only. Since GMCH/MCH Device #0 does not physically reside on PCI_A, many of the bits are not implemented.
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Register Description R 3.8.5 RID – Revision Identification Register (Device #0, Function #1) Address Offset: Default Value: Access: Size: 08h 02h Read Only 8 bits This register contains the revision number of the GMCH/MCH Device #0. These bits are Read Only and Writes to this register have no effect. Bit 7:0 Description Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification number for the GMCH/MCH Device #0. Intel 852GME = 02 Intel 852PM = 02 3.8.
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Register Description R 3.8.8 HDR – Header Type Register (Device #0, Function #1) Address Offset: Default Value: Access: Size: 0Eh 80h Read Only 8 bits This register identifies the header layout of the configuration space. No physical register exists at this location. Bit 7:0 3.8.9 Description PCI Header (HDR): This field always returns 80 to indicate that Device #0 is a multifunction device. Reads and Writes to this location have no effect.
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Register Description R 3.8.11 CAPPTR – Capabilities Pointer Register (Device #0, Function #1) Address Offset: Default Value: Access: Size: 34h 00h Read Only 8 bits The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list. Bit 7:0 3.8.
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Register Description R 3.8.13 DRA – DRAM Row Attribute Register (Device #0, Function #1) Address Offset: Default Value: Access: Size: 50-51h 77h Each Read/Write 8 bits The DDR SDRAM Row Attribute register defines the page sizes to be used when accessing different pairs of rows. Each nibble of information in the DRA registers describes the page size of a pair of rows: Row0, 1: 50h Row2, 3: 51h 52h-5Fh: Reserved.
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Register Description R 3.8.14 DRT – DRAM Timing Register (Device #0, Function #1) Address Offset: Default Value: Access: Size: 60-63h 18004425h Read/Write 32 bits This register controls the timing of the DDR SDRAM controller. Bit 31 Description DDR Internal Write to Read Command delay (tWTR): The tWTR is a std. DDR SDRAM timing parameter with a value of 1 CK for CL=2 and 2.5.
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Register Description R Bit 27:26 Description Back To Back Read-Write commands spacing (DDR, same or different Rows/Bank): This field determines the RD-WR command spacing, in terms of common clocks based on the following formula: CL + 0.5xBL + TA (RD-WR) – DQSS DQSS: is time from Write command to data and is always 1 CK BL: is Burst Length which is set to 4 or 8. TA (RD-WR): is required DQ turn-around, can be set to 1, 2 or 3 CK CL: is CAS latency, can be set to 2 or 2.
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Register Description R Bit 14:12 Description Refresh Cycle Time (tRFC): Refresh Cycle Time is measured for a given row from REF command (to perform a refresh) until following ACT to same row (to perform a Read or Write). It is tracked separately from tRC for DDR SDRAM. Current DDR SDRAM spec requires tRFC of 75 ns (DDR266) and 80 ns (DDR200). Therefore, this field will be set to 8 clocks for DDR200, 10 clocks for DDR266.
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Register Description R Bit 3:2 Description DDR SDRAM RAS# to CAS# Delay (tRCD): This bit controls the number of clocks inserted between a Row Activate command and a Read or Write command to that row. Encoding 1:0 Datasheet tRCD 00: 4 DDR SDRAM Clocks (DDR 333 SDRAM) 01: 3 DDR SDRAM Clocks 10: 2 DDR SDRAM Clocks 11: Reserved DDR SDRAM RAS# Precharge (tRP): This bit controls the number of clocks that are inserted between a row precharge command and an activate command to the same row.
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Register Description R 3.8.15 PWRMG – DRAM Controller Power Management Control Register (Device #0, Function #1) Address Offset: Default Value: Access: Size: 68h-6Bh 00000000h Read/Write 32 bits Bit Description 31:24 Reserved 23:20 Row State Control: This field determines the number of clocks the system memory controller will remain in the idle state before it begins pre-charging all pages or powering down rows.
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Register Description R Bit 12 Description Dynamic Memory Interface Power Management: 0 = Dynamic Memory Interface Power Management Enabled. 1 = Dynamic Memory Interface Power Management Disabled. 11 Rcven DLL shutdown disable: 0 = Normal operation. RCVEN DLL is turned off when the corresponding SO-DIMM is unpopulated. 1 = Reserved 10 ECC SO-DIMM Clock tri-state Disable: 0 = When DDR SDRAM ECC is not enabled, the ECC clocks (i.e., SCK2/SCK2#, SCK5/SCK5#,) are tri- stated.
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Register Description R 3.8.16 DRC – DRAM Controller Mode Register (Device #0, Function #1) Address Offset: Default Value: Access: Size: 70-73h 00000081h RO, Read/Write 32 bits Bit Description 31:30 Revision Number (REV): Reflects the revision number of the format used for DDR SDRAM register definition (Read Only). 29 Initialization Complete (IC): This bit is used for communication of software state between the Memory Controller and the BIOS.
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Register Description R Bit 9:7 Description Refresh Mode Select (RMS): This field determines whether Refresh is enabled and, if so, at what rate Refreshes will be executed. 000: Refresh disabled 001: Refresh enabled. Refresh interval 15.6 µsec 010: Refresh enabled. Refresh interval 7.8 µsec 011: Reserved. 111: Refresh enabled. Refresh interval 64 clocks (fast refresh mode) Other: Reserved Any change in the programming of this field Resets the Refresh counter to zero.
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Register Description R Bit 6:4 Description Mode Select (SMS). These bits select the special operational mode of the DDR SDRAM Interface. The special modes are intended for initialization at power up. 000: Post Reset State – When the GMCH exits Reset (power-up or otherwise), the mode select field is cleared to 000. Software is not expected to Write this value, however if this value is Written, there are no side effects (no Self Refresh or any other special DDR SDRAM cycle).
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Register Description R Bit Description 3 Reserved 2 DDR SDRAM Burst Length: This bit is used to select the DDR SDRAM controller’s Burst Length operation mode. It must be set consistently to the DDR SDRAM component setting. Can be set to 8 in DDR SDRAM mode only.
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Register Description R 3.8.17 DTC – DRAM Throttling Control Register (Device #0, Function #1) Offset Address: Default Value: Access: Size: A0–A3h 00000000h Read/Write/Lock 32 bits Throttling is independent for system memory banks, GMCH Writes, and Thermal Sensor Trips. Read and Write Bandwidth is measured independently for each bank.
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Register Description R Bit Description 0111 = Similar to 0101 for Writes and when the Rank Thermal Sensor is tripped, DDR SDRAM Throttling begins based on the setting in RTTC. 1000 = Only Rank Counter mechanism is enabled. When the threshold set in the GDT field is reached, DDR SDRAM Throttling begins based on the setting in RCTC. 1001 = Rank Counter mechanism is enabled and GMCH Thermal Sensor based throttling are both enabled.
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Register Description R Bit 23:20 Description Write Counter Based Power Throttle Control (WCTC): These bits select the counter based Power Throttle Bandwidth Limits for Write operations to system memory.
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Register Description R Bit 15:12 Description Write Thermal Based Power Throttle Control (WTTC): These bits select the Thermal based Power Throttle Bandwidth Limits for Write operations to system memory. R/W, RO if Throttle Lock 0h = 85% 1h = 70% 2h = 65% 3h = 60% 4h = 55% 5h = 50% 6h = 45% 7h = 40% 8h = 35% 9h = 30% Ah = 20% B-Fh = Reserved 11 Counter Based Throttle Lock (CTLOCK): This bit secures RCTC and WCTC. This bit defaults to 0.
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Register Description R 3.9 Configuration Process Registers (Device #0, Function #3) Table 33 summarizes all Device#0, Function #3 registers. Table 33.
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Register Description R 3.9.1 VID – Vendor Identification Register (Device #0) Address Offset: Default Value: Access: Size: 00-01h 8086h Read Only 16 bits The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification register uniquely identifies any PCI device. Writes to this register have no effect. Bit 15:0 3.9.2 Description Vendor Identification (VID): This register field contains the PCI standard identification for 8086h.
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Register Description R 3.9.3 PCICMD – PCI Command Register (Device #0) Address Offset: Default Value: Access: Size: 04-05h 0006h Read Only, Read/Write 16 bits Since GMCH/MCH Device #0 does not physically reside on PCI_A, many of the bits are not implemented. Bit 128 Description 15:10 Reserved 9 Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast back-to-back Write. Since Device #0 is strictly a target, this bit is not implemented and is hardwired to 0.
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Register Description R 3.9.4 PCISTS – PCI Status Register (Device #0) Address Offset: Default Value: Access: Size: 06-07h 0080h Read Only, Read/WriteClear 16 bits PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0’s PCI Interface. Bit 14 is Read/Write clear. All other bits are Read Only. Since GMCH/MCH Device #0 does not physically reside on PCI_A many of the bits are not implemented.
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Register Description R 3.9.5 RID – Revision Identification Register (Device #0) Address Offset: Default Value: Access: Size: 08h 02h Read Only 8 bits This register contains the revision number of the GMCH/MCH. These bits are Read Only; Writes to this register have no effect. Bit 7:0 Description Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification number for the GMCH/MCH. Intel 852GME = 02 Intel 852PM = 02 3.9.
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Register Description R 3.9.8 HDR – Header Type Register (Device #0) Address Offset: Default Value: Access: Size: 0Eh 80h Read Only 8 bits This register identifies the header layout of the configuration space. No physical register exists at this location. Bit 7:0 3.9.9 Description PCI Header (HDR): This field always returns 80 to indicate that Device #0 is a multifunction device.
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Register Description R 3.9.11 CAPPTR – Capabilities Pointer Register (Device #0) Address Offset: Default Value: Access: Size: 34h 00h Read Only 8 bits The CAPPTR provides the offset that is the pointer to the location of the first device capability in the capability list. Bit Description 7:0 3.9.12 Pointer to the offset of the first capability ID register block: In this case there are no capabilities therefore these bits are hardwired to 00h to indicate the end of the capability-linked list.
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Register Description R 3.9.13 HPLLCC – HPLL Clock Control Register (Device #0) Address Offset: Default Value: Access: Size: C0–C1h 00h Read Only 16 bits Bit Description 15:11 Reserved 10 HPLL VCO Change Sequence Initiate Bit: Software must Write a 0 to clear this bit and then Write a 1 to initiate sequence again. 9 Hphase Reset Bit: 1 = Assert 0 = Deassert (default) 8:2 Reserved 1:0 HPLL Clock Control: See the following tables below Table 34.
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Register Description R 3.10 PCI to AGP Configuration Registers (Device #1, Function #0) Table 35.
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Register Description R Register Name 3.10.1 Register Symbol Register Start Register End Default Value Access Bridge Control Register BCTRL1 3E 3E 00h RO,R/W Error Command Register ERRCMD1 40 40 00h RO,R/W VID1 - Vendor Identification (Device #1) Address Offset: Default Value: Access: Size: 00h 8086h Read Only 16 bits The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identifies any PCI device.
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Register Description R 3.10.3 PCICMD1 - PCI Command Register (Device #1) Address Offset: Default Value: Access: Size: 04h 0000h Read Only, Read/Write 16 bits Bit Description 15:9 Reserved 8 SERR Message Enable (SERRE): This bit is a global enable bit for Device #1 SERR messaging. The GMCH/MCH communicates the SERR# condition by sending an SERR message to the ICH4-M.
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Register Description R 3.10.4 PCISTS1 - PCI Status Register (Device #1) Address Offset: Default Value: Access: Size: 06h 00A0h Read Only, Read/Write Clear 16 bits PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with the primary side of the “virtual” PCI to PCI bridge embedded within the GMCH/MCH. Bit 3.10.
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Register Description R 3.10.6 SUBC1 - Sub-Class Code (Device #1) Address Offset: Default Value: Access: Size: 0Ah 04h Read Only 8 bits This register contains the Sub-Class Code for the GMCH/MCH Device #1. This code is 04h indicating a PCI-to-PCI bridge device. Bit 7:0 3.10.7 Description Sub-Class Code (SUBC): This is an 8-bit value that indicates the category of Bridge into which the Device #1 of the GMCH/MCH falls. The code is 04h indicating a PCI to PCI bridge.
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Register Description R 3.10.9 PBUSN1 - Primary Bus Number (Device #1) Address Offset: Default Value: Access: Size: 18h 00h Read Only 8 bits This register identifies that “virtual” PCI to PCI bridge is connected to bus #0. Bit 7:0 3.10.10 Description Primary Bus Number (BUSN): Configuration software typically programs this field with the number of the bus on the primary side of the bridge. Since Device #1 is an internal device and its primary bus is always 0.
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Register Description R 3.10.11 SUBUSN1 - Subordinate Bus Number (Device #1) Address Offset: Default Value: Access: Size: 1Ah 00h Read/Write 8 bits This register identifies the subordinate bus (if any) that resides at the level below PCI_B/AGP. This number is programmed by the PCI configuration software to allow mapping of configuration cycles to PCI_B/AGP. Bit 7:0 3.10.
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Register Description R 3.10.13 IOBASE1 - I/O Base Address Register (Device #1) Address Offset: Default Value: Access: Size: 1Ch F0h Read Only, Read/Write 8 bits This register controls the CPU to PCI_B/AGP I/O access routing based on the following formula: IO_BASE=< address =
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Register Description R 3.10.15 SSTS1 - Secondary Status Register (Device #1) Address Offset: Default Value: Access: Size: 1Eh 02A0h Read Only, Read/Write Clear 16 bits SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with a secondary side (i.e. PCI_B/AGP side) of the “virtual” PCI to PCI bridge embedded within GMCH/MCH.
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Register Description R 3.10.16 MBASE1 - Memory Base Address Register (Device #1) Address Offset: Default Value: Access: Size: 20h FFF0h Read Only, Read/Write 16 bits This register controls the CPU to PCI_B non-prefetchable memory access routing based on the following formula: MEMORY_BASE=< address =
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Register Description R 3.10.17 MLIMIT1 - Memory Limit Address Register (Device #1) Address Offset: Default Value: Access: Size: 22h 0000h Read Only, Read/Write 16 bits This register controls the CPU to PCI_B non-prefetchable memory access routing based on the following formula: MEMORY_BASE=< address =
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Register Description R 3.10.18 PMBASE1 - Prefetchable Memory Base Address Reg (Device #1) Address Offset: Default Value: Access: Size: 24h FFF0h Read Only, Read/Write 16 bits This register controls the CPU to PCI_B prefetchable memory accesses routing based on the following formula: PREFETCHABLE_MEMORY_BASE=< address =
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Register Description R 3.10.19 PMLIMIT1 - Prefetchable Memory Limit Address Reg (Device #1) Address Offset: Default Value: Access: Size: 26h 0000h Read Only, Read/Write 16 bits This register controls the CPU to PCI_B prefetchable memory accesses routing based on the following formula: PREFETCHABLE_MEMORY_BASE=< address =
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Register Description R 3.10.20 BCTRL - Bridge Control Register (Device #1) Address Offset: Default Value: Access: Size: 3Eh 00h Read Only, Read/Write 8 bits This register provides extensions to the PCICMD1 register that are specific to PCI to PCI bridges. The BCTRL provides additional control for the secondary interface (i.e. PCI_B/AGP) as well as some bits that affect the overall behavior of the “virtual” PCI to PCI bridge embedded within GMCH/MCH, e.g. VGA compatible address ranges mapping.
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Register Description R Bit Description 2 ISA Enable (ISAEN): Modifies the response by the GMCH/MCH to an I/O access issued by the CPU that target ISA I/O addresses. This applies only to I/O addresses that are enabled by the IOBASE and IOLIMIT registers. When this bit is set to 1, GMCH/MCH will not forward to PCI_B/AGP any I/O transactions addressing the last 768 bytes in each 1-KB block even if the addresses are within the range defined by the IOBASE and IOLIMIT registers.
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Register Description R Intel® 852GME GMCH Integrated Graphics Device Registers (Device #2, Function #0) 3.11 This section contains the PCI configuration registers listed in order of ascending offset address. Device #2 incorporates Function #0. Note: C0F0 = Copy of Function #0 and U1F1 = Unique in Function #1. Table 36.
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Register Description R Register Name 3.11.
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Register Description R 3.11.3 PCICMD – PCI Command Register (Device #2) Address Offset: Default: Access: Size: 04−05h 0000h Read Only, Read/Write 16 bits This 16-bit register provides basic control over the IGD’s ability to respond to PCI cycles. The PCICMD register in the IGD disables the IGD PCI compliant master accesses to Main System memory. Bit Description 15:10 Reserved 9 Fast Back-to-Back (FB2B)⎯RO.
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Register Description R 3.11.4 PCISTS – PCI Status Register (Device #2) Address Offset: Default Value: Access: Size: 06−07h 0090h Read Only 16 bits PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the IGD. Bit 3.11.5 Description 15 Detected Parity Error (DPE): Since the IGD does not detect parity, this bit is always set to 0.
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Register Description R 3.11.6 CC – Class Code Register (Device #2) Address Offset: Default Value: Access: Size: 09−0Bh 030000h Read Only 24 bits This register contains the device programming interface information related to the Sub-Class code and Base Class code definition for the IGD. This register also contains the Base Class code and the function sub-class in relation to the Base Class code.
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Register Description R 3.11.9 HDR – Header Type Register (Device #2) Address Offset: Default Value: Access: Size: 0Eh 00h Read Only 8 bits This register contains the Header Type of the IGD. Bit 3.11.10 Description 7 Multi Function Status (MFunc): Indicates if the device is a multi-function device. 6:0 Header Code (H): This is a 7-bit value that indicates the Header code for the IGD. This code has the value 00h, indicating a type 0 configuration space format.
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Register Description R 3.11.11 MMADR – Memory Mapped Range Address Register (Device #2) Address Offset: Default Value: Access: Size: 14−17h 00000000h Read/Write, Read Only 32 bits This register requests allocation for the IGD registers and instruction ports. The allocation is for 512-kB and the base address is defined by bits [31:19]. Bit 3.11.12 Description 31:19 Memory Base Address⎯R/W: Set by the OS, these bits correspond to address signals [31:19].
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Register Description R 3.11.13 SVID – Subsystem Vendor Identification Register (Device #2) Address Offset: Default Value: Access: Size: 2C−2Dh 0000h Read/Write Once 16 bits Bit 15:0 3.11.14 Description Subsystem Vendor ID: This value is used to identify the vendor of the subsystem. This register should be programmed by BIOS during boot-up. Once written, this register becomes Read Only. This register can only be cleared by a reset.
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Register Description R 3.11.16 INTRLINE⎯Interrupt Line Register (Device #2) Address Offset: Default Value: Access: Size: Bit 7:0 3.11.17 INTRPIN⎯Interrupt Pin Register (Device #2) Bit 7:0 3Dh 01h Read Only 8 bits Description Interrupt Pin: As a single function device, the IGD specifies INTA# as its interrupt pin. 01h=INTA#. For Function #1, this register is set to 00h.
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Register Description R 3.11.19 MAXLAT – Maximum Latency Register (Device #2) Address Offset: Default Value: Access: Size: 3Fh 00h Read Only 8 bits Bit 7:0 3.11.20 Description Maximum Latency Value: Bits[7:0]=00h. The IGD has no specific requirements for how often it needs to access the PCI bus.
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Register Description R 3.11.21 PMCS – Power Management Control/Status Register (Device #2) Address Offset: Default Value: Access: Size: D4h−D5h 0000h Read/Write, Read Only 16 bits Bit Description 15 PME_Status ⎯RO: This bit is 0 to indicate that IGD does not support PME# generation from D3 (cold). 14:9 Reserved 8 PME_En⎯RO: This bit is 0 to indicate that PME# assertion from D3 (cold) is disabled.
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Register Description R 3.11.22 GCCC ⎯ GMCH Clock Control Register Address Offset: Default Value: Access: Size: F0–F1h 00 00h Read/Write 16 bits Bit Description 15:10 Reserved 9 Core Display Clock Gate Control (CD-Gate): 0 = Core Display Clock Trunk not Gated, Clock running to the Core. 1 = Core Display Clock Trunk Gated, Clock not running to the Core. 8 Core Render Clock Gate Control (CR-Gate): 0 = Core Render Clock Trunk not Gated, clock running to the core.
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System Address Map R 4 System Address Map A system based on the GMCH/MCH supports 4 GB of addressable system memory space and 64 kB+3 B of addressable I/O space. The I/O and system memory spaces are divided by system configuration software into regions. The system memory ranges are useful either as system memory or as specialized system memory, while the I/O regions are used solely to control the operation of devices in the system.
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System Address Map R Figure 7.
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System Address Map R Figure 8. Detailed View of the Intel® 852GME GMCH and Intel® 852PM MCH System Address Map 4.
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System Address Map R Table 37.
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System Address Map R IGD is not enabled. AGP cycles are allowed to master abort and hub interface writes are forwarded to AGP; hub interface reads are handled as invalid cycles. If IGD is enabled, all hub interface accesses are handled as invalid and AGP accesses are handled as invalid cycles. Monochrome Display Adapter (MDA) Range (0B0000h - 0B7FFFh) Legacy support requires the ability to have a second graphics controller (monochrome) in the system.
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System Address Map R 4.4 Main System Memory Address Range (0010_0000h to Top of Main Memory) The address range from 1-MB to the top of main system memory is mapped to main DDR SDRAM address range controlled by the GMCH/MCH. The GMCH/MCH will forward all accesses to addresses within this range to the DDR SDRAM unless a hole in this range is created using the fixed hole as controlled by the FDHC register. Accesses within this hole are forwarded to hub interface.
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System Address Map R 4.4.2.1 Extended SMRAM Address Range (HSEG and TSEG) The HSEG and TSEG SMM transaction address spaces reside in this extended system memory area. 4.4.2.2 HSEG SMM mode processor accesses to enabled HSEG are remapped to 000A0000h-000BFFFFh. NonSMM mode processor accesses to enabled HSEG are considered invalid are terminated immediately on the FSB. The exceptions to this rule are Non-SMM mode Write Back cycles that are re-mapped to SMM space to maintain cache coherency.
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System Address Map R 1. 2. The first exception is addresses decoded to the Graphics Memory range. One per function in device #2. The second exception is addresses decoded to the system memory mapped range of the Internal Graphics device. One per function in device #2. Both exception cases are forwarded to the Internal Graphics device. As an AGP configuration, there are two exceptions to this rule: 1.
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System Address Map R 4.4.2.8 AGP Memory Address Ranges The GMCH/MCH can be programmed to direct memory accesses to the AGP bus interface when addresses are within either of two ranges specified via registers in GMCH/MCH’s Device #1 configuration space. The first range is controlled via the Memory Base Register (MBASE) and Memory Limit Register (MLIMIT) registers. The second range is controlled via the Prefetchable Memory Base (PMBASE) and Prefetchable Memory Limit (PMLIMIT) registers.
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System Address Map R 4.4.3 System Management Mode (SMM) Memory Range The GMCH/MCH supports the use of main system memory as System Management RAM (SMM RAM) enabling the use of System Management mode. The GMCH/MCH supports three SMM options: Compatible SMRAM (C_SMRAM), High Segment (HSEG), and Top of Memory Segment (TSEG). System Management RAM space provides a system memory area that is available for the SMI handler’s and code and data storage.
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System Address Map R range. Note that the High DDR SDRAM space is the same as the Compatible Transaction Address space. Table 46 describes three unique address ranges: 1. Compatible Transaction Address (Adr C) 2. High Transaction Address (Adr H) 3. TSEG Transaction Address (Adr T) These abbreviations are used later. Table 39. SMM Space Transaction Handling SMM Space Enabled 4.4.3.
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System Address Map R 4.4.4 System Memory Shadowing Any block of system memory that can be designated as Read-Only or Write-Only can be “shadowed” into GMCH/MCH DDR SDRAM. Typically this is done to allow ROM code to execute more rapidly out of main DDR SDRAM. ROM is used as a Read-Only during the copy process while DDR SDRAM at the same time is designated Write-Only. After copying, the DDR SDRAM is designated Read-Only so that ROM is shadowed. CPU bus transactions are routed accordingly. 4.4.
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System Address Map R The GMCH/MCH positively decodes I/O accesses to AGP I/O address space as defined by the following equation: I/O_Base_Address ≤ CPU I/O Cycle Address ≤I/O_Limit_Address The effective size of the range is programmed by the plug-and-play configuration software and it depends on the size of I/O space claimed by the AGP device.
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System Address Map R 4.4.6.1.1 Hub Interface Accesses to GMCH/MCH that Cross Device Boundaries Hub interface accesses are limited to 256-bytes but have no restrictions on crossing address boundaries. A single hub interface request may therefore span device boundaries (AGP, DDR SDRAM) or cross from valid addresses to invalid addresses (or vise versa). The GMCH/MCH does not support transactions that cross device boundaries.
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System Address Map R If a cycle is outside of a valid main memory range then it will terminate as follows: Reads: Remap to memory address 0h, return data from address 0h, and set the IAAF error flag. Writes: Re-mapped to memory address 0h with BE’s de-asserted (effectively dropped “on the floor”) and set the IAAF error flag.
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System Address Map R 176 Datasheet
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Functional Description R 5 Functional Description 5.1 Host Interface Overview The processor system bus uses source synchronous transfers for the address and data signals. The address signals are double pumped and two addresses can be generated every bus clock. At 100 MHz bus frequency, the two address signals run at 200 MT/s for a maximum address queue rate of 50 M addresses/sec. The data is quad pumped and an entire 64 bits cache line can be transferred in two bus clocks.
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Functional Description R PCI bus instead of asserting a hardware signal to the IOxAPIC. The MSI may be directed to the IOxAPIC, which in turn generates an interrupt as an upstream hub interface Memory Write. Alternatively the MSI may be directed directly to the system bus. The target of an MSI is dependent on the address of the interrupt Memory Write. The GMCH forwards inbound hub interface Memory Writes to address 0FEEx_xxxxh, to the System Bus as “Interrupt Message Transactions”. 5.2.
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Functional Description R 5.3.2 Memory Organization and Configuration 5.3.2.1 Configuration Mechanism for SO-DIMMs Detection of the type of DDR SDRAM installed on the SO-DIMM is supported via Serial Presence Detect mechanism as defined in the JEDEC 200-pin SO- DIMM specification. Before any cycles to the system memory interface can be supported, the GMCH/MCH DDR SDRAM registers must be initialized. The GMCH/MCH must be configured for operation with the installed system memory types.
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Functional Description R The above table is only a subset of the defined SPD bytes on the SO-DIMMs. These bytes collectively provide enough data for programming the GMCH/MCH DDR SDRAM registers. 5.3.3 DDR SDRAM Performance Description The overall system memory performance is controlled by the DDR SDRAM timing register, pipelining depth used in GMCH/MCH, system memory speed grade and the type of DDR SDRAM used in the system.
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Functional Description R Figure 9. Intel® 852GME GMCH Graphics Block Diagram DDR/SDRAM Memory Control DAC Overlay Video Engine (MPEG2 Decode) AGP2.0 Instr./ Data Sprite 2D Engine Cursor 3D Engine Primary Display Setup/Transform Scan Conversion Texture Engine Raster Engine LVDS Cursor Alpha Blend/ Gamma/ CRC Cntl Mux Port DVOB DVOC Secondary Display Display C 2nd Overlay DDC A_gmch_blk High bandwidth access to data is provided through the system memory port.
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Functional Description R • Gouraud shading • Alpha-blending • Per Vertex and Per- Pixel fog • Z/W buffering These features are independently controlled via a set of 3D instructions. The 3D pipeline subsystem performs the 3D rendering acceleration. The main blocks of the pipeline are the Setup Engine, Scan Converter, Texture Pipeline, and Raster Pipeline.
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Functional Description R 5.4.2.5 Backface Culling As part of the setup, the GMCH can discard polygons from further processing, if they are either facing away from or towards the user’s viewpoint. This operation, referred to as “Back Face Culling” is accomplished based on the “clockwise” or “counter-clockwise” orientation of the vertices on a primitive. This can be enabled or disabled by the driver. 5.4.2.
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Functional Description R 5.4.2.10 Texture Chromakey Chromakey is a method for removing a specific color or range of colors from a texture map before it is applied to an object. For “nearest” texture filter modes, removing a color simply makes those portions of the object transparent (the previous contents of the back buffer show through). For “linear“ texture filtering modes, the texture filter is modified if only the non-nearest neighbor texels match the key (range).
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Functional Description R • Linear MIP Nearest (Bilinear MIP Mapping): This is used if many LODs are present. The nearest LOD is chosen and a weighted average of a 2x2 area of texels surrounding the desired pixel is used (four texels). This is also referred to as Bilinear MIP Mapping. • Nearest MIP Linear (Point MIP Mapping): This is used if many LODs are present. Two appropriate LODs are selected and within each LOD the texel with coordinates nearest to the desired pixel are selected.
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Functional Description R 5.4.2.15 Bump Mapping The GMCH only supports embossed and dot product bump mapping, not environment bump mapping. 5.4.3 Raster Engine The Raster Engine is where the color data such as fogging, specular RGB, texture map blending, etc. is processed. The final color of the pixel is calculated and the RGB value combined with the corresponding components resulting from the Texture Engine. These textured pixels are modified by the specular and fog parameters.
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Functional Description R 5.4.3.4 Color Dithering Color Dithering in the GMCH helps to hide color quantization errors for 16-bit color buffers. Color Dithering takes advantage of the human eye’s propensity to “average” the colors in a small area. Input color, alpha, and fog components are converted from 8-bit components to 5-bit or 6-bit component by dithering. Dithering is performed on blended textured pixels. In 32-bit mode, dithering is not performed. 5.4.3.
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Functional Description R The frame buffer of the GMCH contains at least two hardware buffers, the Front Buffer (display buffer) and the Back Buffer (rendering buffer). While the back buffer may actually coincide with (or be part of) the visible display surface, a separate (screen or window-sized) back buffer is typically used to permit double-buffered drawing.
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Functional Description R 5.4.4 GMCH 2D Engine The GMCH provides an extensive set of 2D instructions and 2D HW acceleration for block transfers of data (BLTs). The BLT engine provides the ability to copy a source block of data to a destination and perform operations (e.g., ROP1, ROP2, and ROP3) on the data using a pattern, and/or another destination. The Stretch BLT engine is used to move source data to a destination that need not be the same size, with source transparency.
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Functional Description R 5.4.5 GMCH Planes and Engines The GMCH display can be functionally delineated into Planes and Engines (Pipes and Ports). A plane consists of rectangular shaped image that has characteristics such as source, size, position, method, and format. These planes get attached to source surfaces, which are rectangular system memory surfaces with a similar set of characteristics. They are also associated with a particular destination pipe.
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Functional Description R 5.4.6.2 Popup Plane (Second Cursor) The popup plane is used for control functions in mobile applications. Only the hardware cursor has a higher Z-order precedence over the hardware icon. In standard modes (non VGA) either cursor A or cursor B can be used as a Popup Icon. For VGA modes, 32-bpp data format is not supported. 5.4.6.3 Popup Color Formats Source color data for the popup is in an indexed format.
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Functional Description R 5.4.7.5 Color Control Color control provides a method of changing the color characteristics of the pixel data. It is applied to the data while in YUV format and uses input parameters such as brightness, saturation, hue (tint) and contrast. This feature is supplied for the overlay only and works in YUV formats only. 5.4.7.6 Dynamic Bob and Weave Interlaced data that originates from a video camera creates two fields that are temporally offset by 1/60 of a second.
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Functional Description R 5.4.8.3 Sub-picture Support Sub-picture is used for two purposes: Subtitles for movie captions, which are superimposed on a main picture, and for menus to provide some visual operation environments for the user. DVD allows movie subtitles to be recorded as sub-pictures. On a DVD disc, it is called “Subtitle” because it has been prepared for storing captions.
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Functional Description R 5.5.2 Digital Display Interface 5.5.2.1 Dedicated LFP LVDS Interface The GMCH has a dedicated ANSI/TIA/EIA –644-1995 Specification compliant dual channel LFP LVDS interface that can support TFT panel resolutions up to UXGA with a maximum pixel format of 18-bpp, and with SSC supported frequency range from 25 MHz to 112 MHz (single channel/dual channel).
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Functional Description R • References and External Standards 5.5.2.2 LVDS Interface Signals LVDS for flat panel is compatible with the ANSI/TIA/EIA-644 specification. This is an electrical standard only defining driver output characteristics and receiver input characteristics. There are two LVDS transmitter channels (channel A and channel B) in the LVDS interface. Each channel consists of 4-data pairs and a clock pair.
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Functional Description R Figure 11. LVDS Clock and Data Relationship LVDS Clock Pair 1 1 1 0 0 0 1 1 1 LVDS Data Pair 7th data 1st data 2nd data 3rd data 4th data 5th data 6th data 7th data 1st data LVDS Clock and data 5.5.2.4 LVDS Pair States The LVDS pairs can be put into one of five states: powered down tri-state, powered down Zero Volts, common mode, send zeros, or active. When in the active state, several data formats are supported.
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Functional Description R 5.5.2.8 SSC Support The GMCH is designed to tolerate a 0.6%-2.5% down/center spread at a modulation rate range from 30-50 kHz triangle. By using an external SSC clock synthesizer to provide the 66 MHz reference clock into the GMCH Pipe B PLL, spectrally spread 7X, 3.5X, and 1X LVDS clocking is output from the GMCH Pipe B PLL. 5.5.2.
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Functional Description R Table 43. Display Configuration Space Name Panel Power Sequence Timing Parameters Spec Name T1+T2 Vdd On to LVDS Active From Min Max Units To 0.1 Vdd LVDS Active 0 60 ms LVDS Active Backlight on 200 Backlight Off LVDS off X X ms LVDS Off Start power off 0 50 ms Power Off Power On Sequence Start 400 X ms Panel Vdd must be on for a minimum time before the LVDS data stream is enabled.
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Functional Description R The digital display port consists of a digital data bus, VSYNC, HSYNC, and BLANK# signals. The data bus can operate in a 12-bit or 24-bit mode. Embedded sync information or HSYNC and VSYNC signals can optionally provide the basic timing information to the external device and the BLANK# signal indicates which clock cycles contain valid data. The BLANK# signal can be optionally selected to include the border area of the timing.
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Functional Description R GMCH/MCH Host Bridge Max AGP Command C/BE[3:0]# Encoding Cycle Destination Response as PCIx Target 0100 The hub interface Cycle goes to DRAM with BE’s inactive; does not go to the hub interface 0101 Main Memory High Priority Write 0101 The hub interface Cycle goes to DRAM with BE’s inactive; does not go to the hub interface Reserved 0110 N/A No Response Reserved 0111 N/A No Response Long Read 1000 Main Memory Low Priority Read The hub interface Complete lo
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Functional Description R 5.6.4 4X AGP Protocol In addition to the 1X and 2X AGP protocol, the GMCH/MCH supports 4X AGP read and write data transfers and 4X sideband address generation. The 4X operation is compliant with the AGP 2.0 specification. The GMCH/MCH indicates that it supports 4X data transfers through RATE[2] (bit 2) of the AGP Status Register.
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Functional Description R Table 45. Fast Write Initialization 5.6.4.2 FWEN DATA_RATE [2] DATA_RATE [1] DATA_RATE [0] GMCH =>AGP Master Write Protocol 0 X x x 1X 1 0 0 1 1X 1 0 1 0 2X Strobing 1 1 0 0 4X Strobing AGP FRAME# Transactions on AGP The GMCH/MCH accepts and generates AGP FRAME# transactions on the AGP bus. The GMCH/MCH guarantees that AGP FRAME# accesses to DRAM are kept coherent with the processor caches by generating snoops to the host bus.
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Functional Description R GMCH/MCH PCI Command C/BE[3:0]# Encoding Cycle Destination Response as A FRAME# Target Configuration Write 1011 N/A No Response Memory Read Multiple 1100 Main Memory Read 1100 The hub interface No Response Dual Address Cycle 1101 N/A No Response Memory Read Line 1110 Main Memory Read 1110 The hub interface No Response 1111 Main Memory Posts Data 1111 The hub interface No Response Memory Write and Invalidate NOTE: N/A refers to a function that is not
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Functional Description R All other accesses that do not correspond to this programmed address range are forwarded to the hub interface. • Exclusive Access. GMCH/MCH does not issue a locked cycle on the AGP bus on behalf of either the host or the hub interface. The hub interface and host locked transactions to AGP are initiated as unlocked transactions by the GMCH/MCH on the AGP bus. • Configuration Read and Write. Host Configuration cycles to AGP are forwarded as Type 1 Configuration Cycles.
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Functional Description R • The GMCH also reduces I/O power dynamically, by disabling sense amps on input buffers, as well as tri-stating output buffers when possible • Dynamic Clock Power Down reduces power in all modes of operation • Enhanced Intel SpeedStep technology • Flat Panel Power Sequencing 5.8 General Description of Supported CPU States C0 (Full On): This is the only state that runs software. All clocks are running, STPCLK is deasserted, and the processor core is active.
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Functional Description R • C2 Stop Clock. Clock to CPU still running. Clock stopped to CPU core. • C3 Deep Sleep. Clock to CPU stopped. • C4 Deeper Sleep. Same as C3 with reduced voltage on the CPU. System States: • G0/S0 Full On • G1/S1-M Power On Suspend (POS). System Context Preserved 5.10 • G1/S2 Not supported. • G1/S3 Suspend to RAM (STR). Power and context lost to chipset. • G1/S4 Suspend to Disk (STD). All power lost (except wakeup on ICH4-M) • G2/S5 Soft off. Total reboot.
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Functional Description R Additional External Thermal sensor’s outputs, for multiple sensors, can be wire-OR'ed together to allow signaling from multiple sensors located physically separately. Software can, if necessary, distinguish which SO-DIMM(s) is the source of the over-temp through the serial interface. However, since the SO-DIMM(s) will be located on the same system memory bus data lines, any GMCH/MCH-based Read Throttle will apply equally.
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Functional Description R 208 Datasheet
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Electrical Characteristics R 6 Electrical Characteristics 6.1 Absolute Maximum Ratings Table 48 lists the Intel 852GM/852GME/852GMV GMCH and Intel 852PM MCH maximum environmental stress ratings. Functional operation at the absolute maximum and minimum is neither implied nor guaranteed. Functional operating parameters are listed in the AC and DC tables. Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only.
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Electrical Characteristics R Symbol Parameter Min Max Unit VCCADAC 1.5 V DAC Supply Voltage with respect to VSS -0.3 1.65 V VCCDVO 1.5 V Supply Voltage with respect to VSS -0.3 1.65 V VCCDLVDS 1.5 V LVDS Digital power supply -0.3 1.65 V VCCTXLVDS 2.5 V LVDS Data/Clock Transmitter Supply Voltage with respect to VSS -0.3 3.25 V VCCALVDS 1.5 V LVDS Analog Supply voltage with respect to VSS -0.3 1.65 V VCCSM 2.
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Electrical Characteristics R 6.3 Power Characteristics Table 50. Power Characteristics Symbol Parameter Min Typ Max Unit Notes W 1 ® Intel 852GM GMCH Only TDPTyp (max performance) Thermal Design Power ~ 3.2 1.3 V Mobile Intel Pentium 4 processor AGTL+ Supply Current 0.80 A 1.05 V Mobile Intel Celeron processor AGTL+ Supply Current 0.69 A IVCCMax 1.2 V Core Supply Current 1.29 A IVCCHL 1.2 V Hub Interface Supply Current 0.09 A IVCCASM 1.
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Electrical Characteristics R Symbol IVCCSM Parameter Min Typ 2.5 V DDR SDRAM System Memory Data Buffer Supply Current (DDR333 SDRAM) ® Max Unit 2.00 A Notes ® Intel 852GM/852GME/852GMV GMCH and Intel 852PM MCH Common IVCCDLVDS 1.5 V LVDS (Digital) Supply Current 0.04 A IVCCALVDS 1.5 V LVDS (Analog) Supply Current 0.07 A IVCCTXLVDS 2.5 V LVDS (I/O) Supply Current 0.05 A IVCCDAC 1.5 V DAC Supply Current 0.07 A IVCC1_5_DVO 1.5 V DVO Supply Current 0.09 A IVCCGPIO 3.
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Electrical Characteristics R 6.4 Signal Groups The signal description includes the type of buffer used for the particular signal: Signal Description AGTL+ Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for complete details. The GMCH/MCH integrates AGTL+ termination resistors. AGTL+ signals are “inverted bus” style where a low voltage represents a logical 1. DVO/AGP DVO/AGP buffers (1.5 V tolerant) Hub Compatible to Hub Interface 1.
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Electrical Characteristics R Signal Group Signal Type Signals (g) Analog/Ref DVO Miscellaneous Signals GVREF, DVORCOMP Notes AGP Signal Groups (m1) AGP I/O AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, G_FRAME#, G_IRDY#, G_TRDY#, G_STOP#, G_DEVSEL#, G_AD[31:0], G_CBE[3:0]#, G_PAR, GST[2:0] (m2) AGP Input PIPE#, SBA[7:0], RBF#, WBF#, SBSTB, SBSTB#, G_REQ# (m3) AGP Output G_GNT# LVDS Signal Groups (h) LVDS LVDS Outputs IYAP[3:0], IYAM[3:0], IYBP[3:0], IYBM[3:0] (i) Analog LVDS Miscellaneous LIBG
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Electrical Characteristics R Signal Group Signal Type Signals (u) CMOS Clock Outputs SCK[5:0], SCK[5:0]# (w) 1.5 V Clock Inputs DPMS (x) DVO Clock Outputs DVOCCLK, DVOCCLK#, DVOBCLK, DVOBCLK# (z) CMOS Low Voltage Differential Inputs BCLK, BCLK# (a1) LVTTL Inputs DREFCLK, DREFSSCLK (b1) LVDS Clock Outputs ICLKAP, ICLKAM, ICLKBP, ICLKBM Notes I/O Buffer Supply Voltages/Grounds Datasheet (c1) AGTL+ Power Supply VTTLF (d1) 1.2/1.5 V Core VCC (e1) 1.2/1.
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Electrical Characteristics R 6.5 DC Characteristics Table 52. DC Characteristics Symbol Signal Group Parameter Min Nom Max Unit 1.14 1.2 1.26 V 1.2(battery) 1.43 V Notes ® Supply Voltages (Intel 852GM GMCH Only) VCC (d1) Core Voltage VTTLF (c1) Active Range(AGTL+ Power Supply) 1.17 1.3(normal) VCCHL (e1) HI I/O Supply Voltage 1.14 1.2 1.26 V VCCAGPLL VCCAHPLL VCCADPLLA VCCADPLLB (f1) PLL Supply Voltage 1.14 1.2 1.26 V VCCASM (g1) DDR I/O Supply Voltage 1.14 1.
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Electrical Characteristics R Symbol Signal Group Parameter Min Nom Max Unit VCCAGPLL VCCAHPLL VCCADPLLA VCCADPLLB (f1) PLL Supply Voltage 1.425 1.5 1.575 V VCCASM (g1) DDR I/O Supply Voltage 1.425 1.5 1.575 V ® Notes ® Supply Voltages (Intel 852GM/852GME/852GMV GMCH and Intel 852PM MCH Common) VCCSM (g1) DDR I/O Supply Voltage 2.375 2.5 2.625 V VCCDVO (h1) AGP/DVO I/O Voltage 1.425 1.5 1.575 V VCCDLVDS (k1) Digital LVDS Supply Voltage 1.425 1.5 1.
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Electrical Characteristics R Symbol Signal Group Parameter Min Nom Max Unit Notes Reference Voltages (mobile Celeron processor only HAVREF (d) Host Address and Reference Voltage (0.66 x 0.66 x VTTLF (0.66 x VTTLF)+ VTTLF) – 2% 2% V 2 HDVREF[2:0] (d) Host Data Reference Voltage (0.66 x 0.66 x VTTLF (0.66 x VTTLF)+ VTTLF) – 2% 2% V 2 HCCVREF (d) Host Common Clock (0.66 x 0.66 x VTTLF (0.66 x Voltage VTTLF)+ VTTLF) – 2% 2% V 2 (d) Host Compensation Reference Voltage (0.
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Electrical Characteristics R Symbol Signal Group Parameter Min ILEAK_H (a),(c) Host AGTL+ Input Leakage Current CPAD (a),(c) Host AGTL+ Input Capacitance 1 CPCKG (a),(c) Host AGTL+ Input Capacitance (common clock) 1 Nom Max Unit Notes 2 µA VOL
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Electrical Characteristics R Symbol Signal Group CPAD (a),(c) CPCKG (a),(c) Parameter Min Nom Max Unit Host AGTL+ Input Capacitance 1 1.1 1.3 pF Host AGTL+ Input Capacitance (common clock) 1 2 2.5 pF SMVREF _0 – 0.
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Electrical Characteristics R Symbol Signal Group Parameter Min ILEAK_A (m1), (m2) AGP Input Leakage Current CPAD (m1), (m2) AGP Input Capacitance 3 CPCKG (m1), (m2) AGP Input Capacitance 1 Nom Max Unit Notes ±10 µA 0
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Electrical Characteristics R Symbol Signal Group CPAD (l) CPCKG (l) Parameter Min Nom Max Unit Hub Interface Input Capacitance 2 3 4 pF Hub Interface Input Capacitance 1 2 3 pF 345 450 mV 50 mV 1.375 V 50 mV Notes LVDS Interface: Functional Operating Range (VCC=2.
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Electrical Characteristics R Symbol Signal Group CPAD (q) Parameter Input Capacitance Min Nom Max Unit 2.5 3.05 3.6 pF 3 pF Notes (CMOS Inputs) CPCKG (q) Input Capacitance (CMOS Inputs) 1 2 VIL (z) Input Low Voltage -0.15 0 0.660 0.710 0.850 V 0.25 0.35 0.55 V 1 1.1 1.2 pF 1 2 3 pF 0.
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Electrical Characteristics R 6.5.1.1 DAC DC Characteristics Table 53. DAC DC Characteristics: Functional Operating Range (VCCDAC = 1.5 V ±5%) Parameter DAC Resolution Max Luminance (full-scale) Min Typica l Max 8 0.665 Units Bits 0.700 0.770 Notes (1) V (1, 2, 4) white video level voltage Min Luminance 0.000 V (1, 3, 4) black video level voltage LSB Current 73.2 µA (4, 5) Integral Linearity (INL) Differential Linearity (DNL) 0 +2.0 LSB (1, 6) -1.0 +1.
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Testability R 7 Testability In the Intel 852GME GMCH and Intel 852PM MCH, testability for Automated Test Equipment (ATE) board level testing has been implemented as an XOR chain. An XOR-tree is a chain of XOR gates, each with one input pin connected to it. The XOR Chain test mode is used by product engineers during manufacturing and OEMs during board level connectivity tests.
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Testability R 7.2 XOR Chain Exclusion List Table 56 provides a list of pins that are not included in the XOR chains (excluding all VCC/VSS/VTT). Note: Connectivity column is used to identify what need to be driven on that particular pin during XOR chain test mode. Table 56. XOR Chains Exclusion List Item# IN/OUT Pin/VHDL I/O Type Voltage Connectivity 1 IN Y3 GCLKIN PLL CLK 3.3 0 2 - W1 HLVREF Analog 1/3 VCCHL 0.
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Testability R Item# 7.3 IN/OUT Ball Pin/VHDL I/O Type Voltage Connectivity 29 - Y22 HAVREF Analog 2/3 VTTLF 1.0 30 - H28 HYRCOMP Analog N/A N/A 31 - K28 HYSWING Analog N/A N/A 32 IN D28 RSTIN# CMOS 3.3 N/A 33 - AJ24 SMVREF_0 Analog 1/2 VCCSM 1.
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Testability R 19 INOUT M3 DVOBCCLKINT DVO 1.5 20 INOUT L2 RSVD N/A N/A 21 INOUT P7 MDDCCLK DVO 1.5 22 INOUT N6 MI2CDATA DVO 1.5 23 INOUT M6 MDVIDATA DVO 1.5 24 INOUT N7 MDVICLK DVO 1.5 25 INOUT L7 DVODETECT DVO 1.5 26 INOUT K7 MI2CCLK DVO 1.5 27 OUT B2 RSVD N/A N/A 28 IN B3 RSVD N/A N/A XOR Chain DVO 2 XOR Out 228 DVO IN/OUT Ball Pin/VHDL I/O Type Voltage OUT AD5 SMA[11] SSTL_2 2.5 1 INOUT L3 DVOCBLANK# DVO 1.
PAGE 229
Testability R 24 IN F5 ADDID[1] DVO 1.5 25 IN F6 ADDID[7] DVO 1.5 26 IN E2 ADDID[3] DVO 1.5 27 IN E5 ADDID[0] DVO 1.5 28 IN F3 RSVD N/A N/A 29 IN F2 RSVD N/A N/A 30 OUT C2 RSVD N/A N/A 31 IN E3 ADDID[2] DVO 1.5 32 OUT C3 GST[1] DVO 1.5 33 OUT C4 GST[0] DVO 1.5 34 IN G5 ADDID[4] DVO 1.5 35 IN G6 ADDID[6] DVO 1.5 36 IN D5 DPMS DVO 1.
PAGE 230
Testability R 21 INOUT C20 HD[46]# AGTL+ 1.5 22 INOUT C23 HD[35]# AGTL+ 1.5 23 INOUT B23 HD[43]# AGTL+ 1.5 24 INOUT B22 HD[42]# AGTL+ 1.5 25 INOUT B25 DINV[2]# AGTL+ 1.5 26 INOUT D22 HD[36]# AGTL+ 1.5 27 INOUT C24 HD[34]# AGTL+ 1.5 28 INOUT C21 HD[47]# AGTL+ 1.5 29 INOUT E21 HDSTBP[2]# AGTL+ 1.5 30 INOUT E22 HDSTBN[2]# AGTL+ 1.5 31 INOUT D24 HD[39]# AGTL+ 1.5 32 INOUT C25 HD[37]# AGTL+ 1.5 33 INOUT F21 HD[45]# AGTL+ 1.
PAGE 231
Testability R 12 INOUT C28 HD[25]# AGTL+ 1.5 13 INOUT E27 HD[20]# AGTL+ 1.5 14 INOUT F2 HD[17]# AGTL+ 1.5 15 INOUT D27 HD[23]# AGTL+ 1.5 16 INOUT G25 HD[21]# AGTL+ 1.5 17 INOUT F25 HD[16]# AGTL+ 1.5 18 INOUT H23 HD[19]# AGTL+ 1.5 19 INOUT F28 HD[22]# AGTL+ 1.5 20 INOUT K23 HD[11]# AGTL+ 1.5 21 INOUT J23 HD[14]# AGTL+ 1.5 22 INOUT H25 HD[10]# AGTL+ 1.5 23 INOUT G27 HD[12]# AGTL+ 1.5 24 INOUT K22 HD[0]# AGTL+ 1.
PAGE 232
Testability R 232 3 INOUT N27 HIT# AGTL+ 1.5 4 INOUT N28 HITM# AGTL+ 1.5 5 INOUT N25 BNR# AGTL+ 1.5 6 INOUT N24 DRDY# AGTL+ 1.5 7 IN P27 HLOCK# AGTL+ 1.5 8 INOUT M23 BREQ0# AGTL+ 1.5 9 OUT M25 HTRDY# AGTL+ 1.5 10 INOUT M26 DBSY# AGTL+ 1.5 11 INOUT L28 ADS# AGTL+ 1.5 12 INOUT R28 HREQ[0]# AGTL+ 1.5 13 INOUT P25 HREQ[1]# AGTL+ 1.5 14 INOUT T28 HA[5]# AGTL+ 1.5 15 INOUT R27 HA[6]# AGTL+ 1.5 16 INOUT R23 HREQ[2]# AGTL+ 1.
PAGE 233
Testability R 40 INOUT Y24 HA[17]# AGTL+ 1.5 41 INOUT AA27 HA[22]# AGTL+ 1.5 42 INOUT W23 HA[24]# AGTL+ 1.5 43 INOUT AB28 HA[31]# AGTL+ 1.5 44 INOUT AB27 HA[29]# AGTL+ 1.5 45 INOUT AA28 HA[27] AGTL+ 1.5 XOR Chain GPIO XOR Out IN/OUT Ball Pin I/O Type Voltage OUT AD7 SMA[7] SSTL_2 2.5 1 OUT G8 PANELBKLTCTL CMOS 3.3 2 OUT F8 PANELBKLTEN CMOS 3.3 3 OUT C6 LCLKCTLB CMOS 3.3 4 IN D6 EXTTS_0 CMOS 3.3 5 OUT F7 AGPBUSY# CMOS 3.
PAGE 234
Testability R 11 INOUT U3 HL[2] HL1.5 1.2 12 INOUT U7 HL[0] HL1.5 1.2 13 OUT T3 HL[8] HL1.5 1.2 XOR Chain LVDS XOR Out IN/OUT Ball Pin I/O Type Voltage OUT AD17 SMA[3] SSTL_2 2.5 1 INOUT F10 ICLKBP LVDS 1.5 2 INOUT E10 ICLKBM LVDS 1.5 3 INOUT G10 IYBP[3] LVDS 1.5 4 INOUT G11 IYBM[3] LVDS 1.5 5 INOUT G12 IYBP[0] LVDS 1.5 6 INOUT H12 IYBM[0] LVDS 1.5 7 INOUT E11 IYBP[1] LVDS 1.5 8 INOUT E12 IYBM[1] LVDS 1.
PAGE 235
Testability R 7 INOUT AH24 SDQS[6] SSTL_2 2.5 8 OUT AD25 SWE# SSTL_2 2.5 9 OUT AC18 SMA[0] SSTL_2 2.5 10 INOUT AH17 SDQS[4] SSTL_2 2.5 11 OUT AD19 SDM[4] SSTL_2 2.5 12 CLK AC26 SCK[1] SSTL_2 2.5 13 CLK AB23 SCK[4] SSTL_2 2.5 14 CLK AA3 SCK[5] SSTL_2 2.5 15 CLK AC2 SCK[3] SSTL_2 2.5 16 CLK AB2 SCK[0] SSTL_2 2.5 17 CLK AC3 SCK[2] SSTL_2 2.5 18 OUT AH15 SDM[8] SSTL_2 2.
PAGE 236
Testability R 236 7 INOUT AH25 SDQ[51] SSTL_2 2.5 8 INOUT AG25 SDQ[55] SSTL_2 2.5 9 INOUT AF25 SDQ[54] SSTL_2 2.5 10 INOUT AE24 SDQ[50] SSTL_2 2.5 11 INOUT AH23 SDQ[49] SSTL_2 2.5 12 INOUT AF23 SDQ[53] SSTL_2 2.5 13 INOUT AE23 SDQ[48] SSTL_2 2.5 14 INOUT AG23 SDQ[52] SSTL_2 2.5 15 INOUT AE21 SDQS[5] SSTL_2 2.5 16 OUT AD21 SDM[5] SSTL_2 2.5 17 OUT AD20 SBA[1] SSTL_2 2.5 18 OUT AD22 SBA[0] SSTL_2 2.5 19 OUT AC21 SRAS# SSTL_2 2.
PAGE 237
Testability R XOR Chain SM 3 XOR Out Datasheet DDR SDRAM IN/OUT Ball Pin I/O Type Voltage OUT AC22 SCS[2]# SSTL_2 2.5 1 OUT AC24 SCAS# SSTL_2 2.5 2 INOUT AG22 SDQ[47] SSTL_2 2.5 3 INOUT AH22 SDQ[43] SSTL_2 2.5 4 INOUT AF22 SDQ[42] SSTL_2 2.5 5 INOUT AG20 SDQ[41] SSTL_2 2.5 6 INOUT AF20 SDQ[44] SSTL_2 2.5 7 INOUT AH21 SDQ[46] SSTL_2 2.5 8 INOUT AH19 SDQ[45] SSTL_2 2.5 9 INOUT AH20 SDQ[40] SSTL_2 2.5 10 INOUT AH16 SDQ[32] SSTL_2 2.
PAGE 238
Testability R 7.4 33 INOUT AG8 SDQ[17] SSTL_2 2.5 34 INOUT AF7 SDQ[14] SSTL_2 2.5 35 INOUT AG7 SDQ[10] SSTL_2 2.5 36 INOUT AE8 SDQ[11] SSTL_2 2.5 37 INOUT AH6 SDQ[15] SSTL_2 2.5 38 INOUT AF5 SDQ[12] SSTL_2 2.5 39 INOUT AD6 SDQ[8] SSTL_2 2.5 40 INOUT AH4 SDQ[13] SSTL_2 2.5 41 INOUT AG5 SDQ[9] SSTL_2 2.5 42 INOUT AH2 SDQ[3] SSTL_2 2.5 43 INOUT AF4 SDQ[2] SSTL_2 2.5 44 INOUT AG4 SDQ[6] SSTL_2 2.5 45 INOUT AH3 SDQ[7] SSTL_2 2.
PAGE 239
Testability R Name Voltage Level Ball out VTTHF 1.5 A22,A24,H29,M29,V29 VTTLF 1.
PAGE 240
Testability R Table 59.
PAGE 241
Intel® 852GME GMCH and 852PM MCH Strap Pins R 8 Intel® 852GME GMCH and 852PM MCH Strap Pins 8.1 Strapping Configuration Table Table 60.
PAGE 242
Intel® 852GME GMCH and 852PM MCH Strap Pins R 242 Datasheet
PAGE 243
Ballout and Package Information R 9 Ballout and Package Information Figure 14.
PAGE 244
Ballout and Package Information R Table 61.
PAGE 245
Ballout and Package Information R Row Column Datasheet Signal Name Row Column Signal Name H 1 DVOCD[7] T 25 HA[4]# H 3 DVOCD[8] T 28 HA[5]# H 4 DVOCD[9] R 27 HA[6]# H 5 DVOCFLDSTL U 23 HA[7]# K 6 DVOCHSYNC U 24 HA[8]# L 5 DVOCVSYNC R 24 HA[9]# D 1 DVO_GRCOMP T 26 HADSTB[0]# D 6 EXTTS_0 AA 26 HADSTB[1]# Y 3 GCLKIN Y 22 HAVREF C 8 GREEN Y 28 HCCVREF D 8 GREEN# K 22 HD[0]# F 1 GVREF H 27 HD[1]# U 28 HA[10]# H 25 HD[10]# V 28
PAGE 246
Ballout and Package Information R Row Column 246 Signal Name Row Column Signal Name B 28 HD[31]# C 18 HD[63]# B 21 HD[32]# L 23 HD[7]# G 21 HD[33]# L 25 HD[8]# C 24 HD[34]# J 24 HD[9]# C 23 HD[35]# J 28 HDSTBN[0]# D 22 HD[36]# C 27 HDSTBN[1]# C 25 HD[37]# E 22 HDSTBN[2]# E 24 HD[38]# D 18 HDSTBN[3]# D 24 HD[39]# K 27 HDSTBP[0]# J 27 HD[4]# D 26 HDSTBP[1]# G 20 HD[40]# E 21 HDSTBP[2]# E 23 HD[41]# E 18 HDSTBP[3]# B 22 HD[42]# K
PAGE 247
Ballout and Package Information R Row Column Datasheet Signal Name Row Column Signal Name P 25 HREQ[1]# N 7 MDVICLK R 23 HREQ[2]# M 6 MDVIDATA R 25 HREQ[3]# K 7 MI2CCLK T 23 HREQ[4]# N 6 MI2CDATA H 10 HSYNC AJ 29 NC M 25 HTRDY# AH 29 NC B 20 HXRCOMP B 29 NC B 18 HXSWING A 29 NC H 28 HYRCOMP AJ 28 NC K 28 HYSWING A 28 NC D 14 ICLKAM AA 9 NC E 13 ICLKAP AJ 4 NC E 10 ICLKBM AJ 2 NC F 10 ICLKBP A 2 NC G 14 IYAM[0] AH 1
PAGE 248
Ballout and Package Information R Row Column 248 Signal Name Row Column Signal Name D 3 GRBF# AD 21 SDM[5] C 3 GST[1] AD 24 SDM[6] B 3 GREQ# AH 28 SDM[7] F 2 GSBSTB AH 15 SDM[8] D 2 GWBF# AF 2 SDQ[0] C 2 GST[2] AE 3 SDQ[1] B 2 GGNT# AG 7 SDQ[10] AD 22 SBA[0] AE 8 SDQ[11] AD 20 SBA[1] AF 5 SDQ[12] AC 24 SCAS# AH 4 SDQ[13] AB 2 SCK[0] AF 7 SDQ[14] AA 2 SCK[0]# AH 6 SDQ[15] AC 26 SCK[1] AF 8 SDQ[16] AB 25 SCK[1]# AG 8 SDQ[
PAGE 249
Ballout and Package Information R Row Column Datasheet Signal Name Row Column Signal Name AE 18 SDQ[37] AE 15 SDQ[69] AH 18 SDQ[38] AH 3 SDQ[7] AG 19 SDQ[39] AF 16 SDQ[70] AD 3 SDQ[4] AF 17 SDQ[71] AH 20 SDQ[40] AD 6 SDQ[8] AG 20 SDQ[41] AG 5 SDQ[9] AF 22 SDQ[42] AG 2 SDQS[0] AH 22 SDQ[43] AA 17 VCC AF 20 SDQ[44] T 17 VCC AH 19 SDQ[45] P 17 VCC AH 21 SDQ[46] U 16 VCC AG 22 SDQ[47] R 16 VCC AE 23 SDQ[48] N 16 VCC AH 23 SDQ[
PAGE 250
Ballout and Package Information R Row Column 250 Signal Name Row Column Signal Name G 13 VCCDLVDS AB 22 VCCSM P 9 VCCDVO AJ 21 VCCSM M 9 VCCDVO AF 21 VCCSM K 9 VCCDVO AB 20 VCCSM R 8 VCCDVO AF 18 VCCSM N 8 VCCDVO AB 18 VCCSM M 8 VCCDVO AJ 17 VCCSM L 8 VCCDVO AB 16 VCCSM J 8 VCCDVO AF 15 VCCSM H 7 VCCDVO AB 14 VCCSM E 6 VCCDVO AJ 13 VCCSM M 4 VCCDVO AA 13 VCCSM J 4 VCCDVO AF 12 VCCSM E 4 VCCDVO AB 12 VCCSM N 1 VCCDVO
PAGE 251
Ballout and Package Information R Row Column Datasheet Signal Name Row Column Signal Name AA 29 VSS P 24 VSS W 29 VSS M 24 VSS U 29 VSS K 24 VSS N 29 VSS H 24 VSS L 29 VSS F 24 VSS J 29 VSS B 24 VSS G 29 VSS AJ 23 VSS E 29 VSS AC 23 VSS C 29 VSS AA 23 VSS AE 28 VSS D 23 VSS AC 28 VSS A 23 VSS E 28 VSS AE 22 VSS D 28 VSS W 22 VSS AJ 27 VSS U 22 VSS AG 27 VSS R 22 VSS AC 27 VSS N 22 VSS F 27 VSS L 22 VSS
PAGE 252
Ballout and Package Information R Row Column 252 Signal Name Row Column Signal Name F 20 VSS P 14 VSS AE 19 VSS J 14 VSS AB 19 VSS AE 13 VSS H 19 VSS AB 13 VSS D 19 VSS U 13 VSS A 19 VSS R 13 VSS AJ 18 VSS N 13 VSS AG 18 VSS H 13 VSS AA 18 VSS F 13 VSS J 18 VSS D 13 VSS F 18 VSS A 13 VSS AC 17 VSS AJ 12 VSS AB 17 VSS AG 12 VSS U 17 VSS AA 12 VSS R 17 VSS J 12 VSS N 17 VSS AJ 11 VSS H 17 VSS AC 11 VSS
PAGE 253
Ballout and Package Information R Row Column Datasheet Signal Name Row Column Signal Name AC 8 VSS AE 1 VSS Y 8 VSS AA 1 VSS V 8 VSS U 1 VSS T 8 VSS L 1 VSS P 8 VSS G 1 VSS K 8 VSS C 1 VSS H 8 VSS B 8 VSSADAC AJ 7 VSS B 11 VSSALVDS AE 7 VSS J 9 VSYNC AA 7 VSS V 29 VTTHF R 7 VSS M 29 VTTHF M 7 VSS H 29 VTTHF J 7 VSS A 24 VTTHF G 7 VSS A 22 VTTHF E 7 VSS AB 29 VTTLF C 7 VSS Y 29 VTTLF AG 6 VSS K 29 VTTLF
PAGE 254
Ballout and Package Information R Row Column 254 Signal Name Row Column Signal Name M 5 DVOBD[11] H 25 HD[10]# R 6 DVOBD[2] K 23 HD[11]# R 4 DVOBD[3] G 27 HD[12]# P 6 DVOBD[4] K 26 HD[13]# P 5 DVOBD[5] J 23 HD[14]# N 5 DVOBD[6] H 26 HD[15]# P 2 DVOBD[7] F 25 HD[16]# N 2 DVOBD[8] F 26 HD[17]# N 3 DVOBD[9] B 27 HD[18]# M 2 DVOBFLDSTL H 23 HD[19]# T 6 DVOBHSYNC K 25 HD[2]# T 5 DVOBVSYNC E 27 HD[20]# L 3 DVOCBLANK# G 25 HD[21]#
PAGE 255
Ballout and Package Information R Row Column Datasheet Signal Name Row Column Signal Name J 21 HDVREF[1] AH 1 NC J 17 HDVREF[2] B 1 NC N 27 HIT# G 8 PANELBKLTCTL N 28 HITM# F 8 PANELBKLTEN U 7 HL[0] A 5 PANELVDDEN U 4 HL[1] U 2 PSWING V 4 HL[10] J 11 PWROK U 3 HL[2] A 7 RED V 3 HL[3] A 8 RED# W 2 HL[4] E 8 REFSET W 6 HL[5] N 23 RS[0]# V 6 HL[6] P 26 RS[1]# W 7 HL[7] M 27 RS[2]# T 3 HL[8] AD 28 RSTIN# V 5 HL[9] F 12
PAGE 256
Ballout and Package Information R Row Column 256 Signal Name Row Column Signal Name AG 10 SDQ[19] AD 14 SMA[1] AF 4 SDQ[2] AC 19 SMA[10] AH 7 SDQ[20] AD 5 SMA[11] AD 9 SDQ[21] AB 5 SMA[12] AF 10 SDQ[22] AD 13 SMA[2] AE 11 SDQ[23] AD 17 SMA[3] AH 10 SDQ[24] AD 11 SMA[4] AH 11 SDQ[25] AC 13 SMA[5] AG 13 SDQ[26] AD 8 SMA[6] AF 14 SDQ[27] AD 7 SMA[7] AG 11 SDQ[28] AC 6 SMA[8] AD 12 SDQ[29] AC 5 SMA[9] AH 2 SDQ[3] AD 16 SMAB[1] A
PAGE 257
Ballout and Package Information R Row Column Datasheet Signal Name Row Column Signal Name E 1 VCCDVO A 27 VSS A 4 VCCGPIO AJ 26 VSS A 3 VCCGPIO AB 26 VSS V 9 VCCHL W 26 VSS W 8 VCCHL U 26 VSS U 8 VCCHL R 26 VSS V 7 VCCHL N 26 VSS U 6 VCCHL L 26 VSS W 5 VCCHL J 26 VSS Y 1 VCCHL G 26 VSS V 1 VCCHL AE 25 VSS AJ 8 VCCQSM AA 25 VSS AJ 6 VCCQSM D 25 VSS AG 29 VCCSM A 25 VSS AF 29 VCCSM AG 24 VSS AC 29 VCCSM AA 24
PAGE 258
Ballout and Package Information R Row Column 258 Signal Name Row Column Signal Name A 17 VSS Y 5 VSS AE 16 VSS U 5 VSS AA 16 VSS B 5 VSS T 16 VSS AE 4 VSS P 16 VSS AC 4 VSS J 16 VSS AA 4 VSS F 16 VSS W 4 VSS AG 15 VSS T 4 VSS AB 15 VSS N 4 VSS U 15 VSS K 4 VSS R 15 VSS G 4 VSS N 15 VSS D 4 VSS H 15 VSS AJ 3 VSS D 15 VSS AG 3 VSS AC 14 VSS R 2 VSS AA 14 VSS AJ 1 VSS T 14 VSS AE 1 VSS P 14 VSS AA 1
PAGE 259
Ballout and Package Information R Row Column Datasheet Signal Name Row Column Signal Name A 20 VTTLF A 18 VTTLF J 19 VTTLF H 16 VTTLF H 18 VTTLF G 15 VTTLF 259
PAGE 260
Ballout and Package Information R Figure 15.
PAGE 261
Ballout and Package Information R Table 62.
PAGE 262
Ballout and Package Information R Row Column 262 Signal Name Row Column Signal Name V 26 HA[16]# F 25 HD[16]# Y 24 HA[17]# F 26 HD[17]# V 25 HA[18]# B 27 HD[18]# V 23 HA[19]# H 23 HD[19]# W 25 HA[20]# K 25 HD[2]# Y 25 HA[21]# E 27 HD[20]# AA 27 HA[22]# G 25 HD[21]# W 24 HA[23]# F 28 HD[22]# W 23 HA[24]# D 27 HD[23]# W 27 HA[25]# G 24 HD[24]# Y 27 HA[26]# C 28 HD[25]# AA 28 HA[27]# B 26 HD[26]# W 28 HA[28]# G 22 HD[27]# AB 2
PAGE 263
Ballout and Package Information R Row Column Datasheet Signal Name Row Column Signal Name G 18 HD[48]# U 4 HL[1] E 19 HD[49]# V 4 HL[10] G 28 HD[5]# U 3 HL[2] E 20 HD[50]# V 3 HL[3] G 17 HD[51]# W 2 HL[4] D 20 HD[52]# W 6 HL[5] F 19 HD[53]# V 6 HL[6] C 19 HD[54]# W 7 HL[7] C 17 HD[55]# T 3 HL[8] F 17 HD[56]# V 5 HL[9] B 19 HD[57]# P 27 HLOCK# G 16 HD[58]# T 2 HLRCOMP E 16 HD[59]# W 3 HLSTB L 27 HD[6]# V 2 HLSTB# C 16
PAGE 264
Ballout and Package Information R Row Column 264 Signal Name Row Column Signal Name E 14 IYAP[1] U 2 PSWING C 14 IYAP[2] J 11 PWROK B 13 IYAP[3] AC 16 RCVENIN# H 12 IYBM[0] AC 15 RCVENOUT E 12 IYBM[1] A 7 RED C 12 IYBM[2] A 8 RED# G 11 IYBM[3] E 8 REFSET G 12 IYBP[0] N 23 RS[0]# E 11 IYBP[1] P 26 RS[1]# C 11 IYBP[2] M 27 RS[2]# G 10 IYBP[3] AD 28 RSTIN# H 9 LCLKCTLA AA 22 RSVD C 6 LCLKCTLB L 3 DVOCBLANK# A 10 LIBG J 3 D
PAGE 265
Ballout and Package Information R Row Column Datasheet Signal Name Row Column Signal Name C 4 GST[0] AE 9 SDM[2] F 3 RSVD AH 12 SDM[3] D 3 RSVD AD 19 SDM[4] C 3 GST[1] AD 21 SDM[5] B 3 RSVD AD 24 SDM[6] F 2 RSVD AH 28 SDM[7] D 2 RSVD AH 15 SDM[8] C 2 RSVD AF 2 SDQ[0] B 2 RSVD AE 3 SDQ[1] D 7 RSVD AG 7 SDQ[10] AD 22 SBA[0] AE 8 SDQ[11] AD 20 SBA[1] AF 5 SDQ[12] AC 24 SCAS# AH 4 SDQ[13] AB 2 SCK[0] AF 7 SDQ[14] AA 2 SC
PAGE 266
Ballout and Package Information R Row Column 266 Signal Name Row Column Signal Name AF 19 SDQ[34] AE 17 SDQ[66] AE 20 SDQ[35] AG 16 SDQ[67] AD 18 SDQ[36] AH 14 SDQ[68] AE 18 SDQ[37] AE 15 SDQ[69] AH 18 SDQ[38] AH 3 SDQ[7] AG 19 SDQ[39] AF 16 SDQ[70] AD 3 SDQ[4] AF 17 SDQ[71] AH 20 SDQ[40] AD 6 SDQ[8] AG 20 SDQ[41] AG 5 SDQ[9] AF 22 SDQ[42] AG 2 SDQS[0] AH 22 SDQ[43] AH 5 SDQS[1] AF 20 SDQ[44] AH 8 SDQS[2] AH 19 SDQ[45] AE 12
PAGE 267
Ballout and Package Information R Row Column Datasheet Signal Name Row Column Signal Name AB 1 SMRCOMP J 13 VCCDLVDS AJ 24 SMVREF_0 G 13 VCCDLVDS AJ 19 SMVSWINGH P 9 VCCDVO AJ 22 SMVSWINGL M 9 VCCDVO AC 21 SRAS# K 9 VCCDVO AD 25 SWE# R 8 VCCDVO W 21 VCC N 8 VCCDVO AA 19 VCC M 8 VCCDVO AA 17 VCC L 8 VCCDVO T 17 VCC J 8 VCCDVO P 17 VCC H 7 VCCDVO U 16 VCC E 6 VCCDVO R 16 VCC M 4 VCCDVO N 16 VCC J 4 VCCDVO AA 15 VCC E
PAGE 268
Ballout and Package Information R Row Column 268 Signal Name Row Column Signal Name AF 24 VCCSM F 9 VCCTXLVDS AB 22 VCCSM AA 29 VSS AJ 21 VCCSM W 29 VSS AF 21 VCCSM U 29 VSS AB 20 VCCSM N 29 VSS AF 18 VCCSM L 29 VSS AB 18 VCCSM J 29 VSS AJ 17 VCCSM G 29 VSS AB 16 VCCSM E 29 VSS AF 15 VCCSM C 29 VSS AB 14 VCCSM AE 28 VSS AJ 13 VCCSM AC 28 VSS AA 13 VCCSM E 28 VSS AF 12 VCCSM D 28 VSS AB 12 VCCSM AJ 27 VSS AA 11
PAGE 269
Ballout and Package Information R Row Column Datasheet Signal Name Row Column Signal Name T 24 VSS J 20 VSS P 24 VSS F 20 VSS M 24 VSS AE 19 VSS K 24 VSS AB 19 VSS H 24 VSS H 19 VSS F 24 VSS D 19 VSS B 24 VSS A 19 VSS AJ 23 VSS AJ 18 VSS AC 23 VSS AG 18 VSS AA 23 VSS AA 18 VSS D 23 VSS J 18 VSS A 23 VSS F 18 VSS AE 22 VSS AC 17 VSS W 22 VSS AB 17 VSS U 22 VSS U 17 VSS R 22 VSS R 17 VSS N 22 VSS N 17 VS
PAGE 270
Ballout and Package Information R Row Column 270 Signal Name Row Column Signal Name T 14 VSS E 9 VSS P 14 VSS AC 8 VSS J 14 VSS Y 8 VSS AE 13 VSS V 8 VSS AB 13 VSS T 8 VSS U 13 VSS P 8 VSS R 13 VSS K 8 VSS N 13 VSS H 8 VSS H 13 VSS AJ 7 VSS F 13 VSS AE 7 VSS D 13 VSS AA 7 VSS A 13 VSS R 7 VSS AJ 12 VSS M 7 VSS AG 12 VSS J 7 VSS AA 12 VSS G 7 VSS J 12 VSS E 7 VSS AJ 11 VSS C 7 VSS AC 11 VSS AG 6 V
PAGE 271
Ballout and Package Information R Row Column Datasheet Signal Name Row Column Signal Name AJ 1 VSS N 5 RSVD AE 1 VSS P 2 RSVD AA 1 VSS N 2 RSVD U 1 VSS N 3 RSVD L 1 VSS M 2 RSVD G 1 VSS T 6 RSVD C 1 VSS T 5 RSVD B 8 VSSADAC L 7 DVODETECT B 11 VSSALVDS D 1 DVORCOMP J 9 VSYNC D 6 EXTTS_0 V 29 VTTHF Y 3 GCLKIN M 29 VTTHF C 8 GREEN H 29 VTTHF D 8 GREEN# A 24 VTTHF F 1 GVREF A 22 VTTHF U 28 HA[10]# AB 29 VTTLF V 2
PAGE 272
Ballout and Package Information R Row Column 272 Signal Name Row Column Signal Name L 24 HD[3]# P 25 HREQ[1]# G 23 HD[30]# R 23 HREQ[2]# B 28 HD[31]# R 25 HREQ[3]# B 21 HD[32]# T 23 HREQ[4]# G 21 HD[33]# H 10 HSYNC C 24 HD[34]# M 25 HTRDY# C 23 HD[35]# B 20 HXRCOMP D 22 HD[36]# B 18 HXSWING C 25 HD[37]# H 28 HYRCOMP E 24 HD[38]# K 28 HYSWING D 24 HD[39]# D 14 ICLKAM J 27 HD[4]# E 13 ICLKAP G 20 HD[40]# E 10 ICLKBM E 23 HD[
PAGE 273
Ballout and Package Information R Row Column Datasheet Signal Name Row Column Signal Name K 1 DVOCD[1] AH 9 SDQ[18] H 6 DVOCD[10] AG 10 SDQ[19] G 3 DVOCD[11] AF 4 SDQ[2] K 3 DVOCD[2] AH 7 SDQ[20] K 2 DVOCD[3] AD 9 SDQ[21] J 6 DVOCD[4] AF 10 SDQ[22] J 5 DVOCD[5] AE 11 SDQ[23] H 2 DVOCD[6] AH 10 SDQ[24] H 1 DVOCD[7] AH 11 SDQ[25] H 3 DVOCD[8] AG 13 SDQ[26] H 4 DVOCD[9] AF 14 SDQ[27] H 5 DVOCFLDSTL AG 11 SDQ[28] K 6 DVOCHSYNC AD
PAGE 274
Ballout and Package Information R Row Column 274 Signal Name Row Column Signal Name AG 8 SDQ[17] AH 27 SDQS[7] AH 9 SDQ[18] AD 15 SDQS[8] AG 10 SDQ[19] AC 18 SMA[0] AF 4 SDQ[2] AD 14 SMA[1] AH 7 SDQ[20] AC 19 SMA[10] AD 9 SDQ[21] AD 5 SMA[11] AF 10 SDQ[22] AB 5 SMA[12] AE 11 SDQ[23] AD 13 SMA[2] AH 10 SDQ[24] AD 17 SMA[3] AH 11 SDQ[25] AD 11 SMA[4] AG 13 SDQ[26] AC 13 SMA[5] AF 14 SDQ[27] AD 8 SMA[6] AG 11 SDQ[28] AD 7 SMA[7]
PAGE 275
Ballout and Package Information R Row Column Datasheet Signal Name Row Column Signal Name E 1 VCCDVO F 27 VSS A 4 VCCGPIO A 27 VSS A 3 VCCGPIO AJ 26 VSS V 9 VCCHL AB 26 VSS W 8 VCCHL W 26 VSS U 8 VCCHL U 26 VSS V 7 VCCHL R 26 VSS U 6 VCCHL N 26 VSS W 5 VCCHL L 26 VSS Y 1 VCCHL J 26 VSS V 1 VCCHL G 26 VSS AJ 8 VCCQSM AE 25 VSS AJ 6 VCCQSM AA 25 VSS AG 29 VCCSM D 25 VSS AF 29 VCCSM A 25 VSS AC 29 VCCSM AG 24 V
PAGE 276
Ballout and Package Information R Row Column 276 Signal Name Row Column Signal Name D 17 VSS Y 6 VSS A 17 VSS L 6 VSS AE 16 VSS Y 5 VSS AA 16 VSS U 5 VSS T 16 VSS B 5 VSS P 16 VSS AE 4 VSS J 16 VSS AC 4 VSS F 16 VSS AA 4 VSS AG 15 VSS W 4 VSS AB 15 VSS T 4 VSS U 15 VSS N 4 VSS R 15 VSS K 4 VSS N 15 VSS G 4 VSS H 15 VSS D 4 VSS D 15 VSS AJ 3 VSS AC 14 VSS AG 3 VSS AA 14 VSS R 2 VSS T 14 VSS AJ 1 V
PAGE 277
Ballout and Package Information R Row Column Datasheet Signal Name Row Column Signal Name A 20 VTTLF A 18 VTTLF J 19 VTTLF H 16 VTTLF H 18 VTTLF G 15 VTTLF 277
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Ballout and Package Information R 9.1 Package Mechanical Information The following figures provide details on the package information and dimensions of the Intel® 852GME GMCH and Intel 852PM MCH chipsets. The GMCH/MCH comes in a Micro-FCBGA package similar to the mobile processors. The package consists of a silicon die mounted face down on an organic substrate populated with solder balls on the bottom side. Capacitors may be placed in the area surrounding the die.
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Ballout and Package Information R Figure 17.