Intel® Celeron® D Processor 300Δ Sequence Datasheet – On 65 nm Process in the 775-Land Package March 2007 Document Number: 311826-005
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Contents 1 Introduction................................................................................................................. 9 1.1 Terminology ....................................................................................................... 9 1.1.1 Processor Packaging Terminology ............................................................. 10 1.2 References .......................................................................................................
5.2.5 5.2.6 TCONTROL and Fan Speed Reduction ...........................................................81 Thermal Diode........................................................................................81 6 Features ....................................................................................................................85 6.1 Power-On Configuration Options ..........................................................................85 6.2 Clock Control and Low Power States .................
Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Datasheet VCC Static and Transient Tolerance for 775_VR_CONFIG_05A and 775_VR_CONFIG_06 Processors .............................................................................................................. 21 VCC Overshoot Example Waveform ............................................................................. 22 Phase Lock Loop (PLL) Filter Requirements ..................................................................
Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 6 References ..............................................................................................................11 Voltage Identification Definition ..................................................................................15 Absolute Maximum and Minimum Ratings ....................................................................17 Voltage and Current Specifications....................
Revision History Rev No. -001 -002 Description • Initial release • Added 775_VR_CONFIG_06 Specifications Added Celeron D processor 360 specifications • Date May 2006 September 2006 • Added Celeron D processor 347 specifications -003 • Updated Table 16, “GLT+ Bus Voltage Definitions”. October 2006 • Updated VTT_SEL signal descrition in Table 25.
Intel® Celeron® D Processor 300 Sequence Features • Available at 3.66 GHz, 3.46 GHz, 3.33 GHz, 3.2 GHz, and 3.
Introduction 1 Introduction The Intel® Celeron® D processors 365, 360, 356, 352, and 347 are single-core desktop processors on the 65 nm process. The processor uses Flip-Chip Land Grid Array (FCLGA6) package technology, and plugs into the LGA775 socket. Note: In this document the Intel® Celeron® D processor 300 sequence on the 65 nm process is referred to as the “Celeron D processor” or simply “the processor.
Introduction 1.1.1 Processor Packaging Terminology Commonly used terms are explained here for clarification: • Intel® Celeron® D Processor 300 sequence on 65 nm process in the 775land Package— Processor in the FC-LGA6 package with a 512 KB L2 cache. • Processor — For this document, the term processor is the generic form of the Celeron D processor. • Keep-out zone — The area on or near the processor that system design can not use.
Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Table 1. References Document ® Celeron ® Pentium® Intel ® Location D Processor 300 Sequence Specification Update D Processor, Intel® Pentium® Processor Extreme Intel Edition, Intel® Pentium® 4 Processor and Intel® Core™2 Duo Extreme Processor Thermal and Mechanical Design Guidelines http://intel.com/design/ pentiumXE/designex/ 306830.
Introduction 12 Datasheet
Electrical Specifications 2 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided. 2.1 Power and Ground Lands The Celeron D processor has 226 VCC (power), 24 VTT and 273 VSS (ground) inputs for on-chip power distribution. All power lands must be connected to VCC, while all VSS lands must be connected to a system ground plane.
Electrical Specifications 2.2.2 VTT Decoupling Decoupling must be provided on the motherboard. Decoupling solutions must be sized to meet the expected load. To insure compliance with the specifications, various factors associated with the power delivery solution must be considered including regulator type, power plane and trace sizing, and component placement. A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors. 2.2.
Electrical Specifications Table 2. VID5 Voltage Identification Definition VID4 VID3 VID2 VID1 VID0 VID VID5 VID4 VID3 VID2 VID1 VID0 VID 0 0 1 0 1 0 0.8375 0 1 1 0 1 0 1.2125 1 0 1 0 0 1 0.8500 1 1 1 0 0 1 1.2250 0 0 1 0 0 1 0.8625 0 1 1 0 0 1 1.2375 1 0 1 0 0 0 0.8750 1 1 1 0 0 0 1.2500 0 0 1 0 0 0 0.8875 0 1 1 0 0 0 1.2625 1 0 0 1 1 1 0.9000 1 1 0 1 1 1 1.2750 0 0 0 1 1 1 0.9125 0 1 0 1 1 1 1.
Electrical Specifications 2.4 Reserved, Unused, and TESTHI Signals All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands.
Electrical Specifications 2.5 Voltage and Current Specification 2.5.1 Absolute Maximum and Minimum Ratings Table 3 specifies absolute maximum and minimum ratings. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected.
Electrical Specifications 2.5.2 Table 4. DC Voltage and Current Specification Voltage and Current Specifications Symbol VID Range Parameter VID Processor Number VCC 356 3.33 GHz 352 3.2 GHz 347 3.06 GHz Processor Number ICC VCC for 775_VR_CONFIG_05A VTT Max Unit Notes1,2 1.25 — 1.325 V 3 V 4, 5, 6 A 7 A 8,9 Refer to Table 5 and Figure 1 ICC for 775_VR_CONFIG_05A 3.33 GHz 352 3.2 GHz 100 347 3.06_GHz 100 Processor Number — — 100 ICC for 775_VR_CONFIG_06 365 3.
Electrical Specifications NOTES: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date. 2. Adherence to the voltage specifications for the processor are required to ensure reliable processor operation. 3. Each processor is programmed with a maximum valid voltage identification value (VID) that is set at manufacturing and can not be altered.
Electrical Specifications Table 5. VCC Static and Transient Tolerance for 775_VR_CONFIG_05A and 775_VR_CONFIG_06 Processors Voltage Deviation from VID Setting (V)1, ICC (A) Maximum Voltage 1.7 mΩ Typical Voltage 1.75 mΩ 2, 3, 4 Minimum Voltage 1.8 mΩ 0 0.000 -0.019 -0.038 5 -0.008 -0.027 -0.046 10 -0.016 -0.035 -0.055 15 -0.023 -0.043 -0.063 20 -0.031 -0.051 -0.071 25 -0.039 -0.059 -0.079 30 -0.047 -0.067 -0.088 35 -0.054 -0.075 -0.096 40 -0.062 -0.083 -0.
Electrical Specifications Figure 1. VCC Static and Transient Tolerance for 775_VR_CONFIG_05A and 775_VR_CONFIG_06 Processors Icc [A] 0 10 20 30 40 50 60 70 80 90 100 VID - 0.000 VID - 0.019 Vcc Maximum VID - 0.038 VID - 0.057 VID - 0.076 Vcc [V] VID - 0.095 Vcc Typical VID - 0.114 VID - 0.133 Vcc Minimum VID - 0.152 VID - 0.171 VID - 0.190 VID - 0.209 VID - 0.228 NOTES: 1.
Electrical Specifications Figure 2. VCC Overshoot Example Waveform Example Overshoot Waveform Voltage (V) VID + 0.050 VOS VID TOS Time TOS: Overshoot time above VID VOS: Overshoot above VID NOTES: 1. VOS is measured overshoot voltage. 2. TOS is measured time duration above VID. 2.5.4 Die Voltage Validation Overshoot events on processor must meet the specifications in Table 6 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored.
Electrical Specifications 2.6.1 FSB Signal Groups The front side bus signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers that use GTLREF[1:0] as a reference level. In this document, the term “GTL+ Input” refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output group as well as the GTL+ I/O group when driving.
Electrical Specifications Table 7. FSB Signal Groups (Sheet 2 of 2) Signal Group Signals1 Type TAP Output Synchronous to TCK TDO FSB Clock Clock BCLK[1:0], ITP_CLK[1:0]3 VCC, VTT, VCCA, VCCIOPLL, VID[5:0], VSS, VSSA, GTLREF[1:0], COMP[5:4,1:0], RESERVED, TESTHI[13:0], THERMDA, THERMDC, VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE, VSS_MB_REGULATION, BSEL[2:0], SKTOCC#, DBR#3, VTTPWRGD, BOOTSELECT, VTT_OUT_LEFT, VTT_OUT_RIGHT, VTT_SEL, LL_ID[1:0], MSID[1:0], FCx, IMPSEL Power/Other NOTES: 1.
Electrical Specifications 2.6.2 GTL+ Asynchronous Signals Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input buffers. All of these signals follow the same DC requirements as GTL+ signals; however, the outputs are not actively driven high (during a logical 0 to 1 transition) by the processor. These signals do not have setup or hold time specifications in relation to BCLK[1:0].
Electrical Specifications Table 11. GTL+ Asynchronous Signal Group DC Specifications Parameter Min Max Unit Notes1 VIL Input Low Voltage 0.0 VTT/2 – (0.10 * VTT) V 2, 3 VIH Input High Voltage VTT/2 + (0.10 * VTT) VTT V 4, 5, 6, 3 VOH Output High Voltage 0.90*VTT VTT V 7, 5, 6 IOL Output Low Current — VTT/ [(0.
Electrical Specifications 5. 0.24 V is defined at 20% of nominal VTT of 1.2 V. 6. The TAP signal group must meet the signal quality specifications. 7. The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load. 8. Leakage to VSS with land held at VTT. 9. Leakage to VTT with land held at 300 mV. Table 13. VTTPWRGD DC Specifications Symbol Table 14. Parameter Min Typ Max Unit VIL Input Low Voltage — — 0.
Electrical Specifications 2.6.3.1 GTL+ Front Side Bus Specifications In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 8 for details on which GTL+ signals do not include on-die termination. Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF. Table 16 lists the GTLREF specifications.
Electrical Specifications 2.7 Clock Specifications 2.7.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the Celeron D processor core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its default ratio during manufacturing. Refer to Table 17 for the Celeron D processor supported ratios.
Electrical Specifications 2.7.2 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Table 18 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency.
Electrical Specifications . Figure 3. Phase Lock Loop (PLL) Filter Requirements 0.2 dB 0 dB –0.5 dB Forbidden Zone Forbidden Zone –28 dB –34 dB DC 1 Hz Passband fpeak 1 MHz 66 MHz fcore High Frequency Band Filt S NOTES: 1. Diagram not to scale. 2. No specification for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz. 4. fcore represents the maximum core frequency supported by the platform.
Electrical Specifications 2.7.4 BCLK[1:0] Specifications Table 19. Front Side Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Notes1 VL Input Low Voltage -0.150 0.000 N/A V - VH Input High Voltage 0.660 0.700 0.850 V - VCROSS(abs) Absolute Crossing Point 0.250 N/A 0.550 V 2, 3 VCROSS(rel) Relative Crossing Point 0.250 + 0.5(VHAVG – 0.700) N/A 0.550 + 0.5(VHAVG – 0.700) V 4, 3, 5 ΔVCROSS Range of Crossing Points N/A N/A 0.
Package Mechanical Specifications 3 Package Mechanical Specifications The Celeron D processor is packaged in a Flip-Chip Land Grid Array (FC-LGA4) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications Figure 5.
Package Mechanical Specifications Figure 6.
Package Mechanical Specifications Figure 7.
Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 5 and Figure 6 for keep-out zones.
Package Mechanical Specifications 3.5 Package Insertion Specifications The Celeron D processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide. 3.6 Processor Mass Specification The typical mass of the Celeron D processor is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package. 3.
Package Mechanical Specifications 3.9 Processor Land Coordinates Figure 9 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. . Figure 9.
Package Mechanical Specifications 40 Datasheet
Land Listing and Signal Descriptions 4 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown in Figure 10 and Figure 11. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array (top view).
Land Listing and Signal Descriptions Figure 10.
Land Listing and Signal Descriptions Figure 11.
Land Listing and Signal Descriptions Table 23.Alphabetical Land Assignments Land Name 44 Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23.
Land Listing and Signal Descriptions Table 23.Alphabetical Land Assignments Land Name 46 Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23.Alphabetical Land Assignments Land Name TRST# Datasheet Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23.Alphabetical Land Assignments Land Name 48 Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23.Alphabetical Land Assignments Land Name Datasheet Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23.Alphabetical Land Assignments Land Name 50 Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23.Alphabetical Land Assignments Land Name Datasheet Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23.Alphabetical Land Assignments Land Name 52 Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23.Alphabetical Land Assignments Land Name Datasheet Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 24.Numerical Land Assignment 54 Table 24.
Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Land # Datasheet Land Name Signal Buffer Type C22 VSS C23 VCCIOPLL C24 C25 Table 24.
Land Listing and Signal Descriptions Table 24.Numerical Land Assignment 56 Table 24.
Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Datasheet Table 24.
Land Listing and Signal Descriptions Table 24.Numerical Land Assignment 58 Land # Land Name Signal Buffer Type N8 VCC N23 N24 Table 24.
Land Listing and Signal Descriptions Table 24.
Land Listing and Signal Descriptions Table 24.Numerical Land Assignment 60 Land # Land Name Signal Buffer Type AC7 VSS Table 24.
Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Datasheet Land # Land Name Signal Buffer Type AF25 VSS AF26 VSS AF27 AF28 Table 24.
Land Listing and Signal Descriptions Table 24.Numerical Land Assignment 62 Land # Land Name Signal Buffer Type AJ15 VCC AJ16 AJ17 Table 24.
Land Listing and Signal Descriptions Table 24.Numerical Land Assignment Land # Datasheet Land Name Table 24.
Land Listing and Signal Descriptions 4.2 Alphabetical Signals Reference Table 25. Signal Description (Sheet 1 of 9) Name A[35:3]# Type Input/ Output Description A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name BCLK[1:0] Type Input Description The differential pair BCLK (Bus Clock) determines the FSB frequency. All processor FSB agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description BSEL[2:0] Output The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the processor input clock frequency. Table 18 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name DBR# DBSY# DEFER# DP[3:0]# DRDY# Type Description Output DBR# (Debug Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description FERR#/PBE# Output FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name INIT# Type Input Description INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name MSID[1:0] Type Input Description MSID0 is used to indicate to the processor whether the platform supports 775_VR_CONFIG_05B processors. A 775_VR_CONFIG_05B processor will only boot if it’s MSID0 pin/land is electrically low. A 775_VR_CONFIG_05A processor will ignore this input. MSID1 must be electrically low for the processor to boot.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name RSP# Type Description Input RSP# (Response Parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect to the appropriate pins/lands of all processor FSB agents.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name THERMTRIP# Description Output In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 °C above the maximum TC. Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name VSS_MB_ REGULATION Type Description Output This land is provided as a voltage regulator feedback sense point for VSS. It is connected internally in the processor package to the sense point land V27 as described in the Voltage Regulator-Down (VRD) 10.1 Design Guide for Desktop Socket 775. VTT Miscellaneous voltage supply.
Land Listing and Signal Descriptions 74 Datasheet
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The Celeron D processor requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
Thermal Specifications and Design Considerations The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 26 instead of the maximum processor power consumption.
Thermal Specifications and Design Considerations Table 28. Figure 12. Thermal Profile for 775_VR_CONFIG_05A Processors Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power Maximum (W) Tc (°C) 0 44.3 22 50.7 44 57.1 66 63.4 2 44.9 24 51.3 46 57.6 68 64.0 4 45.5 26 51.8 48 58.2 70 64.6 6 46.0 28 52.4 50 58.8 72 65.2 8 46.6 30 53.0 52 59.4 74 65.8 10 47.2 32 53.6 54 60.0 76 66.3 12 47.8 34 54.2 56 60.5 78 66.
Thermal Specifications and Design Considerations Table 29. Figure 13. Thermal Profile for 775_VR_CONFIG_06 Processors Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 43.6 34 54.5 2 44.2 36 55.1 4 44.9 38 55.8 6 45.5 40 56.4 8 46.2 42 57.0 10 46.8 44 57.7 12 47.4 46 58.3 14 48.1 48 59.0 16 48.7 50 59.6 18 49.4 52 60.2 20 50.0 54 60.9 22 50.6 56 61.5 24 51.3 58 62.2 26 51.9 60 62.8 28 52.6 62 63.4 30 53.2 64 64.1 32 53.8 65 64.
Thermal Specifications and Design Considerations 5.1.2 Thermal Metrology The maximum and minimum case temperatures (TC) for the Celeron D processor is specified in Table 26. This temperature specification is meant to help ensure proper operation of the processor. Figure 14 illustrates where Intel recommends TC thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2).
Thermal Specifications and Design Considerations periods of TCC activation is expected to be so minor that it would be immeasurable. An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a TC that exceeds the specified maximum temperature and may affect the long-term reliability of the processor.
Thermal Specifications and Design Considerations 5.2.3 PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.
Thermal Specifications and Design Considerations temperature. Transistor Model parameters (Table 31) have been added to support thermal sensors that use the transistor equation method. The Transistor Model may provide more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits. This thermal "diode" is separate from the Thermal Monitor's thermal sensor and cannot be used to predict the behavior of the Thermal Monitor. Table 30.
Thermal Specifications and Design Considerations When calculating a temperature based on thermal diode measurements, a number of parameters must be either measured or assumed. Most devices measure the diode ideality and assume a series resistance and ideality trim value, although some are capable of also measuring the series resistance. Calculating the temperature is then accomplished using the equations listed under Table 30.
Thermal Specifications and Design Considerations 84 Datasheet
Features 6 Features 6.1 Power-On Configuration Options Several configuration options can be configured by hardware. The Celeron D processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 34. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features Figure 15.
Features 6.2.2.1 HALT Powerdown State HALT is a low power state entered when all the logical processors have executed the HALT or MWAIT instructions. When one of the logical processors executes the HALT instruction, that logical processor is halted, however, the other processor continues normal operation. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself.
Features While in the Stop-Grant State, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop-Grant state, the processor will process a FSB snoop. 6.2.4 Enhanced HALT Snoop or HALT Snoop State, Stop Grant Snoop State The Enhanced HALT Snoop State is used in conjunction with the new Enhanced HALT state.
Boxed Processor Specifications 7 Boxed Processor Specifications The Celeron D processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The Boxed Celeron D processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed Celeron D processor.
Boxed Processor Specifications Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 17 (Side View), and Figure 18 (Top View). The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs. Airspace requirements are shown in Figure 22 and Figure 23.
Boxed Processor Specifications Figure 19. 7.1.2 Space Requirements for the Boxed Processor (Overall View) Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 550 grams. See Chapter 5 and the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for details on the processor weight and heatsink requirements. 7.1.
Boxed Processor Specifications Note: The boxed processor’s fan heatsink requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control. The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power header identification and location should be documented in the platform documentation, or on the system board itself. Figure 21 shows the location of the fan power connector relative to the processor socket.
Boxed Processor Specifications Figure 21. Baseboard Power Header Placement Relative to Processor Socket B R110 [4.33] C 7.3 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution utilized by the boxed processor. 7.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink.
Boxed Processor Specifications Figure 22. Boxed Processor Fan Heatsink Airspace Keep-out Requirements (Side 1 View) Figure 23.
Debug Tools Specifications 8 Debug Tools Specifications 8.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Celeron D processor systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor.
