Intel® Pentium® D Processor 900Δ Sequence and Intel® Pentium® Processor Extreme Edition 955Δ, 965Δ Datasheet – On 65 nm Process in the 775-land LGA Package supporting Intel® 64 Architecture and supporting Intel® Virtualization Technology± January 2007 Document Number: 310306-007
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ContentsContents 1 Introduction ............................................................................................................ 11 1.1 Terminology ..................................................................................................... 12 1.1.1 Processor Packaging Terminology ............................................................. 12 1.2 References .......................................................................................................
5.2.5 5.2.6 5.2.7 THERMTRIP# Signal ................................................................................88 TCONTROL and Fan Speed Reduction ...........................................................88 Thermal Diode........................................................................................88 6 Features ..................................................................................................................91 6.1 Power-On Configuration Options ............................
Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Datasheet VCC Static and Transient Tolerance for 775_VR_CONFIG_05A (Mainstream) and 775_VR_CONFIG_05B (Performance) Processors .......................................................... 24 VCC Overshoot Example Waveform ............................................................................. 25 Phase Lock Loop (PLL) Filter Requirements ..................................................................
Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 6 References ..............................................................................................................13 Voltage Identification Definition ..................................................................................17 Absolute Maximum and Minimum Ratings ....................................................................19 Voltage and Current Specifications.................
Revision HistoryRevision History Revision Number -001 Description • Date Initial release December 2005 -002 • Added specifications for Intel Pentium D processors 950, 940, 930, and 920 January 2006 -003 • • • Added specifications for Intel Pentium processor Extreme Edition 965 Updated Table 2-13. Updated Figures 3-5 and 3-6. March 2006 • Added specifications for Intel Pentium D processor 960 May 2006 • • July 2006 • Added specifications for Intel Pentium D processors 945 and 915.
Datasheet
Intel® Pentium® D Processor 900 Sequence and Intel® Pentium® Processor Extreme Edition 955, 965 Features • Available at 3.46 GHz and 3.73 GHz (Intel Pentium processor Extreme Edition 955, 965 only) • Available at 3.60 GHz, 3.40 GHz, 3.20 GHz, 3 GHz, and 2.
Datasheet
Introduction 1 Introduction The Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor Extreme Edition 955, 965 are Intel’s first desktop dual-core products on the 65 nm process. The processors use Flip-Chip Land Grid Array (FC-LGA6) package technology, and plug into the LGA775 socket.
Introduction The Intel Pentium D processor 900 sequence supports Enhanced Intel® SpeedStep® technology that allows trade-offs to be made between performance and power consumptions. This may lower average power consumption (in conjunction with OS support). The Pentium D processors 960, 950, 940, 930, and 920, and the Pentium processor Extreme Edition 955, 965 support Intel® Virtualization Technology.
Introduction • Intel® 975X Express chipset — Chipset that supports DDR2 memory technology for the processor. • Processor core — Processor core die with integrated L2 cache. • LGA775 socket — The processor mates with the system board through a surface mount, 775-land, LGA socket. • Integrated heat spreader (IHS) —A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface.
Introduction Table 1. References Document Location Intel® 64 and IA-32 Intel Architecture Software Developer's Manual Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A-M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide http://www.intel.
Electrical Specifications 2 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided. 2.1 Power and Ground Lands The processor has 226 VCC (power), 24 VTT and 273 VSS (ground) inputs for on-chip power distribution. All power lands must be connected to VCC, while all VSS lands must be connected to a system ground plane.
Electrical Specifications 2.2.3 FSB Decoupling The processor integrates signal termination on the die. In addition, some of the high frequency capacitance required for the FSB is included on the processor package. However, additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation. 2.
Electrical Specifications Table 2. Voltage Identification Definition VID5 VID4 VID3 VID2 VID1 VID0 VID VID5 VID4 VID3 VID2 VID1 VID0 VID 0 0 1 0 1 0 0.8375 0 1 1 0 1 0 1.2125 1 0 1 0 0 1 0.8500 1 1 1 0 0 1 1.2250 0 0 1 0 0 1 0.8625 0 1 1 0 0 1 1.2375 1 0 1 0 0 0 0.8750 1 1 1 0 0 0 1.2500 0 0 1 0 0 0 0.8875 0 1 1 0 0 0 1.2625 1 0 0 1 1 1 0.9000 1 1 0 1 1 1 1.2750 0 0 0 1 1 1 0.9125 0 1 0 1 1 1 1.
Electrical Specifications 2.4 Reserved, Unused, and TESTHI Signals All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands.
Electrical Specifications 2.5 Voltage and Current Specification 2.5.1 Absolute Maximum and Minimum Ratings Table 3 specifies absolute maximum and minimum ratings. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected.
Electrical Specifications 2.5.2 DC Voltage and Current Specification Table 4. Voltage and Current Specifications Symbol VID Range Processor number VCC 20 Min Typ Max VID 1.200 - 1.3375 3.73 GHz Extreme Edition 955 3.46 GHz 960 3.60 GHz 950 3.40 GHz 940 Processor number 3.20 GHz VCC for 775_VR_CONFIG_05A (Mainstream) 960 3.60 GHz 950/945 3.40 GHz 940/935 3.20 GHz 930/925 3.00 GHz 920/915 2.
Electrical Specifications Table 4. Voltage and Current Specifications Symbol Parameter Processor number ICC_RESET Datasheet Typ Max — — 125 3.73 GHz Extreme Edition 955 3.46 GHz 125 960 3.60 GHz 125 950 3.40 GHz 125 940 3.20 GHz 125 Processor number ICC when PWRGOOD and RESET# are active for 775_VR_CONFIG_05A (Mainstream) — — 960 3.60 GHz 950/945 3.40 GHz 100 940/935 3.20 GHz 100 930/925 3.00 GHz 100 920/915 2.
Electrical Specifications Table 4. Voltage and Current Specifications Symbol Parameter Processor number IENHANCED_ AUTO_HALT ITCC VTT Min Typ Max — — 68 2 ICC Enhanced Auto Halt for 775_VR_CONFIG_05B (Performance) Extreme Edition 965 3.73 GHz Extreme Edition 955 3.46 GHz 960 3.60 GHz 60 950 3.40 GHz 60 940 3.20 GHz 60 Processor number Unit Notes1, 68 ICC Enhanced Auto Halt for 775_VR_CONFIG_05A (Mainstream) 960 3.60 GHz 950/945 3.40 GHz 940/935 3.20 GHz 48 930/925 3.
Electrical Specifications 15. This is maximum total current drawn from VTT plane by only the processor. This specification does not include the current coming from RTT (through the signal line). Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide For Desktop and Transportable LGA775 Socket to determine the total ITT drawn by the system. 16.This is a steady-state ITT current specification, which is applicable when both VTT and VCC are high. 17.
Electrical Specifications Figure 1. VCC Static and Transient Tolerance for 775_VR_CONFIG_05A (Mainstream) and 775_VR_CONFIG_05B (Performance) Processors Icc [A] 0 10 20 30 40 50 60 70 80 90 100 110 120 VID - 0.000 VID - 0.019 Vcc Maximum VID - 0.038 VID - 0.057 VID - 0.076 Vcc [V] VID - 0.095 VID - 0.114 Vcc Typical VID - 0.133 VID - 0.152 Vcc Minimum VID - 0.171 VID - 0.190 VID - 0.209 VID - 0.228 NOTES: 1.
Electrical Specifications Figure 2. VCC Overshoot Example Waveform Exam ple O vershoot W aveform Voltage (V) VID + 0.050 V OS VID T OS Tim e T O S : O vershoot tim e above VID V O S : O vershoot above VID NOTES: 1. VOS is measured overshoot voltage. 2. TOS is measured time duration above VID. 2.5.4 Die Voltage Validation Overshoot events on processor must meet the specifications in Table 6 when measured across the VCC_SENSE and VSS_SENSE lands.
Electrical Specifications 2.6.1 FSB Signal Groups The front side bus signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers that use GTLREF[1:0] as a reference level. In this document, the term “GTL+ Input” refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output group as well as the GTL+ I/O group when driving.
Electrical Specifications Table 7. FSB Signal Groups (Sheet 2 of 2) Signal Group Signals1 Type TAP Output Synchronous to TCK TDO FSB Clock Clock BCLK[1:0], ITP_CLK[1:0]2 VCC, VTT, VCCA, VCCIOPLL, VID[5:0], VSS, VSSA, GTLREF[1:0], COMP[7:6,5:4,3:2,1:0], RESERVED, TESTHI[13:0], THERMDA, THERMDC, VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE, VSS_MB_REGULATION, BSEL[2:0], SKTOCC#, DBR#2, VTTPWRGD, BOOTSELECT, VTT_OUT_LEFT, VTT_OUT_RIGHT, VTT_SEL, LL_ID[1:0], MSID[1:0], FCx, IMPSEL Power/Other NOTES: 1.
Electrical Specifications 2.6.2 GTL+ Asynchronous Signals Legacy input signals such as A20M#, IGNNE#, INIT#, PWRGOOD, SMI#, and STPCLK# use CMOS input buffers. All of these signals follow the same DC requirements as GTL+ signals; however, the outputs are not actively driven high (during a logical 0-to-1 transition) by the processor. These signals do not have setup or hold time specifications in relation to BCLK[1:0].
Electrical Specifications Table 11. GTL+ Asynchronous Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 VIL Input Low Voltage 0.0 VTT/2 – (0.10 * VTT) V 2, 3 VIH Input High Voltage VTT/2 + (0.10 * VTT) VTT V 4, 5, 6, 3 VOH Output High Voltage 0.90*VTT VTT V 7, 5, 6 IOL Output Low Current — VTT/ [(0.
Electrical Specifications Table 13. VTTPWRGD DC Specifications Symbol Table 14. Parameter Min Typ Max Unit VIL Input Low Voltage — — 0.3 V VIH Input High Voltage 0.9 — - V BSEL[2:0] and VID[5:0] DC Specifications Symbol RON Parameter Notes1 Max Unit 120 W 2 BSEL[2:], VID[5:0] Buffer On Resistance IOL Max Land Current 2.4 mA 2,3 IOH Output High Current 460 µA 2,3 VTOL Voltage Tolerance 1.05*VTT V 4 NOTES: 1. 2. 3. 4. Table 15.
Electrical Specifications 2.6.3.1 GTL+ Front Side Bus Specifications In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 8 for details on which GTL+ signals do not include on-die termination. Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF. Table 16 lists the GTLREF specifications.
Electrical Specifications 2.7 Clock Specifications 2.7.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its default ratio during manufacturing. Refer to Table 17 for the processor supported ratios.
Electrical Specifications Table 18. 2.7.3 BSEL[2:0] Frequency Table for BCLK[1:0] BSEL2 BSEL1 BSEL0 FSB Frequency L L L 266 MHz L L H RESERVED L H H RESERVED L H L 200 MHz H H L RESERVED H H H RESERVED H L H RESERVED H L L RESERVED Phase Lock Loop (PLL) and Filter VCCA and VCCIOPLL are power sources required by the PLL clock generators for the processor silicon. Since these PLLs are analog, they require low noise power supplies for minimum jitter.
Electrical Specifications . Figure 3. Phase Lock Loop (PLL) Filter Requirements 0.2 dB 0 dB –0.5 dB Forbidden Zone Forbidden Zone –28 dB –34 dB DC 1 Hz Passband fpeak 1 MHz 66 MHz fcore High Frequency Band NOTES: 1. Diagram not to scale. 2. No specification for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz. 4. fcore represents the maximum core frequency supported by the platform.
Electrical Specifications 2.7.4 BCLK[1:0] Specifications Table 19. Front Side Bus Differential BCLK Specifications Symbol Parameter VL Input Low Voltage VH Min Typ Max Unit Notes1 -0.150 0.000 N/A V - Input High Voltage 0.660 0.700 0.850 V - VCROSS(abs) Absolute Crossing Point 0.250 N/A 0.550 V 2, 3 VCROSS(rel) Relative Crossing Point 0.250 + 0.5(VHavg – 0.700) N/A 0.550 + 0.5(VHavg – 0.700) V 3, 4, 5 ΔVCROSS Range of Crossing Points N/A N/A 0.
Electrical Specifications 36 Datasheet
Package Mechanical Specifications 3 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications Figure 5.
Package Mechanical Specifications Figure 6.
Package Mechanical Specifications Figure 7.
Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 5 and Figure 6 for keep-out zones.
Package Mechanical Specifications 3.6 Processor Mass Specification The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package. 3.7 Processor Materials Table 22 lists some of the package components and associated materials. Table 22. 3.
Package Mechanical Specifications Figure 9. Processor Top-Side Markings Example (Intel® Pentium® Processor Extreme Edition 955, 965) Brand Processor Number/ S-Spec/ Country of Assy Frequency/L2 Cache/Bus/ 775_VR_CONFIG_05x FPO INTEL m © ‘05 XXXXXXXX 965 SLxxx [COO] 3.73GHZ/4M/1066/05B [FPO] e4 Unique Unit Identifier ATPO Serial # Pb-free 2LI Symbol 2-D Matrix Mark ATPO S/N 3.9 Processor Land Coordinates Figure 10 shows the top view of the processor land coordinates.
Package Mechanical Specifications . Figure 10.
Land Listing and Signal Descriptions 4 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown in Figure 11 and Figure 12. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array (top view).
Land Listing and Signal Descriptions Figure 11.
Land Listing and Signal Descriptions Figure 12.
Land Listing and Signal Descriptions Table 23. Land Name A10# 48 Alphabetical Land Assignments Land Signal Buffer # Type U6 Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Datasheet Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Datasheet Alphabetical Land Assignments Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23. Land Name 52 Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Datasheet Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name 54 Alphabetical Land Assignments Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Datasheet Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name 56 Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Datasheet Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Land # Land Name Signal Buffer Type A10 D08# A11 D09# A12 VSS A13 COMP0 A14 D50# A15 VSS A16 Table 24.
Land Listing and Signal Descriptions Table 24. 60 Numerical Land Assignment Land # Land Name AC4 RESERVED AC5 A25# AC6 VSS AC7 AC8 Signal Buffer Type Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Land # Land Name Signal Buffer Type AF29 VSS AF3 Table 24.
Land Listing and Signal Descriptions Table 24. 62 Numerical Land Assignment Land # Land Name Signal Buffer Type AJ12 VCC Table 24.
Land Listing and Signal Descriptions Table 24. Land # Land Name Signal Buffer Type AL23 VSS AL24 Table 24.
Land Listing and Signal Descriptions Table 24. 64 Numerical Land Assignment Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Land # Land Name D16 RESERVED D17 D49# D18 VSS D19 D2 Signal Buffer Type Table 24.
Land Listing and Signal Descriptions Table 24. 66 Numerical Land Assignment Table 24.
Land Listing and Signal Descriptions Table 24. Land # Land Name Signal Buffer Type J14 VCC J15 VCC J16 DP0# J17 DP3# J18 VCC Power/Other J19 VCC Power/Other J2 COMP4 Power/Other J20 VCC J21 VCC J22 Table 24.
Land Listing and Signal Descriptions Table 24. 68 Numerical Land Assignment Land # Land Name Signal Buffer Type M8 VCC Power/Other N1 PWRGOOD Power/Other N2 IGNNE# Asynch GTL+ N23 VCC N24 Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Land # Land Name Signal Buffer Type U28 VCC U29 VCC U3 AP1# Table 24.
Land Listing and Signal Descriptions 4.2 Alphabetical Signals Reference Table 25. Signal Description (Sheet 1 of 9) Name A[35:3]# Type Input/ Output Description A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name BCLK[1:0] Type Input Description The differential pair BCLK (Bus Clock) determines the FSB frequency. All processor FSB agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing VCROSS.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description BSEL[2:0] Output The BCLK[1:0] frequency select signals BSEL[2:0] are used to select the processor input clock frequency. Table 18 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name DBR# DBSY# DEFER# DP[3:0]# DRDY# Type Description Output DBR# (Debug Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name FERR#/PBE# Type Description Output FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name INIT# Type Input Description INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name MSID[1:0] Type Input Description MSID[1:0] (input) MSID0 is used to indicate to the processor whether the platform supports 775_VR_CONFIG_05B processors. A 775_VR_CONFIG_05B processor will only boot if its MSID0 pin is electrically low. A 775_VR_CONFIG_05A processor will ignore this input. MSID1 must be electrically low for the processor to boot.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name RSP# Type Description Input RSP# (Response Parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect to the appropriate pins/lands of all processor FSB agents.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description Output In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 15°C above the maximum TC. Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name VSS_SENSE VSS_MB_ REGULATION Type Output VSS_SENSE is an isolated low impedance connection to processor core VSS. It can be used to sense or measure ground near the silicon with little noise. Output This land is provided as a voltage regulator feedback sense point for VSS. It is connected internally in the processor package to the sense point land V27 as described in the Voltage Regulator-Down (VRD) 10.
Land Listing and Signal Descriptions 80 Datasheet
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The processor requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
Thermal Specifications and Design Considerations Pentium® Processor Extreme Edition, and Intel® Pentium® 4 Processor Thermal and Mechanical Design Guidelines and the Processor Power Characterization Methodology for the details of this methodology. The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods.
Thermal Specifications and Design Considerations Table 27. Figure 13. Thermal Profile for 775_VR_CONFIG_05B Processors (Performance) Power (W) Maximum TC (°C) Power (W) Maximum TC (°C) Power (W) Maximum TC (°C) Power (W) Maximum TC (°C) 0 43.9 34 50.4 68 56.8 102 63.3 2 44.3 36 50.7 70 57.2 104 63.7 4 44.7 38 51.1 72 57.6 106 64.0 6 45.0 40 51.5 74 58.0 108 64.4 8 45.4 42 51.9 76 58.3 110 64.8 10 45.8 44 52.3 78 58.7 112 65.2 12 46.2 46 52.
Thermal Specifications and Design Considerations Table 28. Figure 14. Thermal Profile for 775_VR_CONFIG_05A Processors (Mainstream) Power (W) Maximum TC (°C) Power (W) Maximum TC (°C) Power (W) Maximum TC (°C) 0 43.4 34 50.5 68 57.7 2 43.8 36 51.0 70 58.1 4 44.2 38 51.4 72 58.5 6 44.7 40 51.8 74 58.9 8 45.1 42 52.2 76 59.4 10 45.5 44 52.6 78 59.8 12 45.9 46 53.1 80 60.2 14 46.3 48 53.5 82 60.6 16 46.8 50 53.9 84 61.0 18 47.2 52 54.3 86 61.
Thermal Specifications and Design Considerations 5.1.2 Thermal Metrology The maximum and minimum case temperatures (TC) for the processor is specified in Table 26. This temperature specification is meant to help ensure proper operation of the processor. Figure 15 illustrates where Intel recommends TC thermal measurements should be made.
Thermal Specifications and Design Considerations periods of TCC activation is expected to be so minor that it would be immeasurable. An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a TC that exceeds the specified maximum temperature and may affect the long-term reliability of the processor.
Thermal Specifications and Design Considerations As a bi-directional signal, PROCHOT# allows for some protection of various components from over-temperature situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor (either core) has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components.
Thermal Specifications and Design Considerations 5.2.5 THERMTRIP# Signal Regardless of whether or not Thermal Monitor is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Table 25). At this point, the FSB signal THERMTRIP# will go active and stay active as described in Table 25.
Thermal Specifications and Design Considerations 5. The series resistance, RT, is provided to allow for a more accurate measurement of the junction temperature. RT, as defined, includes the lands of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. RT can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term.
Thermal Specifications and Design Considerations calculated. This Thermal Diode Offset value will be programmed into the new diode correction MSR and when added to the Thermal Diode Base value can be used to correct temperatures read by diode based temperature sensing devices. If the ntrim value used to calculate the Thermal Diode Offset differs from the ntrim value used in a temperature sensing device, the Terror(nf) may not be accurate.
Features 6 Features 6.1 Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, please refer to Table 33. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features Figure 16.
Features The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information. The system can generate a STPCLK# while the processor is in the HALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in HALT Power Down state, the processor will process bus snoops. 6.2.
Features 6.2.4 Enhanced HALT Snoop or HALT Snoop State, Stop Grant Snoop State The Enhanced HALT Snoop State is used in conjunction with the new Enhanced HALT state. If Enhanced HALT state is not enabled in the BIOS, the default Snoop State entered will be the HALT Snoop State. Refer to the following sections for details on HALT Snoop State, Grant Snoop State and Enhanced HALT Snoop State. 6.2.4.
Boxed Processor Specifications 7 Boxed Processor Specifications The Intel Pentium D processor 900 sequence and the Intel Pentium processor Extreme Edition 955, 965 will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution.
Boxed Processor Specifications Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 18 (Side View), and Figure 19 (Top View). The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs. Airspace requirements are shown in Figure 23 and Figure 24.
Boxed Processor Specifications Figure 20. Space Requirements for the Boxed Processor (Overall View) 7.1.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 550 grams. See Chapter 5 and the Intel® Pentium® D Processor, Intel® Pentium® Processor Extreme Edition, and Intel® Pentium® 4 Processor Thermal and Mechanical Design Guidelines for details on the processor weight and heatsink requirements. 7.1.
Boxed Processor Specifications The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power header identification and location should be documented in the platform documentation, or on the system board itself. Figure 22 shows the location of the fan power connector relative to the processor socket. The baseboard power header should be positioned within 4.33 inches from the center of the processor socket. Figure 21.
Boxed Processor Specifications Figure 22. Baseboard Power Header Placement Relative to Processor Socket B R110 [4.33] C 7.3 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. 7.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink.
Boxed Processor Specifications Figure 23. Boxed Processor Fan Heatsink Airspace Keep-out Requirements (Side 1 View) Figure 24.
Balanced Technology Extended (BTX) Boxed Processor Specifications 8 Balanced Technology Extended (BTX) Boxed Processor Specifications The Intel Pentium D processor 900 sequence and the Intel Pentium processor Extreme Edition 955, 965 will be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from largely standard components. The boxed processor will be supplied with a cooling solution known as the Thermal Module Assembly (TMA).
Balanced Technology Extended (BTX) Boxed Processor Specifications Figure 26. Mechanical Representation of the Boxed Processor with a Type II TMA NOTE: The duct, clip, heatsink and fan can differ from this drawing representation but the basic shape and size will remain the same. 8.1 Mechanical Specifications 8.1.1 Balanced Technology Extended (BTX) Type I and Type II Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed Intel processor TMA.
Balanced Technology Extended (BTX) Boxed Processor Specifications Figure 27. Requirements for the Balanced Technology Extended (BTX) Type I Keep-out Volumes NOTE: Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation.
Balanced Technology Extended (BTX) Boxed Processor Specifications Figure 28. Requirements for the Balanced Technology Extended (BTX) Type II Keep-out Volume NOTE: Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. 8.1.2 Boxed Processor Thermal Module Assembly Weight The boxed processor thermal module assembly for Type I BTX will not weigh more than 1200 grams.
Balanced Technology Extended (BTX) Boxed Processor Specifications See the Support and Retention Module (SRM) External Design Requirements Document, Balanced Technology Extended (BTX) System Design Guide, and the Intel® Pentium® D Processor, Intel® Pentium® Processor Extreme Edition, and Intel® Pentium® 4 Processor Thermal and Mechanical Design Guidelines for more detailed information regarding the support and retention module and chassis interface and keepout zones.
Balanced Technology Extended (BTX) Boxed Processor Specifications Note: The boxed processor’s TMA requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control. The power header on the baseboard must be positioned to allow the TMA power cable to reach it. The power header identification and location should be documented in the platform documentation, or on the system board itself.
Balanced Technology Extended (BTX) Boxed Processor Specifications Figure 31. Balanced Technology Extended (BTX) Mainboard Power Header Placement (Hatched Area) 8.3 Thermal Specifications This section describes the cooling requirements of the thermal module assembly solution used by the boxed processor. 8.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a TMA.
Balanced Technology Extended (BTX) Boxed Processor Specifications In addition, Type I TMA must be used with Type I chassis only and Type II TMA with Type II chassis only. Type I TMA will not fit in a Type II chassis due to the height difference. In the event a Type II TMA is installed in a Type I chassis, the gasket on the chassis will not seal against the Type II TMA and poor acoustic performance will occur as a result. 8.3.
Balanced Technology Extended (BTX) Boxed Processor Specifications Table 36. TMA Set Points for 3-wire operation of BTX Type I and Type II Boxed Processors Boxed Processor TMA Set Point (ºC) Boxed Processor Fan Speed Notes X ≤ 23 When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. Recommended maximum internal chassis temperature for nominal operating environment.
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Debug Tools Specifications 9 Debug Tools Specifications 9.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging processor systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor.
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