User's Manual
inter
+7
+5
+3
+1
TASKS
AND
STATE TRANSITIONS
o 7 o
INTEL RESERVED
+6
P 1 DPL I
01
0
10_L
B
11
I
TSS BASE
23
_'6
+4
TSS BASE,s_o
+2
TSS LIMIT o
15
o
• MUST
BE
SET
TO
0 FOR COMPATIBILITY WITH
THE
80386
Figure 8-2. TSS Descriptor
B
~
1 MEANS TASK IS BUSY
AND NOT AVAILABLE
G3010B
The P-bit (Present) flag indicates whether this descriptor contains currently valid information: 1 means
yes,
0
no.
A task switch that attempts to reference a not-present TSS causes a not-present exception
code identifying the task
state segment selector.
The descriptor privilege level
(DPL) controls use of the TSS
by
JMP
or CALL instructions.
By
the
same reasoning
as
that for call gates, DPL can prevent a program from calling the TSS and thereby
cause a task switch. Section 8.3 discusses privilege considerations during a task switch
in
greater detail.
Bit 4
is
always 0 since TSS
is
a control segment descriptor. Control segments cannot be accessed by
SS, DS,
or
ES. Any attempt to load those segment registers with a selector that refers to a control
segment causes general protection trap. This rule prevents the program from improperly changing the
contents of a control segment.
TSS descriptors can have
two
states: idle and busy. Bit 1 of the access byte distinguishes them. The
distinction
is
necessary since tasks are not re-entrant; a busy TSS may not be invoked.
8.3
TASK SWITCHING
A task switch may occur
in
one of four ways:
1.
The destination selector of a long
JMP
or
CALL instruction refers to a TSS descriptor. The offset
part!a!! of
thE>.
rl~~tination
address
is
ignored.
2.
An IRET instruction
is
executed when the
NT
bit
in
the flag word =
1.
The
new
task TSS
selector
is
in the back link field of the current TSS.
3.
The destination selector of a long
JMP
or CALL instruction refers to a task gate. The offset
portion of the destination address
is
ignored. The
new
task TSS selector
is
in
the gate. (See section
8.5
for more information
on
task gates.)
4.
An
interrupt occurs. This interrupt's vector refers to a task gate
in
the interrupt descriptor table.
The
new
task TSS selector
is
in the gate. See section 9.4 for more information
on
interrupt tasks.
8-4