User's Manual

INTERRUPTS AND EXCEPTIONS
Each IDT entry is a 4-word gate descriptor that contains a pointer to the handler. The three types of
gates permitted in the IDT are interrupt gates,
trap gates (discussed in section 9.3), and task gates
(discussed
in section 9.5). Interrupt and task gates process interrupts in the same task, while task gates
cause a task switch. Any other descriptor type
in the IDT will cause an exception if it is referenced by
an interrupt.
The IDT need not contain all 256 entries:
A 16-bit limit register allows less than the full number of
entries.
Unused entries may be signaled by placing a zero in the access rights byte. If an attempt is
made to access an entry outside the table limit, or if the wrong descriptor type is found; a general
protection fault occurs with an error code pushed on the .stack identifying the invalid interrupt vector
(see figure 9-2).
..
Exception error codes that tefer to an IDT entry can be identified by bit 1 of the error code that will
be set. Bit 0 of the error code is 1 if the interrupt was caused by an event external to the program
(Le., an external interrupt, a single step, a processor extension error, ora processor extension not present).
Interrupts
0-31 are reserved for use by InteL Some of the interrupts are used for instruction exceptions.
The IDT limit must be at least
255 (32X8-1) to accommodate the minimum number of interrupts.
The remaining 224 interrupts are available
to the user.
9.2 HARDWARE INITIATED INTERRUPTS
Hardware-initiated interrupts are· caused by some external event that activates either the INTR or
NMI input pins of the processor. Events that use the INTR input are classified as maskable interrupts.
Events that use the
NMI input are classified as non-maskable interrupts. .
All 224 user-defined interrupt sources share the INTR input, blJt each has the ability to use a separate
interrupt handler. An 8-bit vector supplied
by the interrupt controller identifies which interrupt is
being signaled. To read the interrupt id, the processor performs the interrupt acknowledge bus sequence.
Maskable interrupts (from the
INTR input) can be inhibited by software by setting the interrupt flag
bit (IF) to
0 in the flag word. The IF bit does not inhibit exceptions or interrupts caused by the INT
instruction. The IF bit also does· IiOt inhibit processor extension interrupts.
15·14 13 12.11 10 9 8: 7 ·6 5 4 3 ·2 1·; 0
0
0 0 0
o·
E
IDTVECTOR
0
1
X
T
1 An eve."! eXtern8~.~~ __ t~~ _pr~~_~~~_1
fiOIIUtf"U "1e11 ."~'CII"ILIUII v .•. , ...... , ..........
Interrupt, ,Bingle step, processor
extension' error)
o An exception occurred while
procesSing' an instruction at CS:IP
saved on stack
Figure 9-2. lOT Selector Error Code
9-2
G30108