User's Manual

INTERRUPTS AND EXCEPTIONS
The type of gate placed into the IDT for the interrupt vector will control whether other maskable
interrupts remain enabled or not during the servicing of that interrupt. The flag word that
was saved
on the stack reflects the maskable interrupt enable status of the processor prior to the interrupt. The
procedure servicing a maskable interrupt can also prevent further maskable interrupts during its work
by resetting the IF flag.
Non-maskable interrupts are caused
by the NMI input. They have a higher priority than the maskable
interrupts (meaning that
in case of simultaneous requests, the non-maskable interrupt will be serviced
first). A non-maskable interrupt has a fixed vector (#2) and therefore does not require an interrupt
acknowledge sequence on the bus. A typical use of an NMI is to invoke a procedure to handle a power
failure or some other critical hardware exception.
A procedure servicing an NMI will not be further interrupted by other non-maskable interrupt requests
until an
IRET instruction is executed. A further NMI request is remembered by the hardware and will
be serviced after the first
IRET instruction. Only one NMI request can be remembered. To prevent a
maskable interrupt from interrupting the
NMI interrupt handler, the IF flag should be cleared either
by using an interrupt gate
in the IDT or by setting IF = D.in the flag word of the task involved.
9.3 SOFTWARE INITIATED INTERRUPTS
Software initiated interrupts occur explicitly as interrupt instructions or may arise as the result of an
exceptional condition that prevents the continuation of program execution. Software interrupts are not
maskable.
Two interrupt instructions exist which explicitly cause an interrupt: INT nand INT 3. The
first allows specification of any interrupt vector; the second implies interrupt vector 3 (Breakpoint).
Other instructions like INTO,
BOUND, DIY, and IDIY may cause an interrupt, depending on the
overflow flag or values of the operands. These instructions have predefined vectors associated with
them
in the first 32 interrupts reserved by Intel.
A whole class of interrupts called exceptions are intended to detect faults or programming errors (in
the use of operands or privilege levels). Exceptions cannot be masked. They also have fixed vectors
within the first
32 interrupts. Many of these exceptions pass an error code on the stack, which is not
the case with the other interrupt types discussed
in section 9.2. Section 9.5 discusses these error codes
as
well as the priority among interrupts that can occur simultaneously.
9.4 INTERRUPT GATES AND TRAP GATES
Interrupt gates and trap gates are special types of descriptors that may only appear in the interrupt
descriptor table. The difference between a trap and an interrupt gate
is whether the interrupt enable
flag
is to be cleared or not. An interrupt gate specifies a procedure that enters with interrupts disabled
(i.e., with the interrupt enable flag cleared); entry via a trap gate leaves the interrupt enable status
unchanged. The
NT flag is always cleared (after the old NT state is saved on the stack) when an
interrupt uses these gates. Interrupts that have either gate
in the associated IDT entry will be processed
in the current task.
Interrupts and trap gates have the same structure as the call gates discussed in section 7.5.1. The
selector and entry point for a code segment to handle the interrupt or exception
is contained in the
gate.
See figure 9-3.
9-3