User's Manual

INTERRUPTS AND EXCEPTIONS
When an interrupt task is used, the task must be concerned with avoiding further interrupts while it is
operating. A general protection exception will occur if a task gate referring to a busy TSS is used while
processing an interrupt.
If subsequent interrupts can occur while the task is executing, the IF bit in
the flag word (saved in the TSS) must be zero.
9.5.1 Scheduling Considerations
A software-scheduled operating system must be designed to handle the fact that interrupts can come
along
in the middle of scheduled tasks and cause a task switch to other tasks. The interrupt-scheduled
tasks may call the operating system and eventually the scheduler, which needs to recognize that the
task that just called it
is not the one the operating system last scheduled.
If the Task Register (TR) does not contain the TSS selector of the last scheduled task, an interrupt
initiated task switch has occurred. More than one task may have been interrupt-scheduled since the
scheduler last ran. The scheduler must find via the backlink fields
in each TSS all tasks that have been
interrupted. The scheduler can clear those links and reset the busy bit
in the TSS descriptors, putting
them back
in the scheduling queue for a new analysis of execution priorities. Unless the interrupted
tasks are placed back
in the scheduling queue, they would have to await a later restart via the task
that interrupted them.
To locate tasks that have been interrupt-scheduled, the scheduler
looks into the current task's TSS
backlink (word one of the TSS), which points at the interrupted task. If that task was not the last task
scheduled, then it's backlink field
in the TSS also points to an interrupted task.
The backlink field of each interrupt-scheduled task should be set
by the scheduler to point to a sched-
uling task that
will reschedule the highest priority task when the interrupt-scheduled task executes
IRET.
9.5.2 Deciding Between Task, Trap, and Interrupt Gates
Interrupts and exceptions can be handled with either a trap/interrupt gate or a task gate. The advan-
tages of a task gaie are ail
the registers are saved and a new set is loaded with full isolation between
the interrupted task and the interrupt handler. The advantages of a trap/interrupt gate are faster
response to an interrupt for simple operations and easy access to pointers
in the context of the inter-
rupted task. All interrupt handlers use
IRET to resume the interrupted program.
Trap/interrupt gates require that the interrupt handler be able to execute at the same
or greater privi-
lege level than the interrupted program.
If any program executing at level 0 can be interrupted through
a
trap/task gate, the interrupt handler must also execute at level 0 to avoid general protection excep-
tion. All code, data, and stack segment descriptors must be
in the GuT to aiiow access from any task.
But, placing all system interrupt handlers at privilege level
0 may be in consistent with maintaining
the integrity of level
0 programs.
Some exceptions require the use of a task gate. The invalid task state segment exception (#10) can
arise from errors in the original TSS as well as in the target TSS. Handling the exception within the
same task could lead to recursive interrupts
or other undesirable effects that are difficult to trace. The
double fault exception (#8) should also use a task gate to prevent shutdown from another protection
violation occurring during the servicing of the exception.
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