User's Manual

SYSTEM CONTROL
AND
INITIALIZATION
MEMORY
CPU
,
GDTR
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15
0
·
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·
GDTLIMIT
·
23 I
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LDTLIMIT
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PROGRAM
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Figure 10-1. Local and Global
Descriptor
Table Definition
IDTR
!
CPU
o~
15
J
IDTLIMIT
I
IDT BASE
i
23
0
MEMORY
GATE
FOR
INTERRUPT
#n
GATE
FOR
INTERRUPT
#"-1
·
·
·
GATE
FOR
INTERRUPT
#1
~~T!:!=~~
INTERRUPT
#0
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J
,.,
INTERRUPT
DESCRIPTOR
TABLE
(lDT)
Figure 10-2.
Interrupt
Descriptor
Table Definition
10-2
G3010B
G3010B