User's Manual
APPENDIX C
8086/8088
COMPATIBILITY CONSIDERATIONS
SOFTWARE COMPATIBILITY CONSIDERATIONS
In general, the real address mode 80286 will correctly execute ROM-based 8086/8088 software. The
following
is
a list of the minor differences between 8086 and 80286 (Real mode).
1.
Add Six Interrupt Vectors.
The 80286 adds six interrupts which arise only
if
the 8086 program has a hidden bug. These
interrupts occur only for instructions which were undefined
on
the 8086/8088 or
if
a segment
wraparound
is
attempted.
It
is
recommended that you add an interrupt handler to the 8086 software
that
is
to be run
on
the 80286, which will treat these interrupts
as
invalid operations.
This additional software does not significantly effect the existing 8086 software because the
inter-
rupts
do
not normally occur and should not already have been used since they are in the interrupt
group reserved
by
Intel. Table
Col
describes the new 80286 interrupts.
2.
Do
not Rely
on
8086/8088 Instruction Clock Counts.
The 80286 takes fewer clocks for most instructions than the 8086/8088. The areas to look into are
delays between
I/0
operations, and assumed delays in 8086/8088 operating in parallel with an
8087.
3.
Divide Exceptions Point at the DIV Instruction.
Any interrupt on the 80286 will always leave the saved
CS:IP value pointing
at
the beginning of
the instruction
that
failed (including prefixes). On the 8086, the CS:IP value saved for a divide
exception points at the next instruction.
Table C-1. New
80286
Interrupts
Interrupt
Function
Number
5
A BOUND instruction was executed with a register value outside the two limit values.
6
An
undefined opcode was encountered.
7
The
EM
bit in the MSW has been set and
an
ESC.instruction was executed. This
interrupt will
also occur on WAIT instructions if TS is set.
8
The interrupt
table limit was changed by the LlDT instruction to a value between
20H and 43H. The default limit after reset
is
3FFH. enough for all 256 interrupts.
9
A processor extension data transfer exceeded offset OFFFFH
in
a segment. This
interrupt
handler must execute FNINIT before any
ESC
or
WAIT instruction is
executed.
13
Segment wraparound was attempted by a word operation at offset OFFFFH.
16 When 80286 attempted to execute a coprocessor instruction ERROR pin indicated
an
unmasked exception from previous coprocessor instruction.
C-1