User's Manual

80286 BASE ARCHITECTURE
STATUS FLAGS:
CARRY-------- ____________________________ --,
PARITY -------- ___________________ --,
AUXILIARY CARRY ___________________ -'-..,
ZERO I
SIGN ------------- ____ -,
OVERFLOW I
15 14 13 12 ~ 11 10 9 B 7 6 5 4 3
FLAGS: _ NT 10rL OF I OF IF I TF I SF I ZF _ AF _
)1 ::7~;~"
INTERRUPT ENABLE
'--------- DIRECTION FLAG
SPECIAL FIELDS:
'--------------1/0 PRIVILEGE LEVEL
'-------------------- NESTED TASK FLAG
_ INTEL RESERVED
Figure 2-10. Flags Register
2 1
o
G30108
The FLAGS register also contains three control flags that are used, under program control, to direct
certain processor operations. The interrupt-enable flag (IF), if set, enables external interrupts;
other·
wise, interrupts are disabled. The trap flag (TF), if set, puts the processor into a single-step mode for
debugging purposes where the target program
is automatically interrupted to a user supplied debug
routine after the execution of each target program instruction. The direction flag (DF) controls the
forward or backward direction of string operations:
0 = forward or auto increment the address regis-
teres) (SI, DI or
SI and DI), 1 = backward or auto·decrement the address register(s) (SI, DI or SI
and DI).
In general, the interrupt enable flag may be set or reset with special instructions (STI
= set,
CLI = clear) or by placing the flags on the stack, modifying the stack, and returning the flag image
from the stack to the flag register.
If operating in Protected Mode, the ability to alter the IF bit is
subject to protection checks to prevent non·privileged programs from effecting the interrupt state of
the
CPU. This applies to both instruction and stack options for modifying the IF bit.
The
TF flag may only be modified by copying the flag register to the stack, setting the TF bit in the
stack image, and returning the modified stack image to the flag register. The trap interrupt occurs
on
completion of the next instruction. Entry to the single step routine saves the flag register on the stack
with the
TF bit set, and resets the TF bit in the register. After completion of the single step routine,
the
TF bit is automatically set on return to the program being single stepped to interrupt the program
again
arkr completion of the next instruction. Use of TF is not inhibited by the protection mechanism
in Proteckd Mode.
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