User's Manual

COMPATIBILITY BETWEEN THE 80287 NPX AND THE 8087
The processor control instructions for the 80287 may be coded using either a WAIT or No-WAIT
form of mnemonic. The WAIT forms of these instructions cause ASM286
to precede the ESC
instruction with a CPU WAIT instruction, in the identical manner as does ASM86.
10. A recommended way to detect the presence of an 80287 in an 80286 system (or an 8087 in an
8086 system) is shown below. It assumes that the sytem hardware causes the data bus to be high
if
no 80287 is present to drive the data lines during the FSTSW (Store 80287 Status Word)
instruction.
FND_287:
F
N I NIT
FSTSTW STAT
MOV AX,STAT
OR
A L , A L
JZ GOL2 8 7
No 80287 Pre5ent
SMSW AX
OR AX,0004H
LMSW
A X
JMP CONTINUE
initialize numeric p,roce550r.
5tore 5tatu5 word into location
STAT.
Zero Flag reflect5 re5ult of OR.
Zero in AL mean5 80287 i5
pre5ent.
5et EM bit in Machine Statu5
W 0 rd.
to enable 50ftware emulation of
287.
80287 i5 pre5ent in 5ystem
GOT_287: SMSW
OR
LMSW
Continue
CONTINUE:
A X
AX,0002H
A X
5et MP bit in Machine Statu5 Word
to permit normal 80287 operation
i and off we go
An 80286/80287 design must place a pullupresistor on one of the low eight data bus bits of the
80286 to be sure it is read as a high when no 80287 is present.
B-2