Intel® IQ80321 I/O Processor Evaluation Platform Board Manual April 2, 2003 Document Number: 273521-008
Intel® IQ80321 I/O Processor Evaluation Platform INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
Intel® IQ80321 I/O Processor Evaluation Platform Contents Contents 1 Introduction..................................................................................................................................13 1.1 1.2 1.3 1.4 1.5 1.6 1.7 2 Getting Started............................................................................................................................. 19 2.1 2.2 2.3 2.4 2.5 2.6 3 Document Purpose and Scope ..............................................................
Intel® IQ80321 I/O Processor Evaluation Platform Contents 3.8 3.9 3.10 4 3.7.4 Rotary Switch......................................................................................................... 42 3.7.5 Battery Status ........................................................................................................ 43 Debug Interface .................................................................................................................. 44 3.8.1 Console Serial Port...................
Intel® IQ80321 I/O Processor Evaluation Platform Contents 3.10.9.20 Jumper 3.10.9.21 Jumper 3.10.9.22 Jumper 3.10.9.23 Jumper 4 External RAID Section................................................................................................................. 69 4.1 4.2 5 J3E1 ..........................................................................................66 J3G1 ......................................................................................... 66 J9E1 ...............................
Intel® IQ80321 I/O Processor Evaluation Platform Contents B.8 B.9 C Getting Started and Debugger ................................................................................................. 105 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 6 B.7.6 Setting Code|Lab Debug Options .......................................................................... 99 Exploring the Code|Lab Debug Windows ......................................................................... 100 B.8.1 Toolbar Icons ..................
Intel® IQ80321 I/O Processor Evaluation Platform Contents C.9 Debugging Basics .............................................................................................................119 C.9.1 Overview .............................................................................................................. 119 C.9.2 Hardware and Software Breakpoints ................................................................... 119 C.9.2.1 Software Breakpoints ...............................................
Intel® IQ80321 I/O Processor Evaluation Platform Contents Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 8 Intel® 80321 I/O Processor Block Diagram ................................................................................ 16 Serial-UART Communication ..................................................................................................... 24 Ethernet-Network Communication.......................................................................
Intel® IQ80321 I/O Processor Evaluation Platform Contents Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Intel® 80321 I/O Processor Related Documentation List............................................................ 13 Electronic Information ................................................................................................................. 14 Component Reference...............................
Intel® IQ80321 I/O Processor Evaluation Platform Contents 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 10 Switch S8E1 - 3: Settings and Operation Mode ......................................................................... 60 Switch S8E1 - 4: Descriptions .................................................................................................... 60 Switch S8E1 - 4: Settings and Operation Mode ..................
Intel® IQ80321 I/O Processor Evaluation Platform Contents Revision History Date Revision April 2003 008 March 2003 007 November 2002 006 21 October 2002 005 07 October 2002 004 August 2002 003 Description Changed name and references of Tester1LED to Tester321LED. Revised Appendix B, “Getting Started and Debugger”. Added Appendix C, “Getting Started and Debugger”. Added Warning to Section 3.8.4, “Logic-Analyzer Connectors” through Section 3.8.9, “Mictor J2C1”.
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1 Introduction 1.1 Document Purpose and Scope This document describes the Intel® IQ80321 Evaluation Platform Board. This platform is targeted for the Intel® 80321 I/O processor (80321). The board serves as both an evaluation platform for developers using 80321 as well as a Customer Reference Board. The IQ80321 is intended for rapid intelligent I/O development.
Intel® IQ80321 I/O Processor Evaluation Platform Introduction 1.3 Electronic Information Table 2. Electronic Information Support Type Location/Contact The Intel World-Wide Web (WWW) Location: http://www.intel.com Customer Support (US and Canada): 1.4 800-628-8686 Component References Table 3 provides additional information on the major components of IQ80321. Table 3.
Intel® IQ80321 I/O Processor Evaluation Platform Introduction 1.5 Terms and Definitions Table 4. Terms and Definitions Acronym/Term Board Manual Definition ARM Refers to both the microprocessor architecture and the company that licenses it. CRB Customer Reference Board ICE In-Circuit Emulator – A piece of hardware used to mimic all the functions of a microprocessor.
Intel® IQ80321 I/O Processor Evaluation Platform Introduction 1.6 Intel® 80321 I/O Processor About the Intel® 80321 I/O processor. The Intel® 80321 I/O processor combines the Intel® XScale™ core with powerful new features to create an intelligent I/O processor. This single-function PCI device is fully compliant with the PCI Local Bus Specification, Revision 2.2.
Intel® IQ80321 I/O Processor Evaluation Platform Introduction It is an integrated processor that addresses the needs of intelligent I/O applications and helps reduce intelligent I/O system costs. The PCI Bus is an industry standard, high performance low latency system bus. The 80321 PCI Bus is capable of 133 MHz operation in PCI-X mode as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a.
Intel® IQ80321 I/O Processor Evaluation Platform Introduction 1.7 Intel® IQ80321 Evaluation Platform Board Features Table 5. Summary of Features Feature Definition Battery Backup Unit: Battery back up circuit for SDRAM – 64 MB for 72 hours. Ethernet Port: Gigabit Ethernet Debugging/Download Port (using Intel® 82544). Flash ROM: 8 MB Flash ROM 3.3 V – 16-bit Flash I/F. Form & Factor: Modified PCI long-card format – one Secondary PCI-X (SPCI-X) Expansion slots (right angel connector).
Getting Started 2 The IQ80321 is a software development environment for Intel® 80321 I/O processor. 2.1 Kit Content The IQ80321 Kit contains the following items: • • • • • 2.2 Warning: 2.2.1 Intel® IQ80321 Evaluation Platform Board Code|Lab* Development Environment from Accelerated Technology Incorporated* JTAG Emulation unit Serial Cable Evaluation Software Bundle Hardware Installation Static charges can severely damage the boards.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started 2.3 Factory Settings Make sure that the switch/jumper settings are set to proper positions as explained in Section 3.10, “Switches and Jumpers” on page 52. 2.4 Development Strategy 2.4.1 Supported Tool Buckets For developing and debugging software application, the production version of the IQ80321 kit includes the Code|Lab Development Environment. Support for the Code|Lab development environment is available from ATI*.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started 2.5 Target Monitors 2.5.1 Redhat Redboot RedBoot* is an acronym for “Red Hat Embedded Debug and Bootstrap”, and is the standard embedded system debug/bootstrap environment from Red Hat, replacing the previous generation of debug firmware: CygMon and GDB stubs. It provides a bootstrap environment for a range of embedded operating systems, such as embedded Linux and eCos*, and includes facilities such as network downloading and debugging.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started 2.5.2 ARM Firmware Suite The ARM Firmware Suite is a package of low-level routines and libraries that have been designed to help developers rapidly bring up applications and operating systems on Intel® XScale™ microarchitecture-based development platforms, such as the IQ80321. AFS consists of two parts: 1. µHAL, the ARM standard board API, which is low-level firmware, designed to provide a common set of functions across IQ80321.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started 2.5.2.1 ARM Angel Angel is one of the debug monitor programs for 80321. It is provided in source and binary form with the ARM Software Development Toolkit.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started 2.6 Host Communications Examples How to communicate to the host. 2.6.1 Serial-UART Communication Using a serial connection: Figure 2. Serial-UART Communication Host System SW Debugger C/C++ Seria ASM able lC Serial Connectivity Intel® 80321 I/O Processor Running a Debug Monitor Intel® IQ80321 Evaluation Platform Board PCI/PCI-X Platform Serial Connectivity Server/Desktop/Backplane Host System A9647-01 2.6.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started 2.6.3 JTAG Debug Communication Using a JTAG Emulator: Figure 4.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started 2.6.4 GNUPro GDB/Insight 2.6.4.1 Communicating with Redboot Hardware Setup: • Host with UNIX/Linux or Win32 installed • Intel® IQ80321 Evaluation Platform Board with serial cable • Redhat Redboot monitor Flashed to the platform board Recommended Mapping of UART Ports to Host Com Ports • Host port connected to the platform board UART.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started To bring up a HyperTerminal session on a Win32 platform: Go to Start, Programs, Accessories, Communications, HyperTerminal • HyperTerminal setup screens: — “Connection Description” Panel: • Enter name. — “Connect To” Panel: • Select host com2 port (or whichever port you are using).
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started 2.6.4.2 Connecting with GDB Below are the GDB commands entered from the command prompt. Be sure system path is set to access “xscale-elf-gdb.exe”. File name in example “hello”. Bold type represents input by user: >xscale-elf-gdb -nw hello1 • Start GDB executable, loads debug information and symbols. (GDB) set remotebaud 115200 • Set baud rate for the IQ80321.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started 2.6.5 ARM Extended Debugger For further information on the AXD Debugger, refer to the content of the ARM ADS. This setup assumes that Angel is Flashed on the board: Description: Terminal emulator runs on host and communicates with the board via the serial cable. Start: Power up the target board. After the ‘reset’ is asserted, the two 7-segment LEDs display blank. The time for reset is approximately 1 or 2 seconds.
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3 Hardware Reference Section 3.1 Functional Diagram Figure 5 shows the functional block for the IQ80321. Figure 5.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.2 Board Form-Factor/Connectivity Table 6 summarizes the form-factor and connectivity features for the IQ80321. Table 6. Form-Factor/Connectivity Features Description ® The Intel IQ80321 Evaluation Platform Board is a full-size PCI card with form factor depicted by Figure 6. The IQ80321s connects to the Primary PCI-X (PPCI-X) bus a PCI-X. The IQ80321 has one PCI-X expansion slot.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.3 Power The IQ80321 draws power from the PCI-X bus. The power requirements for the IQ80321 are shown in Table 7 below. The numbers do not include the power required by a PCI-X card mounted on the expansion slot. Table 7. Power Features Voltage Note: Board Manual Typical Current Maximum Current +3.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.4 Memory Subsystem Memory subsystem consists of the SDRAM as well as the Flash memory subsystems. 3.4.1 DDR SDRAM The DDR SDRAM interface consists of a 64-bit wide data path to support 1.6 GB/sec throughput. An 8-bit Error Correction Code (ECC) is stored into the DDR SDRAM array along with the data and is checked when the data is read. Table 8.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.4.2 Flash Memory Requirements Total Flash memory size is 8 MB. Table 10.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.5 Intel® 80321 I/O Processor Operation Mode Please refer to user switches section for mode setting during reset.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.6 Interrupt Routing The IQ80321 Interrupt routing. Figure 7.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.7 Intel® IQ80321 Evaluation Platform Board Peripheral Bus The IQ80321 populates the peripheral bus as depicted by Figure 8. Figure 8. Intel® IQ80321 Evaluation Platform Board Peripheral Bus Topology FLASH 28F640J3A 16-bit 8 Mb Agilent* HDSP-G211 Hex Display NKK* DR FC16 Rotary Switch Battery Status Buffers Intel® 80321 I/O Processor Bus Tl* TL16C550C UART * Other names and brands may be claimed as property of others.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.7.1 Flash ROM Table 12. Flash ROM Features Description Flash is an Intel® StrataFlash® technology – Part number: 28F640 Flash size is 8 MB The connection to the peripheral bus is depicted by Figure 9 Figure 9.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.7.2 UART Table 13. UART Features Description UART on the peripheral bus is part of the 16C550 family. The connection to the peripheral bus is depicted by Figure 10. UART Connection on the Peripheral Bus Texas Instruments* TL16C550C UART0 INTERRUPT Intel® 80321 I/O Processor XINT1# CS PCE1 Figure 10. Intel® 80321 Peripheral Bus * Other names and brands may be claimed as property of others.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.7.3 HEX Display Table 14. HEX Display on the Peripheral Bus Description Intel® The IQ80321 Evaluation Platform Board includes a HEX Display unit on the peripheral bus. The HEX display contains two digits (MSB, LSB). The connection to the peripheral bus is depicted by Figure 11. Figure 11.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.7.4 Rotary Switch The IQ80321 provides a Rotary Switch for the user to select from different boot-up flavors. Table 15. Rotary Switch Requirements Description Rotary switch has a 4-bit resolution (16 positions). The connection to the peripheral bus is depicted by Figure 12. Figure 12.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.7.5 Battery Status Table 16. Battery Status Buffer Requirements Description The Intel® IQ80321 Evaluation Platform Board provides the following status for the battery: • Battery-Present status-bit on PB data line 9 • Battery-Charge status-bit on PB data line 10 • Battery-Discharge status-bit on PB data line 12 The connection to the peripheral bus is depicted by Figure 13. Figure 13.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.8 Debug Interface 3.8.1 Console Serial Port The platform has one serial port for debug purposes as described in Section 3.7, “Intel® IQ80321 Evaluation Platform Board Peripheral Bus” on page 38. 3.8.2 Ethernet Port The IQ80321 supports an Intel® 82544EI Gigabit Ethernet Controller on the secondary PCI-X bus. 3.8.2.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.8.3 JTAG Debug The IQ80321 has a 20-pin JTAG connector that is in compliant with ARM Multi-ICE guidelines. 3.8.3.1 JTAG Port Figure 14. JTAG Port Pin-out VTref 1 2 Vsupply nTRST 3 4 GND TDI 5 6 GND TMS 7 8 GND TCK 9 10 GND RTCK 11 12 GND TDO 13 14 GND nSRST 15 16 GND DBGRQ 17 18 GND DBGACK 19 20 GND A9457-01 3.8.4 Warning: Table 17.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.8.5 Warning: Table 18. 46 Mictor J3F2 Be sure to fully understand the pin assignments of the particular logic analyzer being used before connecting to the Intel® IQ80310 Evaluation Platform Board. When voltage is applied, particularly to a NC pin, hardware damage can be incurred.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.8.6 Warning: Table 19. Mictor J2F1 Be sure to fully understand the pin assignments of the particular logic analyzer being used before connecting to the Intel® IQ80310 Evaluation Platform Board. When voltage is applied, particularly to a NC pin, hardware damage can be incurred.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.8.7 Warning: Table 20. Mictor J1C1 Be sure to fully understand the pin assignments of the particular logic analyzer being used before connecting to the Intel® IQ80310 Evaluation Platform Board. When voltage is applied, particularly to a NC pin, hardware damage can be incurred.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.8.8 Warning: Table 21. Mictor J3C1 Be sure to fully understand the pin assignments of the particular logic analyzer being used before connecting to the Intel® IQ80310 Evaluation Platform Board. When voltage is applied, particularly to a NC pin, hardware damage can be incurred.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.8.9 Warning: Table 22. 50 Mictor J2C1 Be sure to fully understand the pin assignments of the particular logic analyzer being used before connecting to the Intel® IQ80310 Evaluation Platform Board. When voltage is applied, particularly to a NC pin, hardware damage can be incurred.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.9 Board Reset Scheme Figure 15 depicts the reset scheme for the IQ80321. Table 23 list the reset schemes for the IQ80321. Table 23. Reset Requirements/Schemes Description Primary PCI reset, resets all devices on the board. It occurs during the power-up. The SRST signal from the JTAG connector is a bi-directional signal that can force a reset similar to the power-up reset on the board. Figure 15.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10 Switches and Jumpers 3.10.1 Switch Summary Table 24.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.2 PCIX Initialization Summary Figure 16 shows a routing guidance on how PCI-X mode is determined/implemented on the secondary side of the PCI-X bridge. The Intel® 80321 I/O processor (80321), GbE device, and the PCI-X expansion slot all reside on this bus. Figure 16.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.3 Default Switch Settings - Visual Table 25. Switch S7E1 a. Table 26. Table 27. Table 28. Table 29. Table 30. Off Offa Off Off Off On Off S7E1 S7E1 S7E1 S7E1 S7E1 S7E1 S7E1 S7E1 1 2 3 4 5 6 7 8 Use opposite settings when using an 80300-BP Backplane from Cyclone Micro Systems or most other PCI-X backplanes (switches S7E1-3, S8E1-7, S4D1-1, 2, 3, 4).
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.4 Jumper Summary Table 31. Jumper Summary Jumper Association Description J1G2 PPCI-X Reset Can isolated the PCI-X reset from getting to the board. 2-3 J3E1 SPCI-X Clock Enables spread-spectrum on the SPCI-X clock. 2-3 J3G1 PCI-X Bridge Enables Bridge access from the SPCI-X side. 2-3 J9E1 PCI-X Bridge Enables Base Address Register (BAR).
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.7 Secondary PCI/PCI-X Operation Settings Table 34. Secondary PCI/PCI-X Operation Settings a. b. c.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.9 Detail Descriptions of Switches/Jumpers 3.10.9.1 Switch S7E1- 2/3 Table 36. Switch S7E1- 2/3: General Descriptions 3.10.9.1.1 Switch Association Description Factory Default S7E1-2 IOP RST_MODE: Sets IOP Reset-Mode operation. Off S7E1-3 IOP RETRY: Sets IOP RETRY-Mode operation.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.9.2 Switch S7E1- 4/5 Table 40. Switch S7E1 - 4/5: Descriptions 3.10.9.2.1 Switch Association Description Factory Default S7E1-4 SPCI-X Bus IDSEL_EN_PCIX1: Enables GPIO IDSEL control for the PCI-X slot. Off S7E1-5 SPCI-X Bus IDSEL_EN_GBE: Enables GPIO IDSEL control for GBE NIC. Off Switch S7E1 - 4 This allows 80321 to hide the device in PCI-X Slot 1under GPIO control. Table 41.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.9.4 Switch S7E1- 8 Table 45. Switch S7E1 - 8: Descriptions Table 46. Switch Association S7E1-8 SPCI-X Clock Description Enables SPCI-X clock circuit enable. Off Switch S7E1 - 8: Settings and Operation Mode S7E1-8 Board Manual Factory Default Operation Mode Off Enable S_CLK<4..0>. On Disable S_S_CLK<4..0>.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.9.5 Switch S8E1- 2 Turn On to enable on-board Gigabit Ethernet, otherwise Off for better PCI-X loading/performance. Table 47. Switch S8E1 - 2: Descriptions Switch S8E1-2 Table 48. Association Description Factory Default SPCI-X Bus QSWITCHEN: Quick-Switch to make GbE NIC visible on the SPCI-X bus. On Switch S8E1 - 2: Settings and Operation Mode S8E1-2 3.10.9.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.9.8 Switch S8E1- 5 When this input is pulled high (off), the bridge changes the output impedance of the drivers to the opposite state than was assumed by default, as shown in Table 54 below: 3.10.9.8.1 Table 53. Switch S8E1 - 5: Descriptions Switch Association S8E1-5 PCI-X Bridge Description S_DRVR_MODE: Driver impedance selection for SPCI-X bus. Operation Mode Off PCI 66, PCI-X 66/100: 40 Ω impedance.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.9.10 Switch S8E1- 7 Used to enable the IDSEL reroute function at reset or power-up. The reset value of the secondary bus private device mask register is modified according to the tie value of the IDSEL_REROUTE_EN pin. 0 = on: reset value of the secondary bus private device mask register is x’00000000’. 1 = off: reset value of the secondary bus private device mask register is x’22F20000’. Table 58. Table 59.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.9.12 Switch S8E2 - 1/2 This feature forces the PCI-X Capability pins for the expansion slot to force a configuration on the Secondary PCI-X bus. Table 62. Table 63. Switch S8E2 - 1/2: Descriptions Switch Association S8E2-1/2 SPCI-X Bus Description PCIXCAP: Force PCI-X capability for SPCI-X Bus S8E2-1 S8E2-2 Operation Mode Off Off PCI-X 133/100 Off On PCI-X 66 On x PCI 66 Switch S8E2 - 4 Table 64.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.9.14 Switch S9E1 - 1:3 Table 66. Switch S9E1 - (1:3) Descriptions Table 67. Switch Association S9E1-1:3 PCI-X Bridge Description PCIXCAP: Set Primary PCI-X capability for the bridge. S9E1-1 S9E1-2 S9E1-3 Off Off On PCI-X 133/100. Off On On PCI-X 66. Off On Off PCI 66. Switch S9E1 - 4 Table 68.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.9.16 Switch S1D1 - 1/2 Switches 1 and 2 have to always be opposite of each other. Table 70. Table 71. 3.10.9.17 Switch S1D1 - 1/2: Descriptions Switch Association S1D1-1 2 3 DDR Memory Description Factory Default SPD EEPROM: Configure serial EEPROM Address Range.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.9.19 Jumper J1G2 Table 76. Jumper J1G2: Descriptions Table 77. Jumper Association J1G2 PPCI-X Reset Description Can isolated the PCI-X reset from getting to the board. Operation Mode Pins 1,2 P_RST (primary side reset) disconnected from reset circuitry. Pins 2,3 P_RST (primary side reset) used to reset board. 3.10.9.20 Jumper J3E1 Table 78.
Intel® IQ80321 I/O Processor Evaluation Platform Hardware Reference Section 3.10.9.22 Jumper J9E1 Base Address Register Enable: Used to enable the base address register at reset or power-up. The 64-bit register located at offsets x'10' and x'14' is used to claim a 1 MB memory region when enabled. The register returns all zeroes to read accesses and the associated memory region is not claimed when disabled. 0 = (1-2): BAR disabled, register reads returns 0s, no memory region claimed.
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4 External RAID Section The IQ80321 provides the capability for the user to develop RAID applications. There is a requirement to provide the ability of making the secondary PCI-X devices private and the ability to route the interrupt lines. The following requirements describe this capability. 4.1 Private Device Configuration The devices on the SPCI-X bus (Expansion Slot and Intel® 82544 Gigabit Ethernet Controller) are configured as private devices based on Table 86 requirements. Table 86.
Intel® IQ80321 I/O Processor Evaluation Platform External RAID Section 4.2 Interrupt Routing The interrupt lines for devices on the SPCI-X bus (Expansion Slot and Intel® 82544 Gigabit Ethernet Controllerr) are routed based on requirements. Table 87. Figure 18. Interrupt Routing for Secondary PCI-X Private Device Number Description 4.2.1 The INTA# and INTB# of PCI-X Expansion Slot are routed to XINT0# and XINT1# External Interrupt inputs on the Intel® 80321 I/O processor. 4.2.
5 Software Reference 5.1 DRAM For DDR SDRAM Sizes and Configurations, see section 7.2.2.1, table 139 of theIntel® 80321 I/O Processor Developer’s Manual. Table 89 provides DDR SDRAM Address Register Definitions, while this sections also contains multiple examples of Address Register Programming. See the Intel® 80321 I/O Processor Design Guide, section 7.1, table 16 for supported DDR and SDRAM configurations. The Intel® 80321 I/O processor (80321) supports 2.5 V DDR memory.
Intel® IQ80321 I/O Processor Evaluation Platform Software Reference 5.2.1 Flash ROM The Flash ROM is an 8 MB Intel® StrataFlash® (part# 38F640) that sits on the Peripheral Bus and is accessed using PCE0. Figure 19. Flash Connection to Peripheral Bus Intel® 80321 I/O Processor CS PCE0 FLASH 28F640J3A 16-bit 8 Mb Intel® 80321 I/O Processor Bus A9452-02 Under normal operation, the very first instruction access by the Intel® XScale™ core begins at location 0x0 on the 80321 Internal Bus.
Intel® IQ80321 I/O Processor Evaluation Platform Software Reference 5.2.2 UART The UART is a TL16C550C. It sits on the Peripheral Bus and is accessed using PCE1 and XINT1# as shown in Figure 20: Figure 20. UART Connection to Peripheral Bus See datasheet at the following link for more information and a pin layout of this device: http://focus.ti.com/docs/prod/productfolder.jhtml?genericPartNumber=TL16C550C. Table 89. UART Register Settings Address 5.2.
Intel® IQ80321 I/O Processor Evaluation Platform Software Reference 5.2.4 HEX Display The HEX Display is an Agilent* HDSP-G211, which allows for monitoring of two digits. It sits on the Peripheral Bus and is accessed using PCE2 and PCE3 as shown here: Figure 21. Hex Display Connection to Peripheral Bus Redboot* uses address range 0xFE84 0000 - 0xFE84 0FFF for the left 7-segment LED (PCE3) and address range 0xFE85 0000 - 0xFE85 0FFF for the right 7-segment LED (PCE2). Figure 22.
Intel® IQ80321 I/O Processor Evaluation Platform Software Reference Figure 24.
Intel® IQ80321 I/O Processor Evaluation Platform Software Reference 5.3 Ethernet The 82544EI utilizes a 32/64-bit, 33/66 MHz direct-interface to the PCI bus. The controller interfaces with the 80321 through on-chip command/status registers and using a shared memory area. The intended usage of this chip is for high speed upload, download, and debugging. It is also used for developing network storage applications. ARM-AFS, Redboot, VxWorks* and other standard OSs come with support for this chip.
Intel® IQ80321 I/O Processor Evaluation Platform Software Reference 5.4 Board Support Package (BSP) Examples Examples provided in this section are based on the Red Hat* Redboot software running on the IQ80321 board. 5.4.1 Intel® 80321 I/O Processor Memory Map Figure 25 depicts the memory space for the IQ80321 (before Redboot boots): Figure 25.
Intel® IQ80321 I/O Processor Evaluation Platform Software Reference 5.4.2 Redboot* Intel® IQ80321 Memory Map The virtual memory maps use a C, B, and X column to indicate the caching policy for the region.
Intel® IQ80321 I/O Processor Evaluation Platform Software Reference 5.4.3 Redboot Intel® IQ80321 Physical Memory Map - Visual Figure 26.
Intel® IQ80321 I/O Processor Evaluation Platform Software Reference 5.4.4 Redboot Intel® IQ80321 Virtual Memory Map - Visual Figure 27.
Intel® IQ80321 I/O Processor Evaluation Platform Software Reference 5.4.5 Redboot Intel® IQ80321 Files Attached in the kit, find a copy of the Red Hat eCos for Intel® 80321 I/O processorr CD. Once the CD is installed, you may find: • •The Redboot initialization code source files from the following location: From the installed directory: ..
Intel® IQ80321 I/O Processor Evaluation Platform Software Reference 5.4.6 Redboot Intel® IQ80321 DDR Memory Initialization Sequence In order to set the correct ECC bits, a DDR memory system (DIMM or discrete components) must be written to with a known value. This process requires 64-bit writes to the entire DDR memory intended for use. The following explains the sequence for memory initialization by Redboot on an IQ80321 board with an ECC DIMM.
Intel® IQ80321 I/O Processor Evaluation Platform Software Reference 5.4.7 Redboot Switching • S8E1-2 ON: Enable GbE on the SPCI-X Bus. • S8E1-7 OFF: PCI-X Bridge hides devices using Private Space Address lines. • S4D1 ON-OFF-ON-OFF: GbE and Expansion Slot Private Space. All other switches are left in default positions.
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IQ80310 and IQ80321 Comparisons A This appendix provides a brief description for differences between IQ80321 and IQ80310. Please also refer to application note: Migrating from the Intel® 80310 I/O Processor Chipset to the Intel® 80321 I/O Processor Application Note 273562. Table 90.
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Getting Started and Debugger B.1 B Introduction This appendix pertains to Code|Lab version 2.2 and earlier, which uses the Microsoft Visual Studio 6.0. For Code|Lab version 2.3 and later, refer to Appendix C, “Getting Started and Debugger”. B.1.1 Purpose The purpose of this appendix is to help the user setup and become familiar with the Intel® IQ80321 Evaluation Platform Board (IQ80321) some of the development tools.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.1.4 Related Web Sites • • • • • 88 Macraigor: http://www.ocdemon.net/ http://developer.intel.com/design/intelxscale/dev_tools/020523/index.htm http://developer.intel.com/design/iio/80321.htm http://developer.intel.com/design/iio/docs/iop321.htm http://developer.intel.com/design/iio/swsup/Tester321LED.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.2 Setup B.2.1 Hardware Setup Use Figure 28 and the rest of the Intel® IQ80321 Evaluation Platform Board Manual, to set up the hardware. • Connect the Raven to the host via the parallel port and to the evaluation board via the 20-pin JTAG connector. Note: The parallel port must be configured to EPP mode for the Macraigor Raven to work properly.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.2.2 Software Setup ATI Code|Lab is a plug-in to Microsoft Visual Studio 6.0; therefore, Microsoft Visual Studio 6.0 must be installed on the host system before installing ATI Code|Lab. To load ATI Code|Lab, run setup.exe under the program directory. Do not install over an old version of ATI Code|Lab.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.3 New Project Setup B.3.1 Creating a New Project 1. Launch Code|Lab EDE and select “Tools/Customize/Add-ins/Macro Files”. a. Check “Code|Lab EDE” and click Close. 2. Select “File/New…/Project”, then “Code|Lab EDE Project Wizard” a. Fill-in the Project Name box with “Tester321LED” b. Set an appropriate Location path. Note: The directory “Tester321LED” is created under the path specified in the Location box. c. Click OK. 3.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.3.2 Configuration On the tool bar, click on the icon that looks like a file folder with the letters “EDE” on it. When the mouse arrow is placed on it, a text box displays “Project Settings”. Note: There is no main menu way to access the project settings. 1. Download and expand the following file into a directory such as “C:\Redhat” http://developer.intel.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.4 Flashing with JTAG B.4.1 Overview Code|Lab and the Raven are capable of reading from, writing to, and erasing the contents of the Flash on the evaluation board. The board comes with RedBoot loaded in the Flash. RedBoot is the RedHat debug monitor which initializes the board and has some debug and diagnostic functions.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.4.2 Using Flash Programmer Note: The parallel port must be set to EPP mode or the Macraigor Raven will not work properly. Download the RedBoot executable files from the following location: http://developer.intel.com/design/intelxscale/dev_tools/020523/RedBoot Debug Monitor for the Intel® IQ80310/IQ80321 boards 1. Double click on the “Code|Lab Debug” icon on the desktop. The Connection Window appears. 2.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.5 Debugging Out of Flash JTAG debuggers can be used on two levels; with or without the source code. When the Flash is programmed, the debugger can monitor the executable code, halt it, step through it, and monitor the memory and registers. The executable code is disassembled so that the assembly code can be examined. Debugging with source code allows the user to examine the C code that is being executed.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.7 Running the Code|Lab Debugger This section is provided to get the system up and running in the Code|Lab Debug environment, but it is not intended as a full-functional tutorial. Please refer to the ATI Code|Lab Debug Reference Manual for more detailed information. B.7.1 Launching and Configuring Debugger 1. In EDE, click on the icon that looks like a red bug. a. The “Connect” dialog appears. 2.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.7.2 Manually Loading and Executing an Application Program 1. Launch the Code|Lab Debug Environment from the desktop icon. 2. Ensure “File…/Program Load Options/Load Executable and Symbols” is checked. 3. file, program load options, load executable and symbols. a. Select “file, open program, browse”. b. go find c:\…\Test1LED\O\Test1LED.elf. 4. Hit Go (80, 3, 32, and 21 cycle on the LEDs). 5.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.7.4 Using Breakpoints Note the small gray circles on the sidebar beside each line of source code. Single-click any of these gray circles and a red dot appears. The red dot represents a break point. Single-click the red dot to remove it, or click the “Remove all breakpoints” icon. Place a breakpoint on the following lines of code in “blink.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.7.5 Stepping Through the Code The “led.c” file contains a function that is called from code in “blink.c”. Tis exercise steps through the code and utilizes a few of the most common step tools. 1. Launch the debugger, open Tester321LED, and open the “blink.c” and “led.c” files. 2. Set a breakpoint on the following line in “blink.c”: displayLED(leds[8],leds[0]); /* LED display '80'*/ 3. Press Go.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.8 Exploring the Code|Lab Debug Windows This section discusses some basics of the debug environment. Some of these windows and concepts have been dealt with during previous exercises in this manual. However, many new windows are also discussed and basic interaction exercises are given. Begin this section by launching the Code|Lab Debugger environment and connection via the JTAG port. B.8.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.8.6 Registers Window Close all the active windows, then bring up the Registers window. Resize the this window and its columns to get a good view of all the registers. Notice that there is a Flags tab at the bottom of this window. This is useful for seeing the system flags defined by the CPSR.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.9 Debugging Basics B.9.1 Overview Debuggers allow developers to interrogate application code by allowing program flow control, data observation, and data manipulation. The flow control functions include the ability to single-step through the code, step into functions, step over functions, and run to breakpoint (hardware or software).
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger B.9.3 Exceptions/Trapping A debug exception causes the processor to re-direct execution to a debug event handling routine.
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Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger Getting Started and Debugger C.1 C Introduction This appendix pertains to Code|Lab version 2.3 and later which uses Microsoft's Visual Studio .NET. For Code|Lab version 2.2 and earlier, refer to appendix B. C.1.1 Purpose The purpose of this appendix is to help the user setup and become familiar with the Intel ® IQ80321 Evaluation Platform Board (IQ80321) and, other related hardware and software.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger C.1.4 Related Web Sites • • • • • 106 Macraigor: http://www.ocdemon.net/ http://developer.intel.com/design/intelxscale/dev_tools/020523/index.htm http://developer.intel.com/design/iio/80321.htm http://developer.intel.com/design/iio/docs/iop321.htm http://developer.intel.com/design/iio/swsup/Tester321LED.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger C.2 Setup C.2.1 Hardware Setup Use Figure 28 and the rest of the Intel® IQ80321 Evaluation Platform Board Manual, to set up the hardware. • Connect the Raven to the host via the parallel port and to the evaluation board via the 20-pin JTAG connector. Note: The parallel port must be configured to EPP mode for the Macraigor Raven to work properly.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger C.2.2 Software Setup ATI Code|Lab is a plug-in to Microsoft Visual Studio .NET, therefore Microsoft Visual Studio .NET must already be loaded on the system. To load ATI Code|Lab, run setup.exe under the program directory. Note: Do not install over an old version of ATI Code|Lab. When necessary, uninstall Code|Lab with Add/Remove programs under the Control Panel before reinstalling.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger C.3 New Project Setup C.3.1 Creating a New Project 1. Launch Code|Lab EDE for .NET. 2. On the Start Page, select “New Project”. a. The “New Projects” window appears. b. Select “Code|Lab Projects” under Project Types and name the project “Project80321” in the name field. Note: The directory “Project80321” is created under the path specified in the Location box. c. Click OK. 3. In the Code|Lab EDE Project Wizard Window: a.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger C.3.2 Configuration Examine the main menu of Code|Lab EDE for .NET. • File • Edit • Project • View • code|lab EDE • Build, Debug • Tools • Window • Help Since Code|Lab is a plug-in to Visual Studio, some of these menu items are Visual Studio and some are specific to Code|Lab. Click on any of these menu items and the drop-down menu displays the subordinate menu items.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger C.4 Flashing with JTAG C.4.1 Overview Code|Lab and Raven are capable of reading from, writing to, and erasing the contents of the Flash on the evaluation board. The board comes with RedBoot loaded in the Flash. RedBoot is the RedHat debug monitor which initializes the board and has some debug and diagnostic functions.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger C.4.2 Note: Using Flash Programmer The parallel port must be set to EPP mode or the Macraigor Raven will not work properly. Download the RedBoot executable files from the following location: http://developer.intel.com/design/intelxscale/dev_tools/020523/RedBoot Debug Monitor for the Intel® IQ80310/IQ80321 boards 1. Double click on the “Code|Lab Debug” icon on the desktop. The Connection Window appears. 2.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger C.5 Debugging Out of Flash JTAG debuggers can be used on two levels; with or without the source code. When the Flash is programmed, the debugger can monitor the executable code, halt it, step through it, and monitor the memory and registers. The executable code is disassembled so that the assembly code can be examined. Debugging with source code allows the user to examine the C code that is being executed.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger C.7 Running the Code|Lab Debugger This section is provided to get the system up and running in the Code|Lab Debug environment, but it is not intended as a full-functional tutorial. Please refer to the ATI Code|Lab Debug Reference Manual for more detailed information. C.7.1 Launching and Configuring Debugger 1. In EDE, click on the icon that looks like a red bug. The “Connect” window appears. 2.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger C.7.3 Displaying Source Code 1. Launch the Code|Lab EDE Debugger and open the “Tester321LED” ELF program. Note: Use the File/Recent Programs menu for quick access. 2. Select the “Files” view in the lower tab of the WorkSpace window. 3. Bring up “blink.c” and “led.c” source code by double-clicking each filename. 4. Use the “Windows” Menu to arrange the windows, or maximize, minimize, and resize manually as desired. 5.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger C.7.5 Stepping Through the Code The “led.c” file contains a function that is called from code in “blink.c”. This exercise steps through the code and utilizes a few of the most common step tools. 1. Launch the debugger, open Tester321LED, and open the “blink.c” and “led.c” files. 2. Set a breakpoint on the following line in “blink.c”: displayLED(leds[8],leds[0]); /* LED display '80'*/ 3. Press Go.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger C.8 Exploring the Code|Lab Debug Windows This section discusses some basics of the debug environment. Some of these windows and concepts have been dealt with during previous exercises in this manual. However, many new windows are also discussed and basic interaction exercises are given. Begin this section by launching the Code|Lab Debugger environment and connection via the JTAG port. C.8.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger C.8.6 Registers Window Close all the active windows, then bring up the Registers window. Resize the this window and its columns to get a good view of all the registers. Notice that there is a Flags tab at the bottom of this window. This is useful for seeing the system flags defined by the CPSR.
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger C.9 Debugging Basics C.9.1 Overview Debuggers allow developers to interrogate application code by allowing program flow control, data observation, and data manipulation. The flow control functions include the ability to single-step through the code, step into functions, step over functions, and run to breakpoint (hardware or software).
Intel® IQ80321 I/O Processor Evaluation Platform Getting Started and Debugger C.9.3 C.9.3 Exceptions/Trapping A debug exception causes the processor to re-direct execution to a debug event handling routine.
