Intel® Xeon® Processor E7 v2 Product Family Specification Update January 2015 Reference Number: 329597-010
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Contents Revision History ........................................................................................................ 4 Preface ...................................................................................................................... 5 Summary Table of Changes ....................................................................................... 7 BIOS ACM Errata Summary ......................................................................................
Revision History Version Date Updated erratum CF139 Added erratum CF153 January 2015 009 Added errata CF150 - CF152 December 2014 008 Added erratum CF149 November 2014 007 Added errata CF137 - CF148 Updated erratum CF125 October 2014 006 Added errata CF130 - CF136 September 2014 005 Updated erratum CF124 Added erratum CF129 July 2014 004 Added errata CF125-CF128 June 2014 003 Added errata CF119-CF124 May 2014 002 Added errata CF107-CF118 April 2014 001 Initial Release November
Preface Preface This document is an update to the specifications contained in the Nomenclature table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents.
Preface Affected Documents Document Number1 Document Title Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Families Datasheet, Volume One 329594 Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Families Datasheet, Volume Two 329595 Notes: 1. Document number subject to change. See IBP for the most up-to-date collateral list. Contact your Intel representative to receive the latest revisions of these documents.
Summary Table of Changes Summary Table of Changes The table included in this section indicates the sightings that apply to the Ivy Bridge-EX Processor. If a sighting becomes a Known Sample Issue, Intel may fix some of the Known Sample Issues in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. Definitions are listed below for terminology used in Table 8 and Table 3.
Summary Table of Changes Table 1. Summary Table of Changes (Sheet 1 of 6) Stepping No. Status Errata D1 8 CF1 X No Fix Core Frequencies at or Below the DRAM DDR Frequency May Result in Unpredictable System Behavior. CF2 X No Fix DWORD Aligned XOR DMA Sources May Prevent Further DMA XOR Progress. CF3 X No Fix Rank Sparing May Cause an Extended System Stall. CF4 X No Fix Intel® QuickData Technology DMA Lock Quiescent Flow Causes DMA State Machine to Hang.
Summary Table of Changes Table 1. Summary Table of Changes (Sheet 2 of 6) Stepping No. Status Errata D1 CF29 X No Fix The Integrated Memory Controller does not Enforce CKE High For tXSDLL DCLKs After Self-Refresh. CF30 X No Fix Intel® QuickData Technology DMA Suspend does not Transition From ARMED to HALT State. CF31 X No Fix Routing Intel® High Definition Audio Traffic Through VC1 May Result in System Hang. CF32 X No Fix Patrol Scrubbing does not Skip Ranks Disabled After DDR Training.
Summary Table of Changes Table 1. Summary Table of Changes (Sheet 3 of 6) Stepping No.
Summary Table of Changes Table 1. Summary Table of Changes (Sheet 4 of 6) Stepping No. Status Errata D1 CF84 X No Fix RDMSR of IA32_PERFEVTSEL4-7 May Return an Incorrect Result CF85 X No Fix MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang CF86 X No Fix PCMPESTRI, PCMPESTRM, VPCMPESTRI and VPCMPESTRM Always Operate With 32-bit Length Registers CF87 X No Fix Clock Modulation Duty Cycle Cannot Be Programmed to 6.
Summary Table of Changes Table 1. Summary Table of Changes (Sheet 5 of 6) Stepping No.
Summary Table of Changes Table 1. Summary Table of Changes (Sheet 6 of 6) Stepping No. Status Errata D1 Table 2.
BIOS ACM Errata Summary BIOS ACM Errata Summary Table 5. Intel® Xeon® Processor E7 v2 Product Family BIOS ACM Errata Release No.
SINIT ACM Errata Summary SINIT ACM Errata Summary Table 6. Intel® Xeon® Processor E7 v2 Product Family SINIT ACM Errata Release No.
Identification Information Identification Information Component identification The Ivy Bridge-EX Processor stepping can be identified by the following register contents. Table 7. Intel® Xeon® Processor E7 v2 Product Family signature/version Reserved Extended family1 Extended model2 Reserved Processor type3 Family code4 Model number5 Stepping ID6 31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0 00000000b 0011b 00b 0110b 1110b D1=0111b Notes: 1.
Identification Information Component Marking The Ivy Bridge-EX Processor can be identified by the following component markings: Figure 1. Processor top-side marking (example) Legend: Mark text (production mark): GRP1LINE1:i{M}{C} YY GRP1LINE2:SUB-BRAND PROC# GRP1LINE3:SSPEC SPEED GRP1LINE4:XXXXX GRP1LINE5:{FPO} {e4} Table 8.
Identification Information Table 8. S-spec number Intel® Xeon® Processor E7 v2 Product Family identification (Sheet 2 of 2) Processor stepping CPUID Core frequency (GHz)/ Intel® QuickPath Interconnect (GT/s)/ Intel® SMI (GT/s) Number of cores Cache size (MB) Number of supported sockets R1H0 D1 0x0306E7 2.0 GHz / 7.2 GT/s / 2.13 GT/s 8 16 4 R1FD D1 0x0306E7 1.9 GHz / 6.4 GT/s / 2.13 GT/s 6 12 4 R1NR D1 0x0306E7 2.8 GHz / 8 GT/s / 2.6 GT/s 15 37.
Errata Errata CF1 Core Frequencies at or Below the DRAM DDR Frequency May Result in Unpredictable System Behavior. Problem: The Enhanced Intel SpeedStep® Technology can dynamically adjust the core operating frequency to as low as 1200 MHz. Due to this erratum, under complex conditions and when the cores are operating at or below the DRAM DDR frequency, unpredictable system behavior may result.
Errata CF4 Intel® QuickData Technology DMA Lock Quiescent Flow Causes DMA State Machine to Hang. Problem: The lock quiescent flow is a means for an agent to gain sole ownership of another agent's resources by preventing other devices from sending transactions. Due to this erratum, during the lock quiescent flow, the Intel® QuickData Technology DMA read and write queues are throttled simultaneously.
Errata CF8 PCIe* TPH Attributes May Result in Unpredictable System Behavior. Problem: TPH (Transactions Processing Hints) are optional aids to optimize internal processing of PCIe* transactions. Due to this erratum, certain transactions with TPH attributes may be misdirected, resulting in unpredictable system behavior. Implication: Use of the TPH feature may affect system stability. Workaround: A BIOS workaround has been identified.
Errata Workaround: None Status: For the affected steppings, see the “Summary Table of Changes”. CF13 A PECI RdPciConfigLocal Command Referencing a Non-Existent Device May Return an Unexpected Value. Problem: Configuration reads to nonexistent PCI configuration registers should return 0FFFF_FFFFH. Due to this erratum, when the PECI RdPciConfigLocal command references a nonexistent PCI configuration register, the value 0000_0000H may be returned instead of the expected 0FFFF_FFFFH.
Errata report that status, but rather report the normal “Waiting for Physical Layer Ready” (0000b). Implication: There is no known problem with this behavior since there is no usage model that relies on polling of the link_init_status state in the “Waiting for Physical Layer Ready” versus “Internal Stall Link Initialization” state, and it only advertises the “Internal Stall Link Initialization” state for a brief period of time during Link Layer Initialization. Workaround: None identified.
Errata CF21 Functionally Benign PCIe* Electrical Specification Violation Compendium. Problem: Violations of PCIe* electrical specifications listed in the table below have been observed. Implication: Specification Violation Description Deemphasis ratio limit: -3.5±0.5 dB Ave: -3.8 dB, Min: -4.09 dB At 5 GT/s operation, the receiver must tolerate AC common mode voltage of 300 mV (peak-to-peak) and must tolerate 78.1 ps jitter.
Errata CF24 Long latency Transactions Can Cause I/O Devices On The Same Link to Time Out. Problem: Certain long latency transactions - for example, master aborts on inbound traffic, locked transactions, peer-to-peer transactions, or vendor defined messages - conveyed over the PCIe* and DMI2 interfaces can block the progress of subsequent transactions for extended periods. In certain cases, these delays may lead to I/O device timeout that can result in device error reports and/or device off-lining.
Errata Implication: Using DRAM RAPL to regulate the memory subsystem power to a very low level may cause platform instability. Workaround: It is possible for the BIOS to contain processor configuration data and code changes as a workaround for this erratum. the latest version of the BIOS spec update. Status: For the affected steppings, see the “Summary Table of Changes”. CF28 TSOD-Related SMBus Transactions may not Complete When Package C-States are Enabled.
Errata CF31 Routing Intel® High Definition Audio Traffic Through VC1 May Result in System Hang. Problem: When bit 9 in the IIOMISCCTRL CSR (Bus 0; Device 5; Function 0; Offset 1C0H) is set, VCp inbound traffic (Intel® HD Audio) is routed through VC1 to optimize isochronous traffic performance. Due to this erratum, VC1 may not have sufficient bandwidth for all traffic routed through it; overflows may occur. Implication: This erratum can result in lost completions that may cause a system hang.
Errata CF35 An Interrupt Recognized Prior to First Iteration of REP MOVSB/STOSB May Result EFLAGS.RF Being Incorrectly Set Problem: If a REP MOVSB/STOSB is executed and an interrupt is recognized prior to completion of the first iteration of the string operation, EFLAGS may be saved with RF=1 even though no data has been copied or stored. The Software Developer’s Manual states that RF will be set to 1 for such interrupt conditions only after the first iteration is complete.
Errata CF39 Unexpected #UD on VZEROALL/VZEROUPPER Problem: Execution of the VZEROALL or VZEROUPPER instructions in 64-bit mode with VEX.W set to 1 may erroneously cause a #UD (invalid-opcode exception). Implication: The affected instructions may produce unexpected invalid-opcode exceptions in 64-bit mode. Workaround: Compilers should encode VEX.W = 0 for the VZEROALL and VZEROUPPER instructions. Status: For the affected steppings, see the “Summary Table of Changes”.
Errata Implication: The INVVPID instruction may fail to invalidate translations for linear addresses that set bits in the range 63:32. Because this erratum applies only to executions outside 64-bit mode, it applies only to attempts by a 32-bit virtual-machine monitor (VMM) to invalidate translations for a 64-bit guest. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the affected steppings, see the “Summary Table of Changes”.
Errata CF47 Concurrently Changing the Memory Type and Page Size May Lead to a System Hang Problem: Under a complex set of microarchitectural conditions, the system may hang if software changes the memory type and page size used to translate a linear address while a TLB (Translation Lookaside Buffer) holds a valid translation for that linear address. Implication: Due to this erratum, the system may hang. Intel has not observed this erratum with any commercially available software.
Errata Workaround: Software should avoid crossing page boundaries from WB or WC memory type to UC, WP or WT memory type within a single REP MOVS or REP STOS instruction that will execute with fast strings enabled. Status: For the affected steppings, see the “Summary Table of Changes”.
Errata • SMI is pending while a lower priority event interrupts • A REP I/O read • A I/O read that redirects to MWAIT Implication: SMM handlers may get false IO_SMI indication. Workaround: The SMM handler has to evaluate the saved context to determine if the SMI was triggered by an instruction that read from an I/O port. The SMM handler must not restart an I/O instruction if the platform has not been configured to generate a synchronous SMI for the recorded I/O port address.
Errata However, if the preempting lower priority faults are resolved by the operating system and the instruction retried, a #GP fault will occur. Implication: Software may observe a lower-priority fault occurring before or in lieu of a #GP fault. Instructions of greater than 15 bytes in length can only occur if redundant prefixes are placed before the instruction. Workaround: None identified. Status: For the affected steppings, see the “Summary Table of Changes”.
Errata SAL/SAR/SHL/SHR, SHLD, SHRD, SUB, XOR, and XADD) causes a page fault or an EPTinduced VM exit, the value saved for EFLAGS may incorrectly contain the arithmetic flag values that the EFLAGS register would have held had the instruction completed without fault or VM exit. For page faults, this can occur even if the fault causes a VM exit or if its delivery causes a nested fault. Implication: None identified.
Errata Status: For the affected steppings, see the “Summary Table of Changes”. CF67 LER MSRs May be Unreliable Problem: Due to certain internal processor events, updates to the LER (Last Exception Record) MSRs, MSR_LER_FROM_LIP (1DDH) and MSR_LER_TO_LIP (1DEH), may happen when no update was expected. Implication: The values of the LER MSRs may be unreliable. Workaround: None Identified. Status: For the affected steppings, see the “Summary Table of Changes”.
Errata CF71 #GP on Segment Selector Descriptor That Straddles Canonical Boundary May Not Provide Correct Exception Error Code Problem: During a #GP (General Protection Exception), the processor pushes an error code on to the exception handler’s stack. If the segment selector descriptor straddles the canonical boundary, the error code pushed onto the stack may be incorrect. Implication: An incorrect error code may be pushed onto the stack.
Errata • Enhanced Intel SpeedStep® Technology • T-state (Thermal Monitor states) • S1-state (ACPI package sleep state) • C1E (Enhanced C1 Low Power state) • Adaptive Thermal Throttling Implication: When the LBRs, BTM or BTS are enabled, some records may have incorrect branch “From” addresses for the first branch after a transition of Enhanced Intel SpeedStep Technology, T-states, S-states, C1E, or Adaptive Thermal Throttling. Workaround: None identified.
Errata Workaround: None identified. Status: For the affected steppings, see the “Summary Table of Changes”. CF79 A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in Certain Conditions Problem: Under specific internal conditions, if software tries to write the IA32_FIXED_CTR1 MSR (30AH) a value that has all bits [31:1] set while the counter was just about to overflow when the write is attempted (i.e.
Errata Workaround: None identified. Status: For the affected steppings, see the “Summary Table of Changes”. CF83 During Package Power States Repeated PCIe* and/or DMI L1 Transitions May Cause a System Hang Problem: Under a complex set of internal conditions and operating temperature, when the processor is in a deep power state (package C3, C6 or C7) and the PCIe and/or DMI links are toggling in and out of L1 state, the system may hang. Implication: Due to this erratum, the system may hang.
Errata Status: For the affected steppings, see the “Summary Table of Changes”. CF88 Processor May Livelock During On Demand Clock Modulation Problem: The processor may livelock when (1) a processor thread has enabled on demand clock modulation via bit 4 of the IA32_CLOCK_MODULATION MSR (19AH) and the clock modulation duty cycle is set to 12.
Errata CF90 Virtual-APIC Page Accesses with 32-Bit PAE Paging May Cause a System Crash Problem: If a logical processor has EPT (Extended Page Tables) enabled, is using 32-bit PAE paging, and accesses the virtual-APIC page then a complex sequence of internal processor micro-architectural events may cause an incorrect address translation or machine check on either logical processor. Implication: This erratum may result in unexpected faults, an uncorrectable TLB error logged in IA32_MC2_STATUS.
Errata CF95 The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not Updated After a UC Error is Logged Problem: When a UC (uncorrected) error is logged in the IA32_MC0_STATUS MSR (401H), corrected errors will continue to update the lower 14 bits (bits 51:38) of the Corrected Error Count. Due to this erratum, the sticky count overflow bit (bit 52) of the Corrected Error Count will not get updated after a UC error is logged.
Errata CF99 Intel® QuickData Technology DMA Access to Invalid Memory Address May Cause System Hang Problem: When an Intel QuickData Technology DMA access request references an invalid memory address, the channel generating the request may fail to abort the invalid address access and cause all channels to hang. Implication: An Intel QuickData Technology DMA access to an invalid memory address may cause all channels to hang. Workaround: None identified.
Errata the compliance patterns should be based on the maximum data rate supported. Due to this erratum, the port may select an 8GT/s data rate and associated de-emphasis level during compliance testing mode. Implication: When doing PCIe load board compliance testing, the DMI port may transmit using 8 GT/s data rate and de-emphasis levels. Workaround: None identified. Status: For the affected steppings, see the “Summary Table of Changes”.
Errata CF109 PCIe* Header of a Malformed TLP is Logged Incorrectly Problem: If a PCIe port receives a malformed TLP (Transaction Layer Packet), an error is logged in the UNCERRSTS register (Device 0; Function 0; Offset 14CH and Device 2-3; Function 0-3; Offset 14CH). Due to this erratum, the header of the malformed TLP is logged incorrectly in the HDRLOG register (Device 0; Function 0; Offset 164H and Device 2-3; Function 0-3; Offset 164H).
Errata Implication: Due to Intel® Turbo Boost Technology using the Power Meter to compare instantaneous power consumption to the rated TDP, the core frequency in P0 may set to a ratio where the processor exceeds its rated TDP. Further, using the average power limit facility (RAPL) may cause the processor to run at a power consumption level that is higher than expected. Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Errata condition: IOH will set Command Completed bit after delivering the new commands written in the Slot Controller register (offset A8h) to VPP. The IOH detects new commands written in Slot Control register by checking the change of value for Power Controller Control (bit[10]), Power Indicator Control (bits[9:8]), Attention Indicator Control (bits[7:6]), or Electromechanical Interlock Control (bit[11]) fields.
Errata Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the affected steppings, see the “Summary Table of Changes”. CF122 Surprise Down Error Status is Not Set Correctly on DMI Port Problem: Due to this erratum, the Surprise_down_error_status (UNCERRSTS Device 0; Function 0; Offset 0x14C; bit 5) is not set to 1 when DMI port detects a surprise down error. Implication: Surprise down errors will not be logged for the DMI port.
Errata CF127 RTID_POOL_CONFIG Registers Incorrectly Behave as a Read-Write Registers Problem: The RTID_POOL_CONFIG CSRs (Device 12; Function 0-7; Offset ACH and Device 13, Function 0-6; Offset ACH) were intended to be Read-Only. Due to this erratum, these registers behave incorrectly as Read-Write. Implication: Writes to the RTID_POOL_CONFIG CSRs may lead to unexpected results. Workaround: None identified.
Errata Workaround: A BIOS code change has been identified and may be implemented as a workaround for this erratum. Status: For the affected steppings, see the “Summary Table of Changes”. CF132 Configuring PCIe* Port 3a as an NTB Disables EOI Forwarding to Port 2a Problem: Configuring PCIe Port 3a as an NTB (non-transparent bridge) requires disabling EOI (End Of Interrupt) broadcast forwarding to this port by setting bit 26 of MISCCTRLSTS CSR (Bus 0; Device 3; Function 0; Offset 188H) to 0.
Errata CF136 Spurious Patrol Scrub Errors May Be Reported During Exit From Deep Package C-States Problem: When exiting from Package C3 or deeper, spurious Memory Scrubbing Errors may be reported with IA32_MC(13-16)_STATUS.MCACOD with a value of 0000_0000_1100_CCCCb (where CCCC is the channel number). Implication: The patrol scrub errors reported when this erratum occurs are uncorrectable and may result in a system reset.
Errata Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the affected steppings, see the “Summary Table of Changes”. CF141 Intel ® QuickData Technology DMA Engine Read Request that Receives a Master Abort or Completer Abort Will Hang Problem: If Intel ® QuickData Technology DMA receives a read completion with a Master Abort or Completer Abort completion, it will cause a system hang. Implication: Due to this erratum, the system may hang.
Errata CF145 PCIe* Type 1 VDMs May be Silently Dropped Problem: Due to this erratum, a PCIe Type 1 VDMs (Vendor Defined Message) is silently dropped unless the vendor ID is the MCTP (Management Component Transport Protocol) value of 0x1AB4. Implication: PCIe Type 1 VDMs may be unexpectedly dropped. Intel has not observed this erratum to impact the operation of any commercially available system. Workaround: None identified. Status: For the affected steppings, see the “Summary Table of Changes”.
Errata Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the affected steppings, see the “Summary Table of Changes”. CF150 Intel® VT-d Memory Check Error on an Intel® QuickData Technology Channel May Cause All Other Channels to Master Abort Problem: An Intel QuickData DMA access to Intel® VT-d protected memory that results in a protected memory check error may cause master abort completions on all other Intel QuickData DMA channels.
Errata Status: 56 For the affected steppings, see the “Summary Table of Changes”.
Documentation Changes Documentation Changes This Documentation Changes listed in this section apply to the following documents: • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M • Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B: Instruction Set Reference Manual N-Z • Intel® 64 and IA-32 Architectures Software Developer’s Manual
BIOS ACM Errata BIOS ACM Errata There are no BIOS ACM errata.
SINIT ACM Errata SINIT ACM Errata There are no SINIT ACM errata.
SINIT ACM Errata 60 Intel® Xeon® Processor E7 v2 Product Family Specification Update January 2015
