Intel® CoreTM Duo Processor and Intel® CoreTM Solo Processor on 65 nm Process Specification Update June 2009 Revision 020
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Contents Revision History ...................................................................................................................4 Preface ...............................................................................................................................6 Summary Tables of Changes ..................................................................................................8 Identification Information ...............................................................................
Revision History Revision History Document Number Revision Description Date 309222 -001 Initial release January 2006 309222 -002 • Updated Processor Identification (Table 1) April 2006 309222 -003 • Added Errata AE35-AE40 May 2006 • Updated Errata A14 and AE29 • Updated Processor Identification (Table 1) 309222 -004 • Added Errata AE41-AE46 June 2006 • Updated Processor Identification (Table 1) • Updated Description for Code ‘A’ in Summary Table of Changes 309222 -005 • Added Errata A
Revision History 309222 -014 • Updated Stepping Codes Used in Summary Table November 2007 • Updated Erratum AE34 • Added Erratum AE83 309222 -015 • Added Specification Clarification AE2 January 2008 • Updated Stepping Codes Used in Summary Table 309222 -016 • Updated Erratum AE32 February 2008 • Updated Erratum AE60 309222 -017 • Updated Stepping Codes Used in Summary Table July 2008 309222 -018 • Added Erratum AE84 October 2008 • Updated Stepping Codes Used in Summary Table 309222 -01
Preface Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
Preface Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics (e.g., core speed, L2 cache size, package type, etc.) as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number Errata are design defects or errors.
Summary Tables of Changes Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed Processor steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
Summary Tables of Changes Note: Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel’s microprocessor Specification Updates: A= Dual-Core Intel® Xeon® processor 7000 sequence C= Intel® Celeron® processor D= Dual-Core Intel® Xeon® processor 2.
Summary Tables of Changes AK = Intel® Core™2 Extreme quad-core processor QX6000Δ sequence and Intel® Core™2 Quad processor Q6000Δ sequence AL = Dual-Core Intel® Xeon® processor 7100 series AM = Intel® Celeron® processor 400 sequence AN = Intel® Pentium® dual-core processor AO = Quad-Core Intel® Xeon® processor 3200 series AP = Dual-Core Intel® Xeon® processor 3000 series AQ = Intel® Pentium® dual-core desktop processor E2000 sequence AR = Intel® Celeron processor 500 series AS = Intel® Xeo
Summary Tables of Changes Number Stepping Plans ERRATA C0 D0 Dual Core Only AE1 X X No Fix FST Instruction with Numeric and Null Segment Exceptions May Take Numeric Exception with Incorrect FPU Operand Pointer AE2 X X No Fix Code Segment Limit Violation May Occur on 4-Gbyte Limit Check AE3 Errata – Removed AE4 X X No Fix REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types May Use an Incorrect Data Size or Lead to Memory-Orderi
Summary Tables of Changes Stepping Number 12 Plans C0 D0 Dual Core Only AE21 X X X AE22 X AE23 ERRATA No Fix Disable Execution-Disable Bit (IA32_MISC_ENABLES [34]) Is Shared between Cores X No Fix Last Branch Records (LBR) Updates May Be Incorrect after a Task Switch X X No Fix Address Reported by Machine-Check Architecture (MCA) on Single-Bit L2 ECC Errors May Be Incorrect AE24 X X No Fix Disabling of Single-Step On Branch Operation May Be Delayed following a POPFD Instruction
Summary Tables of Changes Number Stepping C0 D0 AE40 X X AE41 X X AE42 X X AE43 X AE44 X X AE45 X AE46 Plans ERRATA Dual Core Only No Fix A Write to an APIC Register Sometimes May Appear to Have Not Occurred X No Fix IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly X No Fix Simultaneous Access to the Same Page Table Entries by Both Cores May Lead to Unexpected Processor Behavior X Fixed IO_SMI Indication in SMRAM State Save Area May Be Lost X No Fix Logic
Summary Tables of Changes Stepping Number Plans C0 D0 Dual Core Only AE60 X X No Fix An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception AE61 X X No Fix Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update AE62 X X No Fix Values for LBR/BTS/BTM Will Be Incorrect after an Exit from SMM AE63 14 ERRATA Erratum Removed AE64 X
Summary Tables of Changes Number Stepping Plans ERRATA C0 D0 AE81 X X No Fix Store Ordering May be Incorrect between WC and WP Memory Types AE82 X X No Fix Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions AE83 X X No Fix A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to Memory-Ordering Violations AE84 X X No Fix Corruption of CS Segment Register During RSM While Transitioning From Real Mode to Protected Mode Number AE1 Dual Core Only SPECI
Identification Information Identification Information Component Identification via Programming Interface The Intel Core Duo processor and Intel Core Solo processor on 65 nm process can be identified by the following register contents: 1. 2.
Identification Information QDF/SSPEC# Processor # Package Stepping CPUID FSB(MHz) Speed HFM/LFM (GHz) Notes Table 1. Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process Identification Information SL9JP T2700 Micro-FCPGA D-0 06ECh 667 2.33/1.00 3 SL9K4 T2700 Micro-FCBGA D-0 06ECh 667 2.33/1.00 3 SL9JN T2600 Micro-FCPGA D-0 06ECh 667 2.16/1.00 3 SL9K3 T2600 Micro-FCBGA D-0 06ECh 667 2.16/1.00 3 SL9EH T2500 Micro-FCPGA D-0 06ECh 667 2.00/1.
QDF/SSPEC# Processor # Package Stepping CPUID FSB(MHz) Speed HFM/LFM (GHz) Notes Identification Information SL92X T1400 Micro-FCBGA C-0 06E8h 667 1.83/1.00 1,2 SL8VY T1300 Micro-FCPGA C-0 06E8h 667 1.66/1.00 1,2 SL8W3 T1300 Micro-FCBGA C-0 06E8h 667 1.66/1.00 1,2 SL8VW L2400 Micro-FCBGA C-0 06E8h 667 1.66/1.00 6 SL8VX L2300 Micro-FCBGA C-0 06E8h 667 1.50/1.00 6 SL99V U2500 Micro-FCBGA C-0 06E8h 533 1.20/.
Errata Errata AE1. FST Instruction with Numeric and Null Segment Exceptions May Take Numeric Exception with Incorrect FPU Operand Pointer Problem: If execution of an FST (Store Floating Point Value) instruction would generate both numeric and Null segment exceptions, the numeric exceptions may be taken first and with the Null x87 FPU Instruction Operand (Data) Pointer.
Errata AE4. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types May Use an Incorrect Data Size or Lead to Memory-Ordering Violations Problem: Under certain conditions as described in the IA-32 Intel® Architecture Software Developers Manual, section titled Out-of-Order Stores for String Operations in Pentium® 4, Intel® Xeon®, and P6 Family Processors, the processor performs REP MOVS or REP STOS as fast strings.
Errata AE6. Problem: VM Bit Is Cleared on Second Fault Handled by Task Switch from Virtual-8086 (VM86) Following a task switch to any fault handler that was initiated while the processor was in VM86 mode, if there is an additional fault while servicing the original task switch then the VM bit will be incorrectly cleared in EFLAGS, data segments will not be pushed and the processor will not return to the correct mode upon completion of the second fault handler via IRET.
Errata AE9. LTR Instruction May Result in Unexpected Behavior Problem: Under certain circumstances an LTR (Load Task Register) instruction may result in an unexpected behavior if all the following conditions are met: 1. Invalid data selector of the TR (Task Register) resulting with either #GP (General Protection Fault) or #NP (Segment Not Present Fault). 2. GDT (Global Descriptor Table) is not 8-bytes aligned.
Errata AE12. FP Inexact-Result Exception Flag May Not Be Set Problem: When the result of a floating-point operation is not exactly representable in the destination format (1/3 in binary form, for example), an inexact-result (precision) exception occurs. When this occurs, the PE bit (bit 5 of the FPU status word) is normally set by the processor. Under certain rare conditions, this bit may not be set when this rounding occurs.
Errata AE14. Problem: MOV to/from Debug Register Causes Debug Exception When in V86 mode, if a MOV instruction is executed to/from a debug registers, a general-protection exception (#GP) should be generated. However, in the case when the general detect enable flag (GD) bit is set, the observed behavior is that a debug exception (#DB) is generated instead. Implication: With debug-register protection enabled (i.e.
Errata AE17. Problem: Machine Check Exception May Occur When Interleaving Code between Different Memory Types A small window of opportunity exists where code fetches interleaved between different memory types may cause a machine check exception. A complex set of microarchitectural boundary conditions is required to expose this window. Implication: Interleaved instruction fetches between different memory types may result in a machine check exception.
Errata AE20. LOCK# Asserted during a Special Cycle Shutdown Transaction May Unexpectedly Deassert Problem: During a processor shutdown transaction, when LOCK# is asserted and if a DEFER# is received during a snoop phase and the Locked transaction is pipelined on the front side bus (FSB), LOCK# may unexpectedly deassert. Implication: When this erratum occurs, the system may hang during shutdown. Intel has not observed this erratum with any commercially-available systems or software.
Errata AE24. Problem: Disabling of Single-Step On-branch Operation May Be Delayed following a POPFD Instruction Disabling of Single-step On-branch Operation may be delayed, if the following conditions are met: 4. “Single Step On Branch Mode” is enabled (DebugCtlMSR.BTF and EFLAGS.TF are set) 5. POPFD used to clear EFLAGS.TF 6. A jump instruction (JMP, Jcc, etc.
Errata AE27. General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit Violation above 4-G Limit Problem: Memory accesses to flat data segments (base = 00000000h) that occur above the 4-G limit (0ffffffffh) may not signal a #GP fault. Implication: When such memory accesses occur, the system may not issue a #GP fault. Workaround: Software should ensure that memory accesses do not occur above the 4-G limit (0ffffffffh).
Errata AE31. Data Breakpoint/Single Step on MOV SS/POP SS May Be Lost after Entry into SMM Problem: Data Breakpoint/Single Step exceptions are normally blocked for one instruction following MOV SS/POP SS instructions. Immediately after executing these instructions, if the processor enters SMM (System Management Mode), upon RSM (resume from SMM) operation, normal processing of Data Breakpoint/Single Step exceptions is restored.
Errata Status: 30 For the steppings affected, see the Summary Tables of Changes.
Errata AE34. Problem: Pending x87 FPU Exceptions (#MF) following STI May Be Serviced before Higher Priority Interrupts Interrupts that are pending prior to the execution of the STI (Set Interrupt Flag) instruction are normally serviced immediately after the instruction following the STI. An exception to this is if the following instruction triggers a #MF. In this situation, the interrupt should be serviced before the #MF.
Errata AE37. The Processor May Report a #TS Instead of a #GP Fault Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception) instead of a #GP fault (general protection exception). Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP fault. Intel has not observed this erratum with any commercially-available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AE38.
Errata AE40. A Write to an APIC Register Sometimes May Appear to Have Not Occurred Problem: With respect to the retirement of instructions, stores to the uncacheable memorybased APIC register space are handled in a non-synchronized way. For example if an instruction that masks the interrupt flag, e.g.
Errata AE42. Problem: Simultaneous Access to the Same Page Translation Entries by Both Cores May Lead to Unexpected Processor Behavior When the following conditions occur simultaneously, this may create a rare internal condition which may lead to unexpected processor behavior. • One core is updating a page table entry, including the processor setting the Accessed and/or Dirty bits in the PTE as the result of an access • The other core is using the same translation entry.
Errata AE45. Last Exception Record (LER) MSRs May Be Incorrectly Updated Problem: The LASTINTTOIP and LASTINTFROMIP MSRs (1DDH-1DEH) may contain incorrect values after the following events: masked SSE2 floating-point exception, StopClk, NMI and INT.
Errata AE47. Problem: Writing the Local Vector Table (LVT) When an Interrupt Is Pending May Cause an Unexpected Interrupt If a local interrupt is pending when the LVT entry is written, an interrupt may be taken on the new interrupt vector even if the mask bit is set. Implication: An interrupt may immediately be generated with the new vector when a LVT entry is written, even if the new LVT entry has the mask bit set.
Errata AE49. Problem: Counter Enable Bit [22] of IA32_CR_PerfEvtSel0 and IA32_CR_PerfEvtSel1 Do Not Comply with PerfMon (Architectural Performance Monitoring) Specification According to the Architectural Performance Monitoring specification the two PerfMon counters can be disabled/enabled through the corresponding Counter Enable bit [22] of IA32_CR_PerfEvtSel0/1. Due to this erratum, the following occurs: 1. bit [22] of IA32_CR_PerfEvtSel0 enables/disables both counters 2.
Errata AE51. Performance Monitoring Events for Retired Instructions (C0H) May Not Be Accurate Problem: The INST_RETIRED performance monitor may miscount retired instructions as follows: • Repeat string and repeat I/O operations are not counted when a hardware interrupt is received during or after the last iteration of the repeat flow. • VMLAUNCH and VMRESUME instructions are not counted. • HLT and MWAIT instructions are not counted.
Errata AE54. Problem: SSE/SSE2 Streaming Store Resulting in a Self-Modifying Code (SMC) Event May Cause Unexpected Behavior An SSE or SSE2 streaming store that results in a Self-Modifying Code (SMC) event may cause unexpected behavior. The SMC event occurs on a full address match of code contained in L1 cache. Implication: Due to this erratum, any of the following events may occur: 1. A data access break point may be incorrectly reported on the instruction pointer (IP) just before the store instruction.
Errata AE57. Writing Shared Unaligned Data That Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Problem: Software which is written so that multiple agents can modify the same shared unaligned memory location at the same time may experience a memory ordering issue if multiple loads access this shared data shortly thereafter. Exposure to this problem requires the use of a data write which spans a cache line boundary.
Errata AE60. An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception Problem: A MOV SS/POP SS instruction should inhibit all interrupts including debug breakpoints until after execution of the following instruction. This is intended to allow the sequential execution of MOV SS/POP SS and MOV [r/e]SP, [r/e]BP instructions without having an invalid stack during interrupt handling.
Errata Implication: The value of the LBR, BTS, and BTM immediately after an RSM operation should not be used. Workaround: None identified. Status: 42 For the steppings affected, see the Summary Tables of Changes.
Errata AE63. Erratum removed AE64. EFLAGS Discrepancy on Page Faults after a Translation Change Problem: This erratum is regarding the case where paging structures are modified to change a linear address from writable to non-writable without software performing an appropriate TLB invalidation.
Errata AE67. Performance Monitoring Event FP_ASSIST May Not Be Accurate Problem: Performance monitoring event FP_ASSIST (11H) may be inaccurate as assist events will be counted twice per actual assist in the following specific cases: • FADD and FMUL instructions with a Not a Number (NaN) operand and a memory operand • FDIV instruction with zero-operand value in memory.
Errata AE69. Problem: BTM/BTS Branch-From Instruction Address May Be Incorrect for Software Interrupts When BTM (Branch Trace Message) or BTS (Branch Trace Store) is enabled, a software interrupt may result in the overwriting of BTM/BTS branch-from instruction address by the LBR (Last Branch Record) branch-from instruction address. Implication: A BTM/BTS branch-from instruction address may get corrupted for software interrupts. Workaround: None identified.
Errata AE72. Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame Problem: The ENTER instruction is used to create a procedure stack frame. Due to this erratum, if execution of the ENTER instruction results in a fault, the dynamic storage area of the resultant stack frame may contain unexpected values (i.e., residual stack data as a result of processing the fault). Implication: Data in the created stack frame may be altered following a fault on the ENTER instruction.
Errata AE75. Problem: Microcode Updates Performed During VMX Non-root Operation Could Result in Unexpected Behavior When Intel Virtualization Technology is enabled, microcode updates are allowed only during VMX root operations. Attempts to apply microcode updates while in VMX nonroot operation should be silently ignored. Due to this erratum, the processor may allow microcode updates during VMX non-root operations if not explicitly prevented by the host software.
Errata AE77. Problem: Page Access Bit May Be Set Prior to Signaling a Code Segment Limit Fault If code segment limit is set close to the end of a code page, then due to this erratum the memory page Access bit (A Bit) may be set for the subsequent page prior to general protection fault on code segment limit. Implication: When this erratum occurs, a non-accessed page, which is present in memory and follows a page that contains the code segment limit may be tagged as accessed.
Errata AE80. An Asynchronous MCE during a Far Transfer May Corrupt ESP Problem: If an asynchronous machine check occurs during an interrupt, call through gate, FAR RET or IRET and in the presence of certain internal conditions, ESP may be corrupted. Implication: If the MCE (Machine Check Exception) handler is called without a stack switch, then a triple fault will occur due to the corrupted stack pointer, resulting in a processor shutdown. If the MCE is called with a stack switch, e.g.
Errata stores (referred to as “fast strings”) for optimal performance. FXSAVE may also be internally implemented using write combining stores. Due to this erratum, stores of a WB (write back) memory type to a cache line previously written by a preceding fast string/FXSAVE instruction may be observed before string/FXSAVE stores. Implication: A write-back store may be observed before a previous string or FXSAVE related store. Intel has not observed this erratum with any commercially available software.
Specification Changes Specification Changes There are no specification changes in this specification update revision.
Specification Clarifications Specification Clarifications AE2 Enhanced Cache Error Reporting for D0 Stepping Beginning with the D0 stepping, enhanced cache error reporting - as described in Section 14.4 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual (SDM), Volume 3A: System Programming Guide – is supported by the processor. Older steppings use the original cache error reporting scheme. Please see the SDM, Volume 3A, for more details.
Documentation Changes Documentation Changes There are no documentation changes in this specification update revision. Note: Documentation changes for IA-32 Intel® Architecture Software Developer’s Manuals volumes 1, 2A, 2B, 3A and 3B will be posted in a separate document IA-32 Intel® Architecture and Intel® Extended Memory 64 Technology Software Developer’s Manual Documentation Changes. Follow the link below to become familiar with this file.
