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Reference Number: 314553 Revision: 002

Dual-Core Intel® Xeon® Processor

7100 Series

Datasheet

September 2006

Summary of content (128 pages)

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Dual-Core Intel® Xeon® Processor 7100 Series Datasheet September 2006 Reference Number: 314553 Revision: 002
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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Contents 1 Introduction ............................................................................................................ 11 1.1 Terminology ..................................................................................................... 13 1.2 References ....................................................................................................... 14 1.3 State of Data ....................................................................................................
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6.2.6 6.2.7 6.2.8 THERMTRIP# Signal Pin ...........................................................................80 TCONTROL and Fan Speed Reduction ........................................................80 Thermal Diode........................................................................................81 7 Features ..................................................................................................................83 7.1 Power-On Configuration Options ................................
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6-2 6-3 6-4 7-1 7-2 8-1 8-2 8-3 8-4 8-5 8-6 8-7 95W Dual-Core Intel® Xeon® Processor 7100 Series Thermal Profile ....................... 76 Case Temperature (TCASE) Measurement Location ................................................ 77 Thermal Monitor 2 Frequency and Voltage Ordering ............................................... 79 Stop Clock State Machine ................................................................................... 85 Logical Schematic of SMBus Circuitry ........................
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7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 6 Memory Device SMBus Addressing .......................................................................89 Read Byte SMBus Packet ....................................................................................90 Write Byte SMBus Packet ....................................................................................90 Processor Information ROM Data Sections .............................................................
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Revision History Document Number Revision Number Description 314553 001 • Initial Release 314553 002 • • Added 3.
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Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
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Features Machine Check Architecture (MCA) Available at 3.4, 3.33, 3.2, 3.16, 3.0, 2.6 or 2.
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Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
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Introduction 1 Introduction The Dual-Core Intel® Xeon® Processor 7100 Series, Processor Number 7150, 7140, 7130, 7120 and 7110 is a dual core product for multi-processor servers. The Dual-Core Intel Xeon processor 7100 series is a 64-bit server processor utilizing two physical Intel NetBurst® microarchitecture cores in one package.
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Introduction The Dual-Core Intel Xeon processor 7100 series processor supports Intel® 64 as an enhancement to Intel’s IA-32 architecture. This enhancement allows the processor to execute operating systems and applications written to take advantage of the 64-bit extension technology. Further details can be found in the 64-bit Extension Technology Software Developer’s Guide at http://developer.intel.com/technology/64bitextensions/.
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Introduction 1.1 Terminology A ‘#’ symbol after a signal name refers to an active low signal, indicating that a signal is in the asserted state when driven to a low level. For example, when RESET# is low (i.e. when RESET# is asserted), a reset has been requested. Conversely, when NMI is high (i.e. when NMI is asserted), a nonmaskable interrupt request has occurred.
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Introduction Note: I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. • Storage Conditions — Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose.
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Introduction Document Intel Order Number Notes Vcc Voltage Regulator Module (VRM) and Enterprise Voltage Regulator Down (EVRD) 10.2 Design Guidelines 306760 4 VRM 9.1 DC-DC Converter Design Guidelines 306826 4 ATX/ATX12V Power Supply Design Guidelines 5 MPS Power Supply: A Server System Infrastructure (SSI) Specification For Midrange Chassis Power Supplies 6 System Management Bus (SMBus) Specification 7 Notes: 1.
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Introduction 16 Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
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Electrical Specifications 2 Electrical Specifications 2.1 Front Side Bus and GTLREF Most Dual-Core Intel® Xeon® Processor 7100 Series processor front side bus (FSB) signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. AGTL+ buffers are open-drain and require pull-up resistors to provide the high logic level and termination.
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Electrical Specifications Figure 2-1. On-Die Front Side Bus Termination End Agent Middle Agent V TT R TT Signal Signal RL R TT - On-die termination resistors for AGTL+ signals R L - Additional on-die resistance implemented for proper noise margin and signal integrity (wired-OR signals only) Note: Some AGTL+ signals do not include on-die termination (RTT) and must be terminated on the motherboard. See Table 2-7 for details regarding these signals. 2.1.
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Electrical Specifications Table 2-1. 166 MHz Core Frequency to Front Side Bus Multiplier Configuration (Sheet 2 of 2) Core Frequency to Front Side Bus Multiplier Core Frequency (166 MHz) A21# A20# A19# A18# A17# A16# 1/19 3.16 GHz H L H H L L 1/20 3.33 GHz H L H L H H 1/21 3.50 GHz H L H L H L Notes: 1. Individual processors operate only at or below the frequency marked on the package. 2. Listed frequencies are not necessarily committed production frequencies. 3.
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Electrical Specifications Table 2-3. 2.1.3 BSEL[1:0] Frequency Table for BCLK[1:0] BSEL1 BSEL0 Function 0 0 RESERVED 0 1 RESERVED 1 0 200 MHz 1 1 166 MHz Phase Lock Loop (PLL) Power and Filter VCCA, VCCIOPLL, and VCCA_CACHE are power sources required by the PLL clock generators on the Dual-Core Intel Xeon processor 7100 series. These are analog PLLs and they require low noise power supplies for minimum jitter. These supplies must be low pass filtered from VTT.
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Electrical Specifications 3. 4. 2.2 fpeak, if existent, should be less than 0.05 MHz. fcore represents the maximum core frequency supported by the platform. Voltage Identification (VID) The VID[5:0] pins supply the encodings that determine the voltage to be supplied by the VCC (the core voltage for the Dual-Core Intel Xeon processor 7100 series) voltage regulator.
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Electrical Specifications Table 2-4. VID5 VID4 Voltage Identification (VID) Definition VID3 VID2 VID1 VID0 VID (V) VID5 VID4 VID3 VID2 VID1 VID0 VID (V) 0 0 1 0 1 0 0.8375 0 1 1 0 1 0 1.2125 1 0 1 0 0 1 0.8500 1 1 1 0 0 1 1.2250 0 0 1 0 0 1 0.8625 0 1 1 0 0 1 1.2375 1 0 1 0 0 0 0.8750 1 1 1 0 0 0 1.2500 0 0 1 0 0 0 0.8875 0 1 1 0 0 0 1.2625 1 0 0 1 1 1 0.9000 1 1 0 1 1 1 1.2750 0 0 0 1 1 1 0.
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Electrical Specifications series is defined by the VRM 9.1 DC-DC Converter Design Guidelines. The voltage set by the CVID pins is the maximum VCACHE voltage allowed by the processor. A minimum VCACHE voltage is provided in Table 2-10. Dual-Core Intel Xeon processor 7100 series with the same front side bus frequency, internal cache sizes, and stepping will have consistent CVID values.
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Electrical Specifications silicon. Most unused AGTL+ inputs may be left as no-connects since AGTL+ termination is provided on the processor silicon. See Table 2-7 for details on AGTL+ signals that do not include on-die termination. Unused active-high inputs should be connected through a resistor to ground (VSS). Unused outputs may be left unconnected. However, this may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing.
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Electrical Specifications the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. AGTL+ asynchronous outputs can become active anytime and include an active pMOS pull-up transistor to assist during the first clock of a low-to-high voltage transition. Implementing a source synchronous data bus requires specifying two sets of timing parameters.
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Electrical Specifications Notes: 1. Refer to Section 5.1 for signal descriptions. Table 2-7. Signal Description Table Signals with RTT1 A[39:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, BNR#, BOOT_SELECT2, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DEP[7:0]#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#, HITM#, ID[7:0]#, IDS#, LOCK#, MCERR#, OOD#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY# Signals with RL BINIT#, BNR#, HIT#, HITM#, MCERR# Notes: 1.
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Electrical Specifications 2.8 Test Access Port (TAP) Connection Due to the voltage levels supported by other components in the TAP logic, Intel recommends that the Dual-Core Intel® Xeon® Processor 7100 Series processor(s) be first in the TAP chain, followed by any other components within the system. Use of a translation buffer to connect to the rest of the chain is recommended unless one of the other components is capable of accepting an input of the appropriate voltage.
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Electrical Specifications 2.10 Processor DC Specifications The following notes apply: • The processor DC specifications in this section are defined at the processor core silicon and not at the package pins unless noted otherwise. • The notes associated with each parameter are part of the specification for that parameter. • Unless otherwise noted, all specifications in the tables apply to all frequencies and cache sizes.
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Electrical Specifications Table 2-10. Voltage and Current Specifications (Sheet 2 of 2) Symbol Parameter Core Freq Min Typ Max VID Unit Notes Cache Thermal Design Current (TDC) All freq 35 A ITT FSB termination current All freq. 4 A 11,15 ITT FSB mid-agent current All freq. 1.3 A 11,16 ICC for SMBus supply All freq. 122.5 mA 11 ICACHE_TDC ISM_VCC 100 ISGnt_CORE ICC Stop-Grant Core All freq. 70 A 6,9 ISGnt_CACHE ICC Stop-Grant Cache All freq.
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Electrical Specifications Figure 2-3. Dual-Core Intel® Xeon® Processor 7100 Series Load Current vs. Time 140 Sustained Current (A) 135 130 125 120 115 110 0 .0 1 0 .1 1 10 100 1000 T im e D u r a tio n (s ) Notes: 1. Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. 2. Not 100% tested. Specified by design characterization.
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Electrical Specifications Table 2-11. VCC Static and Transient Tolerance ICC [A] VCC_MAX [V] VCC_TYP [V] VCC_MIN [V] Notes 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 VID - 0.000 VID - 0.006 VID - 0.013 VID - 0.019 VID - 0.025 VID - 0.031 VID - 0.038 VID - 0.044 VID - 0.050 VID - 0.056 VID - 0.063 VID - 0.069 VID - 0.075 VID - 0.081 VID - 0.087 VID - 0.094 VID - 0.100 VID - 0.106 VID - 0.113 VID - 0.119 VID - 0.125 VID - 0.131 VID - 0.138 VID - 0.
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Electrical Specifications Figure 2-4. VCC Static and Transient Tolerance Icc [A] 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 VID - 0.000 VCC Maximum VID - 0.050 Vcc [V] VID - 0.100 VID - 0.150 VCC Typical VID - 0.200 VCC Minimum VID - 0.250 Notes: 1. The VCC_MIN and VCC_MAX load lines represent static and transient limits. 2. Refer to Table 2-10 for processor VID information for VCC. 3.
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Electrical Specifications Table 2-12. VCACHE Static and Transient Tolerance at the Die Sense Location ICACHE [A] V CACHE_MAX [V] 0 5 10 15 20 25 30 35 40 CVID CVID CVID CVID CVID CVID CVID CVID CVID - 0.000 - 0.021 - 0.043 - 0.064 - 0.085 - 0.106 - 0.128 - 0.149 - 0.170 V CACHE_TYP [V] V CACHE_MIN [V] CVID CVID CVID CVID CVID CVID CVID CVID CVID CVID CVID CVID CVID CVID CVID CVID CVID CVID - 0.041 - 0.065 - 0.089 - 0.113 - 0.138 - 0.162 - 0.186 - 0.210 - 0.234 Notes - 0.082 - 0.109 - 0.136 - 0.
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Electrical Specifications Table 2-13. VCACHE Static and Transient Tolerance at the Board ICACHE [A] V CACHE_MAX [V] 0 5 10 15 20 25 30 35 40 CVID CVID CVID CVID CVID CVID CVID CVID CVID - 0.000 - 0.003 - 0.006 - 0.009 - 0.011 - 0.014 - 0.017 - 0.020 - 0.023 V CACHE_TYP [V] V CACHE_MIN [V] CVID CVID CVID CVID CVID CVID CVID CVID CVID CVID CVID CVID CVID CVID CVID CVID CVID CVID - 0.041 - 0.044 - 0.048 - 0.051 - 0.055 - 0.058 - 0.061 - 0.065 - 0.068 Notes - 0.082 - 0.086 - 0.090 - 0.094 - 0.
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Electrical Specifications Table 2-14. VCC Overshoot Specification Symbol Parameter VOS_MAX TOS_MAX Min Max Units Figure Magnitude of VCC overshoot above VID 0.025 V 2-7 Time duration of VCC overshoot above VID 5 μs 2-7 Figure 2-7. VCC Overshoot Example Waveform 2.10.
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Electrical Specifications Figure 2-8. VCACHE Overshoot Example Waveform Vcache Overshoot Example Waveform Vcache_max after unloading transient Vcache (10 mV per division) VOS_cache TOS_cache Vcache_max prior to unloading transient Time (10 µs per division) Notes: 1. VOS_CACHE is measured overshoot voltage. 2. TOS_CACHEis measured time duration above Vcache_max. 2.10.
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Electrical Specifications Table 2-16. Front Side Bus Differential BCLK Specifications (Sheet 2 of 2) Symbol Parameter Min Typ Max Unit Notes Undershoot - 0.300 N/A N/A V 4 VRBM Ringback Margin 0.200 N/A N/A V 5 VTM Threshold Margin VCROSS-0.100 VCROSS+0.100 V 6 VUS Notes: 1. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 is equal to the falling edge of BCLK1. 2. VHavg is the statistical average of the VH measured by the oscilloscope.
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Electrical Specifications Table 2-19. AGTL+ Signal Group DC Specifications Symbol Parameter Min Max Unit Notes VIL Input Low Voltage 0.0 GTLREF - (0.10 * VTT) V 1,3 VIH Input High Voltage GTLREF + (0.10 * VTT) VTT V 2,3 VOH Output High Voltage 0.90 * VTT VTT V 3 IOL Output Low Current N/A VTT / (0.50 * Rtt_min + RON_min || RL) mA 5 ILI Input Leakage Current N/A 4 Output Leakage Current N/A ± 200 ± 200 µA ILO µA 6 RON Buffer On Resistance 8 12 Ω Notes: 1.
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Electrical Specifications Table 2-21. GTL+ Asynchronous and AGTL+ Asynchronous Signal Group DC Specifications Symbol VIL Parameter Min Max Unit Notes Input Low Voltage 0 GTLREF - (10% * VTT) V 2 VIH Input High Voltage GTLREF + (10% * VTT) VTT V 3,4 VIL A20M#, SMI#, IGNNE# Input Low Voltage 0 0.4 * VTT V 2 VIH A20M#, SMI#, IGNNE# Input High Voltage 0.
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Electrical Specifications 2.11 AGTL+ Front Side Bus Specifications Routing topology recommendations are in the appropriate platform design guide. Termination resistors are not required for most AGTL+ signals because they are integrated into the processor silicon. Valid high and low levels are determined by the input buffers which compare a signal’s voltage with a reference voltage called GTLREF. Table 2-23 lists the GTLREF specifications.
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Mechanical Specifications 3 Mechanical Specifications The Dual-Core Intel Xeon processor 7100 series is packaged in a Flip-Chip Micro Pin Grid Array 6 (FC-mPGA6) package that interfaces with the motherboard via a mPGA604 socket. The package consists of a processor core mounted on a substrate pin-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
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Mechanical Specifications 3.1 Package Mechanical Drawing The package mechanical drawings are shown in Figure 3-2 and Figure 3-3. The drawings include dimensions necessary to design a thermal solution for the processor. These dimensions include: 1. Package reference with tolerances (total height, length, width, etc.) 2. IHS parallelism and tilt 3. Pin dimensions 4. Top-side and back-side component keep-out dimensions 5. Reference datums All drawing dimensions are in millimeters.
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Mechanical Specifications Figure 3-2.
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Mechanical Specifications Figure 3-3.
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Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or pin-side of the package substrate. See Figure 3-2 and Figure 3-3 for keepout zones. 3.
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Mechanical Specifications 3.4 Package Handling Guidelines Table 3-2 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal. Table 3-2. Package Handling Guidelines Parameter Maximum Recommended Notes Shear 356 N [80 lbf] 1, 4, 5 Tensile 156 N [35 lbf] 2, 4, 5 Torque 8 N-m [70 lbf-in] 3, 4, 5 Notes: 1.
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Mechanical Specifications Figure 3-4. Processor Topside Markings Processor Name i(m) ©’05 2D Matrix Includes ATPO and Serial Number (front end mark) Pin 1 Indicator Notes: 1. All characters will be in upper case. 2. Drawing is not to scale. Figure 3-5.
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Mechanical Specifications 3.9 Processor Pin-Out Coordinates Figure 3-6 shows the top view of the processor pin coordinates. The coordinates are referred to throughout the document to identify processor pins. Figure 3-6.
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Pin Listing 4 Pin Listing 4.1 Dual-Core Intel® Xeon® Processor 7100 Series Pin Assignments Section 2.6 contains the front side bus signal groups for the Dual-Core Intel Xeon processor 7100 series (see Table 2-6). This section provides a sorted pin list in Table 4-1 and Table 4-2. Table 4-1 is a listing of all processor pins ordered alphabetically by pin name. Table 4-2 is a listing of all processor pins ordered by pin number. 4.1.1 Pin Listing by Pin Name Table 4-1.
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Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 3 of 16) 50 Table 4-1. Pin Listing by Pin Name (Sheet 4 of 16) Pin Name Pin No. Signal Buffer Type Direction Pin Name Pin No.
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Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 5 of 16) Table 4-1. Pin Listing by Pin Name (Sheet 6 of 16) Pin Name Pin No. Signal Buffer Type Direction Pin Name Pin No.
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Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 7 of 16) 52 Table 4-1. Pin Listing by Pin Name (Sheet 8 of 16) Pin Name Pin No. Signal Buffer Type Direction Pin Name Pin No.
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Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 9 of 16) Pin Name Pin No. Signal Buffer Type VCC G24 VCC VCC Table 4-1. Pin Listing by Pin Name (Sheet 10 of 16) Pin Name Pin No.
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Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 11 of 16) Pin Name Pin No. Signal Buffer Type VCC Y16 Power/Other VCC Y22 VCC Y30 Table 4-1. Pin Listing by Pin Name (Sheet 12 of 16) Pin Name Pin No.
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Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 13 of 16) Pin Name Pin No. Signal Buffer Type VSS H4 VSS VSS Table 4-1. Pin Listing by Pin Name (Sheet 14 of 16) Pin Name Pin No.
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Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 15 of 16) 56 Pin Name Pin No. Signal Buffer Type VSS U4 Power/Other VSS U6 VSS U8 VSS VSS Table 4-1. Pin Listing by Pin Name (Sheet 16 of 16) Pin Name Pin No.
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Pin Listing 4.1.2 Pin Listing by Pin Number Table 4-2.Pin Listing by Pin Number (Sheet 2 of 16) Table 4-2.Pin Listing by Pin Number (Sheet 1 of 16) Pin No. Pin Name Signal Buffer Type Direction A1 VID5 Power/Other Output Pin Name Signal Buffer Type B9 VSS Power/Other A21# Source Sync Input/Output Input/Output Pin No.
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Pin Listing Table 4-2.Pin Listing by Pin Number (Sheet 3 of 16) Table 4-2.Pin Listing by Pin Number (Sheet 4 of 16) Pin No. Pin Name Signal Buffer Type Direction Pin No.
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Pin Listing Table 4-2.Pin Listing by Pin Number (Sheet 5 of 16) Table 4-2.Pin Listing by Pin Number (Sheet 6 of 16) Pin No. Pin Name Signal Buffer Type F4 VCC Power/Other F5 BPM3# Common Clk Input/Output F6 BPM0# Common Clk Input/Output Direction Pin No.
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Pin Listing Table 4-2.Pin Listing by Pin Number (Sheet 7 of 16) Pin No. Pin Name Signal Buffer Type J30 VCC J31 K1 K2 K3 K4 K5 K6 K7 K8 K9 K23 K24 60 Table 4-2.Pin Listing by Pin Number (Sheet 8 of 16) Pin No.
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Pin Listing Table 4-2.Pin Listing by Pin Number (Sheet 9 of 16) Pin No. Pin Name Signal Buffer Type P7 VSS P8 P9 Table 4-2.Pin Listing by Pin Number (Sheet 10 of 16) Pin No.
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Pin Listing Table 4-2.Pin Listing by Pin Number (Sheet 11 of 16) Pin No. Pin Name Signal Buffer Type V28 VCC V29 V30 V31 W1 W2 VSS W3 Reserved 62 Table 4-2.Pin Listing by Pin Number (Sheet 12 of 16) Pin No.
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Pin Listing Table 4-2.Pin Listing by Pin Number (Sheet 13 of 16) Table 4-2.Pin Listing by Pin Number (Sheet 14 of 16) Pin No. Pin Name Signal Buffer Type Direction Pin No.
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Pin Listing Table 4-2.Pin Listing by Pin Number (Sheet 15 of 16) Table 4-2.Pin Listing by Pin Number (Sheet 16 of 16) Pin No. Pin Name Signal Buffer Type Pin No.
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Signal Definitions 5 Signal Definitions 5.1 Signal Definitions Table 5-1. Signal Definitions (Sheet 1 of 8) Name A[39:3]# Type Description 40 I/O A[39:3]# (Address) define a 2 -byte physical memory address space. In subphase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the Dual-Core Intel Xeon processor 7100 series front side bus.
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Signal Definitions Table 5-1. Signal Definitions (Sheet 2 of 8) Name Type Description BINIT# I/O BINIT# (Bus Initialization) may be observed and driven by all processor front side bus agents. If used, BINIT# must connect the appropriate pins of all such agents. If the BINIT# driver is enabled, BINIT# is asserted to signal any bus condition that prevents reliable future operation. If BINIT# observation is enabled during power-on configuration (see Section 7.
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Signal Definitions Table 5-1. Signal Definitions (Sheet 3 of 8) Name BR0# BR[3:1]# Type I/O I Description BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The BREQ[3:0]# signals are interconnected in a rotating manner to individual processor pins. The tables below give the rotating interconnect between the processor and bus signals for 3-load configurations.
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Signal Definitions Table 5-1. Signal Definitions (Sheet 4 of 8) Name Type Description DEP[7:0]# I/O The DEP[7:0]# (data bus ECC protection) signals provide optional ECC protection for the data bus. They are driven by the agent responsible for driving D[63:0]#, and, if ECC is implemented, must connect the appropriate pins of all bus agents which use them. Furthermore, the DBI# pins determine the polarity of the ECC signals. Each pair of 2 ECC signals corresponds to one DBI# signal.
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Signal Definitions Table 5-1. Signal Definitions (Sheet 5 of 8) Name Type Description INIT# I INIT# (Initialization), when asserted, resets integer registers inside all processors without affecting their internal caches or floating-point registers. Each processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion.
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Signal Definitions Table 5-1. Signal Definitions (Sheet 6 of 8) Name Type Description I/O REQ[4:0]# (Request Command) must connect the appropriate pins of all processor front side bus agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB[1:0]#. Refer to the AP[1:0]# signal description for details on parity checking of these signals.
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Signal Definitions Table 5-1. Signal Definitions (Sheet 7 of 8) Name Type Description SMI# I SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, processors save the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler.
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Signal Definitions Table 5-1. Signal Definitions (Sheet 8 of 8) Name Type Description VCC_CACHE_SENSE VSS_CACHE_SENSE O VCC_CACHE_SENSE and VSS_CACHE_SENSE provide isolated, low impedance connections to the processor cache voltage (VCACHE) and ground (VSS). They can be used to sense or measure voltage or ground near the silicon with little noise. VCCIOPLL I VCCIOPLL provides isolated power for digital portion of the internal PLL’s.
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Thermal Specifications 6 Thermal Specifications 6.1 Package Thermal Specifications The Dual-Core Intel Xeon processor 7100 series requires a thermal solution to maintain temperatures within operating limits. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems.
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Thermal Specifications The upper point of the thermal profile consists of the Thermal Design Power (TDP) defined in Table 6-1and the associated TCASE value. The lower point of the thermal profile consists of x = PCONTROL_BASE and y = TCASE_MAX @ PCONTROL_BASE. Pcontrol is defined as the processor power at which TCASE, calculated from the thermal profile, corresponds to the lowest possible value of Tcontrol. This point is associated with the Tcontrol value (see Section 6.2.7).
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Thermal Specifications Figure 6-1. 150W Dual-Core Intel® Xeon® Processor 7100 Series Thermal Profile 70 T CASE_MAX [°C] 65 60 55 50 45 20 40 60 80 100 Power [W] Note: Table 6-2. 120 140 160 y = 0.158 * x + 45 Refer to the Dual-Core Intel® Xeon® Processor 7100 Series Thermal/Mechanical Design Guidelines for system and environmental implementation details.
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Thermal Specifications Figure 6-2. 95W Dual-Core Intel® Xeon® Processor 7100 Series Thermal Profile 65 TCASE_MAX [°C] 60 55 50 45 40 35 -35 -25 -15 -5 5 15 25 35 Pow er [W] 45 55 65 75 85 95 y = 0.158 * x + 45 Notes: 1. Refer to the Dual-Core Intel® Xeon® Processor 7100 Series Thermal/Mechanical Design Guidelines for system and environmental implementation details. 2. The TCONTROL_OFFSET for 95W TDP parts is greater than or equal to 16 °C Table 6-3.
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Thermal Specifications 6.1.2 Thermal Metrology The maximum and minimum case temperatures (TCASE) specified in Table 6-1 are measured at the geometric top center of the processor integrated heat spreader (IHS). Figure 6-3 illustrates the location where TCASE temperature measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the Dual-Core Intel® Xeon® Processor 7100 Series Thermal/Mechanical Design Guidelines. Figure 6-3.
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Thermal Specifications With a thermal solution designed to meet the thermal profile, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable. A thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously.
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Thermal Specifications Figure 6-4. Thermal Monitor 2 Frequency and Voltage Ordering TTM2 Temperature fMAX fTM2 Frequency VNOM VTM2 Vcc Time T(hysteresis) The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled.
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Thermal Specifications 6.2.4 PROCHOT# Signal Pin An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature has reached its factory configured trip point. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.
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Thermal Specifications obtained by reading the IA32_TEMPERATURE_TARGET MSR in the processor. The TCONTROL_OFFSET value that is read from the IA32_TEMPERATURE_TARGET MSR (1A2H) must be converted from Hexadecimal to Decimal and added to a TCONTROL_BASE value of 50°C for 150W TDP parts and added to a TCONTROL_BASE value of 40°C for 95W TDP parts. The Platform Id Bits located in the IA32_PLATFORM_ID MSR (17H) Bits[52:50] may be used by the BIOS to determine the TDP of the processor.
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Thermal Specifications 82 Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
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Features 7 Features 7.1 Power-On Configuration Options Several configuration options can be set by hardware. The Dual-Core Intel Xeon processor 7100 series samples its hardware configuration at reset, on the active-toinactive transition of RESET#. For specifications on these options, refer to Table 7-1. The sampled information configures the processor for subsequent operation. These configuration options can only be changed by another reset. All resets configure the processor.
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Features the bus before allowing the processor to be transitioned into one of the lower processor power states. Refer to the applicable chipset specification and the Cedar Mill Processor Family BIOS Writer’s Guide for more information. 7.2.1 Normal State This is the normal operating state for the processor. 7.2.2 HALT or Enhanced Power Down State The Enhanced HALT power down state is configured and enabled via the BIOS.
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Features Figure 7-1.
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Features While in Stop-Grant state, the processor processes snoops on the front side bus and latches interrupts delivered on the front side bus. The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# is asserted if there is any pending interrupt latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear still cause assertion of PBE#. Assertion of PBE# indicates to system logic that it should return the processor to the Normal state. 7.2.
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Features performance and power requirements of the processor and system. Note that the front side bus is not altered; only the internal core frequency is changed. In order to run at reduced power consumption, the voltage is altered in step with the bus ratio. The following are key features of Enhanced Intel SpeedStep technology: • Voltage/frequency selection is software controlled by writing to processor MSR’s (Model Specific Registers), thus eliminating chipset dependency.
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Features Figure 7-2. Logical Schematic of SMBus Circuitry Note: 7.4.1 Actual implementation may vary. This figure is provided to offer a general understanding of the architecture. All SMBus pull-up and pull-down resistors are 10 kΩ and located on the processor. SMBus Device Addressing Of the addresses broadcast across the SMBus, the memory component claims those of the form “1010XXXZb”. The “XXX” bits are defined by pull-up and pull-down resistors on the system baseboard.
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Features via a 1 kΩ or smaller resistor, or leaving the pins floating to achieve the Hi-Z state. If the system designer wants to drive the SM_TS_A[1:0] pins with logic, the designer must still ensure that the pins are at valid input levels prior to or while the SM_VCC supply ramps up. The system designer must also ensure that their particular implementation does not add excessive capacitance to the address inputs. Excess capacitance at the address inputs may cause address recognition problems.
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Features 7.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions The Processor Information ROM (PIROM) responds to two SMBus packet types: Read Byte and Write Byte. However, since the PIROM is write-protected, it will acknowledge a Write Byte command but ignore the data. The Scratch EEPROM responds to Read Byte and Write Byte commands. Table 7-4 diagrams the Read Byte command. Table 7-5 diagrams the Write Byte command.
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Features Table 7-6.
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Features Table 7-6.
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Features 7.4.3.1 Header To maintain backward compatibility, the Header defines the starting address for each subsequent section of the PIROM. Software should check for the offset before reading data from a particular section of the ROM. Example: Code looking for the cache data of a processor would read offset 05h to find a value of 25h. 25h is the first address within the 'Cache Data' section of the PIROM. 7.4.3.1.
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Features 7.4.3.1.4 PCDA: Processor Core Data Address This location provides the offset to the Processor Core Data Section. Writes to this register have no effect. Offset: 04h Bit 7:0 Description Processor Core Data Address Byte pointer to the Processor Data section 00h: Processor Core Data section not present 01h - 15h: Reserved 16h: Processor Core Data section pointer value 17h-FFh: Reserved 7.4.3.1.5 L3CDA: L3 Cache Data Address This location provides the offset to the L3 Cache Data Section.
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Features 7.4.3.1.7 PNDA: Part Number Data Address This location provides the offset to the Part Number Data Section. Writes to this register have no effect. Offset: 07h Bit Description 7:0 Part Number Data Address Byte pointer to the Part Number Data section 00h: Part Number Data section not present 01h - 37h: Reserved 38h: Part Number Data section pointer value 39h-FFh: Reserved 7.4.3.1.8 TRDA: Thermal Reference Data Address This location provides the offset to the Thermal Reference Data Section.
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Features 7.4.3.1.10 ODA: Other Data Address This location provides the offset to the Other Data Section. Writes to this register have no effect. Offset: 0Ah Bit 7:0 Description Other Data Address Byte pointer to the Other Data section 00h: Other Data section not present 01h - 7Dh: Reserved 7Eh: Other Data section pointer value 7Fh- FFh: Reserved 7.4.3.1.11 RES1: Reserved 1 This locations are reserved. Writes to this register have no effect.
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Features Offset: 0Eh-13h Bit 47:40 Description Character 6 S-SPEC or QDF character or 20h 00h-0FFh: ASCII character 39:32 Character 5 S-SPEC or QDF character or 20h 00h-0FFh: ASCII character 31:24 Character 4 S-SPEC or QDF character 00h-0FFh: ASCII character 23:16 Character 3 S-SPEC or QDF character 00h-0FFh: ASCII character 15:8 Character 2 S-SPEC or QDF character 00h-0FFh: ASCII character 7:0 Character 1 S-SPEC or QDF character 00h-0FFh: ASCII character 7.4.3.2.
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Features 7.4.3.2.3 PDCKS: Processor Data Checksum This location provides the checksum of the Processor Data Section. Writes to this register have no effect. Offset: 15h Bit Description 7:0 Processor Data Checksum One Byte Checksum of the Header Section 00h- FFh: See Section 7.4.4 for calculation of the value 7.4.3.3 Processor Core Data This section contains core silicon-related data. 7.4.3.3.1 CPUID: CPUID This location contains the CPUID, Processor Type, Family, Model and Stepping.
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Features 7.4.3.3.2 RES2: Reserved 2 These locations are reserved. Writes to this register have no effect. Offset: 18h-19h Bit 15:0 Description RESERVED 2 0000h-FFFFh: Reserved 7.4.3.3.3 FSB: Front Side Bus Speed This location contains the front side bus frequency information. Systems may need to read this offset to decide if all installed processors support the same front side bus speed.
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Features 7.4.3.3.5 MCF: Maximum Core Frequency This location contains the maximum core frequency for the processor. The frequency should equate to the markings on the processor and/or the QDF/S-spec speed even if the parts are not limited or locked to the intended speed. Format of this field is in MHz, rounded to a whole number, and encoded in hex format. Writes to this register have no effect. Example: A 3.40 GHz processor will have a value of 0D48h, which equates to 3400 decimal.
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Features Example: For a Dual-Core Intel Xeon processor 7100 series the minimum voltage is 0.991 V = 1.100 V (Min VID) - 0.209 V (Voltage Offset at maximum current). Offset 21 - 22h would contain 03DFh (0991 decimal). Offset: 21h-22h Bit 15:0 Description Minimum Core Voltage 0000h-03DEh: Reserved 03DF: 0.991 V 03E0h-FFFFh: Reserved 7.4.3.3.8 TCASE: TCASE Maximum This location provides the maximum TCASE for the processor. The field reflects temperature in degrees Celsius in hex format.
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Features 7.4.3.4.2 L2SIZE: L2 Cache Size This location contains the size of the level two cache in kilobytes. Writes to this register have no effect. Example: The Dual-Core Intel Xeon processor 7100 series has a 2 MB (2048 KB) L2 cache total (1 MB L2 cache per core). Thus, offset 27 - 28h will contain 0800h. Offset: 27h-28h Bit 15:0 Description L2 Cache Size 0000h-07FFh: Reserved 0800h: 2 MB 0801h-FFFFh: Reserved 7.4.3.4.
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Features 7.4.3.4.5 MINCV: Minimum Cache Voltage This location contains the minimum Cache voltage. This field, rounded to the next thousandth, is in mV and is reflected in hex. The minimum VCACHE reflected in this field is the minimum allowable voltage assuming the FMB maximum current draw for two processors. Writes to this register have no effect. Note: The minimum core voltage value in offset 2D - 2Eh is a single value that assumes the FMB maximum current draw for two processors.
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Features Example: The A-0 and A-1 steppings of the Dual-Core Intel Xeon processor 7100 series utilizes the first revision package (FC-mPGA4). Thus, at offset 32-35h, the data is a space followed by 1.0. In hex, this would be 20, 31, 2E, 30. The B-0 stepping of the Dual-Core Intel Xeon processor 7100 series utilizes the second revision package (FC-mPGA6). Thus, at offset 32-35h, the data is a space followed by 2.0. In hex, this would be 20, 32, 2E, 30.
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Features 7.4.3.6.1 PREV: Package Revision This location contains seven ASCII characters reflecting the Intel part number for the processor. This information is typically marked on the outside of the processor. If the part number is less than 7 characters, a leading space is inserted into the value. The part number should match the information found in the marking specification found in Section 3. Writes to this register have no effect.
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Features 7.4.3.6.3 PSERSIG: Processor Serial/Electronic Signature This location contains a 64-bit identification number. The value in this field is either a serial signature or an electronic signature. Bits 5 & 6 of the Processor Feature Flags (Offset 78h) indicates which signature is present. Intel does not guarantee that each processor will have a unique value in this field. Writes to this register have no effect.
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Features 7.4.3.7.2 RES9: Reserved 9 This location is reserved. Writes to this register have no effect. Offset: 71h-72h Bit 15:0 7.4.3.7.3 Description RESERVED 9 TRDCKS: Thermal Reference Data Checksum This location provides the checksum of the Thermal Reference Data Section. Writes to this register have no effect. Offset: 73h Bit 7:0 Description Thermal Reference Data Checksum One Byte Checksum of the Header Section 00h- FFh: See Section 7.4.4 for calculation of the value 7.4.3.
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Features Offset: 78h Bit 7.4.3.8.3 Description 3 Reserved 2 OEM EEPROM present (set if there is a scratch ROM at offset 80 - FFh) 1 Core VID present (set if there is a VID provided by the processor) 0 L3 Cache present (set if there is a level 3 cache on the processor) PTCI: Processor Thread and Core Information This location contains information regarding the number of cores and threads on the processor. Writes to this register have no effect.
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Features 7.4.3.8.5 TAF: Thermal Adjustment Factors This location contains information on thermal adjustment factors for the processor. This field and it’s details are pending and will be updated in a future revision. Writes to this register have no effect. Offset: 7Bh-7Ch Bit 15:8 7:0 Description Measurement Correction Factor Temperature Target 7.4.3.9 Other Data 7.4.3.9.1 RES10: Reserved 10 These locations are reserved. Writes to this register have no effect. Offset: 7Dh-7Eh Bit 15:0 7.4.3.9.
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Features Checksums are automatically calculated and programmed by Intel. The first step in calculating the checksum is to add each byte from the field to the next subsequent byte. This result is then negated to provide the checksum. Example: For a byte string of AA445Ch, the resulting checksum will be B6h. AA = 10101010 44 = 01000100 5C = 0101100 AA + 44 + 5C = 01001010 Negate the sum: 10110101 +1 = 101101 (B6h) 7.4.
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Features 7.4.7 Thermal Sensor Supported SMBus Transactions The thermal sensor responds to five of the SMBus packet types: Write Byte, Read Byte, Send Byte, Receive Byte, and Alert Response Address (ARA). The Send Byte packet can be used for sending one-shot commands. The Receive Byte packet accesses the register commanded by the last Read Byte packet and can be used to continuously read from a register.
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Features Table 7-13. SMBus Thermal Sensor Command Byte Bit Assignments Command R/W Lock4 RESERVED2 00h N/A N/A RESERVED Ch. 1 Temp. Value1 01h R N 0000 0000 Status Register 1 02h R N Undefined Configuration Register 1 03h R Y 0000 0000 Register Conversion Rate Register RESERVED2 Ch. 1 Temp. High Limit1,4 Ch. 1 Temp.
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Features The default command after reset is to a reserved value (00h). After reset, Receive Byte SMBus packets will return invalid data until another command is sent to the thermal sensor. 7.4.8 SMBus Thermal Sensor Registers 7.4.8.1 Thermal Value Registers Once the SMBus thermal sensor reads a processor thermal diode, it performs an analog to digital conversion and stores the data in a temperature value register.
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Features Table 7-15. SMBus Thermal Sensor Status Register 1 Bit Name Reset State Function 7 (MSB) BUSY N/A 6 RESERVED RESERVED Reserved for future use. 5 RESERVED RESERVED Reserved for future use. 4 R1HIGH 0 If set, indicates the processor core 1 thermal diode high temperature alarm has activated. 3 R1LOW 0 If set, indicates the processor core 1 thermal diode low temperature alarm has activated.
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Features Table 7-17. SMBus Thermal Sensor Configuration Register (Sheet 2 of 2) Bit 7.4.8.5 Name Reset State Function 4 RESERVED RESERVED 3 Remote 1/2 0 Setting this bit to 1 enables the user to read the processor core 2 values from the processor core 1 registers. Default = 0 means Read processor core 1 values from the processor core 1 registers. Always set this bit to 0. 2 Temp Range 0 Setting this bit to 1 enables the extended temperature measurement range (-50 °C to +150 °C).
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Features Table 7-18. SMBus Thermal Sensor Conversion Rate Register Bit 7.4.9 Name Reset State 6 RESERVED RESERVED 5:4 Channel Selector 00 3:0 Conversion Rates 1000 Function Reserved for future use. These bits are used to select the temperature measurement channels. 00 = Round robin 01 = Local Temperature 10 = Processor Core 1 Temperature 11 = Processor Core 2 Temperature Default = 00.
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Boxed Processor Specifications 8 Boxed Processor Specifications 8.1 Introduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels. Future revisions may have solutions that differ from those discussed here. The thermal solution for the boxed Dual-Core Intel Xeon processor 7100 series, for each processor frequency, includes an unattached passive heatsink.
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Boxed Processor Specifications Figure 8-1. Passive Dual-Core Intel® Xeon® Processor 7100 Series Thermal Solution (3U and larger) Note: 1. The heatsink in this image is for reference only. 2. This drawing shows the retention scheme for the boxed processor. 8.2 Mechanical Specifications This section documents the mechanical specifications of the boxed processor passive heatsink. 8.2.1 Boxed Processor Heatsink Dimensions The boxed processor is shipped with an unattached passive heatsink.
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Boxed Processor Specifications Figure 8-2.
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Boxed Processor Specifications Figure 8-3.
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Boxed Processor Specifications Figure 8-4.
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Boxed Processor Specifications Figure 8-5.
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Boxed Processor Specifications Figure 8-6.
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Boxed Processor Specifications Figure 8-7.
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Boxed Processor Specifications 8.2.2 Boxed Processor Heatsink Weight The boxed processor heatsink weight is approximately 530 grams. See Section 3 of this document for details on the processor weight and the Dual-Core Intel® Xeon® Processor 7100 Series Thermal/Mechanical Design Guidelines for the enabled heatsink requirements. 8.2.
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Boxed Processor Specifications 8.3.2 Boxed Processor Contents The boxed processor will include the following items: • Dual-Core Intel Xeon processor 7100 series • Unattached Passive Heatsink with captive screws • Thermal Interface Material (pre-attached) • Warranty / Installation manual with Intel Inside logo The other items listed in Figure 8-1, required with this thermal solution should be shipped with either the chassis or the mainboard.
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Debug Tools Specifications 9 Debug Tools Specifications Please refer to the eXtended Debug Port: Debug Port Design Guide for MP Platforms, and the appropriate platform design guide for more detailed information regarding debug tools specifications. 9.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Dual-Core Intel® Xeon® Processor 7100 Series processor systems.
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Debug Tools Specifications 128 Dual-Core Intel® Xeon® Processor 7100 Series Datasheet