Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2A: Instruction Set Reference, A-M NOTE: The Intel 64 and IA-32 Architectures Software Developer's Manual consists of five volumes: Basic Architecture, Order Number 253665; Instruction Set Reference A-M, Order Number 253666; Instruction Set Reference N-Z, Order Number 253667; System Programming Guide, Part 1, Order Number 253668; System Programming Guide, Part 2, Order Number 253669.
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
CONTENTS PAGE CHAPTER 1 ABOUT THIS MANUAL 1.1 IA-32 PROCESSORS COVERED IN THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 OVERVIEW OF VOLUME 2A AND 2B: INSTRUCTION SET REFERENCE . . . . . . . . . . . . . . . . . . 1.3 NOTATIONAL CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 Bit and Byte Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CONTENTS PAGE 3.1.1.7 Operation Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.1.1.8 Intel® C/C++ Compiler Intrinsics Equivalents Section . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.1.1.9 Flags Affected Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.1.1.10 FPU Flags Affected Section. . . . . . . . . . . . . . . . . . . . . . . . .
CONTENTS PAGE CLTS—Clear Task-Switched Flag in CR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMC—Complement Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMOVcc—Conditional Move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CMP—Compare Two Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CONTENTS PAGE CVTSS2SI—Convert Scalar Single-Prec ision Floating-Point Value to Doubleword Integer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-233 CVTTPD2PI—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers . . . . . . . . . . . . . . . . . . . . 3-236 CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers . . . . . . . . . . . . . . . . . .
CONTENTS PAGE FLD—Load Floating Point Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load Constant . . . . . . . . . . . FLDCW—Load x87 FPU Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLDENV—Load x87 FPU Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FMUL/FMULP/FIMUL—Multiply . . . . . . . . . . . . . . . . . . .
CONTENTS PAGE JMP—Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-501 LAHF—Load Status Flags into AH Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-511 LAR—Load Access Rights Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-513 LDDQU—Load Unaligned Integer 128 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CONTENTS PAGE MOVNTDQ—Store Double Quadword Using Non-Temporal Hint . . . . . . . . . . . . . . . . . MOVNTI—Store Doubleword Using Non-Temporal Hint . . . . . . . . . . . . . . . . . . . . . . . . . MOVNTPD—Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOVNTPS—Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint . . . . . . . . . . . . . . . . . . . . . . . . .
CONTENTS PAGE PAUSE—Spin Loop Hint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57 PAVGB/PAVGW—Average Packed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-58 PCMPEQB/PCMPEQW/PCMPEQD— Compare Packed Data for Equal. . . . . . . . . . . . . . . . 4-61 PCMPGTB/PCMPGTW/PCMPGTD—Compare Packed Signed Integers for Greater Than . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CONTENTS PAGE PUSH—Push Word, Doubleword or Quadword Onto the Stack . . . . . . . . . . . . . . . . . . . PUSHA/PUSHAD—Push All General-Purpose Registers. . . . . . . . . . . . . . . . . . . . . . . . . . PUSHF/PUSHFD—Push EFLAGS Register onto the Stack . . . . . . . . . . . . . . . . . . . . . . . . PXOR—Logical Exclusive OR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RCL/RCR/ROL/ROR-—Rotate . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CONTENTS PAGE SWAPGS—Swap GS Base Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-358 SYSCALL—Fast System Call. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-360 SYSENTER—Fast System Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-362 SYSEXIT—Fast Return from Fast System Call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CONTENTS PAGE APPENDIX A OPCODE MAP A.1 USING OPCODE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.2 KEY TO ABBREVIATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 A.2.1 Codes for Addressing Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 A.2.2 Codes for Operand Type . . . . .
CONTENTS PAGE B.2.1 B.3 B.4 B.5 B.5.1 B.5.2 B.5.3 B.6 B.7 B.8 B.8.1 B.9 B.10 B.11 B.12 B.13 General Purpose Instruction Formats and Encodings for 64-Bit Mode . . . . . . . . . . . . . B-24 PENTIUM® PROCESSOR FAMILY INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . B-53 64-BIT MODE INSTRUCTION ENCODINGS FOR SIMD INSTRUCTION EXTENSIONS . . . . . . B-54 MMX INSTRUCTION FORMATS AND ENCODINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-54 Granularity Field (gg) . . . . . . . .
CONTENTS PAGE Figure 3-13. Figure 3-14. Figure 3-15. Figure 3-16. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 4-6. Figure 4-7. Figure 4-8. Figure 4-9. Figure 4-10. Figure 4-11. Figure 4-12. Figure 4-13. Figure 4-14. Figure 4-15. Figure 4-16. Figure 4-17. Figure 4-18. Figure A-1. Figure B-1. HSUBPS—Packed Single-FP Horizontal Subtract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-445 MOVDDUP—Move One Double-FP and Duplicate. . . . . . . . . . . . . . . . . . . . . . . .
CONTENTS PAGE Table 3-13. Table 3-14. Table 3-15. Table 3-16. Table 3-17. Table 3-18. Table 3-19. Table 3-20. Table 3-21. Table 3-22. Table 3-23. Table 3-24. Table 3-25. Table 3-26. Table 3-27. Table 3-28. Table 3-29. Table 3-30. Table 3-31. Table 3-32. Table 3-33. Table 3-34. Table 3-35. Table 3-36. Table 3-37. Table 3-38. Table 3-39. Table 3-40. Table 3-41. Table 3-42. Table 3-43. Table 3-44. Table 3-45. Table 3-46. Table 3-47. Table 3-48. Table 3-49. Table 3-50. Table 3-51. Table 3-52. Table 3-53.
CONTENTS PAGE Table 3-60. Table 3-61. Table 3-62. Table 3-63. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table A-1. Table A-2. Table A-3. Table A-4. Table A-5. Table A-6. Table A-7. Table A-8. Table A-9. Table A-10. Table A-11. Table A-12. Table A-13. Table A-14. Table A-15. Table A-16. Table A-17. Table A-18. Table A-19. Table A-20. Table A-21. Table A-22. Table B-1. Table B-2. Table B-4. Table B-3. Table B-5. Table B-6. Table B-7. Table B-8. Table B-9. Table B-10. Table B-11.
CONTENTS PAGE Table B-16. Table B-17. Table B-18. Table B-19. Table B-20. Table B-21. Table B-22. Table B-23. Table B-24. Table B-25. Table B-26. Table B-27. Table B-28. Table B-29. Table B-30. Table B-31. Table B-32. Table B-33. Table B-34. Table B-35. Table C-1. Table C-2. xviii Vol. 2A Pentium Processor Family Instruction Formats and Encodings, Non-64-Bit Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CHAPTER 1 ABOUT THIS MANUAL The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 2A & 2B: Instruction Set Reference (order numbers 253666 and 253667) are part of a set that describes the architecture and programming environment of all Intel 64 and IA-32 architecture processors. Other volumes in this set are: • The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture (Order Number 253665).
ABOUT THIS MANUAL • • Intel® CoreTM2 Duo processor Intel® Xeon® processor 5100 series P6 family processors are IA-32 processors based on the P6 family microarchitecture. This includes the Pentium® Pro, Pentium® II, Pentium® III, and Pentium® III Xeon® processors. The Pentium® 4, Pentium® D, and Pentium® processor Extreme Editions are based on the Intel NetBurst® microarchitecture. Most early Intel® Xeon® processors are based on the Intel NetBurst® microarchitecture.
ABOUT THIS MANUAL generated. The instructions are arranged in alphabetical order. General-purpose, x87 FPU, Intel MMX™ technology, SSE/SSE2/SSE3 extensions, and system instructions are included. Chapter 4 — Instruction Set Reference, N-Z. Continues the description of IA-32 instructions started in Chapter 3. It provides the balance of the alphabetized list of instructions and starts Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B. Chapter 5 — VMX Instruction Reference.
ABOUT THIS MANUAL Highest Address 31 24 23 Byte 3 Data Structure 8 7 16 15 Byte 2 Byte 1 0 Byte 0 Bit offset 28 24 20 16 12 8 4 0 Lowest Address Byte Offset Figure 1-1. Bit and Byte Order 1.3.2 Reserved Bits and Software Compatibility In many register and memory layout descriptions, certain bits are marked as reserved. When bits are marked as reserved, it is essential for compatibility with future processors that software treat these bits as having a future, though unknown, effect.
ABOUT THIS MANUAL • When loading a register, always load the reserved bits with the values indicated in the documentation, if any, or reload them with values previously read from the same register. NOTE Avoid any software dependence upon the state of reserved bits in IA-32 registers. Depending upon the values of reserved register bits will make software dependent upon the unspecified manner in which the processor handles these bits.
ABOUT THIS MANUAL Base 2 (binary) numbers are represented by a string of 1s and 0s, sometimes followed by the character B (for example, 1010B). The “B” designation is only used in situations where confusion as to the type of number might arise. 1.3.5 Segmented Addressing The processor uses byte addressing. This means memory is organized and accessed as a sequence of bytes. Whether one or more bytes are being accessed, a byte address is used to locate the byte or bytes in memory.
ABOUT THIS MANUAL 1.3.7 A New Syntax for CPUID, CR, and MSR Values Obtain feature flags, status, and system information by using the CPUID instruction, by checking control register bits, and by reading model-specific registers. We are moving toward a new syntax to represent this information. See Figure 1-2.
ABOUT THIS MANUAL 1.4 RELATED LITERATURE Literature related to Intel 64 and IA-32 processors is listed on-line at: http://developer.intel.com/products/processor/index.htm Some of the documents listed at this web site can be viewed on-line; others can be ordered. The literature available is listed by Intel® processor and then by the following literature types: applications notes, data sheets, manuals, papers, and specification updates.
CHAPTER 2 INSTRUCTION FORMAT This chapter describes the instruction format for all Intel 64 and IA-32 processors. The instruction format for protected mode, real-address mode and virtual-8086 mode is described in Section 2.1. Increments provided for IA-32e mode and its submodes are described in Section 2.2. 2.1 INSTRUCTION FORMAT FOR PROTECTED MODE, REAL-ADDRESS MODE, AND VIRTUAL-8086 MODE The Intel 64 and IA-32 architectures instruction encodings are subsets of the format shown in Figure 2-1.
INSTRUCTION FORMAT 2.1.1 Instruction Prefixes Instruction prefixes are divided into four groups, each with a set of allowable prefix codes. For each instruction, one prefix may be used from each of four groups (Groups 1, 2, 3, 4) and be placed in any order.
INSTRUCTION FORMAT The LOCK prefix (F0H) forces an operation that ensures exclusive use of shared memory in a multiprocessor environment. See “LOCK—Assert LOCK# Signal Prefix” in Chapter 3, “Instruction Set Reference, A-M,” for a description of this prefix. Repeat prefixes (F2H, F3H) cause an instruction to be repeated for each element of a string. Use these prefixes only with string instructions (MOVS, CMPS, SCAS, LODS, STOS, INS, and OUTS).
INSTRUCTION FORMAT • A mandatory prefix (66H), an escape opcode byte, plus two additional opcode bytes (same as previous bullet) For example, PHADDW for XMM registers consists of the following sequence: 66 0F 38 01. The first byte is the mandatory prefix. Valid opcode expressions are defined in Appendix A and Appendix B. 2.1.3 ModR/M and SIB Bytes Many instructions that refer to an operand in memory have an addressing-form specifier byte (called the ModR/M byte) following the primary opcode.
INSTRUCTION FORMAT ModR/M byte are in Table 2-1 and 32-bit addressing forms are in Table 2-2. Table 2-3 shows 32-bit addressing forms specified by the SIB byte. In cases where the reg/opcode field in the ModR/M byte represents an extended opcode, valid encodings are shown in Appendix B. In Table 2-1 and Table 2-2, the Effective Address column lists 32 effective addresses that can be assigned to the first operand of an instruction by using the Mod and R/M fields of the ModR/M byte.
INSTRUCTION FORMAT Table 2-1.
INSTRUCTION FORMAT Table 2-2.
INSTRUCTION FORMAT Table 2-3 is organized to give 256 possible values of the SIB byte (in hexadecimal). General purpose registers used as a base are indicated across the top of the table, along with corresponding values for the SIB byte’s base field. Table rows in the body of the table indicate the register used as the index (SIB byte bits 3, 4 and 5) and the scaling factor (determined by SIB byte bits 6 and 7). Table 2-3.
INSTRUCTION FORMAT 2.2 IA-32E MODE IA-32e mode has two sub-modes. These are: • Compatibility Mode. Enables a 64-bit operating system to run most legacy protected mode software unmodified. • 64-Bit Mode. Enables a 64-bit operating system to run applications written to access 64-bit address space. 2.2.1 REX Prefixes REX prefixes are instruction-prefix bytes used in 64-bit mode. They do the following: • • • Specify GPRs and SSE registers. Specify 64-bit operand size.
INSTRUCTION FORMAT 2.2.1.1 Encoding Intel 64 and IA-32 instruction formats specify up to three registers by using 3-bit fields in the encoding, depending on the format: • • ModR/M: the reg and r/m fields of the ModR/M byte • Instructions without ModR/M: the reg field of the opcode ModR/M with SIB: the reg field of the ModR/M byte, the base and index fields of the SIB (scale, index, base) byte In 64-bit mode, these formats do not change.
INSTRUCTION FORMAT Table 2-4. REX Prefix Fields [BITS: 0100WRXB] Field Name Bit Position Definition - 7:4 0100 W 3 0 = Operand size determined by CS.D 1 = 64 Bit Operand Size R 2 Extension of the ModR/M reg field X 1 Extension of the SIB index field B 0 Extension of the ModR/M r/m field, SIB base field, or Opcode reg field 0RG50 %\WH 5(; 35(),; 2SFRGH PRG :5 % UHJ UUU U P EEE 5UUU %EEE 20 ;ILJ Figure 2-4. Memory Addressing Without an SIB Byte; REX.
INSTRUCTION FORMAT 0RG50 %\WH 5(; 35(),; 2SFRGH :5;% PRG UHJ UUU 6,% %\WH U P LQGH[ [[[ VFDOH VV 5UUU ;[[[ EDVH EEE %EEE 20 ;ILJ Figure 2-6. Memory Addressing With a SIB Byte 5(; 35(),; : % 2SFRGH UHJ EEE %EEE 20 ;ILJ Figure 2-7. Register Operand Coded in Opcode Byte; REX.X & REX.
INSTRUCTION FORMAT Table 2-5. Special Cases of REX Encodings Compatibility Mode Implications ModR/M or SIB Sub-field Encodings Compatibility Mode Operation ModR/M Byte mod != 11 SIB byte present. SIB byte required for ESP-based addressing. REX prefix adds a fourth bit (b) which is not decoded (don't care). SIB byte also required for R12-based addressing. ModR/M Byte mod == 0 Base register not used. EBP without a displacement must be done using mod = 01 with displacement of 0.
INSTRUCTION FORMAT 2.2.1.4 Direct Memory-Offset MOVs In 64-bit mode, direct memory-offset forms of the MOV instruction are extended to specify a 64-bit immediate absolute address. This address is called a moffset. No prefix is needed to specify this 64-bit memory offset. For these MOV instructions, the size of the memory offset follows the address-size default (64 bits in 64-bit mode). See Table 2-6. Table 2-6.
INSTRUCTION FORMAT addressing. Redundant forms of 32-bit displacement-addressing exist in the current ModR/M and SIB encodings. There is one ModR/M encoding and there are several SIB encodings. RIP-relative addressing is encoded using a redundant form. In 64-bit mode, the ModR/M Disp32 (32-bit displacement) encoding is re-defined to be RIP+Disp32 rather than displacement-only. See Table 2-7. Table 2-7.
INSTRUCTION FORMAT CR8-CR15 and DR8- DR15. An additional control register (CR8) is defined in 64-bit mode. CR8 becomes the Task Priority Register (TPR). In the first implementation of IA-32e mode, CR9-CR15 and DR8-DR15 are not implemented. Any attempt to access unimplemented registers results in an invalid-opcode exception (#UD). 2-16 Vol.
CHAPTER 3 INSTRUCTION SET REFERENCE, A-M This chapter describes the instruction set for the Intel 64 and IA-32 architectures (A-M) in IA-32e, protected, Virtual-8086, and real modes of operation. The set includes general-purpose, x87 FPU, MMX, SSE/SSE2/SSE3/SSSE3, and system instructions. See also Chapter 4, “Instruction Set Reference, N-Z,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B. For each instruction, each operand combination is described.
INSTRUCTION SET REFERENCE, A-M same order in which they appear in memory. Definitions of entries other than hexadecimal bytes are as follows: • REX.W — Indicates the use of a REX prefix that affects operand size or instruction semantics. The ordering of the REX prefix and other optional/mandatory instruction prefixes are discussed Chapter 2. Note that REX prefixes that promote legacy instructions to 64-bit behavior are not listed explicitly in the opcode column.
INSTRUCTION SET REFERENCE, A-M Table 3-1. Register Codes Associated With +rb, +rw, +rd, +ro (Contd.) Reg Field REX.R Register ro (64-Bit Mode only) Reg Field REX.R Register rd Reg Field REX.R Register rw Reg Field REX.
INSTRUCTION SET REFERENCE, A-M 3.1.1.2 Instruction Column in the Opcode Summary Table The “Instruction” column gives the syntax of the instruction statement as it would appear in an ASM386 program. The following is a list of the symbols used to represent operands in the instruction statements: • rel8 — A relative address in the range from 128 bytes before the end of the instruction to 127 bytes after the end of the instruction.
INSTRUCTION SET REFERENCE, A-M between +9,223,372,036,854,775,807 and –9,223,372,036,854,775,808 inclusive. • r/m8 — A byte operand that is either the contents of a byte general-purpose register (AL, CL, DL, BL, AH, CH, DH, BH, BPL, SPL, DIL and SIL) or a byte from memory. Byte registers R8L - R15L are available using REX.R in 64-bit mode. • r/m16 — A word general-purpose register or memory operand used for instructions whose operand-size attribute is 16 bits.
INSTRUCTION SET REFERENCE, A-M doubleword with which to load the base field of the corresponding GDTR and IDTR registers. The m16&64 operand is used by LIDT and LGDT in 64-bit mode to provide a word with which to load the limit field, and a quadword with which to load the base field of the corresponding GDTR and IDTR registers. • moffs8, moffs16, moffs32, moffs64 — A simple memory variable (memory offset) of type byte, word, or doubleword used by some variants of the MOV instruction.
INSTRUCTION SET REFERENCE, A-M 3.1.1.3 64-bit Mode Column in the Instruction Summary Table The “64-bit Mode” column indicates whether the opcode sequence is supported in 64-bit mode. The column uses the following notation: • • • Valid — Supported. • N.P. — Indicates the REX prefix does not affect the legacy instruction in 64-bit mode. • • N.I. — Indicates the opcode is treated as a new instruction in 64-bit mode. Invalid — Not supported. N.E.
INSTRUCTION SET REFERENCE, A-M 3.1.1.7 Operation Section The “Operation” section contains an algorithm description (frequently written in pseudo-code) for the instruction. Algorithms are composed of the following elements: • • Comments are enclosed within the symbol pairs “(*” and “*)”. • A register name implies the contents of the register. A register name enclosed in brackets implies the contents of the location whose address is contained in that register.
INSTRUCTION SET REFERENCE, A-M ELSE IF Instruction ← MOVQ THEN OperandSize ← 64; FI; FI; FI; See “Operand-Size and Address-Size Attributes” in Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for guidelines on how these attributes are determined. • StackAddrSize — Represents the stack address-size attribute associated with the instruction, which has a value of 16, 32 or 64-bits.
INSTRUCTION SET REFERENCE, A-M –128 (80H); if it is greater than 127, it is represented by the saturated value 127 (7FH). • SaturateToSignedWord — Represents the result of an operation as a signed 16-bit value. If the result is less than –32768, it is represented by the saturated value –32768 (8000H); if it is greater than 32767, it is represented by the saturated value 32767 (7FFFH). • SaturateToUnsignedByte — Represents the result of an operation as a signed 8-bit value.
INSTRUCTION SET REFERENCE, A-M 63 31 21 0 Bit Offset ← 21 Figure 3-1. Bit Offset for BIT[RAX, 21] If BitBase is a memory address, the BitOffset can range has different ranges depending on the operand size (see Table 3-2). Table 3-2.
INSTRUCTION SET REFERENCE, A-M 3.1.1.8 Intel® C/C++ Compiler Intrinsics Equivalents Section The Intel C/C++ compiler intrinsics equivalents are special C/C++ coding extensions that allow using the syntax of C function calls and C variables instead of hardware registers. Using these intrinsics frees programmers from having to manage registers and assembly programming. Further, the compiler optimizes the instruction scheduling so that executable run faster.
INSTRUCTION SET REFERENCE, A-M — Appendix C, “InteL® C/C++ Compiler Intrinsics and Functional Equivalents,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B, for more information on using intrinsics. SSE/SSE2/SSE3 Intrinsics SSE/SSE2/SSE3 intrinsics all make use of the XMM registers of the Pentium III, Pentium 4, and Intel Xeon processors. There are three data types supported by these intrinsics: __m128, __m128d, and __m128i.
INSTRUCTION SET REFERENCE, A-M The suffixes ps and ss are used to denote “packed single” and “scalar single” precision operations. The packed floats are represented in right-to-left order, with the lowest word (right-most) being used for scalar operations: [z, y, x, w]. To explain how memory storage reflects this, consider the following example. The operation: float a[4] ← { 1.0, 2.0, 3.0, 4.0 }; __m128 t ← _mm_load_ps(a); Produces the same result as follows: __m128 t ← _mm_set_ps(4.0, 3.0, 2.0, 1.
INSTRUCTION SET REFERENCE, A-M assignments are described in the “Operation” section. The values of flags listed as undefined may be changed by the instruction in an indeterminate manner. Flags that are not listed are unchanged by the instruction. 3.1.1.10 FPU Flags Affected Section The floating-point instructions have an “FPU Flags Affected” section that describes how each instruction can affect the four condition code flags of the FPU status word. 3.1.1.
INSTRUCTION SET REFERENCE, A-M Table 3-3. Intel 64 and IA-32 General Exceptions (Contd.) Vector No. Protected Mode1 Real Address Mode Virtual 8086 Mode Name Source #DF—Double Fault Any instruction that can generate an exception, an NMI, or an INTR. Yes Yes Yes 10 #TS—Invalid TSS Task switch or TSS access. Yes Reserved Yes 11 #NP—Segment Not Present Loading segment registers or accessing system segments.
INSTRUCTION SET REFERENCE, A-M 3.1.1.14 Floating-Point Exceptions Section The “Floating-Point Exceptions” section lists exceptions that can occur when an x87 FPU floating-point instruction is executed. All of these exception conditions result in a floating-point error exception (#MF, vector number 16) being generated. Table 3-4 associates a one- or two-letter mnemonic with the corresponding exception name.
INSTRUCTION SET REFERENCE, A-M 3.1.1.16 Compatibility Mode Exceptions Section This section lists exception that occur within compatibility mode. 3.1.1.17 64-Bit Mode Exceptions Section This section lists exception that occur within 64-bit mode. 3.2 INSTRUCTIONS (A-M) The remainder of this chapter provides descriptions of Intel 64 and IA-32 instructions (A-M). See also: Chapter 4, “Instruction Set Reference, N-Z,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B.
INSTRUCTION SET REFERENCE, A-M AAA—ASCII Adjust After Addition Opcode 37 Instruction AAA 64-Bit Mode Invalid Compat/ Leg Mode Valid Description ASCII adjust AL after addition. Description Adjusts the sum of two unpacked BCD values to create an unpacked BCD result. The AL register is the implied source and destination operand for this instruction.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions None. Real-Address Mode Exceptions None. Virtual-8086 Mode Exceptions None. Compatibility Mode Exceptions None. 64-Bit Mode Exceptions #UD 3-20 Vol. 2 If in 64-bit mode.
INSTRUCTION SET REFERENCE, A-M AAD—ASCII Adjust AX Before Division Opcode D5 0A D5 ib Instruction AAD (No mnemonic) 64-Bit Mode Invalid Invalid Compat/ Leg Mode Valid Valid Description ASCII adjust AX before division. Adjust AX before division to number base imm8. Description Adjusts two unpacked BCD digits (the least-significant digit in the AL register and the most-significant digit in the AH register) so that a division operation performed on the result will yield a correct unpacked BCD value.
INSTRUCTION SET REFERENCE, A-M Flags Affected The SF, ZF, and PF flags are set according to the resulting binary value in the AL register; the OF, AF, and CF flags are undefined. Protected Mode Exceptions None. Real-Address Mode Exceptions None. Virtual-8086 Mode Exceptions None. Compatibility Mode Exceptions None. 64-Bit Mode Exceptions #UD 3-22 Vol. 2 If in 64-bit mode.
INSTRUCTION SET REFERENCE, A-M AAM—ASCII Adjust AX After Multiply Opcode D4 0A D4 ib Instruction AAM (No mnemonic) 64-Bit Mode Invalid Invalid Compat/ Leg Mode Valid Valid Description ASCII adjust AX after multiply. Adjust AX after multiply to number base imm8. Description Adjusts the result of the multiplication of two unpacked BCD values to create a pair of unpacked (base 10) BCD values. The AX register is the implied source and destination operand for this instruction.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #DE If an immediate value of 0 is used. Real-Address Mode Exceptions Same exception as in Protected Mode. Virtual-8086 Mode Exceptions Same exception as in Protected Mode. Compatibility Mode Exceptions Same exception as in Protected Mode. 64-Bit Mode Exceptions #UD 3-24 Vol. 2 If in 64-bit mode.
INSTRUCTION SET REFERENCE, A-M AAS—ASCII Adjust AL After Subtraction Opcode 3F Instruction AAS 64-Bit Mode Invalid Compat/ Leg Mode Valid Description ASCII adjust AL after subtraction. Description Adjusts the result of the subtraction of two unpacked BCD values to create a unpacked BCD result. The AL register is the implied source and destination operand for this instruction.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions None. Real-Address Mode Exceptions None. Virtual-8086 Mode Exceptions None. Compatibility Mode Exceptions None. 64-Bit Mode Exceptions #UD 3-26 Vol. 2 If in 64-bit mode.
INSTRUCTION SET REFERENCE, A-M ADC—Add with Carry Opcode 14 ib 15 iw 15 id REX.W + 15 id 80 /2 ib REX + 80 /2 ib 81 /2 iw 81 /2 id REX.W + 81 /2 id 83 /2 ib Instruction ADC AL, imm8 ADC AX, imm16 ADC EAX, imm32 ADC RAX, imm32 ADC r/m8, imm8 ADC r/m8*, imm8 ADC r/m16, imm16 ADC r/m32, imm32 ADC r/m64, imm32 64-Bit Mode Valid Valid Valid Compat/ Leg Mode Valid Valid Valid Valid N.E. Valid Valid Valid N.E. Valid Valid Valid Valid Valid N.E. Valid Valid Valid Valid Valid N.E.
INSTRUCTION SET REFERENCE, A-M Opcode 13 /r 13 /r REX.W + 13 /r Instruction ADC r16, r/m16 ADC r32, r/m32 ADC r64, r/m64 64-Bit Mode Valid Valid Valid Compat/ Leg Mode Valid Valid N.E. Description Add with carry r/m16 to r16. Add with CF r/m32 to r32. Add with CF r/m64 to r64. NOTES: * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
INSTRUCTION SET REFERENCE, A-M ADD—Add Opcode 04 ib 05 iw 05 id REX.W + 05 id Instruction ADD AL, imm8 ADD AX, imm16 ADD EAX, imm32 ADD RAX, imm32 64-Bit Mode Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid N.E. 80 /0 ib REX + 80 /0 ib ADD r/m8, imm8 ADD r/m8*, imm8 Valid Valid Valid N.E. 81 /0 iw ADD r/m16, imm16 ADD r/m32, imm32 ADD r/m64, imm32 Valid Valid Valid Valid Valid N.E. 83 /0 ib ADD r/m16, imm8 Valid Valid 83 /0 ib ADD r/m32, imm8 Valid Valid REX.
INSTRUCTION SET REFERENCE, A-M Description Adds the destination operand (first operand) and the source operand (second operand) and then stores the result in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, a register, or a memory location. (However, two memory operands cannot be used in one instruction.) When an immediate value is used as an operand, it is signextended to the length of the destination operand format.
INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
INSTRUCTION SET REFERENCE, A-M ADDPD—Add Packed Double-Precision Floating-Point Values Opcode 66 0F 58 /r Instruction ADDPD xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Add packed double-precision floating-point values from xmm2/m128 to xmm1.
INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CRO.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Vol.
INSTRUCTION SET REFERENCE, A-M ADDPS—Add Packed Single-Precision Floating-Point Values Opcode 0F 58 /r Instruction ADDPS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Add packed singleprecision floating-point values from xmm2/m128 to xmm1.
INSTRUCTION SET REFERENCE, A-M #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH.
INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. 3-38 Vol.
INSTRUCTION SET REFERENCE, A-M ADDSD—Add Scalar Double-Precision Floating-Point Values Opcode F2 0F 58 /r Instruction ADDSD xmm1, xmm2/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Description Add the low doubleprecision floating-point value from xmm2/m64 to xmm1. Description Adds the low double-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the double-precision floating-point result in the destination operand.
INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
INSTRUCTION SET REFERENCE, A-M ADDSS—Add Scalar Single-Precision Floating-Point Values Opcode F3 0F 58 /r Instruction ADDSS xmm1, xmm2/m32 64-Bit Mode Valid Compat/ Leg Mode Valid Description Add the low singleprecision floating-point value from xmm2/m32 to xmm1. Description Adds the low single-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the single-precision floating-point result in the destination operand.
INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CRO.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) 3-44 Vol. 2 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
INSTRUCTION SET REFERENCE, A-M ADDSUBPD—Packed Double-FP Add/Subtract Opcode 66 0F D0 /r Instruction ADDSUBPD xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Add/subtract double-precision floating-point values from xmm2/m128 to xmm1. Description Adds the double-precision floating-point values in the high quadword of the source and destination operands and stores the result in the high quadword of the destination operand.
INSTRUCTION SET REFERENCE, A-M Operation xmm1[63:0] = xmm1[63:0] − xmm2/m128[63:0]; xmm1[127:64] = xmm1[127:64] + xmm2/m128[127:64]; Intel C/C++ Compiler Intrinsic Equivalent ADDSUBPD __m128d _mm_addsub_pd(__m128d a, __m128d b) Exceptions When the source operand is a memory operand, it must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated. SIMD Floating-Point Exceptions Overflow, Underflow, Invalid, Precision, Denormal.
INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. Virtual 8086 Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M ADDSUBPS—Packed Single-FP Add/Subtract Opcode F2 0F D0 /r Instruction ADDSUBPS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Add/subtract single-precision floating-point values from xmm2/m128 to xmm1.
INSTRUCTION SET REFERENCE, A-M Operation xmm1[31:0] = xmm1[31:0] − xmm2/m128[31:0]; xmm1[63:32] = xmm1[63:32] + xmm2/m128[63:32]; xmm1[95:64] = xmm1[95:64] − xmm2/m128[95:64]; xmm1[127:96] = xmm1[127:96] + xmm2/m128[127:96]; Intel C/C++ Compiler Intrinsic Equivalent ADDSUBPS __m128 _mm_addsub_ps(__m128 a, __m128 b) Exceptions When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.
INSTRUCTION SET REFERENCE, A-M #XM For an unmasked Streaming SIMD Extensions numeric exception, CR4.OSXMMEXCPT[bit 10] = 1. #UD If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. Virtual 8086 Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH.
INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. Vol.
INSTRUCTION SET REFERENCE, A-M AND—Logical AND Opcode 24 ib 25 iw 25 id REX.W + 25 id Instruction AND AL, imm8 AND AX, imm16 AND EAX, imm32 AND RAX, imm32 64-Bit Mode Valid Valid Valid Valid Comp/Leg Mode Valid Valid Valid N.E. 80 /4 ib REX + 80 /4 ib AND r/m8, imm8 AND r/m8*, imm8 Valid Valid Valid N.E. 81 /4 iw Valid Valid Valid Valid r/m32 AND imm32. REX.W + 81 /4 id 83 /4 ib AND r/m16, imm16 AND r/m32, imm32 AND r/m64, imm32 AND r/m16, imm8 Description AL AND imm8. AX AND imm16.
INSTRUCTION SET REFERENCE, A-M Description Performs a bitwise AND operation on the destination (first) and source (second) operands and stores the result in the destination operand location. The source operand can be an immediate, a register, or a memory location; the destination operand can be a register or a memory location. (However, two memory operands cannot be used in one instruction.
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode.
INSTRUCTION SET REFERENCE, A-M ANDPD—Bitwise Logical AND of Packed Double-Precision FloatingPoint Values Opcode 66 0F 54 /r Instruction ANDPD xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Bitwise logical AND of xmm2/m128 and xmm1. Description Performs a bitwise logical AND of the two packed double-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the result in the destination operand.
INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault.
INSTRUCTION SET REFERENCE, A-M ANDPS—Bitwise Logical AND of Packed Single-Precision Floating-Point Values Opcode 0F 54 /r Instruction ANDPS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Bitwise logical AND of xmm2/m128 and xmm1. Description Performs a bitwise logical AND of the four packed single-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the result in the destination operand.
INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault.
INSTRUCTION SET REFERENCE, A-M ANDNPD—Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values Opcode 66 0F 55 /r Instruction ANDNPD xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Bitwise logical AND NOT of xmm2/m128 and xmm1.
INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault.
INSTRUCTION SET REFERENCE, A-M ANDNPS—Bitwise Logical AND NOT of Packed Single-Precision Floating-Point Values Opcode 0F 55 /r Instruction ANDNPS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Bitwise logical AND NOT of xmm2/m128 and xmm1.
INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault.
INSTRUCTION SET REFERENCE, A-M ARPL—Adjust RPL Field of Segment Selector Opcode 63 /r Instruction ARPL r/m16, r16 64-Bit Mode N. E. Compat/ Leg Mode Valid Description Adjust RPL of r/m16 to not less than RPL of r16. Description Compares the RPL fields of two segment selectors. The first operand (the destination operand) contains one segment selector and the second operand (source operand) contains the other. (The RPL field is located in bits 0 and 1 of each operand.
INSTRUCTION SET REFERENCE, A-M ELSE ZF ← 0; FI; FI; Flags Affected The ZF flag is set to 1 if the RPL field of the destination operand is less than that of the source operand; otherwise, it is set to 0. Protected Mode Exceptions #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.
INSTRUCTION SET REFERENCE, A-M BOUND—Check Array Index Against Bounds Opcode 62 /r Instruction BOUND r16, m16&16 64-Bit Mode Invalid Compat/ Leg Mode Valid 62 /r BOUND r32, m32&32 Invalid Valid Description Check if r16 (array index) is within bounds specified by m16&16. Check if r32 (array index) is within bounds specified by m16&16. Description BOUND determines if the first operand (array index) is within the bounds of an array specified the second operand (bounds operand).
INSTRUCTION SET REFERENCE, A-M Flags Affected None. Protected Mode Exceptions #BR If the bounds test fails. #UD If second operand is not a memory location. #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #UD If in 64-bit mode. Vol.
INSTRUCTION SET REFERENCE, A-M BSF—Bit Scan Forward Opcode 0F BC /r 0F BC /r REX.W + 0F BC Instruction BSF r16, r/m16 BSF r32, r/m32 BSF r64, r/m64 64-Bit Mode Valid Valid Valid Compat/ Leg Mode Valid Valid N.E. Description Bit scan forward on r/m16. Bit scan forward on r/m32. Bit scan forward on r/m64. Description Searches the source operand (second operand) for the least significant set bit (1 bit).
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
INSTRUCTION SET REFERENCE, A-M BSR—Bit Scan Reverse Opcode 0F BD /r 0F BD /r REX.W + 0F BD Instruction BSR r16, r/m16 BSR r32, r/m32 BSR r64, r/m64 64-Bit Mode Valid Valid Valid Compat/ Leg Mode Valid Valid N.E. Description Bit scan reverse on r/m16. Bit scan reverse on r/m32. Bit scan reverse on r/m64. Description Searches the source operand (second operand) for the most significant set bit (1 bit).
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
INSTRUCTION SET REFERENCE, A-M BSWAP—Byte Swap Opcode 0F C8+rd Instruction BSWAP r32 64-Bit Mode Valid* Compat/ Leg Mode Valid REX.W + 0F C8+rd BSWAP r64 Valid N.E. Description Reverses the byte order of a 32-bit register. Reverses the byte order of a 64-bit register. NOTES: * See IA-32 Architecture Compatibility section below. Description Reverses the byte order of a 32-bit or 64-bit (destination) register.
INSTRUCTION SET REFERENCE, A-M DEST[23:16] ← TEMP[15:8]; DEST[31:24] ← TEMP[7:0]; FI; Flags Affected None. Exceptions (All Operating Modes) None. Vol.
INSTRUCTION SET REFERENCE, A-M BT—Bit Test Opcode 0F A3 Instruction BT r/m16, r16 64-Bit Mode Valid Compat/ Leg Mode Valid 0F A3 BT r/m32, r32 Valid Valid REX.W + 0F A3 BT r/m64, r64 Valid N.E. 0F BA /4 ib BT r/m16, imm8 BT r/m32, imm8 BT r/m64, imm8 Valid Valid Valid Valid Valid N.E. 0F BA /4 ib REX.W + 0F BA /4 ib Description Store selected bit in CF flag. Store selected bit in CF flag. Store selected bit in CF flag. Store selected bit in CF flag. Store selected bit in CF flag.
INSTRUCTION SET REFERENCE, A-M Or, it may access 2 bytes starting from the memory address for a 16-bit operand, using this relationship: Effective Address + (2 ∗ (BitOffset DIV 16)) It may do so even when only a single byte needs to be accessed to reach the given bit. When using this bit addressing mechanism, software should avoid referencing areas of memory close to address space holes. In particular, it should avoid references to memory-mapped I/O registers.
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode.
INSTRUCTION SET REFERENCE, A-M BTC—Bit Test and Complement Opcode 0F BB Instruction BTC r/m16, r16 64Bit Mode Valid 0F BB BTC r/m32, r32 Valid Valid REX.W + 0F BB BTC r/m64, r64 Valid N.E. 0F BA /7 ib BTC r/m16, imm8 Valid Valid 0F BA /7 ib BTC r/m32, imm8 Valid Valid REX.W + 0F BA /7 ib BTC r/m64, imm8 Valid N.E. Compat/ Leg Mode Valid Description Store selected bit in CF flag and complement. Store selected bit in CF flag and complement.
INSTRUCTION SET REFERENCE, A-M prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits. Operation CF ← Bit(BitBase, BitOffset); Bit(BitBase, BitOffset) ← NOT Bit(BitBase, BitOffset); Flags Affected The CF flag contains the value of the selected bit before it is complemented. The OF, SF, ZF, AF, and PF flags are undefined. Protected Mode Exceptions #GP(0) If the destination operand points to a non-writable segment.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
INSTRUCTION SET REFERENCE, A-M BTR—Bit Test and Reset Opcode 0F B3 Instruction BTR r/m16, r16 64-Bit Mode Valid Compat/ Leg Mode Valid 0F B3 BTR r/m32, r32 Valid Valid REX.W + 0F B3 BTR r/m64, r64 Valid N.E. 0F BA /6 ib BTR r/m16, imm8 BTR r/m32, imm8 BTR r/m64, imm8 Valid Valid Valid Valid Valid N.E. 0F BA /6 ib REX.W + 0F BA /6 ib Description Store selected bit in CF flag and clear. Store selected bit in CF flag and clear. Store selected bit in CF flag and clear.
INSTRUCTION SET REFERENCE, A-M prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits. Operation CF ← Bit(BitBase, BitOffset); Bit(BitBase, BitOffset) ← 0; Flags Affected The CF flag contains the value of the selected bit before it is cleared. The OF, SF, ZF, AF, and PF flags are undefined. Protected Mode Exceptions #GP(0) If the destination operand points to a non-writable segment.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-82 Vol.
INSTRUCTION SET REFERENCE, A-M BTS—Bit Test and Set Opcode 0F AB Instruction BTS r/m16, r16 64-Bit Mode Valid Compat/ Leg Mode Valid 0F AB BTS r/m32, r32 Valid Valid REX.W + 0F AB BTS r/m64, r64 Valid N.E. 0F BA /5 ib BTS r/m16, imm8 Valid Valid 0F BA /5 ib BTS r/m32, imm8 Valid Valid REX.W + 0F BA /5 ib BTS r/m64, imm8 Valid N.E. Description Store selected bit in CF flag and set. Store selected bit in CF flag and set. Store selected bit in CF flag and set.
INSTRUCTION SET REFERENCE, A-M Operation CF ← Bit(BitBase, BitOffset); Bit(BitBase, BitOffset) ← 1; Flags Affected The CF flag contains the value of the selected bit before it is set. The OF, SF, ZF, AF, and PF flags are undefined. Protected Mode Exceptions #GP(0) If the destination operand points to a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
INSTRUCTION SET REFERENCE, A-M CALL—Call Procedure Opcode E8 cw Instruction CALL rel16 64-Bit Mode N.S. Compat/ Leg Mode Valid E8 cd CALL rel32 Valid Valid FF /2 CALL r/m16 N.E. Valid FF /2 CALL r/m32 N.E. Valid FF /2 CALL r/m64 Valid N.E. 9A cd CALL ptr16:16 CALL ptr16:32 CALL m16:16 Invalid Valid Invalid Valid Valid Valid 9A cp FF /3 FF /3 CALL m16:32 Valid Valid REX.W + FF /3 CALL m16:64 Valid N.E.
INSTRUCTION SET REFERENCE, A-M This instruction can be used to execute four types of calls: • Near Call — A call to a procedure in the current code segment (the segment currently pointed to by the CS register), sometimes referred to as an intrasegment call. • Far Call — A call to a procedure located in a different segment than the current code segment, sometimes referred to as an inter-segment call.
INSTRUCTION SET REFERENCE, A-M and EIP registers on the stack for use as a return-instruction pointer. The processor then performs a “far branch” to the code segment and offset specified with the target operand for the called procedure. The target operand specifies an absolute far address either directly with a pointer (ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or m16:32).
INSTRUCTION SET REFERENCE, A-M On inter-privilege-level calls, the processor switches to the stack for the privilege level of the called procedure. The segment selector for the new stack segment is specified in the TSS for the currently running task. The branch to the new code segment occurs after the stack switch. (Note that when using a call gate to perform a far call to a segment at the same privilege level, no stack switch occurs.
INSTRUCTION SET REFERENCE, A-M • Far call to a different privilege level (inter-privilege level call), transitioning to 64bit mode Note that a CALL instruction can not be used to cause a task switch in compatibility mode since task switches are not supported in IA-32e mode. In compatibility mode, the processor always uses the segment selector part of the far address to access the corresponding descriptor in the GDT or LDT.
INSTRUCTION SET REFERENCE, A-M Near/(Far) Calls in 64-bit Mode.
INSTRUCTION SET REFERENCE, A-M pointer for the calling procedure’s stack and the segment selector and instruction pointer for the calling procedure’s code segment. (Parameter copy is not supported in IA-32e mode.) Finally, the processor branches to the address of the procedure being called within the new code segment.
INSTRUCTION SET REFERENCE, A-M RIP ← tempRIP; FI; IF OperandSize = 32 THEN tempEIP ← DEST; (* DEST is r/m32 *) IF tempEIP is not within code segment limit THEN #GP(0); FI; IF stack not large enough for a 4-byte return address THEN #SS(0); FI; Push(EIP); EIP ← tempEIP; FI; IF OperandSize = 16 THEN tempEIP ← DEST AND 0000FFFFH; (* DEST is r/m16 *) IF tempEIP is not within code segment limit THEN #GP(0); FI; IF stack not large enough for a 2-byte return address THEN #SS(0); FI; Push(IP); EIP ← tempEIP; FI; FI
INSTRUCTION SET REFERENCE, A-M IF far call and (PE = 1 and VM = 0) (* Protected mode or IA-32e Mode, not virtual-8086 mode*) THEN IF segment selector in target operand NULL THEN #GP(0); FI; IF segment selector index not within descriptor table limits THEN #GP(new code segment selector); FI; Read type and access rights of selected segment descriptor; IF IA32_EFER.
INSTRUCTION SET REFERENCE, A-M THEN #GP(0); FI; IF OperandSize = 32 THEN Push(CS); (* Padded with 16 high-order bits *) Push(EIP); CS ← DEST(CodeSegmentSelector); (* Segment descriptor information also loaded *) CS(RPL) ← CPL; EIP ← tempEIP; ELSE IF OperandSize = 16 THEN Push(CS); Push(IP); CS ← DEST(CodeSegmentSelector); (* Segment descriptor information also loaded *) CS(RPL) ← CPL; EIP ← tempEIP; ELSE (* OperandSize = 64 *) Push(CS); (* Padded with 48 high-order bits *) Push(RIP); CS ← DEST(CodeSegmentS
INSTRUCTION SET REFERENCE, A-M IF tempEIP is non-canonical THEN #GP(0); FI; IF OperandSize = 32 THEN Push(CS); (* Padded with 16 high-order bits *) Push(EIP); CS ← DEST(CodeSegmentSelector); (* Segment descriptor information also loaded *) CS(RPL) ← CPL; EIP ← tempEIP; ELSE IF OperandSize = 16 THEN Push(CS); Push(IP); CS ← DEST(CodeSegmentSelector); (* Segment descriptor information also loaded *) CS(RPL) ← CPL; EIP ← tempEIP; ELSE (* OperandSize = 64 *) Push(CS); (* Padded with 48 high-order bits *) Push(
INSTRUCTION SET REFERENCE, A-M IF IA32_EFER.
INSTRUCTION SET REFERENCE, A-M IF CallGateSize = 32 THEN IF stack does not have room for parameters plus 16 bytes THEN #SS(SS selector); FI; IF CallGate(InstructionPointer) not within code segment limit THEN #GP(0); FI; SS ← newSS; (* Segment descriptor information also loaded *) ESP ← newESP; CS:EIP ← CallGate(CS:InstructionPointer); (* Segment descriptor information also loaded *) Push(oldSS:oldESP); (* From calling procedure *) temp ← parameter count from call gate, masked to 5 bits; Push(parameters fro
INSTRUCTION SET REFERENCE, A-M FI; CPL ← CodeSegment(DPL) CS(RPL) ← CPL END; SAME-PRIVILEGE: IF CallGateSize = 32 THEN IF stack does not have room for 8 bytes THEN #SS(0); FI; IF CallGate(InstructionPointer) not within code segment limit THEN #GP(0); FI; CS:EIP ← CallGate(CS:EIP) (* Segment descriptor information also loaded *) Push(oldCS:oldEIP); (* Return address to calling procedure *) ELSE If CallGateSize = 16 THEN IF stack does not have room for 4 bytes THEN #SS(0); FI; IF CallGate(InstructionPointer)
INSTRUCTION SET REFERENCE, A-M IF TSS segment selector local/global bit is set to local or index not within GDT limits THEN #GP(TSS selector); FI; Access TSS descriptor in GDT; IF TSS descriptor specifies that the TSS is busy (low-order 5 bits set to 00001) THEN #GP(TSS selector); FI; IF TSS not present THEN #NP(TSS selector); FI; SWITCH-TASKS (with nesting) to TSS; IF EIP not within code segment limit THEN #GP(0); FI; END; TASK-STATE-SEGMENT: IF TSS DPL < CPL or RPL or TSS descriptor indicates TSS not ava
INSTRUCTION SET REFERENCE, A-M nonconforming-code segment, call gate, task gate, or task state segment. If the DPL for a nonconforming-code segment is not equal to the CPL or the RPL for the segment’s segment selector is greater than the CPL. If the DPL for a conforming-code segment is greater than the CPL. If the DPL from a call-gate, task-gate, or TSS segment descriptor is less than the CPL or than the RPL of the call-gate, task-gate, or TSS’s segment selector.
INSTRUCTION SET REFERENCE, A-M If the new stack segment is not a writable data segment. If segment-selector index for stack segment is outside descriptor table limits. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
INSTRUCTION SET REFERENCE, A-M If the segment descriptor pointed to by the segment selector in the destination operand is a code segment and has both the Dbit and the L- bit set. If the DPL for a nonconforming-code segment is not equal to the CPL, or the RPL for the segment’s segment selector is greater than the CPL. If the DPL for a conforming-code segment is greater than the CPL. If the DPL from a 64-bit call-gate is less than the CPL or than the RPL of the 64-bit call-gate.
INSTRUCTION SET REFERENCE, A-M CBW/CWDE/CDQE—Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword Opcode 98 98 REX.W + 98 Instruction CBW CWDE CDQE 64-Bit Mode Valid Valid Valid Compat/ Leg Mode Valid Valid N.E. Description AX ← sign-extend of AL. EAX ← sign-extend of AX. RAX ← sign-extend of EAX. Description Double the size of the source operand by means of sign extension.
INSTRUCTION SET REFERENCE, A-M CLC—Clear Carry Flag Opcode F8 Instruction CLC 64-Bit Mode Valid Compat/ Leg Mode Valid Description Clear CF flag. Description Clears the CF flag in the EFLAGS register. Operation is the same in all non-64-bit modes and 64-bit mode. Operation CF ← 0; Flags Affected The CF flag is set to 0. The OF, ZF, SF, AF, and PF flags are unaffected. Exceptions (All Operating Modes) None. Vol.
INSTRUCTION SET REFERENCE, A-M CLD—Clear Direction Flag Opcode FC Instruction CLD 64-Bit Mode Valid Compat/ Leg Mode Valid Description Clear DF flag. Description Clears the DF flag in the EFLAGS register. When the DF flag is set to 0, string operations increment the index registers (ESI and/or EDI). Operation is the same in all non-64-bit modes and 64-bit mode. Operation DF ← 0; Flags Affected The DF flag is set to 0. The CF, OF, ZF, SF, AF, and PF flags are unaffected.
INSTRUCTION SET REFERENCE, A-M CLFLUSH—Flush Cache Line Opcode 0F AE /7 Instruction CLFLUSH m8 64-Bit Mode Valid Compat/ Leg Mode Valid Description Flushes cache line containing m8. Description Invalidates the cache line that contains the linear address specified with the source operand from all levels of the processor cache hierarchy (data and instruction). The invalidation is broadcast throughout the cache coherence domain.
INSTRUCTION SET REFERENCE, A-M Operation Flush_Cache_Line(SRC); Intel C/C++ Compiler Intrinsic Equivalents CLFLUSH void_mm_clflush(void const *p) Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #UD If CPUID.01H:EDX.CLFSH[bit 19] = 0.
INSTRUCTION SET REFERENCE, A-M CLI — Clear Interrupt Flag Opcode FA 64-Bit Mode Valid Instruction CLI Compat/ Leg Mode Valid Description Clear interrupt flag; interrupts disabled when interrupt flag cleared. Description If protected-mode virtual interrupts are not enabled, CLI clears the IF flag in the EFLAGS register. No other flags are affected. Clearing the IF flag causes the processor to ignore maskable external interrupts.
INSTRUCTION SET REFERENCE, A-M Operation IF PE = 0 THEN IF ← 0; (* Reset Interrupt Flag *) ELSE IF VM = 0; THEN IF IOPL ← CPL THEN IF ← 0; (* Reset Interrupt Flag *) ELSE IF ((IOPL < CPL) and (CPL = 3) and (PVI = 1)) THEN VIF ← 0; (* Reset Virtual Interrupt Flag *) ELSE #GP(0); FI; FI; ELSE (* VM = 1 *) IF IOPL = 3 THEN IF ← 0; (* Reset Interrupt Flag *) ELSE IF (IOPL < 3) AND (VME = 1) THEN VIF ← 0; (* Reset Virtual Interrupt Flag *) ELSE #GP(0); FI; FI; FI; FI; Flags Affected If protected-mode virtual i
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If the CPL is greater (has less privilege) than the IOPL of the current program or procedure. Real-Address Mode Exceptions None. Virtual-8086 Mode Exceptions #GP(0) If the CPL is greater (has less privilege) than the IOPL of the current program or procedure. Compatibility Mode Exceptions Same exceptions as in Protected Mode.
INSTRUCTION SET REFERENCE, A-M CLTS—Clear Task-Switched Flag in CR0 Opcode 0F 06 Instruction CLTS 64-Bit Mode Valid Compat/ Leg Mode Valid Description Clears TS flag in CR0. Description Clears the task-switched (TS) flag in the CR0 register. This instruction is intended for use in operating-system procedures. It is a privileged instruction that can only be executed at a CPL of 0. It is allowed to be executed in real-address mode to allow initialization for protected mode.
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #GP(0) If the CPL is greater than 0. Vol.
INSTRUCTION SET REFERENCE, A-M CMC—Complement Carry Flag Opcode F5 Instruction CMC 64-Bit Mode Valid Compat/ Leg Mode Valid Description Complement CF flag. Description Complements the CF flag in the EFLAGS register. CMC operation is the same in non64-bit modes and 64-bit mode. Operation EFLAGS.CF[bit 0]← NOT EFLAGS.CF[bit 0]; Flags Affected The CF flag contains the complement of its original value. The OF, ZF, SF, AF, and PF flags are unaffected. Exceptions (All Operating Modes) None. 3-114 Vol.
INSTRUCTION SET REFERENCE, A-M CMOVcc—Conditional Move Opcode 0F 47 /r Instruction CMOVA r16, r/m16 64-Bit Mode Valid Compat/ Leg Mode Valid 0F 47 /r CMOVA r32, r/m32 Valid Valid REX.W + 0F 47 /r CMOVA r64, r/m64 Valid N.E. 0F 43 /r CMOVAE r16, r/m16 Valid Valid 0F 43 /r CMOVAE r32, r/m32 Valid Valid REX.W + 0F 43 /r CMOVAE r64, r/m64 Valid N.E. 0F 42 /r 0F 42 /r REX.
INSTRUCTION SET REFERENCE, A-M Opcode REX.W + 0F 4D /r Instruction CMOVGE r64, r/m64 64-Bit Mode Valid Compat/ Leg Mode N.E. 0F 4C /r 0F 4C /r REX.W + 0F 4C /r CMOVL r16, r/m16 CMOVL r32, r/m32 CMOVL r64, r/m64 Valid Valid Valid Valid Valid N.E. 0F 4E /r CMOVLE r16, r/m16 Valid Valid 0F 4E /r CMOVLE r32, r/m32 Valid Valid REX.W + 0F 4E /r CMOVLE r64, r/m64 Valid N.E. 0F 46 /r CMOVNA r16, r/m16 Valid Valid 0F 46 /r CMOVNA r32, r/m32 Valid Valid REX.
INSTRUCTION SET REFERENCE, A-M Opcode REX.W + 0F 43 /r Instruction CMOVNC r64, r/m64 64-Bit Mode Valid Compat/ Leg Mode N.E. 0F 45 /r CMOVNE r16, r/m16 Valid Valid 0F 45 /r CMOVNE r32, r/m32 Valid Valid REX.W + 0F 45 /r CMOVNE r64, r/m64 Valid N.E. 0F 4E /r CMOVNG r16, r/m16 Valid Valid 0F 4E /r CMOVNG r32, r/m32 Valid Valid REX.W + 0F 4E /r CMOVNG r64, r/m64 Valid N.E. 0F 4C /r CMOVNGE r16, r/m16 Valid Valid 0F 4C /r CMOVNGE r32, r/m32 Valid Valid REX.
INSTRUCTION SET REFERENCE, A-M Opcode REX.W + 0F 41 /r Instruction CMOVNO r64, r/m64 64-Bit Mode Valid Compat/ Leg Mode N.E. 0F 4B /r CMOVNP r16, r/m16 Valid Valid 0F 4B /r CMOVNP r32, r/m32 Valid Valid REX.W + 0F 4B /r CMOVNP r64, r/m64 Valid N.E. 0F 49 /r 0F 49 /r REX.W + 0F 49 /r 0F 45 /r CMOVNS r16, r/m16 CMOVNS r32, r/m32 CMOVNS r64, r/m64 CMOVNZ r16, r/m16 Valid Valid Valid Valid Valid Valid N.E. Valid 0F 45 /r CMOVNZ r32, r/m32 Valid Valid REX.
INSTRUCTION SET REFERENCE, A-M Opcode 0F 4B /r Instruction CMOVPO r16, r/m16 64-Bit Mode Valid Compat/ Leg Mode Valid 0F 4B /r CMOVPO r32, r/m32 Valid Valid REX.W + 0F 4B /r CMOVPO r64, r/m64 Valid N.E. 0F 48 /r 0F 48 /r REX.W + 0F 48 /r 0F 44 /r 0F 44 /r REX.W + 0F 44 /r CMOVS r16, r/m16 CMOVS r32, r/m32 CMOVS r64, r/m64 CMOVZ r16, r/m16 CMOVZ r32, r/m32 CMOVZ r64, r/m64 Valid Valid Valid Valid Valid Valid Valid Valid N.E. Valid Valid N.E. Description Move if parity odd (PF=0).
INSTRUCTION SET REFERENCE, A-M Operation temp ← SRC IF (64-Bit Mode) THEN IF condition TRUE THEN IF (OperandSize = 64) THEN DEST ← temp; ELSE DEST ← temp AND 0x00000000_FFFFFFFF; FI; FI; ELSE IF condition TRUE THEN DEST ← temp; FI; FI; Flags Affected None. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector.
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode.
INSTRUCTION SET REFERENCE, A-M CMP—Compare Two Operands Opcode 3C ib 3D iw 3D id REX.W + 3D id 80 /7 ib REX + 80 /7 ib 81 /7 iw 81 /7 id REX.W + 81 /7 id 83 /7 ib 83 /7 ib REX.W + 83 /7 ib 38 /r REX + 38 /r 39 /r 39 /r REX.W + 39 /r 3A /r REX + 3A /r 3B /r 3B /r REX.
INSTRUCTION SET REFERENCE, A-M Description Compares the first source operand with the second source operand and sets the status flags in the EFLAGS register according to the results. The comparison is performed by subtracting the second operand from the first operand and then setting the status flags in the same manner as the SUB instruction. When an immediate value is used as an operand, it is sign-extended to the length of the first operand.
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode.
INSTRUCTION SET REFERENCE, A-M CMPPD—Compare Packed Double-Precision Floating-Point Values Opcode 66 0F C2 /r ib Instruction CMPPD xmm1, xmm2/m128, imm8 64-Bit Mode Valid Compat/ Leg Mode Valid Description Compare packed doubleprecision floating-point values in xmm2/m128 and xmm1 using imm8 as comparison predicate.
INSTRUCTION SET REFERENCE, A-M Table 3-7. Comparison Predicate for CMPPD and CMPPS Instructions (Contd.
INSTRUCTION SET REFERENCE, A-M Table 3-8. Pseudo-Op and CMPPD Implementation Pseudo-Op CMPPD Implementation CMPORDPD xmm1, xmm2 CMPPD xmm1, xmm2, 7 The greater-than relations that the processor does not implement require more than one instruction to emulate in software and therefore should not be implemented as pseudo-ops.
INSTRUCTION SET REFERENCE, A-M CMPPD for not-greater-than __m128d _mm_cmpngt_pd(__m128d a, __m128d b) CMPPD for not-greater-than-or-equal __m128d _mm_cmpnge_pd(__m128d a, __m128d b) CMPPD for ordered __m128d _mm_cmpord_pd(__m128d a, __m128d b) CMPPD for unordered __m128d _mm_cmpunord_pd(__m128d a, __m128d b) CMPPD for not-less-than-or-equal __m128d _mm_cmpnle_pd(__m128d a, __m128d b) SIMD Floating-Point Exceptions Invalid if SNaN operand and invalid if QNaN and predicate as listed in above table,
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M CMPPS—Compare Packed Single-Precision Floating-Point Values Opcode 0F C2 /r ib Instruction CMPPS xmm1, xmm2/m128, imm8 64-Bit Mode Valid Compat/ Leg Mode Valid Description Compare packed singleprecision floating-point values in xmm2/mem and xmm1 using imm8 as comparison predicate.
INSTRUCTION SET REFERENCE, A-M Table 3-9.
INSTRUCTION SET REFERENCE, A-M THEN DEST95:64] ← FFFFFFFFH; ELSE DEST[95:64] ← 00000000H; FI; IF CMP3 = TRUE THEN DEST[127:96] ← FFFFFFFFH; ELSE DEST[127:96] ← 00000000H; FI; Intel C/C++ Compiler Intrinsic Equivalents CMPPS for equality __m128 _mm_cmpeq_ps(__m128 a, __m128 b) CMPPS for less-than __m128 _mm_cmplt_ps(__m128 a, __m128 b) CMPPS for less-than-or-equal __m128 _mm_cmple_ps(__m128 a, __m128 b) CMPPS for greater-than __m128 _mm_cmpgt_ps(__m128 a, __m128 b) CMPPS for greater-than-or-equal
INSTRUCTION SET REFERENCE, A-M If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1.
INSTRUCTION SET REFERENCE, A-M CMPS/CMPSB/CMPSW/CMPSD/CMPSQ—Compare String Operands 64-Bit Mode Valid Compat/ Leg Mode Valid CMPS m16, m16 Valid Valid A7 CMPS m32, m32 Valid Valid REX.W + A7 CMPS m64, m64 Valid N.E. A6 CMPSB Valid Valid Opcode A6 Instruction CMPS m8, m8 A7 3-134 Vol. 2 Description For legacy mode, compare byte at address DS:(E)SI with byte at address ES:(E)DI; For 64-bit mode compare byte at address (R|E)SI to byte at address (R|E)DI.
INSTRUCTION SET REFERENCE, A-M Opcode A7 Instruction CMPSW 64-Bit Mode Valid Compat/ Leg Mode Valid A7 CMPSD Valid Valid REX.W + A7 CMPSQ Valid N.E. Description For legacy mode, compare word at address DS:(E)SI with word at address ES:(E)DI; For 64-bit mode compare word at address (R|E)SI with word at address (R|E)DI. The status flags are set accordingly.
INSTRUCTION SET REFERENCE, A-M RDI) registers are assumed by the processor to specify the location of the source operands. The size of the source operands is selected with the mnemonic: CMPSB (byte comparison), CMPSW (word comparison), CMPSD (doubleword comparison), or CMPSQ (quadword comparison using REX.W). After the comparison, the (E/R)SI and (E/R)DI registers increment or decrement automatically according to the setting of the DF flag in the EFLAGS register.
INSTRUCTION SET REFERENCE, A-M (R|E)SI ← (R|E)SI – 2; (R|E)DI ← (R|E)DI – 2; FI; ELSE IF (Doubleword comparison) THEN IF DF = 0 THEN (R|E)SI ← (R|E)SI + 4; (R|E)DI ← (R|E)DI + 4; ELSE (R|E)SI ← (R|E)SI – 4; (R|E)DI ← (R|E)DI – 4; FI; ELSE (* Quadword comparison *) THEN IF DF = 0 (R|E)SI ← (R|E)SI + 8; (R|E)DI ← (R|E)DI + 8; ELSE (R|E)SI ← (R|E)SI – 8; (R|E)DI ← (R|E)DI – 8; FI; FI; ELSE (* Non-64-bit Mode *) IF (byte comparison) THEN IF DF = 0 THEN (E)SI ← (E)SI + 1; (E)DI ← (E)DI + 1; ELSE (E)SI ← (E)SI –
INSTRUCTION SET REFERENCE, A-M ELSE (E)SI ← (E)SI – 4; (E)DI ← (E)DI – 4; FI; FI; FI; Flags Affected The CF, OF, SF, ZF, AF, and PF flags are set according to the temporary result of the comparison. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
INSTRUCTION SET REFERENCE, A-M CMPSD—Compare Scalar Double-Precision Floating-Point Values Opcode F2 0F C2 /r ib Instruction CMPSD xmm1, xmm2/m64, imm8 64-Bit Mode Valid Compat/ Leg Mode Valid Description Compare low doubleprecision floating-point value in xmm2/m64 and xmm1 using imm8 as comparison predicate.
INSTRUCTION SET REFERENCE, A-M Table 3-10.
INSTRUCTION SET REFERENCE, A-M Intel C/C++ Compiler Intrinsic Equivalents CMPSD for equality __m128d _mm_cmpeq_sd(__m128d a, __m128d b) CMPSD for less-than __m128d _mm_cmplt_sd(__m128d a, __m128d b) CMPSD for less-than-or-equal __m128d _mm_cmple_sd(__m128d a, __m128d b) CMPSD for greater-than __m128d _mm_cmpgt_sd(__m128d a, __m128d b) CMPSD for greater-than-or-equal __m128d _mm_cmpge_sd(__m128d a, __m128d b) CMPSD for inequality __m128d _mm_cmpneq_sd(__m128d a, __m128d b) CMPSD for not-less-tha
INSTRUCTION SET REFERENCE, A-M #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode. #PF(fault-code) For a page fault. #AC(0) If alignment checking is enabled and an unaligned memory reference is made.
INSTRUCTION SET REFERENCE, A-M CMPSS—Compare Scalar Single-Precision Floating-Point Values Opcode F3 0F C2 /r ib Instruction CMPSS xmm1, xmm2/m32, imm8 64-Bit Mode Valid Compat/ Leg Mode Valid Description Compare low singleprecision floating-point value in xmm2/m32 and xmm1 using imm8 as comparison predicate.
INSTRUCTION SET REFERENCE, A-M Table 3-11.
INSTRUCTION SET REFERENCE, A-M Intel C/C++ Compiler Intrinsic Equivalents CMPSS for equality __m128 _mm_cmpeq_ss(__m128 a, __m128 b) CMPSS for less-than __m128 _mm_cmplt_ss(__m128 a, __m128 b) CMPSS for less-than-or-equal __m128 _mm_cmple_ss(__m128 a, __m128 b) CMPSS for greater-than __m128 _mm_cmpgt_ss(__m128 a, __m128 b) CMPSS for greater-than-or-equal__m128 _mm_cmpge_ss(__m128 a, __m128 b) CMPSS for inequality __m128 _mm_cmpneq_ss(__m128 a, __m128 b) CMPSS for not-less-than __m128 _mm_cmpnlt_
INSTRUCTION SET REFERENCE, A-M #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode. #PF(fault-code) For a page fault. #AC(0) If alignment checking is enabled and an unaligned memory reference is made.
INSTRUCTION SET REFERENCE, A-M CMPXCHG—Compare and Exchange Opcode 0F B0/r Instruction CMPXCHG r/m8, r8 64-Bit Mode Valid Compat/ Leg Mode Valid* REX + 0F B0/r CMPXCHG r/m8**,r8 Valid N.E. 0F B1/r CMPXCHG r/m16, r16 Valid Valid* 0F B1/r CMPXCHG r/m32, r32 Valid Valid* REX.W + 0F B1/r CMPXCHG r/m64, r64 Valid N.E. Description Compare AL with r/m8. If equal, ZF is set and r8 is loaded into r/m8. Else, clear ZF and load r/m8 into AL. Compare AL with r/m8.
INSTRUCTION SET REFERENCE, A-M In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning of this section for encoding data and limits. IA-32 Architecture Compatibility This instruction is not supported on Intel processors earlier than the Intel486 processors.
INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
INSTRUCTION SET REFERENCE, A-M CMPXCHG8B/CMPXCHG16B—Compare and Exchange Bytes Opcode* 0F C7 /1 m64 Instruction CMPXCHG8B m64 REX.W + 0F C7 /1 m128 CMPXCHG16B m128 64-Bit Mode Valid Compat/ Leg Mode Valid* Valid N.E. Description Compare EDX:EAX with m64. If equal, set ZF and load ECX:EBX into m64. Else, clear ZF and load m64 into EDX:EAX. Compare RDX:RAX with m128. If equal, set ZF and load RCX:RBX into m128. Else, clear ZF and load m128 into RDX:RAX.
INSTRUCTION SET REFERENCE, A-M Operation IF (64-Bit Mode and OperandSize = 64) THEN IF (RDX:RAX = DEST) ZF ← 1; DEST ← RCX:RBX; ELSE ZF ← 0; RDX:RAX ← DEST; FI ELSE IF (EDX:EAX = DEST) ZF ← 1; DEST ← ECX:EBX; ELSE ZF ← 0; EDX:EAX ← DEST; FI; FI; Flags Affected The ZF flag is set if the destination operand and EDX:EAX are equal; otherwise it is cleared. The CF, PF, AF, SF, and OF flags are unaffected. Protected Mode Exceptions #UD If the destination operand is not a memory location.
INSTRUCTION SET REFERENCE, A-M #SS If a memory operand effective address is outside the SS segment limit. Virtual-8086 Mode Exceptions #UD If the destination operand is not a memory location. #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made.
INSTRUCTION SET REFERENCE, A-M COMISD—Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS Opcode 66 0F 2F /r Instruction COMISD xmm1, xmm2/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Description Compare low doubleprecision floating-point values in xmm1 and xmm2/mem64 and set the EFLAGS flags accordingly.
INSTRUCTION SET REFERENCE, A-M int_mm_comile_sd (__m128d a, __m128d b) int_mm_comigt_sd (__m128d a, __m128d b) int_mm_comige_sd (__m128d a, __m128d b) int_mm_comineq_sd (__m128d a, __m128d b) SIMD Floating-Point Exceptions Invalid (if SNaN or QNaN operands), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode. #PF(fault-code) For a page fault. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.
INSTRUCTION SET REFERENCE, A-M COMISS—Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS Opcode 0F 2F /r Instruction COMISS xmm1, xmm2/m32 64-Bit Mode Valid Compat/ Leg Mode Valid Description Compare low single-precision floating-point values in xmm1 and xmm2/mem32 and set the EFLAGS flags accordingly.
INSTRUCTION SET REFERENCE, A-M int_mm_comile_ss (__m128 a, __m128 b) int_mm_comigt_ss (__m128 a, __m128 b) int_mm_comige_ss (__m128 a, __m128 b) int_mm_comineq_ss (__m128 a, __m128 b) SIMD Floating-Point Exceptions Invalid (if SNaN or QNaN operands), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
INSTRUCTION SET REFERENCE, A-M CPUID—CPU Identification Opcode 0F A2 Instruction CPUID 64-Bit Mode Valid Compat/ Leg Mode Valid Description Returns processor identification and feature information to the EAX, EBX, ECX, and EDX registers, as determined by input entered in EAX (and, in some cases, ECX). Description The ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruction.
INSTRUCTION SET REFERENCE, A-M See also: “Serializing Instructions” in Chapter 7, “Multiple-Processor Management,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A AP-485, Intel Processor Identification and the CPUID Instruction (Order Number 241618) Table 3-12.
INSTRUCTION SET REFERENCE, A-M Table 3-12. Information Returned by CPUID Instruction (Contd.) Initial EAX Value 03H Information Provided about the Processor EAX EBX Reserved. Reserved. ECX Bits 00-31 of 96 bit processor serial number. (Available in Pentium III processor only; otherwise, the value in this register is reserved.) EDX Bits 32-63 of 96 bit processor serial number. (Available in Pentium III processor only; otherwise, the value in this register is reserved.
INSTRUCTION SET REFERENCE, A-M Table 3-12. Information Returned by CPUID Instruction (Contd.) Initial EAX Value Information Provided about the Processor CPUID leaves > 3 < 80000000 are visible only when IA32_MISC_ENABLES.BOOT_NT4[bit 22] = 0 (default). Deterministic Cache Parameters Leaf NOTE: 04H EAX EBX ECX EDX 04H output depends on the initial value in ECX. See also: “INPUT EAX = 4: Returns Deterministic Cache Parameters for each level on page 3-180.
INSTRUCTION SET REFERENCE, A-M Table 3-12. Information Returned by CPUID Instruction (Contd.
INSTRUCTION SET REFERENCE, A-M Table 3-12. Information Returned by CPUID Instruction (Contd.
INSTRUCTION SET REFERENCE, A-M Table 3-12. Information Returned by CPUID Instruction (Contd.) Initial EAX Value Information Provided about the Processor 80000001H EAX Extended Processor Signature and Extended Feature Bits.
INSTRUCTION SET REFERENCE, A-M Table 3-12. Information Returned by CPUID Instruction (Contd.
INSTRUCTION SET REFERENCE, A-M A vendor identification string is also returned in EBX, EDX, and ECX.
INSTRUCTION SET REFERENCE, A-M IA32_BIOS_SIGN_ID Returns Microcode Update Signature For processors that support the microcode update facility, the IA32_BIOS_SIGN_ID MSR is loaded with the update signature whenever CPUID executes. The signature is returned in the upper DWORD. For details, see Chapter 9 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.
INSTRUCTION SET REFERENCE, A-M Table 3-14. Processor Type Field Type Encoding Original OEM Processor 00B ® Intel OverDrive Processor 01B Dual processor (not applicable to Intel486 processors) 10B Intel reserved 11B NOTE See AP-485, Intel Processor Identification and the CPUID Instruction (Order Number 241618) and Chapter 14 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for information on identifying earlier IA-32 processors.
INSTRUCTION SET REFERENCE, A-M • Local APIC ID (high byte of EBX) — this number is the 8-bit ID that is assigned to the local APIC on the processor during power up. This field was introduced in the Pentium 4 processor. INPUT EAX = 1: Returns Feature Information in ECX and EDX When CPUID executes with EAX set to 1, feature information is returned in ECX and EDX. • • Figure 3-6 and Table 3-15 show encodings for ECX. Figure 3-7 and Table 3-16 show encodings for EDX.
INSTRUCTION SET REFERENCE, A-M Table 3-15. More on Extended Feature Information Returned in the ECX Register Bit # Mnemonic Description 0 SSE3 Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the processor supports this technology. 1-2 Reserved Reserved 3 MONITOR MONITOR/MWAIT. A value of 1 indicates the processor supports this feature. 4 DS-CPL CPL Qualified Debug Store.
INSTRUCTION SET REFERENCE, A-M ('; 3%(±3HQG %UN (1 70±7KHUP 0RQLWRU +77±0XOWL WKUHDGLQJ 66±6HOI 6QRRS 66( ±66( ([WHQVLRQV 66(±66( ([WHQVLRQV );65±);6$9( );56725 00;±00; 7HFKQRORJ\ $&3,±7KHUPDO 0RQLWRU DQG &ORFN &WUO '6±'HEXJ 6WRUH &/)6+±&)/86+ LQVWUXFWLRQ 361±3URFHVVRU 6HULDO 1XPEHU 36( ± 3DJH 6L]H ([WHQVLRQ 3$7±3DJH $WWULEXWH 7DEOH &029±&RQGLWLRQDO 0RYH &RPSDUH ,QVWUXFWLRQ 0&$±0DFKLQH &KHFN $UFKLWHFWXUH 3*(±37
INSTRUCTION SET REFERENCE, A-M Table 3-16. More on Feature Information Returned in the EDX Register (Contd.) Bit # Mnemonic Description 2 DE Debugging Extensions. Support for I/O breakpoints, including CR4.DE for controlling the feature, and optional trapping of accesses to DR4 and DR5. 3 PSE Page Size Extension. Large pages of size 4 MByte are supported, including CR4.
INSTRUCTION SET REFERENCE, A-M Table 3-16. More on Feature Information Returned in the EDX Register (Contd.) Bit # Mnemonic Description 14 MCA Machine Check Architecture. The Machine Check Architecture, which provides a compatible mechanism for error reporting in P6 family, Pentium 4, Intel Xeon processors, and future processors, is supported. The MCG_CAP MSR contains feature bits describing how many banks of error reporting MSRs are supported. 15 CMOV Conditional Move Instructions.
INSTRUCTION SET REFERENCE, A-M Table 3-16. More on Feature Information Returned in the EDX Register (Contd.) Bit # Mnemonic Description 27 SS Self Snoop. The processor supports the management of conflicting memory types by performing a snoop of its own cache structure for transactions issued to the bus. 28 HTT Multi-Threading. The physical processor package is capable of supporting more than one logical processor. 29 TM Thermal Monitor.
INSTRUCTION SET REFERENCE, A-M Table 3-17.
INSTRUCTION SET REFERENCE, A-M Table 3-17. Encoding of Cache and TLB Descriptors (Contd.
INSTRUCTION SET REFERENCE, A-M Table 3-17. Encoding of Cache and TLB Descriptors (Contd.) Descriptor Value Cache or TLB Description B0H Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries B3H Data TLB: 4 KByte pages, 4-way set associative, 128 entries B4H Data TLB1: 4 KByte pages, 4-way associative, 256 entries F0H 64-Byte prefetching F1H 128-Byte prefetching Example 3-1.
INSTRUCTION SET REFERENCE, A-M INPUT EAX = 4: Returns Deterministic Cache Parameters for Each Level When CPUID executes with EAX set to 4 and ECX contains an index value, the processor returns encoded data that describe a set of deterministic cache parameters (for the cache level associated with the input in ECX). Valid index values start from 0.
INSTRUCTION SET REFERENCE, A-M These two methods are discussed in the following sections. For methods that are available in early processors, see Section: “Identification of Earlier IA-32 Processors” in Chapter 14 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1. The Processor Brand String Method Figure 3-8 describes the algorithm used for detection of the brand string. Processor brand identification software should execute this algorithm on all Intel 64 and IA-32 processors.
INSTRUCTION SET REFERENCE, A-M How Brand Strings Work To use the brand string method, execute CPUID with EAX input of 8000002H through 80000004H. For each input value, CPUID returns 16 ASCII characters using EAX, EBX, ECX, and EDX. The returned string will be NULL-terminated. Table 3-18 shows the brand string that is returned by the first processor in the Pentium 4 processor family. Table 3-18.
INSTRUCTION SET REFERENCE, A-M 6FDQ %UDQG 6WULQJ LQ 5HYHUVH %\WH 2UGHU ]+0 RU 0DWFK ]+* RU 6XEVWULQJ ]+7 )DOVH ,) 6XEVWULQJ 0DWFKHG 'HWHUPLQH )UHT DQG 0XOWLSOLHU ,I ]+0 7UXH ,I ]+* 'HWHUPLQH 0XOWLSOLHU ,I ]+7 6FDQ 'LJLWV 8QWLO %ODQN 'HWHUPLQH )UHT ,Q 5HYHUVH 2UGHU 0D[ 4XDOLILHG )UHTXHQF\ )UHT [ 0XOWLSOLHU 5HSRUW (UURU 0XOWLSOLHU [ 0XOWLSOLHU [ 0XOWLSOLHU [ 5HYHUVH 'LJLWV 7R 'HFLPDO 9DOXH )UHT ;< = LI 'LJLWV = <; 20 Figure
INSTRUCTION SET REFERENCE, A-M family ID = 0FH, model = 03H, brand index method is no longer supported. Use brand string method instead. Table 3-19 shows brand indices that have identification strings associated with them. Table 3-19.
INSTRUCTION SET REFERENCE, A-M IA-32 Architecture Compatibility CPUID is not supported in early models of the Intel486 processor or in any IA-32 processor earlier than the Intel486 processor.
INSTRUCTION SET REFERENCE, A-M BREAK EAX = 4H: EAX ← Deterministic Cache Parameters Leaf; (* See Table 3-12. *) EBX ← Deterministic Cache Parameters Leaf; ECX ← Deterministic Cache Parameters Leaf; EDX ← Deterministic Cache Parameters Leaf; BREAK; EAX = 5H: EAX ← MONITOR/MWAIT Leaf; (* See Table 3-12. *) EBX ← MONITOR/MWAIT Leaf; ECX ← MONITOR/MWAIT Leaf; EDX ← MONITOR/MWAIT Leaf; BREAK; EAX = 6H: EAX ← Thermal and Power Management Leaf; (* See Table 3-12.
INSTRUCTION SET REFERENCE, A-M EAX = 80000002H: EAX ← Processor Brand String; EBX ← Processor Brand String, continued; ECX ← Processor Brand String, continued; EDX ← Processor Brand String, continued; BREAK; EAX = 80000003H: EAX ← Processor Brand String, continued; EBX ← Processor Brand String, continued; ECX ← Processor Brand String, continued; EDX ← Processor Brand String, continued; BREAK; EAX = 80000004H: EAX ← Processor Brand String, continued; EBX ← Processor Brand String, continued; ECX ← Processor
INSTRUCTION SET REFERENCE, A-M EAX ← Reserved; (* Information returned for highest basic information leaf. *) EBX ← Reserved; (* Information returned for highest basic information leaf. *) ECX ← Reserved; (* Information returned for highest basic information leaf. *) EDX ← Reserved; (* Information returned for highest basic information leaf. *) BREAK; ESAC; Flags Affected None. Exceptions (All Operating Modes) None.
INSTRUCTION SET REFERENCE, A-M CVTDQ2PD—Convert Packed Doubleword Integers to Packed DoublePrecision Floating-Point Values Opcode F3 0F E6 Instruction CVTDQ2PD xmm1, xmm2/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert two packed signed doubleword integers from xmm2/m128 to two packed double-precision floating-point values in xmm1.
INSTRUCTION SET REFERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault.
INSTRUCTION SET REFERENCE, A-M CVTDQ2PS—Convert Packed Doubleword Integers to Packed SinglePrecision Floating-Point Values Opcode 0F 5B /r Instruction CVTDQ2PS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert four packed signed doubleword integers from xmm2/m128 to four packed single-precision floating-point values in xmm1.
INSTRUCTION SET REFERENCE, A-M #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.
INSTRUCTION SET REFERENCE, A-M CVTPD2DQ—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers Opcode F2 0F E6 Instruction CVTPD2DQ xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert two packed doubleprecision floating-point values from xmm2/m128 to two packed signed doubleword integers in xmm1.
INSTRUCTION SET REFERENCE, A-M #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0.
INSTRUCTION SET REFERENCE, A-M #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. 3-196 Vol.
INSTRUCTION SET REFERENCE, A-M CVTPD2PI—Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers Opcode 66 0F 2D /r Instruction CVTPD2PI mm, xmm/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert two packed doubleprecision floating-point values from xmm/m128 to two packed signed doubleword integers in mm.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #MF If there is a pending x87 FPU exception. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #MF If there is a pending x87 FPU exception. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
INSTRUCTION SET REFERENCE, A-M CVTPD2PS—Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values Opcode 66 0F 5A /r Instruction CVTPD2PS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert two packed doubleprecision floating-point values in xmm2/m128 to two packed single-precision floating-point values in xmm1.
INSTRUCTION SET REFERENCE, A-M #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.
INSTRUCTION SET REFERENCE, A-M CVTPI2PD—Convert Packed Doubleword Integers to Packed DoublePrecision Floating-Point Values Opcode 66 0F 2A /r Instruction CVTPI2PD xmm, mm/m64* 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert two packed signed doubleword integers from mm/mem64 to two packed doubleprecision floating-point values in xmm. NOTES: * Operation is different for different operand sets; see the Description section.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0.
INSTRUCTION SET REFERENCE, A-M CVTPI2PS—Convert Packed Doubleword Integers to Packed SinglePrecision Floating-Point Values Opcode 0F 2A /r Instruction CVTPI2PS xmm, mm/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert two signed doubleword integers from mm/m64 to two single-precision floating-point values in xmm.
INSTRUCTION SET REFERENCE, A-M #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0.
INSTRUCTION SET REFERENCE, A-M #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) 3-208 Vol.
INSTRUCTION SET REFERENCE, A-M CVTPS2DQ—Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers Opcode 66 0F 5B /r Instruction CVTPS2DQ xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert four packed singleprecision floating-point values from xmm2/m128 to four packed signed doubleword integers in xmm1.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.
INSTRUCTION SET REFERENCE, A-M CVTPS2PD—Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values Opcode 0F 5A /r Instruction CVTPS2PD xmm1, xmm2/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert two packed single-precision floating-point values in xmm2/m64 to two packed double-precision floating-point values in xmm1.
INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) 3-214 Vol. 2 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
INSTRUCTION SET REFERENCE, A-M CVTPS2PI—Convert Packed Single-Precision Floating-Point Values to Packed Doubleword Integers Opcode 0F 2D /r Instruction CVTPS2PI mm, xmm/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert two packed single-precision floating-point values from xmm/m64 to two packed signed doubleword integers in mm.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #MF If there is a pending x87 FPU exception. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.
INSTRUCTION SET REFERENCE, A-M CVTSD2SI—Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer Opcode F2 0F 2D /r Instruction CVTSD2SI r32, xmm/m64 REX.W + F2 0F 2D /r CVTSD2SI r64, xmm/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Valid N.E. Description Convert one doubleprecision floating-point value from xmm/m64 to one signed doubleword integer r32. Convert one doubleprecision floating-point value from xmm/m64 to one signed quadword integer sign-extended into r64.
INSTRUCTION SET REFERENCE, A-M SIMD Floating-Point Exceptions Invalid, Precision. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0.
INSTRUCTION SET REFERENCE, A-M CVTSD2SS—Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value Opcode F2 0F 5A /r Instruction CVTSD2SS xmm1, xmm2/m64 64Bit Mode Valid Compat/ Leg Mode Valid Description Convert one double-precision floating-point value in xmm2/m64 to one single-precision floating-point value in xmm1.
INSTRUCTION SET REFERENCE, A-M #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
INSTRUCTION SET REFERENCE, A-M CVTSI2SD—Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value Opcode F2 0F 2A /r Instruction CVTSI2SD xmm, r/m32 REX.W + F2 0F 2A /r CVTSI2SD xmm, r/m64 64Bit Mode Valid Compat/ Leg Mode Valid Valid N.E. Description Convert one signed doubleword integer from r/m32 to one double-precision floating-point value in xmm. Convert one signed quadword integer from r/m64 to one double-precision floating-point value in xmm.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0.
INSTRUCTION SET REFERENCE, A-M CVTSI2SS—Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value Opcode F3 0F 2A /r Instruction CVTSI2SS xmm, r/m32 REX.W + F3 0F 2A /r CVTSI2SS xmm, r/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Valid N.E. Description Convert one signed doubleword integer from r/m32 to one single-precision floating-point value in xmm. Convert one signed quadword integer from r/m64 to one single-precision floating-point value in xmm.
INSTRUCTION SET REFERENCE, A-M SIMD Floating-Point Exceptions Precision. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0.
INSTRUCTION SET REFERENCE, A-M CVTSS2SD—Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value Opcode F3 0F 5A /r Instruction CVTSS2SD xmm1, xmm2/m32 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert one single-precision floating-point value in xmm2/m32 to one double-precision floating-point value in xmm1.
INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.
INSTRUCTION SET REFERENCE, A-M CVTSS2SI—Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer Opcode F3 0F 2D /r Instruction CVTSS2SI r32, xmm/m32 REX.W + F3 0F 2D /r CVTSS2SI r64, xmm/m32 64-Bit Mode Valid Compat/ Leg Mode Valid Valid N.E. Description Convert one single-precision floating-point value from xmm/m32 to one signed doubleword integer in r32. Convert one single-precision floating-point value from xmm/m32 to one signed quadword integer in r64.
INSTRUCTION SET REFERENCE, A-M SIMD Floating-Point Exceptions Invalid, Precision. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0.
INSTRUCTION SET REFERENCE, A-M CVTTPD2PI—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers Opcode 66 0F 2C /r Instruction CVTTPD2PI mm, xmm/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert two packer double-precision floating-point values from xmm/m128 to two packed signed doubleword integers in mm using truncation.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #MF If there is a pending x87 FPU exception. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
INSTRUCTION SET REFERENCE, A-M CVTTPD2DQ—Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers Opcode 66 0F E6 Instruction CVTTPD2DQ xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert two packed doubleprecision floating-point values from xmm2/m128 to two packed signed doubleword integers in xmm1 using truncation.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.
INSTRUCTION SET REFERENCE, A-M CVTTPS2DQ—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers Opcode F3 0F 5B /r Instruction CVTTPS2DQ xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert four single-precision floating-point values from xmm2/m128 to four signed doubleword integers in xmm1 using truncation.
INSTRUCTION SET REFERENCE, A-M #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
INSTRUCTION SET REFERENCE, A-M #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. 3-244 Vol.
INSTRUCTION SET REFERENCE, A-M CVTTPS2PI—Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Doubleword Integers Opcode 0F 2C /r Instruction CVTTPS2PI mm, xmm/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert two single-precision floatingpoint values from xmm/m64 to two signed doubleword signed integers in mm using truncation.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #MF If there is a pending x87 FPU exception. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
INSTRUCTION SET REFERENCE, A-M CVTTSD2SI—Convert with Truncation Scalar Double-Precision FloatingPoint Value to Signed Doubleword Integer Opcode F2 0F 2C /r Instruction CVTTSD2SI r32, xmm/m64 REX.W + F2 0F 2C /r CVTTSD2SI r64, xmm/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Valid N.E. Description Convert one double-precision floating-point value from xmm/m64 to one signed doubleword integer in r32 using truncation.
INSTRUCTION SET REFERENCE, A-M Intel C/C++ Compiler Intrinsic Equivalent int_mm_cvttsd_si32(__m128d a) SIMD Floating-Point Exceptions Invalid, Precision. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.
INSTRUCTION SET REFERENCE, A-M CVTTSS2SI—Convert with Truncation Scalar Single-Precision FloatingPoint Value to Doubleword Integer Opcode F3 0F 2C /r Instruction CVTTSS2SI r32, xmm/m32 REX.W + F3 0F 2C /r CVTTSS2SI r64, xmm/m32 64-Bit Mode Valid Compat/ Leg Mode Valid Valid N.E. Description Convert one single-precision floating-point value from xmm/m32 to one signed doubleword integer in r32 using truncation.
INSTRUCTION SET REFERENCE, A-M Intel C/C++ Compiler Intrinsic Equivalent int_mm_cvttss_si32(__m128d a) SIMD Floating-Point Exceptions Invalid, Precision. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.
INSTRUCTION SET REFERENCE, A-M CWD/CDQ/CQO—Convert Word to Doubleword/Convert Doubleword to Quadword Opcode 99 99 Instruction CWD CDQ 64-Bit Mode Valid Valid Compat/ Leg Mode Valid Valid REX.W + 99 CQO Valid N.E. Description DX:AX ← sign-extend of AX. EDX:EAX ← sign-extend of EAX. RDX:RAX← sign-extend of RAX.
INSTRUCTION SET REFERENCE, A-M Operation IF OperandSize = 16 (* CWD instruction *) THEN DX ← SignExtend(AX); ELSE IF OperandSize = 32 (* CDQ instruction *) EDX ← SignExtend(EAX); FI; ELSE IF 64-Bit Mode and OperandSize = 64 (* CQO instruction*) RDX ← SignExtend(RAX); FI; FI; Flags Affected None. Exceptions (All Operating Modes) None. Vol.
INSTRUCTION SET REFERENCE, A-M DAA—Decimal Adjust AL after Addition Opcode 27 Instruction DAA 64-Bit Mode Invalid Compat/ Leg Mode Valid Description Decimal adjust AL after addition. Description Adjusts the sum of two packed BCD values to create a packed BCD result. The AL register is the implied source and destination operand. The DAA instruction is only useful when it follows an ADD instruction that adds (binary addition) two 2-digit, packed BCD values and stores a byte result in the AL register.
INSTRUCTION SET REFERENCE, A-M Example ADD AL, BL Before: AL=79H BL=35H EFLAGS(OSZAPC)=XXXXXX After: AL=AEH BL=35H EFLAGS(0SZAPC)=110000 DAA Before: AL=AEH BL=35H EFLAGS(OSZAPC)=110000 After: AL=14H BL=35H EFLAGS(0SZAPC)=X00111 DAA Before: AL=2EH BL=35H EFLAGS(OSZAPC)=110000 After: AL=34H BL=35H EFLAGS(0SZAPC)=X00101 Flags Affected The CF and AF flags are set if the adjustment of the value results in a decimal carry in either digit of the result (see the “Operation” section above).
INSTRUCTION SET REFERENCE, A-M DAS—Decimal Adjust AL after Subtraction Opcode 2F Instruction DAS 64-Bit Mode Invalid Compat/ Leg Mode Valid Description Decimal adjust AL after subtraction. Description Adjusts the result of the subtraction of two packed BCD values to create a packed BCD result. The AL register is the implied source and destination operand.
INSTRUCTION SET REFERENCE, A-M Example SUB AL, BL Before: AL=35H BL=47H EFLAGS(OSZAPC)= XXXXXX After: AL=EEH BL=47H EFLAGS(0SZAPC)= 010111 DAA Before: AL=EEH BL=47H EFLAGS(OSZAPC)= 010111 After: AL=88H BL=47H EFLAGS(0SZAPC)= X10111 Flags Affected The CF and AF flags are set if the adjustment of the value results in a decimal borrow in either digit of the result (see the “Operation” section above). The SF, ZF, and PF flags are set according to the result. The OF flag is undefined.
INSTRUCTION SET REFERENCE, A-M DEC—Decrement by 1 Opcode FE /1 REX + FE /1 FF /1 FF /1 REX.W + FF /1 48+rw 48+rd Instruction DEC r/m8 DEC r/m8* DEC r/m16 DEC r/m32 DEC r/m64 DEC r16 DEC r32 64-Bit Mode Valid Valid Valid Valid Valid N.E. N.E. Compat/ Leg Mode Valid N.E. Valid Valid N.E. Valid Valid Description Decrement r/m8 by 1. Decrement r/m8 by 1. Decrement r/m16 by 1. Decrement r/m32 by 1. Decrement r/m64 by 1. Decrement r16 by 1. Decrement r32 by 1.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If the destination operand is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
INSTRUCTION SET REFERENCE, A-M DIV—Unsigned Divide Opcode F6 /6 Instruction DIV r/m8 64-Bit Mode Valid Compat/ Leg Mode Valid REX + F6 /6 DIV r/m8* Valid N.E. F7 /6 DIV r/m16 Valid Valid F7 /6 DIV r/m32 Valid Valid REX.W + F7 /6 DIV r/m64 Valid N.E. Description Unsigned divide AX by r/m8, with result stored in AL ← Quotient, AH ← Remainder. Unsigned divide AX by r/m8, with result stored in AL ← Quotient, AH ← Remainder.
INSTRUCTION SET REFERENCE, A-M Table 3-20.
INSTRUCTION SET REFERENCE, A-M FI; ELSE IF 64-Bit Mode and Operandsize = 64 (* Doublequadword/quadword operation *) THEN temp ← RDX:RAX / SRC; IF temp > FFFFFFFFFFFFFFFFH THEN #DE; (* Divide error *) ELSE RAX ← temp; RDX ← RDX:RAX MOD SRC; FI; FI; FI; Flags Affected The CF, OF, SF, ZF, AF, and PF flags are undefined. Protected Mode Exceptions #DE If the source operand (divisor) is 0 #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #DE If the source operand (divisor) is 0. If the quotient is too large for the designated register. #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made.
INSTRUCTION SET REFERENCE, A-M DIVPD—Divide Packed Double-Precision Floating-Point Values Opcode 66 0F 5E /r Instruction DIVPD xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Divide packed double-precision floatingpoint values in xmm1 by packed doubleprecision floating-point values xmm2/m128.
INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. 3-268 Vol.
INSTRUCTION SET REFERENCE, A-M DIVPS—Divide Packed Single-Precision Floating-Point Values Opcode 0F 5E /r Instruction DIVPS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Divide packed single-precision floatingpoint values in xmm1 by packed singleprecision floating-point values xmm2/m128.
INSTRUCTION SET REFERENCE, A-M #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.
INSTRUCTION SET REFERENCE, A-M DIVSD—Divide Scalar Double-Precision Floating-Point Values Opcode F2 0F 5E /r Instruction DIVSD xmm1, xmm2/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Description Divide low double-precision floatingpoint value n xmm1 by low doubleprecision floating-point value in xmm2/mem64.
INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0.
INSTRUCTION SET REFERENCE, A-M DIVSS—Divide Scalar Single-Precision Floating-Point Values Opcode Instruction F3 0F 5E /r DIVSS xmm1, xmm2/m32 64-Bit Mode Compat/ Leg Mode Valid Valid Description Divide low single-precision floatingpoint value in xmm1 by low singleprecision floating-point value in xmm2/m32.
INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
INSTRUCTION SET REFERENCE, A-M EMMS—Empty MMX Technology State Opcode 0F 77 Instruction EMMS 64-Bit Mode Valid Compat/ Leg Mode Valid Description Set the x87 FPU tag word to empty. Description Sets the values of all the tags in the x87 FPU tag word to empty (all 1s). This operation marks the x87 FPU data registers (which are aliased to the MMX technology registers) as available for use by x87 FPU floating-point instructions.
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol.
INSTRUCTION SET REFERENCE, A-M ENTER—Make Stack Frame for Procedure Parameters Opcode C8 iw 00 Instruction ENTER imm16, 0 64Bit Mode Valid C8 iw 01 ENTER imm16,1 Valid Valid C8 iw ib ENTER imm16, imm8 Valid Valid Compat/ Leg Mode Valid Description Create a stack frame for a procedure. Create a nested stack frame for a procedure. Create a nested stack frame for a procedure. Description Creates a stack frame for a procedure.
INSTRUCTION SET REFERENCE, A-M Operation NestingLevel ← NestingLevel MOD 32 IF 64-Bit Mode (StackSize = 64) THEN Push(RBP); FrameTemp ← RSP; ELSE IF StackSize = 32 THEN Push(EBP); FrameTemp ← ESP; FI; ELSE (* StackSize = 16 *) Push(BP); FrameTemp ← SP; FI; IF NestingLevel = 0 THEN GOTO CONTINUE; FI; IF (NestingLevel > 1) THEN FOR i ← 1 to (NestingLevel - 1) DO IF 64-Bit Mode (StackSize = 64) THEN RBP ← RBP - 8; Push([RBP]); (* Quadword push *) ELSE IF OperandSize = 32 THEN IF StackSize = 32 EBP ← EBP - 4;
INSTRUCTION SET REFERENCE, A-M FI; FI; OD; FI; IF 64-Bit Mode (StackSize = 64) THEN Push(FrameTemp); (* Quadword push *) ELSE IF OperandSize = 32 THEN Push(FrameTemp); FI; (* Doubleword push *) ELSE (* OperandSize = 16 *) Push(FrameTemp); (* Word push *) FI; CONTINUE: IF 64-Bit Mode (StackSize = 64) THEN RBP ← FrameTemp; RSP ← RSP − Size; ELSE IF StackSize = 32 THEN EBP ← FrameTemp; ESP ← ESP − Size; FI; ELSE (* StackSize = 16 *) BP ← FrameTemp; SP ← SP − Size; FI; END; Flags Affected None.
INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #SS(0) If the new value of the SP or ESP register is outside the stack segment limit. Virtual-8086 Mode Exceptions #SS(0) If the new value of the SP or ESP register is outside the stack segment limit. #PF(fault-code) If a page fault occurs or if a write using the final value of the stack pointer (within the current stack segment) would cause a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode.
INSTRUCTION SET REFERENCE, A-M F2XM1—Compute 2x–1 Opcode D9 F0 Instruction F2XM1 64-Bit Mode Valid Compat/ Leg Mode Valid Description Replace ST(0) with (2ST(0) – 1). Description Computes the exponential value of 2 to the power of the source operand minus 1. The source operand is located in register ST(0) and the result is also stored in ST(0). The value of the source operand must lie in the range –1.0 to +1.0. If the source value is outside this range, the result is undefined.
INSTRUCTION SET REFERENCE, A-M #D Source is a denormal value. #U Result is too small for destination format. #P Value cannot be represented exactly in destination format. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Real-Address Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Virtual-8086 Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Compatibility Mode Exceptions Same exceptions as in Protected Mode.
INSTRUCTION SET REFERENCE, A-M FABS—Absolute Value Opcode D9 E1 Instruction FABS 64Bit Mode Valid Compat/ Leg Mode Valid Description Replace ST with its absolute value. Description Clears the sign bit of ST(0) to create the absolute value of the operand. The following table shows the results obtained when creating the absolute value of various classes of numbers. Table 3-22.
INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Virtual-8086 Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol.
INSTRUCTION SET REFERENCE, A-M FADD/FADDP/FIADD—Add Opcode D8 /0 Instruction FADD m32fp 64-Bit Mode Valid Compat/ Leg Mode Valid DC /0 FADD m64fp Valid Valid D8 C0+i FADD ST(0), ST(i) Valid Valid DC C0+i FADD ST(i), ST(0) Valid Valid DE C0+i FADDP ST(i), ST(0) Valid Valid DE C1 FADDP Valid Valid DA /0 FIADD m32int Valid Valid DE /0 FIADD m16int Valid Valid Description Add m32fp to ST(0) and store result in ST(0). Add m64fp to ST(0) and store result in ST(0).
INSTRUCTION SET REFERENCE, A-M When the sum of two operands with opposite signs is 0, the result is +0, except for the round toward −∞ mode, in which case the result is −0. When the source operand is an integer 0, it is treated as a +0. When both operand are infinities of the same sign, the result is ∞ of the expected sign. If both operands are infinities of opposite signs, an invalid-operation exception is generated. See Table 3-23. Table 3-23.
INSTRUCTION SET REFERENCE, A-M FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Point Exceptions #IS Stack underflow occurred. #IA Operand is an SNaN value or unsupported format. Operands are infinities of unlike sign. #D Source operand is a denormal value. #U Result is too small for destination format. #O Result is too large for destination format.
INSTRUCTION SET REFERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs.
INSTRUCTION SET REFERENCE, A-M FBLD—Load Binary Coded Decimal Opcode DF /4 Instruction FBLD m80 dec 64-Bit Mode Valid Compat/ Leg Mode Valid Description Convert BCD value to floating-point and push onto the FPU stack. Description Converts the BCD source operand into double extended-precision floating-point format and pushes the value onto the FPU stack. The source operand is loaded without rounding errors. The sign of the source operand is preserved, including that of −0.
INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.
INSTRUCTION SET REFERENCE, A-M FBSTP—Store BCD Integer and Pop Opcode DF /6 Instruction FBSTP m80bcd 64-Bit Mode Valid Compat/ Leg Mode Valid Description Store ST(0) in m80bcd and pop ST(0). Description Converts the value in the ST(0) register to an 18-digit packed BCD integer, stores the result in the destination operand, and pops the register stack.
INSTRUCTION SET REFERENCE, A-M arithmetic-operand exception (#IA) is generated and no value is stored in the destination operand. If the invalid-operation exception is masked, the packed BCD indefinite value is stored in memory. This instruction’s operation is the same in non-64-bit modes and 64-bit mode. Operation DEST ← BCD(ST(0)); PopRegisterStack; FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined.
INSTRUCTION SET REFERENCE, A-M #SS If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs.
INSTRUCTION SET REFERENCE, A-M FCHS—Change Sign Opcode D9 E0 Instruction FCHS 64-Bit Mode Valid Compat/ Leg Mode Valid Description Complements sign of ST(0). Description Complements the sign bit of ST(0). This operation changes a positive value into a negative value of equal magnitude or vice versa. The following table shows the results obtained when changing the sign of various classes of numbers. Table 3-25.
INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Virtual-8086 Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. 3-298 Vol.
INSTRUCTION SET REFERENCE, A-M FCLEX/FNCLEX—Clear Exceptions Opcode* 9B DB E2 Instruction FCLEX 64-Bit Mode Valid Compat/ Leg Mode Valid DB E2 FNCLEX* Valid Valid Description Clear floating-point exception flags after checking for pending unmasked floating-point exceptions. Clear floating-point exception flags without checking for pending unmasked floating-point exceptions. NOTES: * See IA-32 Architecture Compatibility section below.
INSTRUCTION SET REFERENCE, A-M FPU Flags Affected The PE, UE, OE, ZE, DE, IE, ES, SF, and B flags in the FPU status word are cleared. The C0, C1, C2, and C3 flags are undefined. Floating-Point Exceptions None. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Real-Address Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Virtual-8086 Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Compatibility Mode Exceptions Same exceptions as in Protected Mode.
INSTRUCTION SET REFERENCE, A-M FCMOVcc—Floating-Point Conditional Move Opcode* DA C0+i DA C8+i DA D0+i Instruction FCMOVB ST(0), ST(i) FCMOVE ST(0), ST(i) FCMOVBE ST(0), ST(i) 64Bit Mode Valid Valid Valid DA D8+i DB C0+i DB C8+i DB D0+i FCMOVU ST(0), ST(i) FCMOVNB ST(0), ST(i) FCMOVNE ST(0), ST(i) FCMOVNBE ST(0), ST(i) Valid Valid Valid Valid Valid Valid Valid Valid DB D8+i FCMOVNU ST(0), ST(i) Valid Valid Compat/ Leg Mode* Valid Valid Valid Description Move if below (CF=1).
INSTRUCTION SET REFERENCE, A-M Operation IF condition TRUE THEN ST(0) ← ST(i); FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred. C0, C2, C3 Undefined. Floating-Point Exceptions #IS Stack underflow occurred. Integer Flags Affected None. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode.
INSTRUCTION SET REFERENCE, A-M FCOM/FCOMP/FCOMPP—Compare Floating Point Values Opcode D8 /2 DC /2 D8 D0+i D8 D1 D8 /3 Instruction FCOM m32fp FCOM m64fp FCOM ST(i) FCOM FCOMP m32fp 64-Bit Mode Valid Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid Valid Valid DC /3 FCOMP m64fp Valid Valid D8 D8+i FCOMP ST(i) Valid Valid D8 D9 FCOMP Valid Valid DE D9 FCOMPP Valid Valid Description Compare ST(0) with m32fp. Compare ST(0) with m64fp. Compare ST(0) with ST(i).
INSTRUCTION SET REFERENCE, A-M The FCOMP instruction pops the register stack following the comparison operation and the FCOMPP instruction pops the register stack twice following the comparison operation. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The FCOM instructions perform the same operation as the FUCOM instructions. The only difference is how they handle QNaN operands.
INSTRUCTION SET REFERENCE, A-M Floating-Point Exceptions #IS Stack underflow occurred. #IA One or both operands are NaN values or have unsupported formats. Register is marked empty. #D One or both operands are denormal values. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-306 Vol.
INSTRUCTION SET REFERENCE, A-M FCOMI/FCOMIP/ FUCOMI/FUCOMIP—Compare Floating Point Values and Set EFLAGS Opcode DB F0+i Instruction FCOMI ST, ST(i) 64-Bit Mode Valid Compat/ Leg Mode Valid DF F0+i FCOMIP ST, ST(i) Valid Valid DB E8+i FUCOMI ST, ST(i) Valid Valid DF E8+i FUCOMIP ST, ST(i) Valid Valid Description Compare ST(0) with ST(i) and set status flags accordingly. Compare ST(0) with ST(i), set status flags accordingly, and pop register stack.
INSTRUCTION SET REFERENCE, A-M If the operation results in an invalid-arithmetic-operand exception being raised, the status flags in the EFLAGS register are set only if the exception is masked. The FCOMI/FCOMIP and FUCOMI/FUCOMIP instructions clear the OF flag in the EFLAGS register (regardless of whether an invalid-operation exception is detected). The FCOMIP and FUCOMIP instructions also pop the register stack following the comparison operation.
INSTRUCTION SET REFERENCE, A-M FI; FI; FI; IF Instruction is FCOMIP or FUCOMIP THEN PopRegisterStack; FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred; otherwise, set to 0. C0, C2, C3 Not affected. Floating-Point Exceptions #IS Stack underflow occurred. #IA (FCOMI or FCOMIP instruction) One or both operands are NaN values or have unsupported formats. (FUCOMI or FUCOMIP instruction) One or both operands are SNaN values (but not QNaNs) or have undefined formats.
INSTRUCTION SET REFERENCE, A-M FCOS—Cosine Opcode D9 FF Instruction FCOS 64-Bit Mode Valid Compat/ Leg Mode Valid Description Replace ST(0) with its cosine. Description Computes the cosine of the source operand in register ST(0) and stores the result in ST(0). The source operand must be given in radians and must be within the range − 263 to +263. The following table shows the results obtained when taking the cosine of various classes of numbers. Table 3-28.
INSTRUCTION SET REFERENCE, A-M Operation IF |ST(0)| < 263 THEN C2 ← 0; ST(0) ← cosine(ST(0)); ELSE (* Source operand is out-of-range *) C2 ← 1; FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. Undefined if C2 is 1. C2 Set to 1 if outside range (−263 < source operand < +263); otherwise, set to 0. C0, C3 Undefined. Floating-Point Exceptions #IS Stack underflow occurred. #IA Source operand is an SNaN value, ∞, or unsupported format.
INSTRUCTION SET REFERENCE, A-M FDECSTP—Decrement Stack-Top Pointer Opcode D9 F6 Instruction FDECSTP 64-Bit Mode Valid Compat/ Leg Mode Valid Description Decrement TOP field in FPU status word. Description Subtracts one from the TOP field of the FPU status word (decrements the top-ofstack pointer). If the TOP field contains a 0, it is set to 7. The effect of this instruction is to rotate the stack by one position. The contents of the FPU data registers and tag register are not affected.
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol.
INSTRUCTION SET REFERENCE, A-M FDIV/FDIVP/FIDIV—Divide Opcode D8 /6 Instruction FDIV m32fp 64-Bit Mode Valid Compat/ Leg Mode Valid DC /6 FDIV m64fp Valid Valid D8 F0+i FDIV ST(0), ST(i) Valid Valid DC F8+i FDIV ST(i), ST(0) Valid Valid DE F8+i FDIVP ST(i), ST(0) Valid Valid DE F9 FDIVP Valid Valid DA /6 FIDIV m32int Valid Valid DE /6 FIDIV m16int Valid Valid Description Divide ST(0) by m32fp and store result in ST(0). Divide ST(0) by m64fp and store result in ST(0).
INSTRUCTION SET REFERENCE, A-M If an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if the exception is masked, an ∞ of the appropriate sign is stored in the destination operand. The following table shows the results obtained when dividing various classes of numbers, assuming that neither overflow nor underflow occurs. Table 3-29.
INSTRUCTION SET REFERENCE, A-M IF Instruction = FDIVP THEN PopRegisterStack; FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Point Exceptions #IS Stack underflow occurred. #IA Operand is an SNaN value or unsupported format. #D Source is a denormal value. #Z DEST / ±0, where DEST is not equal to ±0. #U Result is too small for destination format.
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode.
INSTRUCTION SET REFERENCE, A-M FDIVR/FDIVRP/FIDIVR—Reverse Divide Opcode D8 /7 Instruction FDIVR m32fp 64Bit Mode Valid DC /7 FDIVR m64fp Valid Valid D8 F8+i Valid Valid Valid Valid Valid Valid DE F1 FDIVR ST(0), ST(i) FDIVR ST(i), ST(0) FDIVRP ST(i), ST(0) FDIVRP Valid Valid DA /7 FIDIVR m32int Valid Valid DE /7 FIDIVR m16int Valid Valid DC F0+i DE F0+i Compat/ Leg Mode Valid Description Divide m32fp by ST(0) and store result in ST(0).
INSTRUCTION SET REFERENCE, A-M If an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if the exception is masked, an ∞ of the appropriate sign is stored in the destination operand. The following table shows the results obtained when dividing various classes of numbers, assuming that neither overflow nor underflow occurs. Table 3-30.
INSTRUCTION SET REFERENCE, A-M FI; IF Instruction = FDIVRP THEN PopRegisterStack; FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Point Exceptions #IS Stack underflow occurred. #IA Operand is an SNaN value or unsupported format. #D Source is a denormal value. ±∞ / ±∞; ±0 / ±0 #Z SRC / ±0, where SRC is not equal to ±0. #U Result is too small for destination format.
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode.
INSTRUCTION SET REFERENCE, A-M FFREE—Free Floating-Point Register Opcode DD C0+i Instruction FFREE ST(i) 64-Bit Mode Valid Compat/ Leg Mode Valid Description Sets tag for ST(i) to empty. Description Sets the tag in the FPU tag register associated with register ST(i) to empty (11B). The contents of ST(i) and the FPU stack-top pointer (TOP) are not affected. This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
INSTRUCTION SET REFERENCE, A-M FICOM/FICOMP—Compare Integer Opcode DE /2 DA /2 DE /3 Instruction FICOM m16int FICOM m32int FICOMP m16int 64-Bit Mode Valid Valid Valid Compat/ Leg Mode Valid Valid Valid DA /3 FICOMP m32int Valid Valid Description Compare ST(0) with m16int. Compare ST(0) with m32int. Compare ST(0) with m16int and pop stack register. Compare ST(0) with m32int and pop stack register.
INSTRUCTION SET REFERENCE, A-M ESAC; IF Instruction = FICOMP THEN PopRegisterStack; FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred; otherwise, set to 0. C0, C2, C3 See table on previous page. Floating-Point Exceptions #IS Stack underflow occurred. #IA One or both operands are NaN values or have unsupported formats. #D One or both operands are denormal values.
INSTRUCTION SET REFERENCE, A-M #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M FILD—Load Integer Opcode DF /0 DB /0 DF /5 Instruction FILD m16int FILD m32int FILD m64int 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Valid Valid Description Push m16int onto the FPU register stack. Push m32int onto the FPU register stack. Push m64int onto the FPU register stack. Description Converts the signed-integer source operand into double extended-precision floatingpoint format and pushes the value onto the FPU register stack.
INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.
INSTRUCTION SET REFERENCE, A-M FINCSTP—Increment Stack-Top Pointer Opcode D9 F7 Instructio n FINCSTP 64-Bit Mode Valid Compat/ Leg Mode Valid Description Increment the TOP field in the FPU status register. Description Adds one to the TOP field of the FPU status word (increments the top-of-stack pointer). If the TOP field contains a 7, it is set to 0. The effect of this instruction is to rotate the stack by one position. The contents of the FPU data registers and tag register are not affected.
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol.
INSTRUCTION SET REFERENCE, A-M FINIT/FNINIT—Initialize Floating-Point Unit Opcode 9B DB E3 Instruction FINIT 64-Bit Mode Valid Compat/ Leg Mode Valid DB E3 FNINIT* Valid Valid Description Initialize FPU after checking for pending unmasked floating-point exceptions. Initialize FPU without checking for pending unmasked floating-point exceptions. NOTES: * See IA-32 Architecture Compatibility section below.
INSTRUCTION SET REFERENCE, A-M Operation FPUControlWord ← 037FH; FPUStatusWord ← 0; FPUTagWord ← FFFFH; FPUDataPointer ← 0; FPUInstructionPointer ← 0; FPULastInstructionOpcode ← 0; FPU Flags Affected C0, C1, C2, C3 set to 0. Floating-Point Exceptions None. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode.
INSTRUCTION SET REFERENCE, A-M FIST/FISTP—Store Integer Opcode DF /2 DB /2 DF /3 Instruction FIST m16int FIST m32int FISTP m16int 64-Bit Mode Valid Valid Valid Compat/ Leg Mode Valid Valid Valid DB /3 FISTP m32int Valid Valid DF /7 FISTP m64int Valid Valid Description Store ST(0) in m16int. Store ST(0) in m32int. Store ST(0) in m16int and pop register stack. Store ST(0) in m32int and pop register stack. Store ST(0) in m64int and pop register stack.
INSTRUCTION SET REFERENCE, A-M Table 3-32. FIST/FISTP Results (Contd.) ST(0) DEST NaN * NOTES: F Means finite floating-point value. I Means integer. * Indicates floating-point invalid-operation (#IA) exception. ** 0 or ±1, depending on the rounding mode. If the source value is a non-integral value, it is rounded to an integer value, according to the rounding mode specified by the RC field of the FPU control word.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
INSTRUCTION SET REFERENCE, A-M FISTTP—Store Integer with Truncation Opcode DF /1 Instruction FISTTP m16int 64-Bit Mode Valid Compat/ Leg Mode Valid DB /1 FISTTP m32int Valid Valid DD /1 FISTTP m64int Valid Valid Description Store ST(0) in m16int with truncation. Store ST(0) in m32int with truncation. Store ST(0) in m64int with truncation.
INSTRUCTION SET REFERENCE, A-M Numeric Exceptions Invalid, Stack Invalid (stack underflow), Precision. Protected Mode Exceptions #GP(0) If the destination is in a nonwritable segment. For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #NM If CR0.EM[bit 2] = 1.
INSTRUCTION SET REFERENCE, A-M #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-338 Vol.
INSTRUCTION SET REFERENCE, A-M FLD—Load Floating Point Value Instructio n FLD m32fp FLD m64fp FLD m80fp FLD ST(i) Opcode D9 /0 DD /0 DB /5 D9 C0+i 64-Bit Mode Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid Valid Description Push m32fp onto the FPU register stack. Push m64fp onto the FPU register stack. Push m80fp onto the FPU register stack. Push ST(i) onto the FPU register stack. Description Pushes the source operand onto the FPU register stack.
INSTRUCTION SET REFERENCE, A-M Floating-Point Exceptions #IS Stack underflow or overflow occurred. #IA Source operand is an SNaN. Does not occur if the source operand is in double extended-precision floating-point format (FLD m80fp or FLD ST(i)). #D Source operand is a denormal value. Does not occur if the source operand is in double extended-precision floating-point format. Protected Mode Exceptions #GP(0) If destination is located in a non-writable segment.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
INSTRUCTION SET REFERENCE, A-M FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ—Load Constant Opcode* D9 E8 D9 E9 D9 EA D9 EB D9 EC D9 ED D9 EE Instruction FLD1 FLDL2T FLDL2E FLDPI FLDLG2 FLDLN2 FLDZ 64-Bit Mode Valid Valid Valid Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid Valid Valid Valid Valid Description Push +1.0 onto the FPU register stack. Push log210 onto the FPU register stack. Push log2e onto the FPU register stack. Push π onto the FPU register stack.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol.
INSTRUCTION SET REFERENCE, A-M FLDCW—Load x87 FPU Control Word Opcode D9 /5 Instruction FLDCW m2byte 64Bit Mode Valid Compat/ Leg Mode Valid Description Load FPU control word from m2byte. Description Loads the 16-bit source operand into the FPU control word. The source operand is a memory location. This instruction is typically used to establish or change the FPU’s mode of operation.
INSTRUCTION SET REFERENCE, A-M #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M FLDENV—Load x87 FPU Environment Opcode D9 /4 Instruction FLDENV m14/28byte 64-Bit Mode Valid Compat/ Leg Mode Valid Description Load FPU environment from m14byte or m28byte. Description Loads the complete x87 FPU operating environment from memory into the FPU registers. The source operand specifies the first byte of the operating-environment data in memory. This data is typically written to the specified memory location by a FSTENV or FNSTENV instruction.
INSTRUCTION SET REFERENCE, A-M FPU Flags Affected The C0, C1, C2, C3 flags are loaded. Floating-Point Exceptions None; however, if an unmasked exception is loaded in the status word, it is generated upon execution of the next “waiting” floating-point instruction. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-348 Vol.
INSTRUCTION SET REFERENCE, A-M FMUL/FMULP/FIMUL—Multiply Opcode D8 /1 Instruction FMUL m32fp 64-Bit Mode Valid Compat/ Leg Mode Valid DC /1 FMUL m64fp Valid Valid D8 C8+i FMUL ST(0), ST(i) Valid Valid DC C8+i FMUL ST(i), ST(0) Valid Valid DE C8+i FMULP ST(i), ST(0) Valid Valid DE C9 FMULP Valid Valid DA /1 FIMUL m32int Valid Valid DE /1 FIMUL m16int Valid Valid Description Multiply ST(0) by m32fp and store result in ST(0). Multiply ST(0) by m64fp and store result in ST(0).
INSTRUCTION SET REFERENCE, A-M The sign of the result is always the exclusive-OR of the source signs, even if one or more of the values being multiplied is 0 or ∞. When the source operand is an integer 0, it is treated as a +0. The following table shows the results obtained when multiplying various classes of numbers, assuming that neither overflow nor underflow occurs. Table 3-34.
INSTRUCTION SET REFERENCE, A-M FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Point Exceptions #IS #IA Stack underflow occurred. Operand is an SNaN value or unsupported format. One operand is ±0 and the other is ±∞. #D Source operand is a denormal value. #U Result is too small for destination format. #O Result is too large for destination format.
INSTRUCTION SET REFERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs.
INSTRUCTION SET REFERENCE, A-M FNOP—No Operation Opcode D9 D0 Instruction FNOP 64Bit Mode Valid Compat/ Leg Mode Valid Description No operation is performed. Description Performs no FPU operation. This instruction takes up space in the instruction stream but does not affect the FPU or machine context, except the EIP register. This instruction’s operation is the same in non-64-bit modes and 64-bit mode. FPU Flags Affected C0, C1, C2, C3 undefined. Floating-Point Exceptions None.
INSTRUCTION SET REFERENCE, A-M FPATAN—Partial Arctangent Opcode * D9 F3 Instructio n FPATAN 64-Bit Mode Valid Compat/ Leg Mode Valid Description Replace ST(1) with arctan(ST(1)/ST(0)) and pop the register stack. NOTES: * See IA-32 Architecture Compatibility section below. Description Computes the arctangent of the source operand in register ST(1) divided by the source operand in register ST(0), stores the result in ST(1), and pops the FPU register stack.
INSTRUCTION SET REFERENCE, A-M Table 3-35. FPATAN Results ST(0) −∞ ST(1) −F −0 +0 +F +∞ NaN −∞ −3π/4* −π/2 −π/2 −π/2 −π/2 −π/4* NaN −F −π −π to −π/2 −π/2 −π/2 −π/2 to − 0 -0 NaN −0 −π −π −π* −0* −0 −0 NaN +0 +π +π +π* +0* +0 +0 NaN +F +π +π to +π/2 +π/2 +π/2 +π/2 to +0 +0 NaN +∞ +3π/4* +π/2 +π/2 +π/2 +π/2 +π/4* NaN NaN NaN NaN NaN NaN NaN NaN NaN NOTES: F Means finite floating-point value.
INSTRUCTION SET REFERENCE, A-M FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Point Exceptions #IS Stack underflow occurred. #IA Source operand is an SNaN value or unsupported format. #D Source operand is a denormal value. #U Result is too small for destination format. #P Value cannot be represented exactly in destination format. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M FPREM—Partial Remainder Instructio n FPREM Opcode D9 F8 64-Bit Mode Valid Compat/ Leg Mode Valid Description Replace ST(0) with the remainder obtained from dividing ST(0) by ST(1). Description Computes the remainder obtained from dividing the value in the ST(0) register (the dividend) by the value in the ST(1) register (the divisor or modulus), and stores the result in ST(0).
INSTRUCTION SET REFERENCE, A-M The FPREM instruction does not compute the remainder specified in IEEE Std 754. The IEEE specified remainder can be computed with the FPREM1 instruction. The FPREM instruction is provided for compatibility with the Intel 8087 and Intel287 math coprocessors. The FPREM instruction gets its name “partial remainder” because of the way it computes the remainder. This instruction arrives at a remainder through iterative subtraction.
INSTRUCTION SET REFERENCE, A-M FPU Flags Affected C0 Set to bit 2 (Q2) of the quotient. C1 Set to 0 if stack underflow occurred; otherwise, set to least significant bit of quotient (Q0). C2 Set to 0 if reduction complete; set to 1 if incomplete. C3 Set to bit 1 (Q1) of the quotient. Floating-Point Exceptions #IS Stack underflow occurred. #IA Source operand is an SNaN value, modulus is 0, dividend is ∞, or unsupported format. #D Source operand is a denormal value.
INSTRUCTION SET REFERENCE, A-M FPREM1—Partial Remainder Instructio n FPREM1 Opcode D9 F5 64-Bit Mode Valid Compat/ Leg Mode Valid Description Replace ST(0) with the IEEE remainder obtained from dividing ST(0) by ST(1). Description Computes the IEEE remainder obtained from dividing the value in the ST(0) register (the dividend) by the value in the ST(1) register (the divisor or modulus), and stores the result in ST(0).
INSTRUCTION SET REFERENCE, A-M The FPREM1 instruction computes the remainder specified in IEEE Standard 754. This instruction operates differently from the FPREM instruction in the way that it rounds the quotient of ST(0) divided by ST(1) to an integer (see the “Operation” section below). Like the FPREM instruction, FPREM1 computes the remainder through iterative subtraction, but can reduce the exponent of ST(0) by no more than 63 in one execution of the instruction.
INSTRUCTION SET REFERENCE, A-M C2 Set to 0 if reduction complete; set to 1 if incomplete. C3 Set to bit 1 (Q1) of the quotient. Floating-Point Exceptions #IS Stack underflow occurred. #IA Source operand is an SNaN value, modulus (divisor) is 0, dividend is ∞, or unsupported format. #D Source operand is a denormal value. #U Result is too small for destination format. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception.
INSTRUCTION SET REFERENCE, A-M FPTAN—Partial Tangent Opcode D9 F2 Instruction FPTAN 64-Bit Mode Valid Compat/ Leg Mode Valid Description Replace ST(0) with its tangent and push 1 onto the FPU stack. Description Computes the tangent of the source operand in register ST(0), stores the result in ST(0), and pushes a 1.0 onto the FPU register stack. The source operand must be given in radians and must be less than ±263.
INSTRUCTION SET REFERENCE, A-M instance, the cotangent (which is the reciprocal of the tangent) can be computed by executing a FDIVR instruction after the FPTAN instruction. This instruction’s operation is the same in non-64-bit modes and 64-bit mode. Operation IF ST(0) < 263 THEN C2 ← 0; ST(0) ← tan(ST(0)); TOP ← TOP − 1; ST(0) ← 1.0; ELSE (* Source operand is out-of-range *) C2 ← 1; FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred; set to 1 if stack overflow occurred.
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol.
INSTRUCTION SET REFERENCE, A-M FRNDINT—Round to Integer Opcode D9 FC Instruction FRNDINT 64-Bit Mode Valid Compat/ Leg Mode Valid Description Round ST(0) to an integer. Description Rounds the source value in the ST(0) register to the nearest integral value, depending on the current rounding mode (setting of the RC field of the FPU control word), and stores the result in ST(0). If the source value is ∞, the value is not changed.
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol.
INSTRUCTION SET REFERENCE, A-M FRSTOR—Restore x87 FPU State Opcode DD /4 Instruction FRSTOR m94/108byte 64-Bit Mode Valid Compat/ Leg Mode Valid Description Load FPU state from m94byte or m108byte. Description Loads the FPU state (operating environment and register stack) from the memory area specified with the source operand. This state data is typically written to the specified memory location by a previous FSAVE/FNSAVE instruction.
INSTRUCTION SET REFERENCE, A-M ST(6) ← SRC[ST(6)]; ST(7) ← SRC[ST(7)]; FPU Flags Affected The C0, C1, C2, C3 flags are loaded. Floating-Point Exceptions None; however, this operation might unmask an existing exception that has been detected but not generated, because it was masked. Here, the exception is generated at the completion of the instruction. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-370 Vol.
INSTRUCTION SET REFERENCE, A-M FSAVE/FNSAVE—Store x87 FPU State Opcode 9B DD /6 Instruction FSAVE m94/108byte 64-Bit Mode Valid Compat/ Leg Mode Valid DD /6 FNSAVE* m94/108byte Valid Valid Description Store FPU state to m94byte or m108byte after checking for pending unmasked floatingpoint exceptions. Then reinitialize the FPU. Store FPU environment to m94byte or m108byte without checking for pending unmasked floating-point exceptions. Then re-initialize the FPU.
INSTRUCTION SET REFERENCE, A-M instructions separately. If an exception is generated for either of these instructions, the save EIP points to the instruction that caused the exception. This instruction’s operation is the same in non-64-bit modes and 64-bit mode. IA-32 Architecture Compatibility For Intel math coprocessors and FPUs prior to the Intel Pentium processor, an FWAIT instruction should be executed before attempting to read from the memory image stored with a prior FSAVE/FNSAVE instruction.
INSTRUCTION SET REFERENCE, A-M FPU Flags Affected The C0, C1, C2, and C3 flags are saved and then cleared. Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) If destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-374 Vol.
INSTRUCTION SET REFERENCE, A-M FSCALE—Scale Opcode D9 FD Instruction FSCALE 64-Bit Mode Valid Compat/ Leg Mode Valid Description Scale ST(0) by ST(1). Description Truncates the value in the source operand (toward 0) to an integral value and adds that value to the exponent of the destination operand. The destination and source operands are floating-point values located in registers ST(0) and ST(1), respectively. This instruction provides rapid multiplication or division by integral powers of 2.
INSTRUCTION SET REFERENCE, A-M In this example, the FXTRACT instruction extracts the significand and exponent from the value in ST(0) and stores them in ST(0) and ST(1) respectively. The FSCALE then scales the significand in ST(0) by the exponent in ST(1), recreating the original value before the FXTRACT operation was performed.
INSTRUCTION SET REFERENCE, A-M FSIN—Sine Opcode D9 FE Instruction FSIN 64-Bit Mode Valid Compat/ Leg Mode Valid Description Replace ST(0) with its sine. Description Computes the sine of the source operand in register ST(0) and stores the result in ST(0). The source operand must be given in radians and must be within the range − 263 to +263. The following table shows the results obtained when taking the sine of various classes of numbers, assuming that underflow does not occur. Table 3-40.
INSTRUCTION SET REFERENCE, A-M Operation IF ST(0) < 263 THEN C2 ← 0; ST(0) ← sin(ST(0)); ELSE (* Source operand out of range *) C2 ← 1; FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C2 Set to 1 if outside range (−263 < source operand < +263); otherwise, set to 0. C0, C3 Undefined. Floating-Point Exceptions #IS Stack underflow occurred. #IA Source operand is an SNaN value, ∞, or unsupported format.
INSTRUCTION SET REFERENCE, A-M FSINCOS—Sine and Cosine Opcode D9 FB Instruction FSINCOS 64-Bit Mode Valid Compat/ Leg Mode Valid Description Compute the sine and cosine of ST(0); replace ST(0) with the sine, and push the cosine onto the register stack. Description Computes both the sine and the cosine of the source operand in register ST(0), stores the sine in ST(0), and pushes the cosine onto the top of the FPU register stack.
INSTRUCTION SET REFERENCE, A-M This instruction’s operation is the same in non-64-bit modes and 64-bit mode. Operation IF ST(0) < 263 THEN C2 ← 0; TEMP ← cosine(ST(0)); ST(0) ← sine(ST(0)); TOP ← TOP − 1; ST(0) ← TEMP; ELSE (* Source operand out of range *) C2 ← 1; FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred; set to 1 of stack overflow occurs. Set if result was rounded up; cleared otherwise. C2 Set to 1 if outside range (−263 < source operand < +263); otherwise, set to 0.
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol.
INSTRUCTION SET REFERENCE, A-M FSQRT—Square Root Opcode D9 FA Instructio n FSQRT 64-Bit Mode Valid Compat/ Leg Mode Valid Description Computes square root of ST(0) and stores the result in ST(0). Description Computes the square root of the source value in the ST(0) register and stores the result in ST(0). The following table shows the results obtained when taking the square root of various classes of numbers, assuming that neither overflow nor underflow occurs. Table 3-42.
INSTRUCTION SET REFERENCE, A-M Floating-Point Exceptions #IS #IA Stack underflow occurred. Source operand is an SNaN value or unsupported format. Source operand is a negative value (except for −0). #D Source operand is a denormal value. #P Value cannot be represented exactly in destination format. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. Real-Address Mode Exceptions Same exceptions as in Protected Mode.
INSTRUCTION SET REFERENCE, A-M FST/FSTP—Store Floating Point Value Opcode D9 /2 DD /2 DD D0+i D9 /3 DD /3 DB /7 DD D8+i Instruction FST m32fp FST m64fp FST ST(i) FSTP m32fp FSTP m64fp FSTP m80fp FSTP ST(i) 64-Bit Mode Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Description Copy ST(0) to m32fp. Copy ST(0) to m64fp. Copy ST(0) to ST(i). Copy ST(0) to m32fp and pop register stack. Copy ST(0) to m64fp and pop register stack.
INSTRUCTION SET REFERENCE, A-M If the destination operand is a non-empty register, the invalid-operation exception is not generated. This instruction’s operation is the same in non-64-bit modes and 64-bit mode. Operation DEST ← ST(0); IF Instruction = FSTP THEN PopRegisterStack; FI; FPU Flags Affected C1 Set to 0 if stack underflow occurred. Indicates rounding direction of if the floating-point inexact exception (#P) is generated: 0 ← not roundup; 1 ← roundup. C0, C2, C3 Undefined.
INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.
INSTRUCTION SET REFERENCE, A-M FSTCW/FNSTCW—Store x87 FPU Control Word Opcode 9B D9 /7 Instruction FSTCW m2byte 64Bit Mode Valid D9 /7 FNSTCW* m2byte Valid Compat/ Leg Mode Valid Valid Description Store FPU control word to m2byte after checking for pending unmasked floating-point exceptions. Store FPU control word to m2byte without checking for pending unmasked floating-point exceptions. NOTES: * See IA-32 Architecture Compatibility section below.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
INSTRUCTION SET REFERENCE, A-M FSTENV/FNSTENV—Store x87 FPU Environment Opcode 9B D9 /6 Instruction FSTENV m14/28byte D9 /6 FNSTENV* m14/28byte 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Store FPU environment to m14byte or m28byte after checking for pending unmasked floating-point exceptions. Then mask all floating-point exceptions. Store FPU environment to m14byte or m28byte without checking for pending unmasked floating-point exceptions.
INSTRUCTION SET REFERENCE, A-M IA-32 Architecture Compatibility When operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual circumstances) for an FNSTENV instruction to be interrupted prior to being executed to handle a pending FPU exception. See the section titled “No-Wait FPU Instructions Can Get FPU Interrupt in Window” in Appendix D of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a description of these circumstances.
INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.
INSTRUCTION SET REFERENCE, A-M FSTSW/FNSTSW—Store x87 FPU Status Word Opcode 9B DD /7 Instruction FSTSW m2byte 64-Bit Mode Valid Compat/ Leg Mode Valid 9B DF E0 FSTSW AX Valid Valid DD /7 FNSTSW* m2byte Valid Valid DF E0 FNSTSW* AX Valid Valid Description Store FPU status word at m2byte after checking for pending unmasked floatingpoint exceptions. Store FPU status word in AX register after checking for pending unmasked floatingpoint exceptions.
INSTRUCTION SET REFERENCE, A-M IA-32 Architecture Compatibility When operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual circumstances) for an FNSTSW instruction to be interrupted prior to being executed to handle a pending FPU exception. See the section titled “No-Wait FPU Instructions Can Get FPU Interrupt in Window” in Appendix D of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a description of these circumstances.
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode.
INSTRUCTION SET REFERENCE, A-M FSUB/FSUBP/FISUB—Subtract Opcode D8 /4 Instruction FSUB m32fp 64-Bit Mode Valid Compat/ Leg Mode Valid DC /4 FSUB m64fp Valid Valid D8 E0+i FSUB ST(0), ST(i) Valid Valid DC E8+i FSUB ST(i), ST(0) Valid Valid DE E8+i FSUBP ST(i), ST(0) Valid Valid DE E9 FSUBP Valid Valid DA /4 FISUB m32int Valid Valid DE /4 FISUB m16int Valid Valid Description Subtract m32fp from ST(0) and store result in ST(0).
INSTRUCTION SET REFERENCE, A-M Table 3-43 shows the results obtained when subtracting various classes of numbers from one another, assuming that neither overflow nor underflow occurs. Here, the SRC value is subtracted from the DEST value (DEST − SRC = result). When the difference between two operands of like sign is 0, the result is +0, except for the round toward −∞ mode, in which case the result is −0. This instruction also guarantees that +0 − (−0) = +0, and that −0 − (+0) = −0.
INSTRUCTION SET REFERENCE, A-M FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Point Exceptions #IS Stack underflow occurred. #IA Operand is an SNaN value or unsupported format. Operands are infinities of like sign. #D Source operand is a denormal value. #U Result is too small for destination format. #O Result is too large for destination format.
INSTRUCTION SET REFERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #PF(fault-code) If a page fault occurs.
INSTRUCTION SET REFERENCE, A-M FSUBR/FSUBRP/FISUBR—Reverse Subtract Opcode D8 /5 Instruction FSUBR m32fp 64-Bit Mode Valid Compat/ Leg Mode Valid DC /5 FSUBR m64fp Valid Valid D8 E8+i FSUBR ST(0), ST(i) Valid Valid DC E0+i FSUBR ST(i), ST(0) Valid Valid DE E0+i FSUBRP ST(i), ST(0) Valid Valid DE E1 FSUBRP Valid Valid DA /5 FISUBR m32int Valid Valid DE /5 FISUBR m16int Valid Valid Description Subtract ST(0) from m32fp and store result in ST(0).
INSTRUCTION SET REFERENCE, A-M The FISUBR instructions convert an integer source operand to double extendedprecision floating-point format before performing the subtraction. The following table shows the results obtained when subtracting various classes of numbers from one another, assuming that neither overflow nor underflow occurs. Here, the DEST value is subtracted from the SRC value (SRC − DEST = result).
INSTRUCTION SET REFERENCE, A-M FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Point Exceptions #IS Stack underflow occurred. #IA Operand is an SNaN value or unsupported format. Operands are infinities of like sign. #D Source operand is a denormal value. #U Result is too small for destination format. #O Result is too large for destination format.
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode.
INSTRUCTION SET REFERENCE, A-M FTST—TEST Opcode D9 E4 Instruction FTST 64-Bit Mode Valid Compat/ Leg Mode Valid Description Compare ST(0) with 0.0. Description Compares the value in the ST(0) register with 0.0 and sets the condition code flags C0, C2, and C3 in the FPU status word according to the results (see table below). Table 3-45. FTST Results Condition C3 C2 C0 ST(0) > 0.0 0 0 0 ST(0) < 0.0 0 0 1 ST(0) = 0.
INSTRUCTION SET REFERENCE, A-M Floating-Point Exceptions #IS Stack underflow occurred. #IA The source operand is a NaN value or is in an unsupported format. #D The source operand is a denormal value. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode.
INSTRUCTION SET REFERENCE, A-M FUCOM/FUCOMP/FUCOMPP—Unordered Compare Floating Point Values Opcode DD E0+i DD E1 DD E8+i Instruction FUCOM ST(i) FUCOM FUCOMP ST(i) 64-Bit Mode Valid Valid Valid Compat/ Leg Mode Valid Valid Valid DD E9 FUCOMP Valid Valid DA E9 FUCOMPP Valid Valid Description Compare ST(0) with ST(i). Compare ST(0) with ST(1). Compare ST(0) with ST(i) and pop register stack. Compare ST(0) with ST(1) and pop register stack. Compare ST(0) with ST(1) and pop register stack twice.
INSTRUCTION SET REFERENCE, A-M The FUCOMP instruction pops the register stack following the comparison operation and the FUCOMPP instruction pops the register stack twice following the comparison operation. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
INSTRUCTION SET REFERENCE, A-M Floating-Point Exceptions #IS Stack underflow occurred. #IA One or both operands are SNaN values or have unsupported formats. Detection of a QNaN value in and of itself does not raise an invalid-operand exception. #D One or both operands are denormal values. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. Real-Address Mode Exceptions Same exceptions as in Protected Mode.
INSTRUCTION SET REFERENCE, A-M FXAM—ExamineModR/M Opcode D9 E5 Instruction FXAM 64-Bit Mode Valid Compat/ Leg Mode Valid Description Classify value or number in ST(0). Description Examines the contents of the ST(0) register and sets the condition code flags C0, C2, and C3 in the FPU status word to indicate the class of value or number in the register (see the table below). . Table 3-47.
INSTRUCTION SET REFERENCE, A-M FPU Flags Affected C1 Sign of value in ST(0). C0, C2, C3 See Table 3-47. Floating-Point Exceptions None. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode.
INSTRUCTION SET REFERENCE, A-M FXCH—Exchange Register Contents Opcode D9 C8+i Instruction FXCH ST(i) 64-Bit Mode Valid Compat/ Leg Mode Valid D9 C9 FXCH Valid Valid Description Exchange the contents of ST(0) and ST(i). Exchange the contents of ST(0) and ST(1). Description Exchanges the contents of registers ST(0) and ST(i). If no source operand is specified, the contents of ST(0) and ST(1) are exchanged.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. 3-412 Vol.
INSTRUCTION SET REFERENCE, A-M FXRSTOR—Restore x87 FPU, MMX Technology, SSE, SSE2, and SSE3 State Opcode 0F AE /1 Instruction FXRSTOR m512byte 64-Bit Mode Valid Compat/ Leg Mode Valid Description Restore the x87 FPU, MMX, XMM, and MXCSR register state from m512byte. Description Reloads the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte memory image specified in the source operand.
INSTRUCTION SET REFERENCE, A-M x87 FPU and SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. (See alignment check exception [#AC] below.) #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CPUID.01H:EDX.FXSR[bit 24] = 0.
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. #AC For unaligned memory reference. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment.
INSTRUCTION SET REFERENCE, A-M FXSAVE—Save x87 FPU, MMX Technology, SSE, and SSE2 State Opcode 0F AE /0 64-Bit Mode Valid Instruction FXSAVE m512byte Compat/ Leg Mode Valid Description Save the x87 FPU, MMX, XMM, and MXCSR register state to m512byte. Description Saves the current state of the x87 FPU, MMX technology, XMM, and MXCSR registers to a 512-byte memory location specified in the destination operand.
INSTRUCTION SET REFERENCE, A-M Table 3-48. Non-64-bit-Mode Layout of FXSAVE and FXRSTOR Memory Region (Contd.) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XMM7 272 Reserved 288 Reserved 304 Reserved 320 Reserved 336 Reserved 352 Reserved 368 Reserved 384 Reserved 400 Reserved 416 Reserved 432 Reserved 448 Reserved 464 Reserved 480 Reserved 496 The destination operand contains the first byte of the memory image, and it must be aligned on a 16-byte boundary.
INSTRUCTION SET REFERENCE, A-M Table 3-49. Field Definitions (Contd.) Field Definition FTW x87 FPU Tag Word (8 bits). The tag information saved here is abridged, as described in the following paragraphs. See Figure 8-7 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for the layout of the x87 FPU tag word. FOP x87 FPU Opcode (16 bits). The lower 11 bits of this field contain the opcode, upper 5 bits are reserved.
INSTRUCTION SET REFERENCE, A-M Table 3-49. Field Definitions (Contd.) Field Definition ST0/MM0 through ST7/MM7 x87 FPU or MMX technology registers. These 80-bit fields contain the x87 FPU data registers or the MMX technology registers, depending on the state of the processor prior to the execution of the FXSAVE instruction.
INSTRUCTION SET REFERENCE, A-M retains the current state. To clean the x87 FPU state, an application must explicitly execute an FINIT instruction after an FXSAVE instruction to reinitialize the x87 FPU state. • The format of the memory image saved with the FXSAVE instruction is the same regardless of the current addressing mode (32-bit or 16-bit) and operating mode (protected, real address, or system management).
INSTRUCTION SET REFERENCE, A-M registers, XMM0 through XMM15, are saved. But the layout of the 64-bit FXSAVE map has two flavors, depending on the value of the REX.W bit. The difference of these two flavors is in the FPU IP and FPU DP pointers. When REX.W = 0, the FPU IP is saved as CS with the 32 bit IP, and the FPU DP is saved as DS with the 32 bit DP. When REX.W = 1, the FPU IP and FPU DP are both 64 bit values without and segment selectors.
INSTRUCTION SET REFERENCE, A-M Table 3-51. Layout of the 64-bit-mode FXSAVE Map with Promoted OperandSize (Contd.) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 448 Reserved 464 Reserved 480 Reserved 496 Table 3-52.
INSTRUCTION SET REFERENCE, A-M Table 3-52. Layout of the 64-bit-mode FXSAVE Map with Default OperandSize (Contd.) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 416 Reserved 432 Reserved 448 Reserved 464 Reserved 480 Reserved 496 Operation IF 64-Bit Mode THEN IF REX.
INSTRUCTION SET REFERENCE, A-M exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may vary with implementation, as follows. In all implementations where #AC is not signaled, a general protection exception is signaled in its place. In addition, the width of the alignment check may also vary with implementation.
INSTRUCTION SET REFERENCE, A-M #AC If this exception is disabled a general protection exception (#GP) is signaled if the memory operand is not aligned on a 16-byte boundary, as described above. If the alignment check exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may vary with implementation, as follows. In all implementations where #AC is not signaled, a general protection exception is signaled in its place.
INSTRUCTION SET REFERENCE, A-M FXTRACT—Extract Exponent and Significand Opcode D9 F4 Instruction FXTRACT 64-Bit Mode Valid Compat/ Leg Mode Valid Description Separate value in ST(0) into exponent and significand, store exponent in ST(0), and push the significand onto the register stack. Description Separates the source value in the ST(0) register into its exponent and significand, stores the exponent in ST(0), and pushes the significand onto the register stack.
INSTRUCTION SET REFERENCE, A-M Floating-Point Exceptions #IS Stack underflow or overflow occurred. #IA Source operand is an SNaN value or unsupported format. #Z ST(0) operand is ±0. #D Source operand is a denormal value. Protected Mode Exceptions #NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode.
INSTRUCTION SET REFERENCE, A-M FYL2X—Compute y ∗ log2x Opcode D9 F1 Instruction FYL2X 64-Bit Mode Valid Compat/ Leg Mode Valid Description Replace ST(1) with (ST(1) ∗ log2ST(0)) and pop the register stack. Description Computes (ST(1) ∗ log2 (ST(0))), stores the result in resister ST(1), and pops the FPU register stack. The source operand in ST(0) must be a non-zero positive number.
INSTRUCTION SET REFERENCE, A-M Operation ST(1) ← ST(1) ∗ log2ST(0); PopRegisterStack; FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined. Floating-Point Exceptions #IS Stack underflow occurred. #IA Either operand is an SNaN or unsupported format. Source operand in register ST(0) is a negative finite value (not −0). #Z Source operand in register ST(0) is ±0. #D Source operand is a denormal value.
INSTRUCTION SET REFERENCE, A-M FYL2XP1—Compute y ∗ log2(x +1) Opcode D9 F9 Instruction FYL2XP1 64-Bit Mode Valid Compat/ Leg Mode Valid Description Replace ST(1) with ST(1) ∗ log2(ST(0) + 1.0) and pop the register stack. Description Computes (ST(1) ∗ log2(ST(0) + 1.0)), stores the result in register ST(1), and pops the FPU register stack. The source operand in ST(0) must be in the range: – ( 1 – 2 ⁄ 2 ) )to ( 1 – 2 ⁄ 2 ) The source operand in ST(1) can range from −∞ to +∞.
INSTRUCTION SET REFERENCE, A-M equation is used to calculate the scale factor for a particular logarithm base, where n is the logarithm base desired for the result of the FYL2XP1 instruction: scale factor ← logn 2 This instruction’s operation is the same in non-64-bit modes and 64-bit mode. Operation ST(1) ← ST(1) ∗ log2(ST(0) + 1.0); PopRegisterStack; FPU Flags Affected C1 Set to 0 if stack underflow occurred. Set if result was rounded up; cleared otherwise. C0, C2, C3 Undefined.
INSTRUCTION SET REFERENCE, A-M HADDPD—Packed Double-FP Horizontal Add Opcode 66 0F 7C /r 64-Bit Mode Valid Instruction HADDPD xmm1, xmm2/m128 Compat/ Leg Mode Valid Description Horizontal add packed doubleprecision floating-point values from xmm2/m128 to xmm1. Description Adds the double-precision floating-point values in the high and low quadwords of the destination operand and stores the result in the low quadword of the destination operand.
INSTRUCTION SET REFERENCE, A-M Operation xmm1[63:0] = xmm1[63:0] + xmm1[127:64]; xmm1[127:64] = xmm2/m128[63:0] + xmm2/m128[127:64]; Intel C/C++ Compiler Intrinsic Equivalent HADDPD __m128d _mm_hadd_pd(__m128d a, __m128d b) Exceptions When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated. Numeric Exceptions Overflow, Underflow, Invalid, Precision, Denormal.
INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. Virtual 8086 Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M HADDPS—Packed Single-FP Horizontal Add Opcode F2 0F 7C /r Instruction HADDPS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Horizontal add packed singleprecision floating-point values from xmm2/m128 to xmm1. Description Adds the single-precision floating-point values in the first and second dwords of the destination operand and stores the result in the first dword of the destination operand.
INSTRUCTION SET REFERENCE, A-M In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
INSTRUCTION SET REFERENCE, A-M Real Address Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM If CR0.TS[bit 3] = 1. #XM For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1). #UD If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0.
INSTRUCTION SET REFERENCE, A-M #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID feature flag SSE3 is 0. 3-438 Vol.
INSTRUCTION SET REFERENCE, A-M HLT—Halt Opcode F4 Instruction HLT 64-Bit Mode Valid Compat/ Leg Mode Valid Description Halt Description Stops instruction execution and places the processor in a HALT state. An enabled interrupt (including NMI and SMI), a debug exception, the BINIT# signal, the INIT# signal, or the RESET# signal will resume execution.
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. 3-440 Vol.
INSTRUCTION SET REFERENCE, A-M HSUBPD—Packed Double-FP Horizontal Subtract Opcode 66 0F 7D /r Instruction HSUBPD xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Horizontal subtract packed doubleprecision floating-point values from xmm2/m128 to xmm1. Description The HSUBPD instruction subtracts horizontally the packed DP FP numbers of both operands.
INSTRUCTION SET REFERENCE, A-M Operation xmm1[63:0] = xmm1[63:0] − xmm1[127:64]; xmm1[127:64] = xmm2/m128[63:0] − xmm2/m128[127:64]; Intel C/C++ Compiler Intrinsic Equivalent HSUBPD __m128d _mm_hsub_pd(__m128d a, __m128d b) Exceptions When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated. Numeric Exceptions Overflow, Underflow, Invalid, Precision, Denormal.
INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. Virtual 8086 Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M HSUBPS—Packed Single-FP Horizontal Subtract Opcode F2 0F 7D /r Instruction HSUBPS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Horizontal subtract packed singleprecision floating-point values from xmm2/m128 to xmm1. Description Subtracts the single-precision floating-point value in the second dword of the destination operand from the first dword of the destination operand and stores the result in the first dword of the destination operand.
INSTRUCTION SET REFERENCE, A-M +68%36 [PP [PP P > @ > @ > @ > @ [PP P > @ > @ > @ > @ [PP [PP P > @ [PP P > @ [PP P > @ [PP P > @ [PP > @ [PP > @ [PP > @ [PP > @ > @ > @ > @ 5(68/7 [PP > @ 20 Figure 3-13. HSUBPS—Packed Single-FP Horizontal Subtract In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
INSTRUCTION SET REFERENCE, A-M Numeric Exceptions Overflow, Underflow, Invalid, Precision, Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM For an unmasked Streaming SIMD Extensions numeric exception (CR4.
INSTRUCTION SET REFERENCE, A-M Virtual 8086 Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM If CR0.TS[bit 3] = 1. #XM For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 1). #UD If CR0.EM[bit 2] = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0). If CR4.OSFXSR[bit 9] = 0.
INSTRUCTION SET REFERENCE, A-M IDIV—Signed Divide Opcode F6 /7 Instruction IDIV r/m8 64-Bit Mode Valid Compat/ Leg Mode Valid REX + F6 /7 IDIV r/m8* Valid N.E. F7 /7 IDIV r/m16 Valid Valid F7 /7 IDIV r/m32 Valid Valid REX.W + F7 /7 IDIV r/m64 Valid N.E. Description Signed divide AX by r/m8, with result stored in: AL ← Quotient, AH ← Remainder. Signed divide AX by r/m8, with result stored in AL ← Quotient, AH ← Remainder.
INSTRUCTION SET REFERENCE, A-M Table 3-55.
INSTRUCTION SET REFERENCE, A-M (* If a positive result is greater than 7FFFFFFFH or a negative result is less than 80000000H *) THEN #DE; (* Divide error *) ELSE EAX ← temp; EDX ← EDXE:AX SignedModulus SRC; FI; FI; ELSE IF OperandSize = 64 (* Doublequadword/quadword operation *) temp ← RDX:RAX / SRC; (* Signed division *) IF (temp > 7FFFFFFFFFFFH) or (temp < 8000000000000000H) (* If a positive result is greater than 7FFFFFFFFFFFH or a negative result is less than 8000000000000000H *) THEN #DE; (* Divide er
INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #DE If the source operand (divisor) is 0. The signed result (quotient) is too large for the destination. #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. Virtual-8086 Mode Exceptions #DE If the source operand (divisor) is 0. The signed result (quotient) is too large for the destination.
INSTRUCTION SET REFERENCE, A-M IMUL—Signed Multiply Opcode F6 /5 F7 /5 F7 /5 REX.W + F7 /5 0F AF /r Instruction IMUL r/m8* IMUL r/m16 IMUL r/m32 IMUL r/m64 IMUL r16, r/m16 64-Bit Mode Valid Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid N.E. Valid 0F AF /r IMUL r32, r/m32 Valid Valid REX.W + 0F AF /r 6B /r ib IMUL r64, r/m64 Valid N.E. Valid Valid Valid Valid Valid N.E.
INSTRUCTION SET REFERENCE, A-M Opcode 69 /r id REX.W + 69 /r id Instruction IMUL r32, imm32 IMUL r64, imm32 64-Bit Mode Valid Compat/ Leg Mode Valid Valid N.E. Description doubleword register ← r/m32 ∗ immediate doubleword. Quadword register ← r/m64 ∗ immediate doubleword. NOTES: * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH. Description Performs a signed multiplication of two operands.
INSTRUCTION SET REFERENCE, A-M signed or unsigned. The CF and OF flags, however, cannot be used to determine if the upper half of the result is non-zero. In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R prefix permits access to additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. Use of REX.W modifies the three forms of the instruction as follows.
INSTRUCTION SET REFERENCE, A-M THEN temp ← DEST ∗ SRC (* Signed multiplication; temp is double DEST size *) DEST ← DEST ∗ SRC (* Signed multiplication *) IF temp ≠ DEST THEN CF ← 1; OF ← 1; ELSE CF ← 0; OF ← 0; FI; ELSE (* NumberOfOperands = 3 *) DEST ← SRC1 ∗ SRC2 (* Signed multiplication *) temp ← SRC1 ∗ SRC2 (* Signed multiplication; temp is double SRC1 size *) IF temp ≠ DEST THEN CF ← 1; OF ← 1; ELSE CF ← 0; OF ← 0; FI; FI; FI; Flags Affected For the one operand form of the instruction, the CF and OF
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode.
INSTRUCTION SET REFERENCE, A-M IN—Input from Port Opcode E4 ib Instruction IN AL, imm8 64-Bit Mode Valid Compat/ Leg Mode Valid E5 ib IN AX, imm8 Valid Valid E5 ib IN EAX, imm8 Valid Valid EC ED ED IN AL,DX IN AX,DX IN EAX,DX Valid Valid Valid Valid Valid Valid Description Input byte from imm8 I/O port address into AL. Input word from imm8 I/O port address into AX. Input dword from imm8 I/O port address into EAX. Input byte from I/O port in DX into AL.
INSTRUCTION SET REFERENCE, A-M FI; ELSE (Real Mode or Protected Mode with CPL ≤ IOPL *) DEST ← SRC; (* Read from selected I/O port *) FI; Flags Affected None. Protected Mode Exceptions #GP(0) If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the corresponding I/O permission bits in TSS for the I/O port being accessed is 1. Real-Address Mode Exceptions None.
INSTRUCTION SET REFERENCE, A-M INC—Increment by 1 Opcode FE /0 REX + FE /0 FF /0 FF /0 REX.W + FF /0 40+ rw** 40+ rd Instruction INC r/m8 INC r/m8* INC r/m16 INC r/m32 INC r/m64 INC r16 INC r32 64-Bit Mode Valid Valid Valid Valid Valid N.E. N.E. Compat/ Leg Mode Valid N.E. Valid Valid N.E. Valid Valid Description Increment r/m byte by 1. Increment r/m byte by 1. Increment r/m word by 1. Increment r/m doubleword by 1. Increment r/m quadword by 1. Increment word register by 1.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If the destination operand is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULLsegment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
INSTRUCTION SET REFERENCE, A-M INS/INSB/INSW/INSD—Input from Port to String Opcode 6C Instruction INS m8, DX 64-Bit Mode Valid Compat/ Leg Mode Valid 6D INS m16, DX Valid Valid 6D INS m32, DX Valid Valid 6C INSB Valid Valid 6D INSW Valid Valid 6D INSD Valid Valid Description Input byte from I/O port specified in DX into memory location specified in ES:(E)DI or RDI.1 Input word from I/O port specified in DX into memory location specified in ES:(E)DI or RDI.
INSTRUCTION SET REFERENCE, A-M destination operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword), but it does not have to specify the correct location. The location is always specified by the ES:(E)DI registers, which must be loaded correctly before the INS instruction is executed. The no-operands form provides “short forms” of the byte, word, and doubleword versions of the INS instructions.
INSTRUCTION SET REFERENCE, A-M IF (Byte transfer) THEN IF DF = 0 THEN (E)DI ← (E)DI + 1; ELSE (E)DI ← (E)DI – 1; FI; ELSE IF (Word transfer) THEN IF DF = 0 THEN (E)DI ← (E)DI + 2; ELSE (E)DI ← (E)DI – 2; FI; ELSE (* Doubleword transfer *) THEN IF DF = 0 THEN (E)DI ← (E)DI + 4; ELSE (E)DI ← (E)DI – 4; FI; FI; FI; FI64-bit Mode: IF (Byte transfer) THEN IF DF = 0 THEN (E|R)DI ← (E|R)DI + 1; ELSE (E|R)DI ← (E|R)DI – 1; FI; ELSE IF (Word transfer) THEN IF DF = 0 THEN (E)DI ← (E)DI + 2; ELSE (E)DI ← (E)DI – 2; F
INSTRUCTION SET REFERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit. Virtual-8086 Mode Exceptions #GP(0) If any of the I/O permission bits in the TSS for the I/O port being accessed is 1.
INSTRUCTION SET REFERENCE, A-M INT n/INTO/INT 3—Call to Interrupt Procedure Opcode CC CD ib Instruction INT 3 INT imm8 64-Bit Mode Valid Valid Compat/ Leg Mode Valid Valid CE INTO Invalid Valid Description Interrupt 3—trap to debugger. Interrupt vector number specified by immediate byte. Interrupt 4—if overflow flag is 1.
INSTRUCTION SET REFERENCE, A-M The action of the INT n instruction (including the INTO and INT 3 instructions) is similar to that of a far call made with the CALL instruction. The primary difference is that with the INT n instruction, the EFLAGS register is pushed onto the stack before the return address. (The return address is a far address consisting of the current values of the CS and EIP registers.
INSTRUCTION SET REFERENCE, A-M Table 3-56. Decision Table (Contd.) Y INTERRUPT-FROMVIRTUAL-8086MODE TASK-GATE #GP Y Y Y Y NOTES: − Don't Care. Y Yes, action taken. Blank Action not taken. When the processor is executing in virtual-8086 mode, the IOPL determines the action of the INT n instruction. If the IOPL is less than 3, the processor generates a #GP(selector) exception; if the IOPL is 3, the processor executes a protected mode interrupt to privilege level 0.
INSTRUCTION SET REFERENCE, A-M REAL-ADDRESS-MODE: IF ((vector_number ∗ 4) + 3) is not within IDT limit THEN #GP; FI; IF stack not large enough for a 6-byte return information THEN #SS; FI; Push (EFLAGS[15:0]); IF ← 0; (* Clear interrupt flag *) TF ← 0; (* Clear trap flag *) AC ← 0; (* Clear AC flag *) Push(CS); Push(IP); (* No error codes are pushed *) CS ← IDT(Descriptor (vector_number ∗ 4), selector)); EIP ← IDT(Descriptor (vector_number ∗ 4), offset)); (* 16 bit offset AND 0000FFFFH *) END; PROTECTED-MO
INSTRUCTION SET REFERENCE, A-M ELSE (* Generated by INTO *) THEN #UD; FI; IF gate not present THEN #NP((vector_number ∗ 16) + 2 + EXT); FI; IF ((vector_number * 16)[IST] ≠ 0) NewRSP ← TSS[ISTx]; FI; GOTO TRAP-OR-INTERRUPT-GATE; (* Trap/interrupt gate *) END; TASK-GATE: (* PE = 1, task gate *) Read segment selector in task gate (IDT descriptor); IF local/global bit is set to local or index not within GDT limits THEN #GP(TSS selector); FI; Access TSS descriptor in GDT; IF TSS descriptor specifies that the TS
INSTRUCTION SET REFERENCE, A-M IF VM = 0 THEN GOTO INTER-PRIVILEGE-LEVEL-INTERRUPT; (* PE = 1, interrupt or trap gate, nonconforming code segment, DPL < CPL, VM = 0 *) ELSE (* VM = 1 *) IF code segment DPL ≠ 0 THEN #GP; (new code segment selector); GOTO INTERRUPT-FROM-VIRTUAL-8086-MODE; FI; (* PE = 1, interrupt or trap gate, DPL < CPL, VM = 1 *) FI; ELSE (* PE = 1, interrupt or trap gate, DPL ≥ CPL *) IF VM = 1 THEN #GP(new code segment selector); FI; IF code segment is conforming or code segment DPL = CPL
INSTRUCTION SET REFERENCE, A-M NewESP ← TSS[RSP FOR NEW TARGET DPL]; NewSS ← 0; FI; FI; IF segment selector is NULL THEN #TS(EXT); FI; IF segment selector index is not within its descriptor table limits or segment selector's RPL ≠ DPL of code segment, THEN #TS(SS selector + EXT); FI; IF (IA32_EFER.
INSTRUCTION SET REFERENCE, A-M FI; IF 32-bit gate THEN CS:EIP ← Gate(CS:EIP); (* Segment descriptor information also loaded *) ELSE IF 16-bit gate THEN CS:IP ← Gate(CS:IP); (* Segment descriptor information also loaded *) ELSE (* 64-bit gate *) CS:RIP ← Gate(CS:RIP); (* Segment descriptor information also loaded *) FI; FI; IF 32-bit gate THEN Push(far pointer to old stack); (* Old SS and ESP, 3 words padded to 4 *) Push(EFLAGS); Push(far pointer to return instruction); (* Old CS and EIP, 3 words padded to
INSTRUCTION SET REFERENCE, A-M TF ← 0; VM ← 0; RF ← 0; NT ← 0; END; INTERRUPT-FROM-VIRTUAL-8086-MODE: (* Check segment selector and descriptor for privilege level 0 stack in current TSS *) IF current TSS is 32-bit TSS THEN TSSstackAddress ← (new code segment DPL ∗ 8) + 4; IF (TSSstackAddress + 7) > TSS limit THEN #TS(current TSS selector); FI; NewSS ← TSSstackAddress + 4; NewESP ← stack address; ELSE (* TSS is 16-bit *) TSSstackAddress ← (new code segment DPL ∗ 4) + 2; IF (TSSstackAddress + 4) > TSS limit
INSTRUCTION SET REFERENCE, A-M IF StackAddress is non-canonical THEN #SS(0); FI; FI; IF instruction pointer is not within code segment limits THEN #GP(0); FI; tempEFLAGS ← EFLAGS; VM ← 0; TF ← 0; RF ← 0; NT ← 0; IF service through interrupt gate THEN IF = 0; FI; TempSS ← SS; TempESP ← ESP; SS:ESP ← TSS(SS0:ESP0); (* Change to level 0 stack segment *) (* Following pushes are 16 bits for 16-bit gate and 32 bits for 32-bit gates; Segment selector pushes in 32-bit mode are padded to two words *) Push(GS); Push
INSTRUCTION SET REFERENCE, A-M THEN IF current stack does not have room for 16 bytes (error code pushed) or 12 bytes (no error code pushed) THEN #SS(0); FI; ELSE IF 16-bit gate IF current stack does not have room for 8 bytes (error code pushed) or 6 bytes (no error code pushed) THEN #SS(0); FI; ELSE (* 64-bit gate*) IF StackAddress is non-canonical THEN #SS(0); FI; FI; IF instruction pointer not within code segment limit THEN #GP(0); FI; IF 32-bit gate THEN Push (EFLAGS); Push (far pointer to return instru
INSTRUCTION SET REFERENCE, A-M NT ← 0; VM ← 0; RF ← 0; END; Flags Affected The EFLAGS register is pushed onto the stack. The IF, TF, NT, AC, RF, and VM flags may be cleared, depending on the mode of operation of the processor when the INT instruction is executed (see the “Operation” section). If the interrupt uses a task gate, any flags may be set or cleared, controlled by the EFLAGS image in the new task’s TSS.
INSTRUCTION SET REFERENCE, A-M #TS(selector) If the RPL of the stack segment selector in the TSS is not equal to the DPL of the code segment being accessed by the interrupt or trap gate. If DPL of the stack segment descriptor pointed to by the stack segment selector in the TSS is not equal to the DPL of the code segment descriptor for the interrupt or trap gate. If the stack segment selector in the TSS is NULL. If the stack segment for the TSS is not a writable data segment.
INSTRUCTION SET REFERENCE, A-M If pushing the return address, flags, error code, stack segment pointer, or data segments exceeds the bounds of the stack segment. #NP(selector) If code segment, interrupt-, trap-, or task gate, or TSS is not present. #TS(selector) If the RPL of the stack segment selector in the TSS is not equal to the DPL of the code segment being accessed by the interrupt or trap gate.
INSTRUCTION SET REFERENCE, A-M #SS(0) If a push of the old EFLAGS, CS selector, EIP, or error code is in non-canonical space with no stack switch. #SS(selector) If a push of the old SS selector, ESP, EFLAGS, CS selector, EIP, or error code is in non-canonical space on a stack switch (either CPL change or no-CPL with IST). #NP(selector) If the 64-bit interrupt-gate, 64-bit trap-gate, or code segment is not present.
INSTRUCTION SET REFERENCE, A-M INVD—Invalidate Internal Caches Opcode* 0F 08 Instruction INVD 64-Bit Mode Valid Compat/ Leg Mode Valid Description Flush internal caches; initiate flushing of external caches. NOTES: * See the IA-32 Architecture Compatibility section below. Description Invalidates (flushes) the processor’s internal caches and issues a special-function bus cycle that directs external caches to also flush themselves. Data held in internal caches is not written back to main memory.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If the current privilege level is not 0. Real-Address Mode Exceptions None. Virtual-8086 Mode Exceptions #GP(0) The INVD instruction cannot be executed in virtual-8086 mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol.
INSTRUCTION SET REFERENCE, A-M INVLPG—Invalidate TLB Entry Opcode 0F 01/7 Instruction INVLPG m 64-Bit Mode Valid Compat/ Leg Mode Valid Description Invalidate TLB Entry for page that contains m. NOTES: * See the IA-32 Architecture Compatibility section below. Description Invalidates (flushes) the translation lookaside buffer (TLB) entry specified with the source operand. The source operand is a memory address.
INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #UD Operand is a register. Virtual-8086 Mode Exceptions #GP(0) The INVLPG instruction cannot be executed at the virtual-8086 mode. 64-Bit Mode Exceptions #GP(0) If the current privilege level is not 0. #UD Operand is a register. Vol.
INSTRUCTION SET REFERENCE, A-M IRET/IRETD—Interrupt Return Opcode CF Instruction IRET 64-Bit Mode Valid Compat/ Leg Mode Valid CF IRETD Valid Valid REX.W + CF IRETQ Valid N.E. Description Interrupt return (16-bit operand size). Interrupt return (32-bit operand size). Interrupt return (64-bit operand size).
INSTRUCTION SET REFERENCE, A-M As with a real-address mode interrupt return, the IRET instruction pops the return instruction pointer, return code segment selector, and EFLAGS image from the stack to the EIP, CS, and EFLAGS registers, respectively, and then resumes execution of the interrupted program or procedure. If the return is to another privilege level, the IRET instruction also pops the stack pointer and SS from the stack, before resuming program execution.
INSTRUCTION SET REFERENCE, A-M EFLAGS ← (tempEFLAGS AND 257FD5H) OR (EFLAGS AND 1A0000H); ELSE (* OperandSize = 16 *) IF top 6 bytes of stack are not within stack limits THEN #SS; FI; EIP ← Pop(); (* 16-bit pop; clear upper 16 bits *) CS ← Pop(); (* 16-bit pop *) EFLAGS[15:0] ← Pop(); FI; END; PROTECTED-MODE: IF VM = 1 (* Virtual-8086 mode: PE = 1, VM = 1 *) THEN GOTO RETURN-FROM-VIRTUAL-8086-MODE; (* PE = 1, VM = 1 *) FI; IF NT = 1 THEN GOTO TASK-RETURN; (* PE = 1, VM = 0, NT = 1 *) FI; IF OperandSize = 3
INSTRUCTION SET REFERENCE, A-M IF NT = 1 THEN #GP(0); ELSE IF OperandSize = 32 THEN IF top 12 bytes of stack not within stack limits THEN #SS(0); FI; tempEIP ← Pop(); tempCS ← Pop(); tempEFLAGS ← Pop(); ELSE IF OperandSize = 16 THEN IF top 6 bytes of stack are not within stack limits THEN #SS(0); FI; tempEIP ← Pop(); tempCS ← Pop(); tempEFLAGS ← Pop(); tempEIP ← tempEIP AND FFFFH; tempEFLAGS ← tempEFLAGS AND FFFFH; FI; ELSE (* OperandSize = 64 *) THEN tempRIP ← Pop(); tempCS ← Pop(); tempEFLAGS ← Pop(); te
INSTRUCTION SET REFERENCE, A-M THEN #SS(0); FI; IF instruction pointer not within code segment limits THEN #GP(0); FI; EIP ← Pop(); EIP ← EIP AND 0000FFFFH; CS ← Pop(); (* 16-bit pop *) EFLAGS[15:0] ← Pop(); (* IOPL in EFLAGS not modified by pop *) FI; ELSE #GP(0); (* Trap to virtual-8086 monitor: PE = 1, VM = 1, IOPL < 3 *) FI; END; RETURN-TO-VIRTUAL-8086-MODE: (* Interrupted procedure was in virtual-8086 mode: PE = 1, VM IF top 24 bytes of stack are not within stack segment limits THEN #SS(0); FI; IF i
INSTRUCTION SET REFERENCE, A-M SWITCH-TASKS (without nesting) to TSS specified in link field of current TSS; Mark the task just abandoned as NOT BUSY; IF EIP is not within code segment limit THEN #GP(0); FI; END; PROTECTED-MODE-RETURN: (* PE = 1, VM = 0 in flags image *) IF return code segment selector is NULL THEN GP(0); FI; IF return code segment selector addresses descriptor beyond descriptor table limit THEN GP(selector); FI; Read segment descriptor pointed to by the return code segment selector; IF re
INSTRUCTION SET REFERENCE, A-M IF CPL = 0 THEN EFLAGS(IOPL) ← tempEFLAGS; IF OperandSize = 32 THEN EFLAGS(VM, VIF, VIP) ← tempEFLAGS; FI; IF OperandSize = 64 THEN EFLAGS( VIF, VIP) ← tempEFLAGS; FI; FI; END; RETURN-TO-OUTER-PRIVILEGE-LEVEL: IF OperandSize = 32 THEN IF top 8 bytes on stack are not within limits THEN #SS(0); FI; ELSE (* OperandSize = 16 *) IF top 4 bytes on stack are not within limits THEN #SS(0); FI; FI; Read return segment selector; IF stack segment selector is NULL THEN #GP(0); FI; IF ret
INSTRUCTION SET REFERENCE, A-M THEN EFLAGS(RF, AC, ID) ← tempEFLAGS; FI; IF CPL ≤ IOPL THEN EFLAGS(IF) ← tempEFLAGS; FI; IF CPL = 0 THEN EFLAGS(IOPL) ← tempEFLAGS; IF OperandSize = 32 THEN EFLAGS(VM, VIF, VIP) ← tempEFLAGS; FI; IF OperandSize = 64 THEN EFLAGS( VIF, VIP) ← tempEFLAGS; FI; FI; CPL ← RPL of the return code segment selector; FOR each of segment register (ES, FS, GS, and DS) DO IF segment register points to data or non-conforming code segment and CPL > segment descriptor DPL (* Stored in hidden
INSTRUCTION SET REFERENCE, A-M Flags Affected All the flags and fields in the EFLAGS register are potentially modified, depending on the mode of operation of the processor. If performing a return from a nested task to a previous task, the EFLAGS register will be modified according to the EFLAGS image stored in the previous task’s TSS. Protected Mode Exceptions #GP(0) If the return code or stack segment selector is NULL. If the return instruction pointer is not within the return code segment limit.
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #GP(0) If the return instruction pointer is not within the return code segment limit. IF IOPL not equal to 3. #PF(fault-code) If a page fault occurs. #SS(0) If the top bytes of stack are not within stack limits. #AC(0) If an unaligned memory reference occurs and alignment checking is enabled. Compatibility Mode Exceptions #GP(0) If EFLAGS.NT[bit 14] = 1. Other exceptions same as in Protected Mode.
INSTRUCTION SET REFERENCE, A-M If the stack segment selector RPL is not equal to the RPL of the return code segment selector. #SS(0) If an attempt to pop a value off the stack violates the SS limit. If an attempt to pop a value off the stack causes a non-canonical address to be referenced. #NP(selector) If the return code or stack segment is not present. #PF(fault-code) If a page fault occurs. #AC(0) If an unaligned memory reference occurs when the CPL is 3 and alignment checking is enabled.
INSTRUCTION SET REFERENCE, A-M Jcc—Jump if Condition Is Met Opcode 77 cb 73 cb 72 cb 76 cb Instruction JA rel8 JAE rel8 JB rel8 JBE rel8 64-Bit Mode Valid Valid Valid Valid Compat/ Leg Mode Valid Valid Valid Valid 72 cb E3 cb E3 cb E3 cb 74 cb 7F cb JC rel8 JCXZ rel8 JECXZ rel8 JRCXZ rel8 JE rel8 JG rel8 Valid N.E. Valid Valid Valid Valid Valid Valid Valid N.E.
INSTRUCTION SET REFERENCE, A-M Opcode 7A cb 7B cb 78 cb Instruction JPE rel8 JPO rel8 JS rel8 64-Bit Mode Valid Valid Valid Compat/ Leg Mode Valid Valid Valid 74 cb 0F 87 cw JZ rel8 JA rel16 Valid N.S. Valid Valid 0F 87 cd 0F 83 cw JA rel32 JAE rel16 Valid N.S. Valid Valid 0F 83 cd 0F 82 cw JAE rel32 JB rel16 Valid N.S. Valid Valid 0F 82 cd 0F 86 cw JB rel32 JBE rel16 Valid N.S. Valid Valid 0F 86 cd JBE rel32 Valid Valid 0F 82 cw JC rel16 N.S.
INSTRUCTION SET REFERENCE, A-M Opcode 0F 8E cd Instruction JLE rel32 64-Bit Mode Valid Compat/ Leg Mode Valid 0F 86 cw JNA rel16 N.S. Valid 0F 86 cd 0F 82 cw JNA rel32 JNAE rel16 Valid N.S. Valid Valid 0F 82 cd 0F 83 cw JNAE rel32 JNB rel16 Valid N.S. Valid Valid 0F 83 cd 0F 87 cw JNB rel32 JNBE rel16 Valid N.S. Valid Valid 0F 87 cd JNBE rel32 Valid Valid 0F 83 cw JNC rel16 N.S. Valid 0F 83 cd 0F 85 cw JNC rel32 JNE rel16 Valid N.S.
INSTRUCTION SET REFERENCE, A-M Opcode 0F 81 cw Instruction JNO rel16 64-Bit Mode N.S. Compat/ Leg Mode Valid 0F 81 cd 0F 8B cw JNO rel32 JNP rel16 Valid N.S. Valid Valid 0F 8B cd 0F 89 cw JNP rel32 JNS rel16 Valid N.S. Valid Valid 0F 89 cd 0F 85 cw JNS rel32 JNZ rel16 Valid N.S. Valid Valid 0F 85 cd 0F 80 cw JNZ rel32 JO rel16 Valid N.S. Valid Valid 0F 80 cd 0F 8A cw JO rel32 JP rel16 Valid N.S. Valid Valid 0F 8A cd 0F 8A cw JP rel32 JPE rel16 Valid N.S.
INSTRUCTION SET REFERENCE, A-M The target instruction is specified with a relative offset (a signed offset relative to the current value of the instruction pointer in the EIP register). A relative offset (rel8, rel16, or rel32) is generally specified as a label in assembly code, but at the machine code level, it is encoded as a signed, 8-bit or 32-bit immediate value, which is added to the instruction pointer. Instruction coding is most efficient for offsets of –128 to +127.
INSTRUCTION SET REFERENCE, A-M Operation IF condition THEN tempEIP ← EIP + SignExtend(DEST); IF OperandSize = 16 THEN tempEIP ← tempEIP AND 0000FFFFH; FI; IF tempEIP is not within code segment limit THEN #GP(0); ELSE EIP ← tempEIP FI; FI; Protected Mode Exceptions #GP(0) If the offset being jumped to is beyond the limits of the CS segment. Real-Address Mode Exceptions #GP If the offset being jumped to is beyond the limits of the CS segment or is outside of the effective address space from 0 to FFFFH.
INSTRUCTION SET REFERENCE, A-M JMP—Jump Opcode EB cb Instruction JMP rel8 64-Bit Mode Valid Compat/ Leg Mode Valid E9 cw JMP rel16 N.S. Valid E9 cd JMP rel32 Valid Valid FF /4 JMP r/m16 N.S. Valid FF /4 JMP r/m32 N.S. Valid FF /4 JMP r/m64 Valid N.E. EA cd JMP ptr16:16 JMP ptr16:32 JMP m16:16 JMP m16:32 JMP m16:64 Inv. Valid Inv. Valid Valid Valid Valid Valid Valid N.E. EA cp FF /5 FF /5 REX.
INSTRUCTION SET REFERENCE, A-M • Far jump—A jump to an instruction located in a different segment than the current code segment but at the same privilege level, sometimes referred to as an intersegment jump. • Task switch—A jump to an instruction located in a different task. A task switch can only be executed in protected mode (see Chapter 6, in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A, for information on performing task switches with the JMP instruction).
INSTRUCTION SET REFERENCE, A-M In protected mode, the processor always uses the segment selector part of the far address to access the corresponding descriptor in the GDT or LDT. The descriptor type (code segment, call gate, task gate, or TSS) and access rights determine the type of jump to be performed. If the selected descriptor is for a code segment, a far jump to a code segment at the same privilege level is performed.
INSTRUCTION SET REFERENCE, A-M In 64-Bit Mode — The instruction’s operation size is fixed at 64 bits. If a selector points to a gate, then RIP equals the 64-bit displacement taken from gate; else RIP equals the zero-extended offset from the far pointer referenced in the instruction. See the summary chart at the beginning of this section for encoding data and limits.
INSTRUCTION SET REFERENCE, A-M tempEIP ← DEST(Offset); (* DEST is ptr16:32 or [m16:32] *) IF tempEIP is beyond code segment limit THEN #GP(0); FI; CS ← DEST(segment selector); (* DEST is ptr16:32 or [m16:32] *) IF OperandSize = 32 THEN EIP ← tempEIP; (* DEST is ptr16:32 or [m16:32] *) ELSE (* OperandSize = 16 *) EIP ← tempEIP AND 0000FFFFH; (* Clear upper 16 bits *) FI; FI; IF far jump and (PE = 1 and VM = 0) (* IA-32e mode or protected mode, not virtual-8086 mode *) THEN IF effective address in the CS, DS
INSTRUCTION SET REFERENCE, A-M IF segment not present THEN #NP(segment selector); FI; tempEIP ← DEST(Offset); IF OperandSize = 16 THEN tempEIP ← tempEIP AND 0000FFFFH; FI; IF (IA32_EFER.
INSTRUCTION SET REFERENCE, A-M Read code segment descriptor; IF code-segment segment descriptor does not indicate a code segment or code-segment segment descriptor is conforming and DPL > CPL or code-segment segment descriptor is non-conforming and DPL ≠ CPL THEN #GP(code segment selector); FI; IF IA32_EFER.
INSTRUCTION SET REFERENCE, A-M IF TSS is not present THEN #NP(TSS selector); FI; SWITCH-TASKS to TSS; IF EIP not within code segment limit THEN #GP(0); FI; END; Flags Affected All flags are affected if a task switch occurs; no flags are affected if a task switch does not occur. Protected Mode Exceptions #GP(0) If offset in target operand, call gate, or TSS is beyond the code segment limits. If the segment selector in the destination operand, call gate, task gate, or TSS is NULL.
INSTRUCTION SET REFERENCE, A-M #SS(0) #NP (selector) If a memory operand effective address is outside the SS segment limit. If the code segment being accessed is not present. If call gate, task gate, or TSS not present. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. (Only occurs when fetching target from memory.
INSTRUCTION SET REFERENCE, A-M If the code segment or 64-bit call gate overlaps non-canonical space. If the segment descriptor from a 64-bit call gate is in noncanonical space. If the segment descriptor pointed to by the segment selector in the destination operand is not for a conforming-code segment, nonconforming-code segment, 64-bit call gate. If the segment descriptor pointed to by the segment selector in the destination operand is a code segment, and has both the D-bit and the L-bit set.
INSTRUCTION SET REFERENCE, A-M LAHF—Load Status Flags into AH Register Opcode 9F Instruction LAHF 64-Bit Mode Invalid* Compat/ Leg Mode Valid Description Load: AH ← EFLAGS(SF:ZF:0:AF:0:PF:1:CF). NOTES: * Valid in specific steppings. See Description section. Description Moves the low byte of the EFLAGS register (which includes status flags SF, ZF, AF, PF, and CF) to the AH register. Reserved bits 1, 3, and 5 of the EFLAGS register are set in the AH register as shown in the “Operation” section below.
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions None. 64-Bit Mode Exceptions #UD 3-512 Vol. 2 If CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 0.
INSTRUCTION SET REFERENCE, A-M LAR—Load Access Rights Byte Opcode 0F 02 /r 0F 02 /r REX.W + 0F 02 /r Instruction LAR r16, r16/m16 LAR r32, r32/m161 LAR r64, r32/m161 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Valid N.E. Description r16 ← r16/m16 masked by FF00H. r32 ← r32/m16 masked by 00FxFF00H r64 ← r32/m16 masked by 00FxFF00H and zero extended NOTES: 1. For all loads (regardless of source or destination sizing) only bits 16-0 are used. Other bits are ignored.
INSTRUCTION SET REFERENCE, A-M • If the segment is not a conforming code segment, it checks that the specified segment descriptor is visible at the CPL (that is, if the CPL and the RPL of the segment selector are less than or equal to the DPL of the segment selector). If the segment descriptor cannot be accessed or is an invalid type for the instruction, the ZF flag is cleared and no access rights are loaded in the destination operand.
INSTRUCTION SET REFERENCE, A-M Operation IF Offset(SRC) > descriptor table limit THEN ZF = 0; ELSE IF SegmentDescriptor(Type) ≠ conforming code segment and (CPL > DPL) or (RPL > DPL) or segment type is not valid for instruction THEN ZF ← 0 ELSE TEMP ← Read segment descriptor ; IF OperandSize = 64 THEN DEST ← (ACCESSRIGHTWORD(TEMP) AND 00000000_00FxFF00H); ELSE (* OperandSize = 32*) DEST ← (ACCESSRIGHTWORD(TEMP) AND 00FxFF00H); ELSE (* OperandSize = 16 *) DEST ← (ACCESSRIGHTWORD(TEMP) AND FF00H); FI; FI; FI
INSTRUCTION SET REFERENCE, A-M Real-Address Mode Exceptions #UD The LAR instruction is not recognized in real-address mode. Virtual-8086 Mode Exceptions #UD The LAR instruction cannot be executed in virtual-8086 mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If the memory operand effective address referencing the SS segment is in a non-canonical form. #GP(0) If the memory operand effective address is in a non-canonical form.
INSTRUCTION SET REFERENCE, A-M LDDQU—Load Unaligned Integer 128 Bits Opcode F2 0F F0 /r Instruction LDDQU xmm1, mem 64-Bit Mode Valid Compat/ Leg Mode Valid Description Load unaligned data from mem and return double quadword in xmm1. Description The instruction is functionally similar to MOVDQU xmm, m128 for loading from memory.
INSTRUCTION SET REFERENCE, A-M Intel C/C++ Compiler Intrinsic Equivalent LDDQU __m128i _mm_lddqu_si128(__m128i const *p) Numeric Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR4.OSFXSR[bit 9] = 0. If CR0.EM[bit 2] = 1. If CPUID.01H:ECX.SSE3[bit 0] = 0.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. #PF(fault-code) If a page fault occurs. Vol.
INSTRUCTION SET REFERENCE, A-M LDMXCSR—Load MXCSR Register Opcode 0F,AE,/2 Instruction LDMXCSR m32 64-Bit Mode Valid Compat/ Leg Mode Valid Description Load MXCSR register from m32. Description Loads the source operand into the MXCSR control/status register. The source operand is a 32-bit memory location. See “MXCSR Control and Status Register” in Chapter 10, of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for a description of the MXCSR register and its contents.
INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real Address Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to FFFFH. For an attempt to set reserved bits in MXCSR. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.
INSTRUCTION SET REFERENCE, A-M LDS/LES/LFS/LGS/LSS—Load Far Pointer Opcode C5 /r C5 /r 0F B2 /r 0F B2 /r REX + 0F B2 /r C4 /r C4 /r 0F B4 /r 0F B4 /r REX + 0F B4 /r 0F B5 /r 0F B5 /r REX + 0F B5 /r Instruction LDS r16,m16:16 LDS r32,m16:32 LSS r16,m16:16 LSS r32,m16:32 LSS r64,m16:64 LES r16,m16:16 LES r32,m16:32 LFS r16,m16:16 LFS r32,m16:32 LFS r64,m16:64 LGS r16,m16:16 LGS r32,m16:32 LGS r64,m16:64 64-Bit Mode Invalid Compat/ Leg Mode Valid Invalid Valid Valid Valid Valid Valid Valid N.E.
INSTRUCTION SET REFERENCE, A-M If one of these instructions is executed in protected mode, additional information from the segment descriptor pointed to by the segment selector in the source operand is loaded in the hidden part of the selected segment register. Also in protected mode, a NULL selector (values 0000 through 0003) can be loaded into DS, ES, FS, or GS registers without causing a protection exception.
INSTRUCTION SET REFERENCE, A-M FI; SegmentRegister ← SegmentSelector(SRC) ; SegmentRegister ← SegmentDescriptor([SRC]); FI; ELSE IF FS, or GS is loaded with a NULL selector: THEN SegmentRegister ← NULLSelector; SegmentRegister(DescriptorValidBit) ← 0; FI; (* Hidden flag; not accessible by software *) FI; DEST ← Offset(SRC); PREOTECTED MODE OR COMPATIBILITY MODE; IF SS is loaded THEN IF SegementSelector = NULL THEN #GP(0); ELSE IF Segment selector index is not within descriptor table limits or segment selec
INSTRUCTION SET REFERENCE, A-M FI; DEST ← Offset(SRC); Real-Address or Virtual-8086 Mode SegmentRegister ← SegmentSelector(SRC); FI; DEST ← Offset(SRC); Flags Affected None. Protected Mode Exceptions #UD If source operand is not a memory location. #GP(0) If a NULL selector is loaded into the SS register. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector.
INSTRUCTION SET REFERENCE, A-M #SS If a memory operand effective address is outside the SS segment limit. #UD If source operand is not a memory location. Virtual-8086 Mode Exceptions #UD If source operand is not a memory location. #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
INSTRUCTION SET REFERENCE, A-M #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. #UD If source operand is not a memory location. Vol.
INSTRUCTION SET REFERENCE, A-M LEA—Load Effective Address Opcode 8D /r Instruction LEA r16,m 64-Bit Mode Valid Compat/ Leg Mode Valid 8D /r LEA r32,m Valid Valid REX.W + 8D /r LEA r64,m Valid N.E. Description Store effective address for m in register r16. Store effective address for m in register r32. Store effective address for m in register r64. Description Computes the effective address of the second operand (the source operand) and stores it in the first operand (destination operand).
INSTRUCTION SET REFERENCE, A-M Table 3-59. 64-bit Mode LEA Operation with Address and Operand Size Attributes Operand Size Address Size Action Performed 16 32 32-bit effective address is calculated (using 67H prefix). The lower 16 bits of the address are stored in the requested 16-bit register destination (using 66H prefix). 16 64 64-bit effective address is calculated (default address size).
INSTRUCTION SET REFERENCE, A-M THEN temp ← EffectiveAddress(SRC); (* 64-bit address *) DEST ← temp[0:15]; (* 16-bit address *) FI; ELSE IF OperandSize = 32 and AddressSize = 64 THEN temp ← EffectiveAddress(SRC); (* 64-bit address *) DEST ← temp[0:31]; (* 16-bit address *) FI; ELSE IF OperandSize = 64 and AddressSize = 64 THEN DEST ← EffectiveAddress(SRC); (* 64-bit address *) FI; FI; Flags Affected None. Protected Mode Exceptions #UD If source operand is not a memory location.
INSTRUCTION SET REFERENCE, A-M LEAVE—High Level Procedure Exit Opcode C9 C9 C9 Instruction LEAVE LEAVE LEAVE 64-Bit Mode Valid N.E. Valid Compat/ Leg Mode Valid Valid N.E. Description Set SP to BP, then pop BP. Set ESP to EBP, then pop EBP. Set RSP to RBP, then pop RBP. Description Releases the stack frame set up by an earlier ENTER instruction.
INSTRUCTION SET REFERENCE, A-M Flags Affected None. Protected Mode Exceptions #SS(0) If the EBP register points to a location that is not within the limits of the current stack segment. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP If the EBP register points to a location outside of the effective address space from 0 to FFFFH.
INSTRUCTION SET REFERENCE, A-M LFENCE—Load Fence Opcode 0F AE /5 Instruction LFENCE 64-Bit Mode Valid Compat/ Leg Mode Valid Description Serializes load operations. Description Performs a serializing operation on all load-from-memory instructions that were issued prior the LFENCE instruction.
INSTRUCTION SET REFERENCE, A-M LGDT/LIDT—Load Global/Interrupt Descriptor Table Register Opcode 0F 01 /2 0F 01 /3 0F 01 /2 0F 01 /3 Instruction LGDT m16&32 LIDT m16&32 LGDT m16&64 LIDT m16&64 64-Bit Mode N.E. N.E. Valid Valid Compat/ Leg Mode Valid Valid N.E. N.E. Description Load m into GDTR. Load m into IDTR. Load m into GDTR. Load m into IDTR. Description Loads the values in the source operand into the global descriptor table register (GDTR) or the interrupt descriptor table register (IDTR).
INSTRUCTION SET REFERENCE, A-M Operation IF Instruction is LIDT THEN IF OperandSize = 16 THEN IDTR(Limit) ← SRC[0:15]; IDTR(Base) ← SRC[16:47] AND 00FFFFFFH; ELSE IF 32-bit Operand Size THEN IDTR(Limit) ← SRC[0:15]; IDTR(Base) ← SRC[16:47]; FI; ELSE IF 64-bit Operand Size (* In 64-Bit Mode *) THEN IDTR(Limit) ← SRC[0:15]; IDTR(Base) ← SRC[16:79]; FI; FI; ELSE (* Instruction is LGDT *) IF OperandSize = 16 THEN GDTR(Limit) ← SRC[0:15]; GDTR(Base) ← SRC[16:47] AND 00FFFFFFH; ELSE IF 32-bit Operand Size THEN G
INSTRUCTION SET REFERENCE, A-M If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. Real-Address Mode Exceptions #UD If source operand is not a memory location.
INSTRUCTION SET REFERENCE, A-M LLDT—Load Local Descriptor Table Register Opcode 0F 00 /2 Instruction LLDT r/m16 64-Bit Mode Valid Compat/ Leg Mode Valid Description Load segment selector r/m16 into LDTR. Description Loads the source operand into the segment selector field of the local descriptor table register (LDTR). The source operand (a general-purpose register or a memory location) contains a segment selector that points to a local descriptor table (LDT).
INSTRUCTION SET REFERENCE, A-M ELSE LDTR ← INVALID FI; Flags Affected None. Protected Mode Exceptions #GP(0) If the current privilege level is not 0. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #GP(selector) If the selector operand does not point into the Global Descriptor Table or if the entry in the GDT is not a Local Descriptor Table. Segment selector is beyond GDT limit.
INSTRUCTION SET REFERENCE, A-M LMSW—Load Machine Status Word Opcode 0F 01 /6 Instruction LMSW r/m16 64-Bit Mode Valid Compat/ Leg Mode Valid Description Loads r/m16 in machine status word of CR0. Description Loads the source operand into the machine status word, bits 0 through 15 of register CR0. The source operand can be a 16-bit general-purpose register or a memory location. Only the low-order 4 bits of the source operand (which contains the PE, MP, EM, and TS flags) are loaded into CR0.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If the current privilege level is not 0. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
INSTRUCTION SET REFERENCE, A-M LOCK—Assert LOCK# Signal Prefix Opcode* F0 Instruction LOCK 64-Bit Mode Valid Compat/ Leg Mode Valid Description Asserts LOCK# signal for duration of the accompanying instruction. NOTES: * See IA-32 Architecture Compatibility section below. Description Causes the processor’s LOCK# signal to be asserted during execution of the accompanying instruction (turns the instruction into an atomic instruction).
INSTRUCTION SET REFERENCE, A-M Operation AssertLOCK#(DurationOfAccompaningInstruction); Flags Affected None. Protected Mode Exceptions #UD If the LOCK prefix is used with an instruction not listed in the “Description” section above. Other exceptions can be generated by the instruction that the LOCK prefix is being applied to. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode.
INSTRUCTION SET REFERENCE, A-M LODS/LODSB/LODSW/LODSD/LODSQ—Load String Opcode AC Instruction LODS m8 64-Bit Mode Valid Compat/ Leg Mode Valid AD LODS m16 Valid Valid AD LODS m32 Valid Valid REX.W + AD AC LODS m64 LODSB Valid Valid N.E. Valid AD LODSW Valid Valid AD LODSD Valid Valid REX.W + AD LODSQ Valid N.E. Description For legacy mode, Load byte at address DS:(E)SI into AL. For 64-bit mode load byte at address (R)SI into AL.
INSTRUCTION SET REFERENCE, A-M The no-operands form provides “short forms” of the byte, word, and doubleword versions of the LODS instructions. Here also DS:(E)SI is assumed to be the source operand and the AL, AX, or EAX register is assumed to be the destination operand. The size of the source and destination operands is selected with the mnemonic: LODSB (byte loaded into register AL), LODSW (word loaded into AX), or LODSD (doubleword loaded into EAX).
INSTRUCTION SET REFERENCE, A-M ELSE IF RAX ← SRC; (* Quadword load *) THEN IF DF = 0 THEN (R)SI ← (R)SI + 8; ELSE (R)SI ← (R)SI – 8; FI; FI; FI; Flags Affected None. Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. 3-546 Vol.
INSTRUCTION SET REFERENCE, A-M LOOP/LOOPcc—Loop According to ECX Counter Opcode E2 cb Instructio n LOOP rel8 64-Bit Mode Valid Compat/ Leg Mode Valid REX.W + E2 cb LOOP rel8 Valid N.E. E1 cb LOOPE rel8 Valid Valid REX.W + E1 cb LOOPE rel8 Valid N.E. E0 cb LOOPNE rel8 LOOPNZ rel8 Valid Valid Valid N.E. REX.W + E0 cb Description Decrement count; jump short if count ≠ 0. Decrement 64-bit count in RCX; jump short if count ≠ 0. Decrement count; jump short if count ≠ 0 and ZF = 1.
INSTRUCTION SET REFERENCE, A-M Operation IF AddressSize = 32 THEN Count is ECX; ELSE IF AddressSize = 64 and REX.
INSTRUCTION SET REFERENCE, A-M FI; FI; ELSE Terminate loop and continue program execution at (R/E)IP; FI; Flags Affected None. Protected Mode Exceptions #GP(0) If the offset being jumped to is beyond the limits of the CS segment. Real-Address Mode Exceptions #GP If the offset being jumped to is beyond the limits of the CS segment or is outside of the effective address space from 0 to FFFFH. This condition can occur if a 32-bit address size override prefix is used.
INSTRUCTION SET REFERENCE, A-M LSL—Load Segment Limit Opcode 0F 03 /r 0F 03 /r REX.W + 0F 03 /r Instruction LSL r16, r16/m16 LSL r32, r32/m161 LSL r64, r32/m161 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Valid Valid Description Load: r16 ← segment limit, selector r16/m16. Load: r32 ← segment limit, selector r32/m16. Load: r64 ← segment limit, selector r32/m16 NOTES: 1 For all loads (regardless of destination sizing), only bits 16-0 are used. Other bits are ignored.
INSTRUCTION SET REFERENCE, A-M • If the segment is not a conforming code segment, the instruction checks that the specified segment descriptor is visible at the CPL (that is, if the CPL and the RPL of the segment selector are less than or equal to the DPL of the segment selector). If the segment descriptor cannot be accessed or is an invalid type for the instruction, the ZF flag is cleared and no value is loaded in the destination operand. Table 3-60.
INSTRUCTION SET REFERENCE, A-M Operation IF SRC(Offset) > descriptor table limit THEN ZF ← 0; FI; Read segment descriptor; IF SegmentDescriptor(Type) ≠ conforming code segment and (CPL > DPL) OR (RPL > DPL) or Segment type is not valid for instruction THEN ZF ← 0; ELSE temp ← SegmentLimit([SRC]); IF (G ← 1) THEN temp ← ShiftLeft(12, temp) OR 00000FFFH; ELSE IF OperandSize = 32 THEN DEST ← temp; FI; ELSE IF OperandSize = 64 (* REX.
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions #UD The LAR instruction cannot be executed in virtual-8086 mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If the memory operand effective address referencing the SS segment is in a non-canonical form. #GP(0) If the memory operand effective address is in a non-canonical form. #PF(fault-code) If a page fault occurs.
INSTRUCTION SET REFERENCE, A-M LTR—Load Task Register Opcode 0F 00 /3 Instruction LTR r/m16 64-Bit Mode Valid Compat/ Leg Mode Valid Description Load r/m16 into task register. Description Loads the source operand into the segment selector field of the task register. The source operand (a general-purpose register or a memory location) contains a segment selector that points to a task state segment (TSS).
INSTRUCTION SET REFERENCE, A-M Flags Affected None. Protected Mode Exceptions #GP(0) If the current privilege level is not 0. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the source operand contains a NULL segment selector. If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment selector. #GP(selector) If the source selector points to a segment that is not a TSS or to one for a task that is already busy.
INSTRUCTION SET REFERENCE, A-M #NP(selector) If the TSS is marked not present. #PF(fault-code) If a page fault occurs. 3-556 Vol.
INSTRUCTION SET REFERENCE, A-M MASKMOVDQU—Store Selected Bytes of Double Quadword Opcode 66 0F F7 /r Instruction MASKMOVDQU xmm1, xmm2 64-Bit Mode Valid Compat/ Leg Mode Valid Description Selectively write bytes from xmm1 to memory location using the byte mask in xmm2. The default memory location is specified by DS:EDI. Description Stores selected bytes from the source operand (first operand) into an 128-bit memory location.
INSTRUCTION SET REFERENCE, A-M In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #GP(0) If the memory address is in a non-canonical form. #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #PF(fault-code) For a page fault (implementation specific). #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Vol.
INSTRUCTION SET REFERENCE, A-M MASKMOVQ—Store Selected Bytes of Quadword Opcode 0F F7 /r Instruction MASKMOVQ mm1, mm2 64-Bit Mode Valid Compat/ Leg Mode Valid Description Selectively write bytes from mm1 to memory location using the byte mask in mm2. The default memory location is specified by DS:EDI. Description Stores selected bytes from the source operand (first operand) into a 64-bit memory location.
INSTRUCTION SET REFERENCE, A-M The MASKMOVQ instruction can be used to improve performance for algorithms that need to merge data on a byte-by-byte basis. It should not cause a read for ownership; doing so generates unnecessary bandwidth since data is to be written directly using the byte-mask without allocating old data prior to the store. In 64-bit mode, the memory address is specified by DS:RDI.
INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault (implementation specific). #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #GP(0) If the memory address is in a non-canonical form.
INSTRUCTION SET REFERENCE, A-M MAXPD—Return Maximum Packed Double-Precision Floating-Point Values Opcode 66 0F 5F /r Instruction MAXPD xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Return the maximum doubleprecision floating-point values between xmm2/m128 and xmm1.
INSTRUCTION SET REFERENCE, A-M THEN DEST[127:64]; ELSE SRC[127:64]; FI; FI; Intel C/C++ Compiler Intrinsic Equivalent MAXPD __m128d _mm_max_pd(__m128d a, __m128d b) SIMD Floating-Point Exceptions Invalid (including QNaN source operand), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M MAXPS—Return Maximum Packed Single-Precision Floating-Point Values Opcode 0F 5F /r Instruction MAXPS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Return the maximum single-precision floating-point values between xmm2/m128 and xmm1.
INSTRUCTION SET REFERENCE, A-M THEN DEST[127:96]; ELSE SRC[127:96]; FI; FI; Intel C/C++ Compiler Intrinsic Equivalent MAXPS __m128d _mm_max_ps(__m128d a, __m128d b) SIMD Floating-Point Exceptions Invalid (including QNaN source operand), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M MAXSD—Return Maximum Scalar Double-Precision Floating-Point Value Opcode F2 0F 5F /r Instruction MAXSD xmm1, xmm2/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Description Return the maximum scalar double-precision floating-point value between xmm2/mem64 and xmm1.
INSTRUCTION SET REFERENCE, A-M Intel C/C++ Compiler Intrinsic Equivalent MAXSD __m128d _mm_max_sd(__m128d a, __m128d b) SIMD Floating-Point Exceptions Invalid (including QNaN source operand), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
INSTRUCTION SET REFERENCE, A-M MAXSS—Return Maximum Scalar Single-Precision Floating-Point Value Opcode F3 0F 5F /r Instruction MAXSS xmm1, xmm2/m32 64-Bit Mode Valid Compat/ Leg Mode Valid Description Return the maximum scalar single-precision floating-point value between xmm2/mem32 and xmm1.
INSTRUCTION SET REFERENCE, A-M SIMD Floating-Point Exceptions Invalid (including QNaN source operand), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.
INSTRUCTION SET REFERENCE, A-M MFENCE—Memory Fence Opcode 0F AE /6 Instructio n MFENCE 64-Bit Mode Valid Compat/ Leg Mode Valid Description Serializes load and store operations. Description Performs a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior the MFENCE instruction.
INSTRUCTION SET REFERENCE, A-M MINPD—Return Minimum Packed Double-Precision Floating-Point Values Opcode 66 0F 5D /r Instruction MINPD xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Return the minimum doubleprecision floating-point values between xmm2/m128 and xmm1.
INSTRUCTION SET REFERENCE, A-M THEN DEST[127:64] ELSE SRC[127:64]; FI; FI; Intel C/C++ Compiler Intrinsic Equivalent MINPD __m128d _mm_min_pd(__m128d a, __m128d b) SIMD Floating-Point Exceptions Invalid (including QNaN source operand), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) #GP(0) If a memory address referencing the SS segment is in a noncanonical form. If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M MINPS—Return Minimum Packed Single-Precision Floating-Point Values Opcode 0F 5D /r Instruction MINPS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Return the minimum singleprecision floating-point values between xmm2/m128 and xmm1.
INSTRUCTION SET REFERENCE, A-M THEN DEST[127:96] ELSE SRC[127:96]; FI; FI; Intel C/C++ Compiler Intrinsic Equivalent MINPS __m128d _mm_min_ps(__m128d a, __m128d b) SIMD Floating-Point Exceptions Invalid (including QNaN source operand), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M MINSD—Return Minimum Scalar Double-Precision Floating-Point Value Opcode F2 0F 5D /r Instruction MINSD xmm1, xmm2/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Description Return the minimum scalar doubleprecision floating-point value between xmm2/mem64 and xmm1.
INSTRUCTION SET REFERENCE, A-M SIMD Floating-Point Exceptions Invalid (including QNaN source operand), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.
INSTRUCTION SET REFERENCE, A-M MINSS—Return Minimum Scalar Single-Precision Floating-Point Value Opcode F3 0F 5D /r Instruction MINSS xmm1, xmm2/m32 64-Bit Mode Valid Compat/ Leg Mode Valid Description Return the minimum scalar singleprecision floating-point value between xmm2/mem32 and xmm1.
INSTRUCTION SET REFERENCE, A-M SIMD Floating-Point Exceptions Invalid (including QNaN source operand), Denormal. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.
INSTRUCTION SET REFERENCE, A-M MONITOR—Set Up Monitor Address Opcode OF 01 C8 Instruction MONITOR 64-Bit Mode Valid Compat/ Leg Mode Valid Description Sets up a linear address range to be monitored by hardware and activates the monitor. The address range should be a write-back memory caching type. The default address is DS:EAX.
INSTRUCTION SET REFERENCE, A-M Operation MONITOR sets up an address range for the monitor hardware using the content of EAX as an effective address and puts the monitor hardware in armed state. Always use memory of the write-back caching type. A store to the specified address range will trigger the monitor hardware. The content of ECX and EDX are used to communicate other information to the monitor hardware.
INSTRUCTION SET REFERENCE, A-M #UD If CPUID.01H:ECX.MONITOR[bit 3] = 0. If executed at privilege level 1 through 3 when the instruction is not available. If LOCK, REP, REPNE/NZ and Operand Size override prefixes are used. #PF(fault-code) For a page fault. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #GP(0) If the current privilege level is not 0. If the memory address is in a non-canonical form. If ECX ≠ 0. #PF(fault-code) For a page fault.
INSTRUCTION SET REFERENCE, A-M MOV—Move Opcode 88 /r REX + 88 /r 89 /r 89 /r REX.W + 89 /r 8A /r REX + 8A /r 8B /r 8B /r REX.W + 8B /r 8C /r Instruction MOV r/m8,r8 MOV r/m8***,r8*** MOV r/m16,r16 MOV r/m32,r32 MOV r/m64,r64 MOV r8,r/m8 MOV r8***,r/m8*** MOV r16,r/m16 MOV r32,r/m32 MOV r64,r/m64 MOV r/m16,Sreg** 64-Bit Mode Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Compat/ Leg Mode Valid N.E. Valid Valid N.E. Valid N.E. Valid Valid N.E. Valid REX.
INSTRUCTION SET REFERENCE, A-M Opcode REX + B0+ rb B8+ rw B8+ rd REX.W + B8+ rd C6 /0 REX + C6 /0 C7 /0 C7 /0 REX.W + C7 /0 Instruction MOV r8***, imm8 MOV r16, imm16 MOV r32, imm32 MOV r64, imm64 MOV r/m8, imm8 MOV r/m8***, imm8 MOV r/m16, imm16 MOV r/m32, imm32 MOV r/m64, imm32 64-Bit Mode Valid Valid Valid Valid Valid Valid Compat/ Leg Mode N.E. Valid Valid N.E. Valid N.E. Description Move imm8 to r8. Move imm16 to r16. Move imm32 to r32. Move imm64 to r64. Move imm8 to r/m8. Move imm8 to r/m8.
INSTRUCTION SET REFERENCE, A-M below). The segment descriptor data is obtained from the GDT or LDT entry for the specified segment selector. A NULL segment selector (values 0000-0003) can be loaded into the DS, ES, FS, and GS registers without causing a protection exception. However, any subsequent attempt to reference a segment whose corresponding segment register is loaded with a NULL value causes a general protection exception (#GP) and no memory reference occurs.
INSTRUCTION SET REFERENCE, A-M Loading a segment register while in protected mode results in special checks and actions, as described in the following listing. These checks are performed on the segment selector and the segment descriptor to which it points.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If attempt is made to load SS register with NULL segment selector. If the destination operand is in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #GP(selector) If segment selector index is outside descriptor table limits.
INSTRUCTION SET REFERENCE, A-M #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #UD If attempt is made to load the CS register. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #GP(0) If the memory address is in a non-canonical form. If an attempt is made to load SS register with NULL segment selector when CPL = 3.
INSTRUCTION SET REFERENCE, A-M MOV—Move to/from Control Registers Opcode 0F 22 /r 0F 22 /r 0F 22 /r 0F 22 /r 0F 22 /r 0F 22 /r 0F 22 /r 0F 22 /r 0F 20 /r 0F 20 /r 0F 20 /r 0F 20 /r 0F 20 /r 0F 20 /r 0F 20 /r 0F 20 /r 0F 20 /r REX + 0F 20 /r Instruction MOV CR0,r32 MOV CR0,r64 MOV CR2,r32 MOV CR2,r64 MOV CR3,r32 MOV CR3,r64 MOV CR4,r32 MOV CR4,r64 MOV r32,CR0 MOV r64,CR0 MOV r32,CR2 MOV r64,CR2 MOV r32,CR3 MOV r64,CR3 MOV r32,CR4 MOV r64,CR4 MOV r32,CR8 MOV r64,CR8 64-Bit Mode N.E. Valid N.E. Valid N.E.
INSTRUCTION SET REFERENCE, A-M At the opcode level, the reg field within the ModR/M byte specifies which of the control registers is loaded or read. The 2 bits in the mod field are always 11B. The r/m field specifies the general-purpose register loaded or read.
INSTRUCTION SET REFERENCE, A-M If an attempt is made to write a 1 to any reserved bit in CR4. If any of the reserved bits are set in the page-directory pointers table (PDPT) and the loading of a control register causes the PDPT to be loaded into the processor. Real-Address Mode Exceptions #GP If an attempt is made to write a 1 to any reserved bit in CR4. If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1 when the PE flag is set to 0).
INSTRUCTION SET REFERENCE, A-M MOV—Move to/from Debug Registers Opcode 0F 21/r REX.W + 0F 21/r Instruction MOV r32, DR0-DR7 MOV r64, DR0-DR7 64-Bit Mode Valid Valid Compat/ Leg Mode Valid N.E. 0F 23 /r REX.W + 0F 23 /r MOV DR0-DR7,r32 MOV DR0-DR7,r64 Valid Valid Valid N.E. Description Move debug register to r32 Move extended debug register to r64. Move r32 to debug register Move r64 to extended debug register.
INSTRUCTION SET REFERENCE, A-M Flags Affected The OF, SF, ZF, AF, PF, and CF flags are undefined. Protected Mode Exceptions #GP(0) If the current privilege level is not 0. #UD If CR4.DE[bit 3] = 1 (debug extensions) and a MOV instruction is executed involving DR4 or DR5. #DB If any debug register is accessed while the DR7.GD[bit 13] = 1. Real-Address Mode Exceptions #UD If CR4.DE[bit 3] = 1 (debug extensions) and a MOV instruction is executed involving DR4 or DR5.
INSTRUCTION SET REFERENCE, A-M MOVAPD—Move Aligned Packed Double-Precision Floating-Point Values Opcode 66 0F 28 /r Instruction MOVAPD xmm1, xmm2/m128 66 0F 29 /r MOVAPD xmm2/m128, xmm1 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Move packed double-precision floating-point values from xmm2/m128 to xmm1. Move packed double-precision floating-point values from xmm1 to xmm2/m128.
INSTRUCTION SET REFERENCE, A-M If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
INSTRUCTION SET REFERENCE, A-M MOVAPS—Move Aligned Packed Single-Precision Floating-Point Values Opcode 0F 28 /r Instruction MOVAPS xmm1, xmm2/m128 0F 29 /r MOVAPS xmm2/m128, xmm1 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Move packed single-precision floating-point values from xmm2/m128 to xmm1. Move packed single-precision floating-point values from xmm1 to xmm2/m128.
INSTRUCTION SET REFERENCE, A-M #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.
INSTRUCTION SET REFERENCE, A-M MOVD/MOVQ—Move Doubleword/Move Quadword Opcode 0F 6E /r REX.W + 0F 6E /r 0F 7E /r REX.W + 0F 7E /r 66 0F 6E /r REX.W + 66 0F 6E /r 66 0F 7E /r REX.W + 66 0F 7E /r Instruction MOVD mm, r/m32 MOVQ mm, r/m64 MOVD r/m32, mm MOVQ r/m64, mm MOVD xmm, r/m32 MOVQ xmm, r/m64 MOVD r/m32, xmm MOVQ r/m64, xmm 64-Bit Mode Valid Compat/ Leg Mode Valid Valid N.E. Valid Valid Valid N.E. Valid Valid Valid N.E. Valid Valid Valid N.E.
INSTRUCTION SET REFERENCE, A-M Operation MOVD instruction when destination operand is MMX technology register: DEST[31:0] ← SRC; DEST[63:32] ← 00000000H; MOVD instruction when destination operand is XMM register: DEST[31:0] ← SRC; DEST[127:32] ← 000000000000000000000000H; MOVD instruction when source operand is MMX technology or XMM register: DEST ← SRC[31:0]; MOVQ instruction when destination operand is XMM register: DEST[63:0] ← SRC[63:0]; DEST[127:64] ← 0000000000000000H; MOVQ instruction when destinati
INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0. Execution of 128-bit instructions on a non-SSE2 capable processor (one that is MMX technology capable) will result in the instruction operating on the mm registers, not #UD. #NM If CR0.TS[bit 3] = 1. #MF (MMX register operations only) If there is a pending FPU exception. #PF(fault-code) If a page fault occurs.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #UD If CR0.EM[bit 2] = 1. (XMM register operations only) if CR4.OSFXSR[bit 9] = 0. (XMM register operations only) if CPUID.01H:EDX.SSE2[bit 26] = 0. #NM If CR0.TS[bit 3] = 1. #MF (MMX register operations only) If there is a pending FPU exception. #PF(fault-code) If a page fault occurs.
INSTRUCTION SET REFERENCE, A-M MOVDDUP—Move One Double-FP and Duplicate Opcode F2 0F 12 /r Instruction MOVDDUP xmm1, xmm2/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Description Move one double-precision floatingpoint value from the lower 64-bit operand in xmm2/m64 to xmm1 and duplicate. Description The linear address corresponds to the address of the least-significant byte of the referenced memory data. When a memory address is indicated, the 8 bytes of data at memory location m64 are loaded.
INSTRUCTION SET REFERENCE, A-M Operation IF (Source == m64) THEN (* Load instruction *) xmm1[63:0] = m64; xmm1[127:64] = m64; ELSE (* Move instruction *) xmm1[63:0] = xmm2[63:0]; xmm1[127:64] = xmm2[63:0]; FI; Intel C/C++ Compiler Intrinsic Equivalent MOVDDUP __m128d _mm_movedup_pd(__m128d a) __m128d _mm_loaddup_pd(double const * dp) Exceptions None Numeric Exceptions None Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
INSTRUCTION SET REFERENCE, A-M Real Address Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. Virtual 8086 Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.
INSTRUCTION SET REFERENCE, A-M MOVDQA—Move Aligned Double Quadword Opcode 66 0F 6F /r 66 0F 7F /r Instruction MOVDQA xmm1, xmm2/m128 MOVDQA xmm2/m128, xmm1 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Move aligned double quadword from xmm2/m128 to xmm1. Move aligned double quadword from xmm1 to xmm2/m128. Description Moves a double quadword from the source operand (second operand) to the destination operand (first operand).
INSTRUCTION SET REFERENCE, A-M #SS(0) If a memory operand effective address is outside the SS segment limit. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0 Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside of the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.
INSTRUCTION SET REFERENCE, A-M MOVDQU—Move Unaligned Double Quadword Opcode F3 0F 6F /r Instruction MOVDQU xmm1, xmm2/m128 F3 0F 7F /r MOVDQU xmm2/m128, xmm1 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Move unaligned double quadword from xmm2/m128 to xmm1. Move unaligned double quadword from xmm1 to xmm2/m128. Description Moves a double quadword from the source operand (second operand) to the destination operand (first operand).
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #PF(fault-code) If a page fault occurs.
INSTRUCTION SET REFERENCE, A-M MOVDQ2Q—Move Quadword from XMM to MMX Technology Register Opcode F2 0F D6 Instruction MOVDQ2Q mm, xmm 64-Bit Mode Valid Compat/ Leg Mode Valid Description Move low quadword from xmm to mmx register. Description Moves the low quadword from the source operand (second operand) to the destination operand (first operand). The source operand is an XMM register and the destination operand is an MMX technology register.
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. 3-618 Vol.
INSTRUCTION SET REFERENCE, A-M MOVHLPS— Move Packed Single-Precision Floating-Point Values High to Low Opcode OF 12 /r Instruction MOVHLPS xmm1, xmm2 64-Bit Mode Valid Compat/ Leg Mode Valid Description Move two packed singleprecision floating-point values from high quadword of xmm2 to low quadword of xmm1. Description Moves two packed single-precision floating-point values from the high quadword of the source operand (second operand) to the low quadword of the destination operand (first operand).
INSTRUCTION SET REFERENCE, A-M Virtual 8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. 3-620 Vol.
INSTRUCTION SET REFERENCE, A-M MOVHPD—Move High Packed Double-Precision Floating-Point Value Opcode 66 0F 16 /r Instruction MOVHPD xmm, m64 66 0F 17 /r MOVHPD m64, xmm 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Move double-precision floating-point value from m64 to high quadword of xmm. Move double-precision floating-point value from high quadword of xmm to m64.
INSTRUCTION SET REFERENCE, A-M #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M MOVHPS—Move High Packed Single-Precision Floating-Point Values Opcode 0F 16 /r Instruction MOVHPS xmm, m64 0F 17 /r MOVHPS m64, xmm 64Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Move two packed single-precision floating-point values from m64 to high quadword of xmm. Move two packed single-precision floating-point values from high quadword of xmm to m64.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
INSTRUCTION SET REFERENCE, A-M MOVLHPS—Move Packed Single-Precision Floating-Point Values Low to High Opcode OF 16 /r Instruction MOVLHPS xmm1, xmm2 64Bit Mode Valid Compat/ Leg Mode Valid Description Move two packed single-precision floating-point values from low quadword of xmm2 to high quadword of xmm1. Description Moves two packed single-precision floating-point values from the low quadword of the source operand (second operand) to the high quadword of the destination operand (first operand).
INSTRUCTION SET REFERENCE, A-M Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol.
INSTRUCTION SET REFERENCE, A-M MOVLPD—Move Low Packed Double-Precision Floating-Point Value Opcode 66 0F 12 /r Instruction MOVLPD xmm, m64 66 0F 13 /r MOVLPD m64, xmm 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Move double-precision floating-point value from m64 to low quadword of xmm register. Move double-precision floating-point nvalue from low quadword of xmm register to m64.
INSTRUCTION SET REFERENCE, A-M #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M MOVLPS—Move Low Packed Single-Precision Floating-Point Values Opcode 0F 12 /r Instruction MOVLPS xmm, m64 0F 13 /r MOVLPS m64, xmm 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Move two packed single-precision floating-point values from m64 to low quadword of xmm. Move two packed single-precision floating-point values from low quadword of xmm to m64.
INSTRUCTION SET REFERENCE, A-M #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M MOVMSKPD—Extract Packed Double-Precision Floating-Point Sign Mask Opcode 66 0F 50 /r Instruction MOVMSKPD r32, xmm 66 + REX.W 0F 50 /r MOVMSKPD r64, xmm 64-Bit Mode Valid Compat/ Leg Mode Valid Valid N.E. Description Extract 2-bit sign mask from xmm and store in r32. Extract 2-bit sign mask from xmm and store in r64. Zero extend 32-bit results to 64-bits.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #NM #UD If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol.
INSTRUCTION SET REFERENCE, A-M MOVMSKPS—Extract Packed Single-Precision Floating-Point Sign Mask Opcode 0F 50 /r REX.W + 0F 50 /r Instruction MOVMSKPS r32, xmm MOVMSKPS r64, xmm 64-Bit Mode Valid Compat/ Leg Mode Valid Valid N.E. Description Extract 4-bit sign mask from xmm and store in r32. Extract 4-bit sign mask from xmm and store in r64. Zero extend 32-bit results to 64-bits.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #NM #UD If CR0.TS[bit 3] = 1. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Real-Address Mode Exceptions Same exceptions as in Protected Mode. Virtual 8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol.
INSTRUCTION SET REFERENCE, A-M MOVNTDQ—Store Double Quadword Using Non-Temporal Hint Opcode 66 0F E7 /r Instruction MOVNTDQ m128, xmm 64-Bit Mode Valid Compat/ Leg Mode Valid Description Move double quadword from xmm to m128 using nontemporal hint. Description Moves the double quadword in the source operand (second operand) to the destination operand (first operand) using a non-temporal hint to prevent caching of the data during the write to memory.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0.
INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. 3-638 Vol.
INSTRUCTION SET REFERENCE, A-M MOVNTI—Store Doubleword Using Non-Temporal Hint Opcode 0F C3 /r Instruction MOVNTI m32, r32 REX.W + 0F C3 /r MOVNTI m64, r64 64-Bit Mode Valid Compat/ Leg Mode Valid Valid N.E. Description Move doubleword from r32 to m32 using non-temporal hint. Move quadword from r64 to m64 using non-temporal hint.
INSTRUCTION SET REFERENCE, A-M SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #UD If CPUID.01H:EDX.SSE2[bit 26] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
INSTRUCTION SET REFERENCE, A-M MOVNTPD—Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint Opcode 66 0F 2B /r Instruction MOVNTPD m128, xmm 64-Bit Mode Valid Compat/ Leg Mode Valid Description Move packed double-precision floating-point values from xmm to m128 using non-temporal hint.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Vol.
INSTRUCTION SET REFERENCE, A-M MOVNTPS—Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint Opcode 0F 2B /r Instruction MOVNTPS m128, xmm 64-Bit Mode Valid Compat/ Leg Mode Valid Description Move packed single-precision floatingpoint values from xmm to m128 using non-temporal hint.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0.
INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. 3-646 Vol.
INSTRUCTION SET REFERENCE, A-M MOVNTQ—Store of Quadword Using Non-Temporal Hint Opcode 0F E7 /r Instruction MOVNTQ m64, mm 64-Bit Mode Valid Compat/ Leg Mode Valid Description Move quadword from mm to m64 using non-temporal hint. Description Moves the quadword in the source operand (second operand) to the destination operand (first operand) using a non-temporal hint to minimize cache pollution during the write to memory.
INSTRUCTION SET REFERENCE, A-M #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #MF If there is a pending x87 FPU exception. #UD If CR0.EM[bit 2] = 1. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment.
INSTRUCTION SET REFERENCE, A-M MOVQ—Move Quadword Opcode 0F 6F /r Instruction MOVQ mm, mm/m64 64-Bit Mode Valid Compat/ Leg Mode Valid 0F 7F /r MOVQ mm/m64, mm Valid Valid F3 0F 7E 66 0F D6 MOVQ xmm1, xmm2/m64 MOVQ xmm2/m64, xmm1 Valid Valid Valid Valid Description Move quadword from mm/m64 to mm. Move quadword from mm to mm/m64. Move quadword from xmm2/mem64 to xmm1. Move quadword from xmm1 to xmm2/mem64.
INSTRUCTION SET REFERENCE, A-M Flags Affected None. SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) If the destination operand is in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS(0) If a memory operand effective address is outside the SS segment limit. #UD If CR0.EM[bit 2] = 1. 128-bit operations will generate #UD only if CR4.OSFXSR[bit 9] = 0.
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in Real Address Mode #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #UD If CR0.EM[bit 2] = 1.
INSTRUCTION SET REFERENCE, A-M MOVQ2DQ—Move Quadword from MMX Technology to XMM Register Opcode F3 0F D6 Instruction MOVQ2DQ xmm, mm 64-Bit Mode Valid Compat/ Leg Mode Valid Description Move quadword from mmx to low quadword of xmm. Description Moves the quadword from the source operand (second operand) to the low quadword of the destination operand (first operand). The source operand is an MMX technology register and the destination operand is an XMM register.
INSTRUCTION SET REFERENCE, A-M Virtual-8086 Mode Exceptions Same exceptions as in Protected Mode. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions Same exceptions as in Protected Mode. Vol.
INSTRUCTION SET REFERENCE, A-M MOVS/MOVSB/MOVSW/MOVSD/MOVSQ—Move Data from String to String \ 64-Bit Mode Valid Compat/ Leg Mode Valid MOVS m16, m16 Valid Valid A5 MOVS m32, m32 Valid Valid REX.W + A5 Valid N.E. A4 MOVS m64, m64 MOVSB Valid Valid A5 MOVSW Valid Valid A5 MOVSD Valid Valid REX.W + A5 MOVSQ Valid N.E. Opcode A4 Instruction MOVS m8, m8 A5 Description For legacy mode, Move byte from address DS:(E)SI to ES:(E)DI.
INSTRUCTION SET REFERENCE, A-M At the assembly-code level, two forms of this instruction are allowed: the “explicitoperands” form and the “no-operands” form. The explicit-operands form (specified with the MOVS mnemonic) allows the source and destination operands to be specified explicitly. Here, the source and destination operands should be symbols that indicate the size and location of the source value and the destination, respectively.
INSTRUCTION SET REFERENCE, A-M (E)SI ← (E)SI – 1; (E)DI ← (E)DI – 1; FI; ELSE IF (Word move) THEN IF DF = 0 (E)SI ← (E)SI + 2; (E)DI ← (E)DI + 2; FI; ELSE (E)SI ← (E)SI – 2; (E)DI ← (E)DI – 2; FI; ELSE IF (Doubleword move) THEN IF DF = 0 (E)SI ← (E)SI + 4; (E)DI ← (E)DI + 4; FI; ELSE (E)SI ← (E)SI – 4; (E)DI ← (E)DI – 4; FI; FI; 64-bit Mode: IF (Byte move) THEN IF DF = 0 THEN (R|E)SI ← (R|E)SI + 1; (R|E)DI ← (R|E)DI + 1; ELSE (R|E)SI ← (R|E)SI – 1; (R|E)DI ← (R|E)DI – 1; FI; ELSE IF (Word move) THEN IF DF
INSTRUCTION SET REFERENCE, A-M (R|E)SI ← (R|E)SI + 4; (R|E)DI ← (R|E)DI + 4; FI; ELSE (R|E)SI ← (R|E)SI – 4; (R|E)DI ← (R|E)DI – 4; FI; ELSE IF (Quadword move) THEN IF DF = 0 (R|E)SI ← (R|E)SI + 8; (R|E)DI ← (R|E)DI + 8; FI; ELSE (R|E)SI ← (R|E)SI – 8; (R|E)DI ← (R|E)DI – 8; FI; FI; Flags Affected None. Protected Mode Exceptions #GP(0) If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
INSTRUCTION SET REFERENCE, A-M #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form.
INSTRUCTION SET REFERENCE, A-M MOVSD—Move Scalar Double-Precision Floating-Point Value Opcode F2 0F 10 /r Instruction MOVSD xmm1, xmm2/m64 F2 0F 11 /r MOVSD xmm2/m64, xmm1 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Move scalar double-precision floating-point value from xmm2/m64 to xmm1 register. Move scalar double-precision floating-point value from xmm1 register to xmm2/m64.
INSTRUCTION SET REFERENCE, A-M Intel C/C++ Compiler Intrinsic Equivalent MOVSD __m128d _mm_load_sd (double *p) MOVSD void _mm_store_sd (double *p, __m128d a) MOVSD __m128d _mm_store_sd (__m128d a, __m128d b) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
INSTRUCTION SET REFERENCE, A-M MOVSHDUP—Move Packed Single-FP High and Duplicate Opcode F3 0F 16 /r Instruction MOVSHDUP xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Move two single-precision floating-point values from the higher 32-bit operand of each qword in xmm2/m128 to xmm1 and duplicate each 32-bit operand to the lower 32-bits of each qword. Description The linear address corresponds to the address of the least-significant byte of the referenced memory data.
INSTRUCTION SET REFERENCE, A-M Operation IF (Source == m128) THEN (* Load instruction *) xmm1[31:0] = m128[63:32]; xmm1[63:32] = m128[63:32]; xmm1[95:64] = m128[127:96]; xmm1[127:96] = m128[127:96]; ELSE (* Move instruction *) xmm1[31:0] = xmm2[63:32]; xmm1[63:32] = xmm2[63:32]; xmm1[95:64] = xmm2[127:96]; xmm1[127:96] = xmm2[127:96]; FI; Intel C/C++ Compiler Intrinsic Equivalent MOVSHDUP __m128 _mm_movehdup_ps(__m128 a) Exceptions General protection exception if not aligned on 16-byte boundary, regardl
INSTRUCTION SET REFERENCE, A-M Real Address Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. Virtual 8086 Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH.
INSTRUCTION SET REFERENCE, A-M MOVSLDUP—Move Packed Single-FP Low and Duplicate Opcode F3 0F 12 /r Instruction MOVSLDUP xmm1, xmm2/m128 64Bit Mode Valid Compat/ Leg Mode Valid Description Move two single-precision floatingpoint values from the lower 32-bit operand of each qword in xmm2/m128 to xmm1 and duplicate each 32-bit operand to the higher 32bits of each qword. Description The linear address corresponds to the address of the least-significant byte of the referenced memory data.
INSTRUCTION SET REFERENCE, A-M Operation IF (Source == m128) THEN (* Load instruction *) xmm1[31:0] = m128[31:0]; xmm1[63:32] = m128[31:0]; xmm1[95:64] = m128[95:64]; xmm1[127:96] = m128[95::64]; ELSE (* Move instruction *) xmm1[31:0] = xmm2[31:0]; xmm1[63:32] = xmm2[31:0]; xmm1[95:64] = xmm2[95:64]; xmm1[127:96] = xmm2[95:64]; FI; Intel C/C++ Compiler Intrinsic Equivalent MOVSLDUP __m128 _mm_moveldup_ps(__m128 a) Exceptions General protection exception if not aligned on 16-byte boundary, regardless of
INSTRUCTION SET REFERENCE, A-M Real Address Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If memory operand is not aligned on a 16-byte boundary, regardless of segment. #NM If CR0.TS[bit 3] = 1.If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:ECX.SSE3[bit 0] = 0. Virtual 8086 Mode Exceptions GP(0) If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH.
INSTRUCTION SET REFERENCE, A-M MOVSS—Move Scalar Single-Precision Floating-Point Values Opcode F3 0F 10 /r Instruction MOVSS xmm1, xmm2/m32 F3 0F 11 /r MOVSS xmm2/m32, xmm 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Move scalar single-precision floating-point value from xmm2/m32 to xmm1 register. Move scalar single-precision floating-point value from xmm1 register to xmm2/m32.
INSTRUCTION SET REFERENCE, A-M Intel C/C++ Compiler Intrinsic Equivalent MOVSS __m128 _mm_load_ss(float * p) MOVSS void_mm_store_ss(float * p, __m128 a) MOVSS __m128 _mm_move_ss(__m128 a, __m128 b) SIMD Floating-Point Exceptions None. Protected Mode Exceptions #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) 3-670 Vol. 2 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
INSTRUCTION SET REFERENCE, A-M MOVSX/MOVSXD—Move with Sign-Extension Opcode 0F BE /r Instruction MOVSX r16, r/m8 64-Bit Mode Valid Compat/ Leg Mode Valid 0F BE /r MOVSX r32, r/m8 Valid Valid REX + 0F BE /r MOVSX r64, r/m8* Valid N.E. 0F BF /r MOVSX r32, r/m16 Valid Valid REX.W + 0F BF /r MOVSX r64, r/m16 Valid N.E. REX.W** + 63 /r MOVSXD r64, r/m32 Valid N.E. Description Move byte to word with sign-extension. Move byte to doubleword with sign-extension.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #GP(0) If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a NULL segment selector. #SS(0) If a memory operand effective address is outside the SS segment limit. #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
INSTRUCTION SET REFERENCE, A-M MOVUPD—Move Unaligned Packed Double-Precision Floating-Point Values Opcode 66 0F 10 /r Instruction MOVUPD xmm1, xmm2/m128 66 0F 11 /r MOVUPD xmm2/m128, xmm 64-Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Move packed double-precision floating-point values from xmm2/m128 to xmm1. Move packed double-precision floating-point values from xmm1 to xmm2/m128.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0.
INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Vol.
INSTRUCTION SET REFERENCE, A-M MOVUPS—Move Unaligned Packed Single-Precision Floating-Point Values Opcode 0F 10 /r Instruction MOVUPS xmm1, xmm2/m128 0F 11 /r MOVUPS xmm2/m128, xmm1 64Bit Mode Valid Compat/ Leg Mode Valid Valid Valid Description Move packed single-precision floating-point values from xmm2/m128 to xmm1. Move packed single-precision floating-point values from xmm1 to xmm2/m128.
INSTRUCTION SET REFERENCE, A-M Protected Mode Exceptions #AC(0) If alignment checking is enabled and an unaligned memory reference is made. #GP(0) For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. #SS(0) For an illegal address in the SS segment. #PF(fault-code) For a page fault. #NM If CR0.TS[bit 3] = 1. #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0.
INSTRUCTION SET REFERENCE, A-M #UD If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. 3-678 Vol.
INSTRUCTION SET REFERENCE, A-M MOVZX—Move with Zero-Extend Opcode 0F B6 /r Instruction MOVZX r16, r/m8 64-Bit Mode Valid Compat/ Leg Mode Valid 0F B6 /r MOVZX r32, r/m8 Valid Valid REX.W + 0F B6 /r 0F B7 /r MOVZX r64, r/m8* Valid N.E. MOVZX r32, r/m16 Valid Valid REX.W + 0F B7 /r MOVZX r64, r/m32 Valid N.E. Description Move byte to word with zeroextension. Move byte to doubleword, zero-extension. Move byte to quadword, zero-extension. Move word to doubleword, zero-extension.
INSTRUCTION SET REFERENCE, A-M #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions #GP If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. #SS If a memory operand effective address is outside the SS segment limit.
INSTRUCTION SET REFERENCE, A-M MUL—Unsigned Multiply Opcode F6 /4 REX + F6 /4 F7 /4 Instruction MUL r/m8 MUL r/m8* MUL r/m16 64-Bit Mode Valid Valid Valid Compat/ Leg Mode Valid N.E. Valid F7 /4 MUL r/m32 Valid Valid REX.W + F7 /4 MUL r/m64 Valid N.E. Description Unsigned multiply (AX ← AL ∗ r/m8). Unsigned multiply (AX ← AL ∗ r/m8). Unsigned multiply (DX:AX ← AX ∗ r/m16). Unsigned multiply (EDX:EAX ← EAX ∗ r/m32). Unsigned multiply (RDX:RAX ← RAX ∗ r/m64.
INSTRUCTION SET REFERENCE, A-M Operation IF (Byte operation) THEN AX ← AL ∗ SRC; ELSE (* Word or doubleword operation *) IF OperandSize = 16 THEN DX:AX ← AX ∗ SRC; ELSE IF OperandSize = 32 THEN EDX:EAX ← EAX ∗ SRC; FI; ELSE (* OperandSize = 64 *) RDX:RAX ← RAX ∗ SRC; FI; FI; Flags Affected The OF and CF flags are set to 0 if the upper half of the result is 0; otherwise, they are set to 1. The SF, ZF, AF, and PF flags are undefined.
INSTRUCTION SET REFERENCE, A-M #PF(fault-code) If a page fault occurs. #AC(0) If alignment checking is enabled and an unaligned memory reference is made. Compatibility Mode Exceptions Same exceptions as in Protected Mode. 64-Bit Mode Exceptions #SS(0) If a memory address referencing the SS segment is in a noncanonical form. #GP(0) If the memory address is in a non-canonical form. #PF(fault-code) If a page fault occurs.
INSTRUCTION SET REFERENCE, A-M MULPD—Multiply Packed Double-Precision Floating-Point Values Opcode 66 0F 59 /r Instruction MULPD xmm1, xmm2/m128 64Bit Mode Valid Compat/ Leg Mode Valid Description Multiply packed double-precision floating-point values in xmm2/m128 by xmm1.
INSTRUCTION SET REFERENCE, A-M #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.
INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. 3-686 Vol.
INSTRUCTION SET REFERENCE, A-M MULPS—Multiply Packed Single-Precision Floating-Point Values Opcode 0F 59 /r Instruction MULPS xmm1, xmm2/m128 64-Bit Mode Valid Compat/ Leg Mode Valid Description Multiply packed single-precision floating-point values in xmm2/mem by xmm1.
INSTRUCTION SET REFERENCE, A-M #XM If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1. #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Real-Address Mode Exceptions #GP(0) If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. Vol.
INSTRUCTION SET REFERENCE, A-M MULSD—Multiply Scalar Double-Precision Floating-Point Values Opcode F2 0F 59 /r Instruction MULSD xmm1, xmm2/m64 64-Bit Mode Valid Compat/ Leg Mode Valid Description Multiply the low double-precision floating-point value in xmm2/mem64 by low doubleprecision floating-point value in xmm1.
INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE2[bit 26] = 0. #AC(0) 3-692 Vol. 2 If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.
INSTRUCTION SET REFERENCE, A-M MULSS—Multiply Scalar Single-Precision Floating-Point Values Opcode F3 0F 59 /r Instruction MULSS xmm1, xmm2/m32 64Bit Mode Valid Compat/ Leg Mode Valid Description Multiply the low single-precision floating-point value in xmm2/mem by the low single-precision floating-point value in xmm1.
INSTRUCTION SET REFERENCE, A-M #UD If an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0. If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Real-Address Mode Exceptions GP(0) If any part of the operand lies outside the effective address space from 0 to FFFFH. #NM If CR0.TS[bit 3] = 1.
INSTRUCTION SET REFERENCE, A-M If CR4.OSFXSR[bit 9] = 0. If CPUID.01H:EDX.SSE[bit 25] = 0. #AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3. Vol.
INSTRUCTION SET REFERENCE, A-M MWAIT—Monitor Wait Opcode OF 01 C9 Instruction MWAIT 64-Bit Mode Valid Compat/ Leg Mode Valid Description A hint that allow the processor to stop instruction execution and enter an implementation-dependent optimized state until occurrence of a class of events. Description MWAIT instruction provides hints to allow the processor to enter an implementationdependent optimized state. There are two principal targeted usages: address-range monitor and advanced power management.
INSTRUCTION SET REFERENCE, A-M processor will exit the state and handle the interrupt. If an SMI caused the processor to exit the implementation-dependent-optimized state, execution will resume at the instruction following MWAIT after handling of the SMI. Unlike the HLT instruction, the MWAIT instruction does not support a restart at the MWAIT instruction.
INSTRUCTION SET REFERENCE, A-M Table 3-63.
INSTRUCTION SET REFERENCE, A-M MWAIT EAX, ECX } } The above code sequence makes sure that a triggering store does not happen between the first check of the trigger and the execution of the monitor instruction. Without the second check that triggering store would go un-noticed. Typical usage of MONITOR and MWAIT would have the above code sequence within a loop. Numeric Exceptions None. Protected Mode Exceptions ≠ 0 and CPUID.05H.ECX[0] = 0. #GP(0) If ECX #UD If CPUID.01H:ECX.MONITOR[bit 3] = 0.
INSTRUCTION SET REFERENCE, A-M 64-Bit Mode Exceptions #GP(0) If the current privilege level is not 0. #UD If CPUID.01H:ECX.MONITOR[bit 3] = 0. If RCX ≠ 0 and CPUID.05H.ECX[0] = 0. If the F3H, F2H, 66H or LOCK prefix is used. 3-700 Vol.
INTEL SALES OFFICES ASIA PACIFIC Australia Intel Corp. Level 2 448 St Kilda Road Melbourne VIC 3004 Australia Fax:613-9862 5599 China Intel Corp. Rm 709, Shaanxi Zhongda Int'l Bldg No.30 Nandajie Street Xian AX710002 China Fax:(86 29) 7203356 Intel Corp. Room 0724, White Rose Hotel No 750, MinZhu Road WuChang District Wuhan UB 430071 China Viet Nam Intel Corp. Hanoi Tung Shing Square, Ste #1106 2 Ngo Quyen St Hoan Kiem District Hanoi Viet Nam India Intel Corp.
Intel Corp. 999 CANADA PLACE, Suite 404,#11 Vancouver BC V6C 3E2 Canada Fax:604-844-2813 Intel Corp. 2650 Queensview Drive, Suite 250 Ottawa ON K2B 8H6 Canada Fax:613-820-5936 Intel Corp. 190 Attwell Drive, Suite 500 Rexcdale ON M9W 6H8 Canada Fax:416-675-2438 Intel Corp. 171 St. Clair Ave. E, Suite 6 Toronto ON Canada Intel Corp. 1033 Oak Meadow Road Oakville ON L6M 1J6 Canada USA California Intel Corp. 551 Lundy Place Milpitas CA 95035-6833 USA Fax:408-451-8266 Intel Corp. 1551 N.
