Intel Pentium 4 Processor with 512-KBL2 Cache on 0.13 Micron Process and Intel Pentium 4 Processor ExtremeEdition Supporting Hyper-ThreadingTechnology1

ManualsBrandsIntel ManualsOtherPentium 4 Processor Extreme Edition supporting HT Technology 3.73 GHz, 2M Cache, 1066 MHz FSB

Intel

Pentium

4 Processor with 512-KB

L2 Cache on 0.13 Micron Process and

Intel

Pentium

4 Processor Extreme

Edition Supporting Hyper-Threading

Technology

Datasheet

2 GHz – 3.40 GHz Frequencies Supporting Hyper-Threading

Technology

at 3.06 GHz with 533 MHz System Bus and All

Frequencies with 800 MHz System Bus

The Intel

Pentium

4 processor family supporting Hyper-Threading Technology

(HT Technology) delivers Intel's most advanced, most powerful processors for desktop PCs and

entry-level workstations, which are based on the Intel NetBurst

microarchitecture. The

Pentium 4 processor is designed to deliver performance across applications and usages where

end-users can truly appreciate and experience the performance. These applications include

Internet audio and streaming video, image processing, video content creation, speech, 3D, CAD,

games, multimedia, and multitasking user environments. The Intel

Pentium

4 processor

Extreme Edition supporting HT Technology features 2 MB of L3 cache and offers high levels of

performance targeted specifically for high-end gamers and computing power users.

■ Available at 2 GHz, 2.20 GHz, 2.26 GHz,

2.40 GHz, 2.50 GHz, 2.53 GHz, 2.60 GHz,

2.66 GHz, 2.80 GHz, 3 GHz, 3.06 GHz,

3.20 GHz, and 3.40 GHz

■ Supports Hyper-Threading Technology

(HT Technology) at 3.06 GHz with 533 MHz

system bus and all frequencies with 800 MHz

system bus

■ Binary compatible with applications running

on previous members of the Intel

microprocessor line

■ Intel NetBurst

microarchitecture

■ System bus frequency at 400 MHz, 533 MHz,

and 800 MHz

■ Rapid Execution Engine: Arithmetic Logic

Units (ALUs) run at twice the processor core

frequency

■ Hyper-Pipelined Technology

— Advance Dynamic Execution

— Very deep out-of-order execution

■ Enhanced branch prediction

■ Optimized for 32-bit applications running on

advanced 32-bit operating systems

■ 8-KB Level 1 data cache

■ Level 1 Execution Trace Cache stores 12-K

micro-ops and removes decoder latency from

main execution loops

■ 512-KB Advanced Transfer Cache (on-die,

full-speed Level 2 (L2) cache) with 8-way

associativity and Error Correcting Code

(ECC)

■ 2-MB Integrated Level 3 (L3) cache with

8-way associativity that is supported by Intel

Pentium

4 Processor Extreme Edition

Supporting Hyper-Threading Technology

■ 144 Streaming SIMD Extensions 2 (SSE2)

instructions

■ Enhanced floating point and multimedia unit

for enhanced video, audio, encryption, and

3D performance

■ Power Management capabilities

— System Management mode

— Multiple low-power states

■ 8-way cache associativity provides improved

cache hit rate on load/store operations

■ 478-Pin Package

February 2004

Document Number: 298643-012

Summary of content (85 pages)

PAGE 1
Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process and Intel® Pentium® 4 Processor Extreme Edition Supporting Hyper-Threading Technology1 Datasheet 2 GHz – 3.40 GHz Frequencies Supporting Hyper-Threading Technology1 at 3.06 GHz with 533 MHz System Bus and All Frequencies with 800 MHz System Bus ■ ■ ■ ■ ■ ■ ■ ■ ■ Available at 2 GHz, 2.20 GHz, 2.26 GHz, 2.40 GHz, 2.50 GHz, 2.53 GHz, 2.60 GHz, 2.66 GHz, 2.80 GHz, 3 GHz, 3.06 GHz, 3.20 GHz, and 3.
PAGE 2
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
PAGE 3
Contents 1 Introduction .................................................................................................................. 9 1.1 1.2 2 Electrical Specifications ........................................................................................15 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 3 Processor Pin Assignments ................................................................................45 Signal Descriptions..........................................................
PAGE 4
6.3 7 Boxed Processor Specifications ....................................................................... 77 7.1 7.2 7.3 7.4 8 Introduction ......................................................................................................... 77 Mechanical Specifications................................................................................... 78 7.2.1 Boxed Processor Cooling Solution Dimensions ..................................... 78 7.2.2 Boxed Processor Fan Heatsink Weight...........
PAGE 5
Figures 2-1 2-2 2-3 2-4 2-5 2-6 2-7 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 5-1 5-2 6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 VCCVID Pin Voltage and Current Requirements .................................................17 Typical VCCIOPLL, VCCA and VSSA Power Distribution ..................................19 Phase Lock Loop (PLL) Filter Requirements ......................................................19 VCC Static and Transient Tolerance (For Intel® Pentium® 4 Processor With 512-KB L2 Cache on 0.13 Micron Process)....
PAGE 6
Tables 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 3-1 3-2 3-3 3-4 4-1 4-2 4-3 5-1 6-1 6-2 6-3 7-1 7-2 6 References.......................................................................................................... 12 VCCVID Pin Voltage Requirements ..................................................................... 17 Voltage Identification Definition........................................................................... 18 System Bus Pin Groups .........................
PAGE 7
Revision History Revision Description Date -005 Added Thermal and Electrical Specifications for frequencies through 3.06 GHz and included multiple VID specifications. Updated the THERMTRIP# and DBI# signal descriptions. Removed Deep Sleep State section. Updated Boxed Processor Fan Heatsink Set Points table and figure. Update Poweron Configuration Option pins table. November 2002 -006 Minor update to DC specifications December 2002 -007 Corrected Table 4-3, Signal Description.
PAGE 8
This page is intentionally left blank. 8 Intel® Pentium® 4 Processor on 0.
PAGE 9
Introduction Introduction 1 The Intel® Pentium® 4 processor with 512-KB L2 cache on 0.13 micron process and the Intel® Pentium® 4 processor Extreme Edition supporting Hyper-Threading Technology are follow-on processors to the Intel® Pentium® 4 processor in the 478-pin package with Intel NetBurst® microarchitecture. These processors use Flip-Chip Pin Grid Array (FC-PGA2) package technology, and plug into a 478-pin surface mount, Zero Insertion Force (ZIF) socket, referred to as the mPGA478B socket.
PAGE 10
Introduction Additional features within the Intel NetBurst microarchitecture include advanced dynamic execution, advanced transfer cache, enhanced floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2). The advanced dynamic execution improves speculative execution and branch prediction internal to the processor. The advanced transfer cache is a 512-KB, on-die level 2 (L2) cache.
PAGE 11
Introduction 1.1 Terminology A ‘#’ symbol after a signal name refers to an active low signal, indicating that the signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol indicates that the signal is inverted.
PAGE 12
Introduction • Processor core — Pentium 4 processor with 512-KB L2 cache on 0.13 micron process core • • • • 1.2 die with integrated L2 cache and the Pentium 4 processor Extreme Edition supporting HyperThreading Technology core die with integrated L2 and L3 caches. FC-PGA2 package — Flip-Chip Pin Grid Array package with 50-mil pin pitch and integrated heat spreader. mPGA478B socket — Surface mount, 478 pin, Zero Insertion Force (ZIF) socket with 50-mil pin pitch.
PAGE 13
Introduction Table 1-1. References (Sheet 2 of 2) Document ® Location IA-32 Intel Architecture Software Developer’s Manual Volume 1: Basic Architecture http://developer.intel.com/design/ pentium4/manuals/245470.htm IA-32 Intel® Architecture Software Developer’s Manual, Volume 2: Instruction Set Reference http://developer.intel.com/design/ pentium4/manuals/245471.htm IA-32 Intel® Architecture Software Developer’s Manual, Volume 3: System Programming Guide http://developer.intel.
PAGE 14
Introduction This page is intentionally left blank. 14 Intel® Pentium® 4 Processor on 0.
PAGE 15
Electrical Specifications Electrical Specifications 2.1 2 System Bus and GTLREF Most Pentium 4 processor on 0.13 micron process system bus signals use Assisted Gunning Transceiver Logic (AGTL+) signalling technology. As with the P6 family of microprocessors, this signalling technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. Like the Pentium 4 processor in the 478-pin package, the termination voltage level for the Pentium 4 processor on 0.
PAGE 16
Electrical Specifications 2.3 Decoupling Guidelines Because of the large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 2-6.
PAGE 17
Electrical Specifications Power source characteristics must be stable when the supply to the voltage regulator is stable. Refer to the appropriate platform design guide for timing details of the power up sequence. Refer to the appropriate platform design guide for implementation details. The Voltage Identification circuit requires an independent 1.2 V supply. This voltage must be routed to the processor VCCVID pin. Figure 2-1 and Table 2-1 show the voltage and current requirements of the VCCVID pin.
PAGE 18
Electrical Specifications Table 2-2. Voltage Identification Definition Processor Pins 2.4.1 VCC_MAX VID4 VID3 VID2 VID1 VID0 1 1 1 1 1 VRM output off 1 1 1 1 0 1.100 1 1 1 0 1 1.125 1 1 1 0 0 1.150 1 1 0 1 1 1.175 1 1 0 1 0 1.200 1 1 0 0 1 1.225 1 1 0 0 0 1.250 1 0 1 1 1 1.275 1 0 1 1 0 1.300 1 0 1 0 1 1.325 1 0 1 0 0 1.350 1 0 0 1 1 1.375 1 0 0 1 0 1.400 1 0 0 0 1 1.425 1 0 0 0 0 1.450 0 1 1 1 1 1.
PAGE 19
Electrical Specifications Figure 2-2. Typical VCCIOPLL, VCCA and VSSA Power Distribution VCC L VCCA CA PLL VSSA Processor Core CIO VCCIOPLL L . Figure 2-3. Phase Lock Loop (PLL) Filter Requirements 0.2 dB 0 dB –0.5 dB Forbidden Zone Forbidden Zone –28 dB –34 dB DC 1 Hz fpeak 1 MHz Passband 66 MHz fcore High Frequency Band NOTES: 1. Diagram not to scale. 2. No specification for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 MHz.
PAGE 20
Electrical Specifications 2.5 Reserved, Unused Pins, and TESTHI[12:0] All RESERVED pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future Pentium 4 processors on 0.13 micron process. See Chapter 4 for a pin listing of the processor and the location of all RESERVED pins.
PAGE 21
Electrical Specifications 2.6 System Bus Signal Groups To simplify the following discussion, the system bus signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers that use GTLREF as a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
PAGE 22
Electrical Specifications 2.7 Asynchronous GTL+ Signals The Pentium 4 processor on 0.13 micron process does not use CMOS voltage levels on any signals that connect to the processor. As a result, legacy input signals (such as A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, and STPCLK#) use GTL+ input buffers. Legacy output FERR# and other non-AGTL+ signals (THERMTRIP#) use GTL+ output buffers. PROCHOT# uses GTL+ input/output buffer.
PAGE 23
Electrical Specifications 2.10 Maximum Ratings Table 2-5 lists the processor’s maximum environmental stress ratings. The processor should not receive a clock while subjected to these conditions. Functional operating parameters are listed in the DC tables. Extended exposure to the maximum ratings may affect device reliability.
PAGE 24
Electrical Specifications Table 2-6. Voltage and Current Specifications (Sheet 1 of 4) Symbol Parameter Min Typ Max Unit Notes10 VCC for Processor at VID=1.475 V 2A GHz 2.20 GHz 2.40 GHz 2.50 GHz 2.60 GHz VCC (400 MHz FSB) 1.315 1.310 1.300 1.300 1.295 VCC for Processor at VID=1.500 V 2A GHz 2.20 GHz 2.40 GHz 2.50 GHz 2.60 GHz 1.340 1.335 1.330 1.325 1.320 1.390 1.385 1.380 1.375 1.375 Refer to Table 2-7 and Figure 2-4 1.415 1.410 1.405 1.400 1.
PAGE 25
Electrical Specifications Table 2-6. Voltage and Current Specifications (Sheet 2 of 4) Symbol VCC (800 MHz FSB with 512-KB L2 Cache Only) Parameter Min VCC for Processor at VID=1.475 V 2.40C GHz 2.60C GHz 2.80C GHz 3 GHz 3.20C GHz 3.40 GHz 1.295 1.290 1.288 1.265 1.260 1.280 1.375 1.370 1.369 1.350 1.345 1.350 VCC for Processor at VID=1.500 V 2.40C GHz 2.60C GHz 2.80C GHz 3 GHz 3.20C GHz 3.40 GHz 1.320 1.315 1.313 1.290 1.285 1.305 1.400 1.395 1.394 1.375 1.370 1.375 VCC for Process or at VID=1.
PAGE 26
Electrical Specifications Table 2-6. Voltage and Current Specifications (Sheet 3 of 4) Symbol Parameter Min Typ Max Unit Notes10 ICC for Processor at VID=1.500 V 2A GHz 2.20 GHz 2.40 GHz 2.50 GHz ICC (400 MHz FSB) 44.3 47.1 49.8 51.3 ICC for Processor at VID=1.525 V 2A GHz 2.20 GHz 2.40 GHz 2.50 GHz 2.60 GHz 45.1 47.9 50.7 52.0 53.5 A 3,4,6,10 A 3,4,6,10 A 3,4,6,10 A 4,6,10,13 ICC for Processor with multiple VIDs 2A GHz 2.20 GHz 2.40 GHz 2.50 GHz 2.60 GHz 45.1 47.9 50.7 52.0 53.
PAGE 27
Electrical Specifications Table 2-6. Voltage and Current Specifications (Sheet 4 of 4) Symbol Parameter Min Typ Max 23 ISGNT Islp ICC Stop-Grant 27 32 Notes10 Unit 5,7,8 A 35 5,7,11 5,7,12 5,7,14 ITCC ICC TCC active ICC A ICC PLL ICC for PLL pins 60 mA 6 NOTES: 1. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Table 2-2 for more information.
PAGE 28
Electrical Specifications Table 2-7. VCC Static and Transient Tolerance (For Intel® Pentium® 4 Processor With 512-KB L2 Cache on 0.13 Micron Process at Frequencies up to and Including 3.2 GHz) Voltage Deviation from VID Setting (V)1,2,3 Icc (A) Maximum Typical Minimum 0 0.000 –0.025 –0.050 5 –0.010 –0.036 –0.062 10 –0.019 –0.047 –0.075 15 –0.029 –0.058 –0.087 20 –0.038 –0.069 –0.099 25 –0.048 –0.079 –0.111 30 –0.057 –0.090 –0.124 35 –0.067 –0.101 –0.136 40 –0.076 –0.
PAGE 29
Electrical Specifications Figure 2-4. VCC Static and Transient Tolerance (For Intel® Pentium® 4 Processor With 512-KB L2 Cache on 0.13 Micron Process at Frequencies up to and Including 3.2 GHz) VID +50 mV VID VCC Maximum VCC (V) VID -50 mV VID -100 mV VCC Typical VID -150 mV VCC Minimum VID -200 mV VID -250 mV 0 10 20 40 30 50 60 70 ICC (A) NOTES: 1. The loadline specification includes both static and transient limits. 2.
PAGE 30
Electrical Specifications Table 2-8. Vcc Static and Transient Tolerance (For Intel® Pentium® 4 Processor Extreme Edition Supporting Hyper-Threading Technology, and Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process at 3.4 GHz) Voltage Deviation from VID Setting (V)1,2,3 Icc (A) 0 Maximum Typical Minimum 0 -0.019 -0.038 5 -0.009 -0.029 -0.049 10 -0.019 -0.039 -0.059 15 -0.028 -0.049 -0.070 20 -0.037 -0.059 -0.080 25 -0.046 -0.068 -0.091 30 -0.056 -0.078 -0.
PAGE 31
Electrical Specifications Figure 2-5. VCC Static and Transient Tolerance (For Intel® Pentium® 4 Processor Extreme Edition Supporting Hyper-Threading Technology, and Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process at 3.4 GHz) VID+25 mV VID VID-25 mV VCC Maximum VID-50 mV VCC Typical VCC (Volts) VID-75 mV VID-100 mV VID-125 mV VCC Minimum VID-150 mV VID-175 mV VID-200 mV VID-225 mV VID-250 mV 0 10 20 30 40 50 60 70 80 90 ICC (Amperes) NOTES: 1.
PAGE 32
Electrical Specifications . Table 2-9. AGTL+ Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 GTLREF Reference Voltage 2/3 VCC – 2% 2/3 VCC + 2% V GTLREF Compatible Reference Voltage 0.63 VCC – 2% 0.63 VCC +2% V 10 VIH Input High Voltage 1.10*GTLREF VCC V 2,5 VIL Input Low Voltage 0.0 0.
PAGE 33
Electrical Specifications Table 2-11.
PAGE 34
Electrical Specifications Figure 2-6. ITPCLKOUT[1:0] Output Buffer Diagram VCC Ron To Debug Port Processor Package Rext NOTES: 1. See Table 2-12 for range of Ron. 2. The VCC referred to in this figure is the instantaneous Vcc. 3. Refer to the ITP 700 Debug Port Design Guide and the appropriate platform design guidelines for the value of Rext. Table 2-13. BSEL [1:0] and VID[4:0] DC Specifications Symbol Ron (BSEL) Ron (VID) IHI Parameter Notes1 Min Max Unit Buffer On Resistance 9.2 14.
PAGE 35
Electrical Specifications 2.12 AGTL+ System Bus Specifications Routing topology recommendations may be found in the appropriate platform design guide listed in Table 1-1. Termination resistors are not required for most AGTL+ signals because they are integrated into the processor silicon. Valid high and low levels are determined by the input buffers which compare a signal’s voltage with a reference voltage called GTLREF (known as VREF in previous documentation). Table 2-14 lists the GTLREF specifications.
PAGE 36
Electrical Specifications This page is intentionally left blank. 36 Intel® Pentium® 4 Processor on 0.
PAGE 37
Package Mechanical Specifications Package Mechanical Specifications 3 The Pentium 4 processor on 0.13 micron process is packaged in a Flip-Chip Pin Grid Array (FC-PGA2) package. Components of the package include an integrated heat spreader (IHS), processor die, and the substrate which is the pin carrier. Mechanical specifications for the processor are given in this section. See Section 1.1. for a terminology listing. The processor socket that accepts the Pentium 4 processor on 0.
PAGE 38
Package Mechanical Specifications Figure 3-2. Processor Package Table 3-1. Description Table for Processor Dimensions Dimension (mm) Code Letter Notes Min Nominal Max A1 2.266 2.378 2.490 Original package (6 layer) A2 0.980 1.080 1.180 Original package (6 layer) A1 2.42 2.55 2.67 Alternate equivalent package (8 layer) A2 1.13 1.20 1.27 Alternate equivalent package (8 layer) B1 30.800 31.000 31.200 B2 30.800 31.000 31.200 C1 33.000 Includes placement tolerance C2 33.
PAGE 39
Package Mechanical Specifications Figure 3-3 details the keep-in specification for pin-side components. The Pentium 4 processor on 0.13 micron process may contain pin-side capacitors mounted to the processor package. Figure 3-5 details the flatness and tilt specifications for the IHS. Tilt is measured with the reference datum set to the bottom of the processor susbstrate. Figure 3-3. Processor Cross-Section and Keep-In FCPGA 2 IHS Substrate 1.25mm 13.
PAGE 40
Package Mechanical Specifications Figure 3-5. IHS Flatness Specification IHS SUBSTRATE NOTES: 1. Flatness is specific as overall, not per unit of length. 2. All Dimensions are in millimeters. 3.1 Package Load Specifications Table 3-2 provides dynamic and static load specifications for the processor IHS. These mechanical load limits should not be exceeded during heatsink assembly, mechanical stress testing, or standard drop and shipping conditions.
PAGE 41
Package Mechanical Specifications 3.2 Processor Insertion Specifications The Pentium 4 processor on 0.13 micron process can be inserted and removed 15 times from a mPGA478B socket meeting the Intel® Pentium® 4 Processor 478-Pin Socket (mPGA478B) Socket Design Guidelines document. 3.3 Processor Mass Specifications Table 3-3 specifies the processor’s mass. This includes all components which make up the entire processor product. Table 3-3. Processor Mass Processor Intel® Pentium® 4 processor on 0.
PAGE 42
Package Mechanical Specifications 3.5 Processor Markings Figure 3-6 and Figure 3-7 detail the processor top-side markings and is provided to aid in the identification of the Pentium 4 processors on 0.13 micron process. Figure 3-6. Processor Markings (Processors with Fixed VID) INTEL m c `01 PENTIUM® 4 Frequency/Cache/Bus/Voltage 2.40 GHZ/512/800/1.50V S-Spec/Country of Assy SYYYY XXXXXX FFFFFFFF–NNNN FPO – Serial # 2-D Matrix Mark Figure 3-7.
PAGE 43
Package Mechanical Specifications Figure 3-8. The Coordinates of the Processor Pins As Viewed from the Top of the Package Intel® Pentium® 4 Processor on 0.
PAGE 44
Package Mechanical Specifications This page is intentionally left blank. 44 Intel® Pentium® 4 Processor on 0.
PAGE 45
Pin Lists and Signal Descriptions Pin Lists and Signal Descriptions 4.1 4 Processor Pin Assignments This section contains pin lists for the Pentium 4 processor on 0.13 micron process. Table 4-1 is ordered alphabetically by pin name; Table 4-2 is ordered alphabetically by pin number. Intel® Pentium® 4 Processor on 0.
PAGE 46
Pin Lists and Signal Descriptions Table 4-1. Pin Listing by Pin Name Pin Name 46 Pin Number Signal Buffer Type Direction Table 4-1.
PAGE 47
Pin Lists and Signal Descriptions Table 4-1. Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type Direction Table 4-1.
PAGE 48
Pin Lists and Signal Descriptions Table 4-1. Pin Listing by Pin Name Pin Name 48 Pin Number Signal Buffer Type Direction Table 4-1.
PAGE 49
Pin Lists and Signal Descriptions Table 4-1. Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type Direction Table 4-1.
PAGE 50
Pin Lists and Signal Descriptions Table 4-1. Pin Listing by Pin Name Pin Name 50 Pin Number Signal Buffer Type Direction Table 4-1.
PAGE 51
Pin Lists and Signal Descriptions Table 4-1. Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type Direction Table 4-1.
PAGE 52
Pin Lists and Signal Descriptions Table 4-2. Pin Listing by Pin Number Pin Number 52 Pin Name Signal Buffer Type A2 THERMTRIP# Asynch GTL+ A3 VSS Power/Other A4 VSS_SENSE Power/Other Direction Table 4-2.
PAGE 53
Pin Lists and Signal Descriptions Table 4-2. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Direction Table 4-2.
PAGE 54
Pin Lists and Signal Descriptions Table 4-2. Pin Listing by Pin Number Pin Number 54 Pin Name Signal Buffer Type Direction Table 4-2.
PAGE 55
Pin Lists and Signal Descriptions Table 4-2. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Direction Table 4-2.
PAGE 56
Pin Lists and Signal Descriptions Table 4-2. Pin Listing by Pin Number Pin Number 56 Pin Name Signal Buffer Type Direction Table 4-2.
PAGE 57
Pin Lists and Signal Descriptions Table 4-2. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type U25 VSS Power/Other U26 D48# Source Synch V1 VSS Power/Other V2 A27# Source Synch V3 A32# Source Synch Direction Table 4-2.
PAGE 58
Pin Lists and Signal Descriptions 4.2 Signal Descriptions Table 4-3. Signal Descriptions (Sheet 1 of 8) Name A[35:3]# Type Input/ Output Description A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the Intel® Pentium® 4 processor on 0.13 micron process system bus.
PAGE 59
Pin Lists and Signal Descriptions Table 4-3. Signal Descriptions (Sheet 2 of 8) Name Type Description BINIT# (Bus Initialization) may be observed and driven by all processor system bus agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power-on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation.
PAGE 60
Pin Lists and Signal Descriptions Table 4-3. Signal Descriptions (Sheet 3 of 8) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period.
PAGE 61
Pin Lists and Signal Descriptions Table 4-3. Signal Descriptions (Sheet 4 of 8) Name DRDY# Type Input/ Output Description DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of all processor system bus agents.
PAGE 62
Pin Lists and Signal Descriptions Table 4-3. Signal Descriptions (Sheet 5 of 8) Name IGNNE# Type Input Description IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
PAGE 63
Pin Lists and Signal Descriptions Table 4-3. Signal Descriptions (Sheet 6 of 8) Name Type Description MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor system bus agents. MCERR# assertion conditions are configurable at a system level. Assertion options are defined by the following options: MCERR# Input/ Output • Enabled or disabled. • Asserted, if configured, for internal errors along with IERR#.
PAGE 64
Pin Lists and Signal Descriptions Table 4-3. Signal Descriptions (Sheet 7 of 8) Name RSP# SKTOCC# SLP# SMI# Type Input Description RSP# (Response Parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect to the appropriate pins of all processor system bus agents.
PAGE 65
Pin Lists and Signal Descriptions Table 4-3. Signal Descriptions (Sheet 8 of 8) Name Type Description Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level where permanent silicon damage may occur. Measurement of the temperature is accomplished through an internal thermal sensor which is configured to trip at approximately 135°C.
PAGE 66
Pin Lists and Signal Descriptions This page is intentionally left blank. 66 Intel® Pentium® 4 Processor on 0.
PAGE 67
Thermal Specifications and Design Considerations Thermal Specifications and Design Considerations 5 The Pentium 4 processor on 0.13 micron process uses an Integrated Heat Spreader (IHS) for heatsink attachment that is intended to provide for multiple types of thermal solutions. This chapter provides data necessary for development of a thermal solution. See Figure 5-1 for an enlarged view of an example of the Pentium 4 processor on 0.13 micron process thermal solution.
PAGE 68
Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The Pentium 4 processor on 0.13 micron process requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system.
PAGE 69
Thermal Specifications and Design Considerations Table 5-1. Processor Thermal Design Power Front Side Bus Frequency Processor and Core Frequency Processors with VID=1.500 V 2A GHz 2.20 GHz 2.40 GHz 2.50 GHz Thermal Design Power1,2 (W) Minimum TC (°C) Maximum TC (°C) 52.4 55.1 57.8 59.3 5 5 5 5 68 69 70 71 54.3 57.1 59.8 61.0 62.6 5 5 5 5 5 69 70 71 72 72 54.3 57.1 59.8 61.0 62.6 5 5 5 5 5 69 70 71 72 72 56.0 57.8 59.3 5 5 5 70 70 71 58.0 59.8 61.5 66.1 68.4 5 5 5 5 5 70 71 72 74 75 58.
PAGE 70
Thermal Specifications and Design Considerations NOTES: 1. These values are specified at VCC_MAX for the processor. Systems must be designed to ensure that the processor is not subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC. Refer to loadline specifications in Chapter 2. 2. The numbers in this column reflect Intel’s recommended design point and are not indicative of the maximum power the processor can dissipate under worst case conditions.
PAGE 71
Features 6 Features 6.1 Power-On Configuration Options Several configuration options can be configured by hardware. The Pentium 4 processor on 0.13 micron process samples hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 6-1. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
PAGE 72
Features 6.2.2 AutoHALT Powerdown State—State 2 AutoHALT is a low power state entered when the processor executes the HALT instruction. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the AutoHALT Power Down state.
PAGE 73
Features 6.2.3 Stop-Grant State—State 3 When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop-Grant Acknowledge special bus cycle. Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven (allowing the level to return to VCC) for minimum power drawn by the termination resistors in this state.
PAGE 74
Features 6.2.5 Sleep State—State 5 The Sleep state is a very low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can be entered only from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state upon the assertion of the SLP# signal. The SLP# pin should be asserted only when the processor is in the Stop-Grant state.
PAGE 75
Features cause a noticeable performance loss, and in some cases may result in a TC that exceeds the specified maximum temperature and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. Refer to the Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Thermal Design Guidelines for information on designing a thermal solution.
PAGE 76
Features 6.3.1 Thermal Diode The Pentium 4 processor on 0.13 micron process incorporates an on-die thermal diode. A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management/long term die temperature change purposes. Table 6-2 and Table 6-3 provide the diode parameter and interface specifications. This thermal diode is separate from the Thermal Monitor’s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor. Table 6-2.
PAGE 77
Boxed Processor Specifications Boxed Processor Specifications 7.1 7 Introduction The Pentium 4 processor on 0.13 micron process will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from motherboards and standard components. The boxed Pentium 4 processor on 0.13 micron process will be supplied with a cooling solution.
PAGE 78
Boxed Processor Specifications 7.2 Mechanical Specifications 7.2.1 Boxed Processor Cooling Solution Dimensions This section describes the mechanical specifications of the boxed Pentium 4 processor on 0.13 micron process. The boxed processor will be shipped with an unattached fan heatsink. Figure 7-1 shows a mechanical representation of the boxed Pentium 4 processor on 0.13 micron process. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.
PAGE 79
Boxed Processor Specifications Figure 7-3. Top View Space Requirements for the Boxed Processor 7.2.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5 and the Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Thermal Design Guidelines for details on the processor weight and heatsink requirements. 7.2.
PAGE 80
Boxed Processor Specifications The target load applied by the clips to the processor heat spreader for Intel’s reference design is 75 ± 15 lbf (maximum load is constrained by the package load capability). It is normal to observe a bow or bend in the board due to this compressive load on the processor package and the socket. The level of bow or bend depends on the motherboard material properties and component layout.
PAGE 81
Boxed Processor Specifications Table 7-1. Fan Heatsink Power and Signal Specifications Description +12 V: 12 Volt fan power supply Min Typ Max 10.2 12 13.8 V 740 mA IC: Fan current draw SENSE: SENSE frequency 2 Unit pulses per fan revolution Notes 1 NOTE: 1. Motherboard should pull this pin up to VCC with a resistor. Figure 7-5. MotherBoard Power Header Placement Relative to Processor Socket Intel® Pentium® 4 Processor on 0.
PAGE 82
Boxed Processor Specifications 7.4 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution utilized by the boxed processor. 7.4.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and is ultimately the responsibility of the system integrator.
PAGE 83
Boxed Processor Specifications Figure 7-7. Boxed Processor Fan Heatsink Airspace Keep-Out Requirements (Side 2 View) 7.4.2 Variable Speed Fan The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low.
PAGE 84
Boxed Processor Specifications Table 7-2. Boxed Processor Fan Heatsink Set Points Boxed Processor Fan Heatsink Set Point (ºC) Boxed Processor Fan Speed Notes Boxed Intel® Pentium® 4 Processors 2.80 GHz (and below) X ≤ 33 When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. Recommended maximum internal chassis temperature for nominal operating environment.
PAGE 85
Debug Tools Specifications Debug Tools Specifications 8 Refer to the ITP 700 Debug Port Design Guide and the appropriate platform design guidelines for more detailed information regarding debug tools specifications (such as integration details). 8.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Pentium 4 processors on 0.13 micron process systems.