R Intel® Pentium® 4 Processor on 90 nm Process Specification Update September 2006 Notice: The Intel® Pentium® processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
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R Contents Revision History .................................................................................................................. 4 Preface................................................................................................................................ 6 Summary Tables of Changes ............................................................................................. 8 General Information ......................................................................................
Revision History R Revision History Revision Number Description -001 • Initial Release -002 • Added content for Intel Pentium 4 processor on 90 nm process in 775-land package Date June 2004 ® ® • Added 775-land package processor upside marking diagram in Figure 2 • Added processor identification information for 775-land package to Table 1 “Out-of-Cycle” June 21 2004 • Notes added to clarify that C0 errata only apply to 478 pin package • Modified for Processor Identification information Table Not
Revision History R Revision Number -012 Description • Updated Processor Identification Table and its notes and updated summary table of changes Date February 2005 • Added errata R83, R84, R85 -013 • Updated Processor Identification Table, and Summary Table of Changes, and processor upside marking for 660, 650, 640, and Δ 630 processor • Added N-stepping information “Out of Cycle” February 22, 2005 • Added Errata R86 -014 • Updated Processor Identification Table, and Summary Table of Changes March
Preface R Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
Preface R Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics, e.g., core speed, L2 cache size, package type, etc. as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number Errata are design defects or errors. Errata may cause the Intel® Pentium® processor’s behavior to deviate from published specifications.
Summary Tables of Changes R Summary Tables of Changes The following table indicates the Errata, Documentation Changes, Specification Clarifications, or Specification Changes that apply to Pentium 4 processors on 90 nm process. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or specification changes as noted.
Summary Tables of Changes R O = Intel® Xeon® processor MP P = Intel® Xeon® processor Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading Technology on 90-nm process technology R = Intel® Pentium® 4 processor on 90 nm process S = 64-bit Intel® Xeon® Processor with 800 MHz system bus T = Mobile Intel® Pentium® 4 processor – M U = 64-bit Intel® Xeon® processor MP with up to 8MB L3 Cache V = Mobile Intel® Celeron® processor on 0.
Summary Tables of Changes R NO.
Summary Tables of Changes R 1 X X R26 X X X X X X X X X No Fix Incorrect Debug Exception (#DB) May Occur When a Data Breakpoint is set on an FP Instruction R27 X X X X X X X X X No Fix xAPIC May Not Report Some Illegal Vector Errors R29 R30 X X X X X X X X X X X LG1 LN0 LR0 2 X X G1 2 R25 X LE0 2 X X E0 1 R24 X LD0 2 C0 R28 D0 2 NO.
Summary Tables of Changes R 1 2 X X R39 X X R40 X Fixed CPUID Instruction May Report Incorrect L2 Associativity in Leaf 0x80000006 R41 X Fixed The FP_ASSIST EMON Event May Return an Incorrect Count R42 X X X X X X X X X No Fix Machine Check Exceptions May not Update Last-Exception Record MSRs (LERs) R43 X X X X X X X X X No Fix MOV CR3 Performs Incorrect Reserved Bit Checking When in PAE Paging No Fix Stores to Page Tables May Not Be Visible to Pagewalks for Subseque
Summary Tables of Changes R NO.
Summary Tables of Changes R NO. 1 C0 D0 LD0 2 E0 LE0 2 G1 1 2 LG1 LN0 2 LR0 2 Plan ERRATA R65 X Fixed Execute Disable Bit Set with AD Assist Will Cause Livelock R66 X Fixed The Execute Disable Bit Fault May be Reported Before Other Types of Page Fault When Both Occur R67 X Fixed Writes to IA32_MISC_ENABLE May Not Update Flags for Both Logical Processors Threads R68 X Fixed Execute Disable Mode Bit Set with CR4.
Summary Tables of Changes R NO.
Summary Tables of Changes R NO.
Summary Tables of Changes R NO.
Summary Tables of Changes R NO.
Summary Tables of Changes R 3. 4. 5. NO. R1 NO. ® ® This erratum applies to Pentium 4 processor supporting Intel Extended Memory 64 Technology (Intel EM64T) for Single-Processor Server/Workstation Platform configurations only. Non-server/workstation desktop configurations do not support the Intel Extended Memory 64 Technology. This erratum does not apply to Pentium 4 processors for single-processor server/workstation platform configurations.
Summary Tables of Changes R 20 Intel® Pentium® 4 Processor on 90 nm Process Specification Update
General Information R General Information Figure 1. Intel® Pentium® 4 Processor on 90 nm Process in the 478-pin Package Brand SSPEC/Country of Assy 2-D Matrix Mark INTEL m c `03 PENTIUM® 4 X.XXGHZ / 1M / 800 SLXXX MALAY BBBBBBBB AAAAAAAA NNNN Copyright Info Product Code FPO ATPO Serial # Figure 2.
General Information R Figure 4. Intel® Pentium® 4 Processor 670, 660, 650, 640, and 630Δ on 90 nm Process in the 775-Land LGA Package Figure 5.
Identification Information R Identification Information The Pentium 4 processor on 90 nm process can be identified by the following values: Family1 Model2 1111b 0011b 1111b 0100b NOTES: 1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan. 2.
Identification Information R Table 1. Intel® Pentium® 4 Processor on 90 nm Process Processor Identification Information S-Spec 24 Core Stepping L2 Cache Size (bytes) CPUID Speed Core/Bus Package and Revision Notes 2, 4, 7 SL7E2 D0 1M 0F34h 2.80GHz/533MHz 35.0 x 35.0 mm FC-mPGA4 Rev 2.0 SL7E3 D0 1M 0F34h 2.80GHz/800MHz 35.0 x 35.0 mm FC-mPGA4 Rev 2.0 2, 4, 7, 11 SL7KA D0 1M 0F34h 2.80GHz/800MHz 35.0 x 35.0 mm FC-mPGA4 Rev 2.0 1, 4, 7, 11 SL7K9 D0 1M 0F34h 2.80GHz/533MHz 35.
Identification Information R Table 1. Intel® Pentium® 4 Processor on 90 nm Process Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) CPUID Speed Core/Bus Package and Revision Notes 4, 8, 11 SL7J7 D0 1M 0F34h 3.20GHz/800MHz 775-land FC-LGA4 37.5 x 37.5 mm Rev 01 SL7KL D0 1M 0F34h 3.20GHz/800MHz 775-land FC-LGA4 37.5 x 37.5 mm Rev 01 1, 4, 8, 11 SL7LA D0 1M 0F34h 3.20GHz/800MHz 775-land FC-LGA4 37.5 x 37.
Identification Information R Table 1. Intel® Pentium® 4 Processor on 90 nm Process Processor Identification Information S-Spec 26 Core Stepping L2 Cache Size (bytes) CPUID Speed Core/Bus Package and Revision Notes 4, 8, 15, 19 SL7PT E0 1M 0F41h 2.66GHz/533MHz 775-land FC-LGA4 37.5 x 37.5 mm Rev 01 SL82V E0 1M 0F41h 2.80GHz/800MHz 775-land FC-LGA4 37.5 x 37.5 mm Rev 01 1, 4, 8, 15 SL7PR E0 1M 0F41h 2.80GHz/800MHz 775-land FC-LGA4 37.5 x 37.
Identification Information R Table 1. Intel® Pentium® 4 Processor on 90 nm Process Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) CPUID Speed Core/Bus Package and Revision Notes 1, 4, 9, 11, 13, 14, 15 SL84X E0 1M 0F41h 3.60GHz/800MHz 775-land FC-LGA4 37.5 x 37.5 mm Rev 01 SL7Q2 E0 1M 0F41h 3.60GHz/800MHz 775-land FC-LGA4 37.5 x 37.5 mm Rev 01 2, 4, 9, 11, 13, 14, 15 SL7NZ E0 1M 0F41h 3.60GHz/800MHz 775-land FC-LGA4 37.5 x 37.
Identification Information R Table 1. Intel® Pentium® 4 Processor on 90 nm Process Processor Identification Information S-Spec 28 Core Stepping L2 Cache Size (bytes) CPUID Speed Core/Bus Package and Revision Notes 4, 8, 12, 13, 14, 15, 19 SL8PN G1 1M 0F49h 3.06GHz/533MHz 775-land FC-LGA4 37.5 x 37.5 mm Rev 01 SL9CA G1 1M 0F49h 3.06GHz/533MHz 775-land FC-LGA4 37.5 x 37.5 mm Rev 01 4, 8, 11, 12, 15, 19 SL8PQ G1 1M 0F49h 3.00GHz/800MHz 775-land FC-LGA4 37.5 x 37.
Identification Information R Table 1. Intel® Pentium® 4 Processor on 90 nm Process Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) CPUID Speed Core/Bus Package and Revision Notes 4, 5, 9, 11, 12, 13, 14, 15, 16, 18 4, 5, 9, 11, 12, 13, 14, 15, 16, 17, 18 SL8PY R0 2M 0F4Ah 3.80GHz/800MHz 775-land FC-LGA4 37.5 x 37.5 mm Rev 01 SL8Q9 R0 2M 0F4Ah 3.80GHz/800MHz 775-land FC-LGA4 37.5 x 37.5 mm Rev 01 NOTES: 1.
Errata R Errata R1. Transaction Is Not Retried after BINIT# Problem: If the first transaction of a locked sequence receives a HITM# and DEFER# during the snoop phase it should be retried and the locked sequence restarted. However, if BINIT# is also asserted during this transaction, it will not be retried. Implication: When this erratum occurs, locked transactions will unexpectedly not be retried. Workaround: None identified. Status: For the steppings affected see the Summary Tables of Changes. R2.
Errata R R4. Memory Type of the Load Lock Different from Its Corresponding Store Unlock Problem: A use-once protocol is employed to ensure that the processor in a multi-agent system may access data that is loaded into its cache on a Read-for-Ownership operation at least once before it is snooped out by another agent. This protocol is necessary to avoid a multi-agent livelock scenario in which the processor cannot gain ownership of a line and modify it before that data is snooped out by another agent.
Errata R • When one-half of a 64-byte instruction fetch from the L2 cache has an uncorrectable error and the other 32-byte half of the same fetch from the L2 cache has a correctable error, the processor will attempt to correct the correctable error but cannot proceed due to the uncorrectable error. When this occurs the processor will hang.
Errata R • The Overflow Error bit (bit 62) in the IA32_MC0_STATUS register indicates, when set, that a machine check error occurred while the results of a previous error were still in the error reporting bank (i.e. The Valid bit was set when the new error occurred). If an uncorrectable error is logged in the error-reporting bank and another error occurs, the overflow bit will not be set.
Errata R R6. Debug Mechanisms May Not Function As Expected Problem: Certain debug mechanisms may not function as expected on the processor.
Errata R R8. EMON Event Counting of x87 Loads May Not Work As Expected Problem: If a performance counter is set to count x87 loads and floating point exceptions are unmasked, the FPU Operand Data Pointer (FDP) may become corrupted. Implication: When this erratum occurs, the FPU Operand Data Pointer (FDP) may become corrupted. Workaround: This erratum will not occur with floating point exceptions masked.
Errata R R11. FSW May Not Be Completely Restored after Page Fault on FRSTOR or FLDENV Instructions Problem: If the FPU operating environment or FPU state (operating environment and register stack) being loaded by an FLDENV or FRSTOR instruction wraps around a 64-KB or 4-GB boundary and a page fault (#PF) or segment limit fault (#GP or #SS) occurs on the instruction near the wrap boundary, the upper byte of the FPU status word (FSW) might not be restored.
Errata R R14. Shutdown and IERR# May Result Due to a Machine Check Exception on a Hyper-Threading Technology1 Enabled Processor Problem: When a Machine Check Exception (MCE) occurs due to an internal error, both logical processors on a Hyper-Threading Technology enabled processor normally vector to the MCE handler. However, if one of the logical processors is in the “Wait-for-SIPI” state, that logical processor will not have an MCE handler and will shut down and assert IERR#.
Errata R R17. A Write to an APIC Registers Sometimes May Appear to Have Not Occurred Problem: With respect to the retirement of instructions, stores to the uncacheable memory-based APIC register space are handled in a non-synchronized way. For example if an instruction that masks the interrupt flag, e.g.
Errata R R20. BPM4# Signal Not Being Asserted According to Specification Problem: BPM4# signal is not being asserted according to the specification. This may cause incorrect operation of In-Target Debuggers, particularly at higher FSB frequencies. Implication: In-Target Debuggers may not function at higher than 133/533 MHz FSB. Workaround: One method is to reduce the FSB common clock frequency to 133 MHz or lower.
Errata R R23. Bus Locks and SMC Detection May Cause the Processor to Hang Temporarily Problem: The processor may temporarily hang in a Hyper-Threading Technology enabled system if one logical processor executes a synchronization loop that includes one or more locks and is waiting for release by the other logical processor.
Errata R R26. Incorrect Debug Exception (#DB) May Occur When a Data Breakpoint Is Set on an FP Instruction Problem: The default Microcode Floating Point Event Handler routine executes a series of loads to obtain data about the FP instruction that is causing the FP event. If a data breakpoint is set on the instruction causing the FP event, the load in the microcode routine will trigger the data breakpoint resulting in a Debug Exception.
Errata R R29. Incorrect Duty Cycle is Chosen when On-Demand Clock Modulation Is Enabled in a Processor Supporting Hyper-Threading Technology Problem: When a processor supporting Hyper-Threading Technology enables On-Demand Clock Modulation on both logical processors, the processor is expected to select the lowest duty cycle of the two potentially different values. When one logical processor enters the AUTOHALT state, the duty cycle implemented should be unaffected by the halted logical processor.
Errata R R32. STPCLK# Signal Assertion under Certain Conditions May Cause a System Hang Problem: The assertion of STPCLK# signal before a logical processor awakens from the "Wait-forSIPI" state for the first time, may cause a system hang.
Errata R R35. Simultaneous Page Faults at Similar Page Offsets on Both Logical Processors of a Hyper-Threading Technology Enabled Processor May Cause Application Failure Problem: An incorrect value of CR2 may be presented to one of the logical processors of an HyperThreading Technology enabled processor if a page access fault is encountered on one logical processor in the same clock cycle that the other logical processor also encounters a page fault.
Errata R R37. Using STPCLK# and Executing Code from Very Slow Memory Could Lead to a System Hang Problem: The system may hang when the following conditions are met: 1. Periodic STPCLK# mechanism is enabled via the chipset 2. Hyper-Threading Technology is enabled 3. 4. One logical processor is waiting for an event (i.e. hardware interrupt) The other logical processor executes code from very slow memory such that every code fetch is deferred long enough for the STPCLK# to be re-asserted.
Errata R R40. CPUID Instruction May Report Incorrect L2 Associativity in Leaf 0x80000006 Problem: L2 associativity reported by CPUID with EAX=80000006H instruction may be incorrect. Implication: Software may see an incorrect L2 associativity when viewed via CPUID with EAX=80000006H, however, when viewed via CPUID with EAX=4H, the associativity value is correct. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. R41.
Errata R R44. Stores to Page Tables May Not Be Visible to Pagewalks for Subsequent Loads without Serializing or Invalidating the Page Table Entry Problem: Under rare timing circumstances, a page table load on behalf of a programmatically younger memory access may not get data from a programmatically older store to the page table entry if there is not a fencing operation or page translation invalidate operation between the store and the younger memory access.
Errata R R48. Read for Ownership and Simultaneous Fetch May Cause the Processor to Hang Problem: The processor may hang when it attempts to fetch from cache line X and line X+1 simultaneously with a Read for Ownership to cache line X. If the fetch to cache line X+1 occur within a small window of time, the processor will detect this as self-modifying code and the Read for Ownership will be infinitely recycled. Implication: If this erratum occurs, the processor may hang.
Errata R R52. Incorrect Access Controls to MSR_LASTBRANCH_0_FROM_LIP MSR Registers Problem: When an access is made to the MSR_LASTBRANCH_0_FROM_LIP MSR register, an expected #GP fault may not happen. Implication: A read of the MSR_LASTBRANCH_0_FROM_LIP MSR register may not cause a #GP fault. Workaround: It is possible for the BIOS to contain a workaround for this erratum Status: For the steppings affected, see the Summary Tables of Changes. R53.
Errata R R56. The Base of a Null Segment May Be Non-zero on a Processor Supporting Intel® Extended Memory 64 Technology (Intel® EM64T) Problem: In IA-32e mode of the Intel EM64T processor, the base of a null segment may be non-zero. Implication: Due to this erratum, Intel EM64T enabled systems may encounter unexpected behavior when accessing memory using the null selector. Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Errata R R59. Loading a Stack Segment with a Selector that References a Non-canonical Address Can Lead to a #SS Fault on a Processor Supporting Intel® Extended Memory 64 Technology (Intel® EM64T) Problem: When a processor supporting Intel EM64T is in IA-32e mode, loading a stack segment with a selector which references a non-canonical address will result in a #SS fault instead of a #GP fault. Implication: When this erratum occurs, Intel EM64T enabled systems may encounter unexpected behavior.
Errata R R62. Enhanced Halt State (C1E) Voltage Transition May Affect a System’s Power Management in a Hyper-Threading Technology Enabled Processor Problem: In an Hyper-Threading Technology enabled system, the second logical Processor may fail to wake up from "Wait-for-SIPI" state during a C1E voltage transition. Implication: This erratum may affect a system’s entry into the power management mode offered by the C1E event for HT Technology enabled platforms.
Errata R R66. The Execute Disable Bit Fault May Be Reported before Other Types of Page Fault When Both Occur Problem: If the Execute Disable Bit is enabled and both the Execute Disable Bit fault and page faults occur, the Execute Disable Bit fault will be reported prior to other types of page fault being reported. Implication: No impact to properly written code since both types of faults will be generated but in the opposite order.
Errata R R70. The IA32_MCi_STATUS MSR May Improperly Indicate that Additional MCA Information May Have Been Captured Problem: When a data parity error is detected and the bus queue is busy, the ADDRV and MISCV bits of the IA32_MCi_STATUS register may be asserted even though the contents of the IA32_MCi_ADDR and IA32_MCi_MISC MSRs were not properly captured.
Errata R R73. MCA Corrected Memory Hierarchy Error Counter May Not Increment Correctly Problem: An MCA corrected memory hierarchy error counter can report a maximum of 255 errors. Due to the incorrect increment of the counter, the number of errors reported may be incorrect. Implication: Due to this erratum, the MCA counter may report incorrect number of soft errors. Workaround: None Identified. Status: For the steppings affected, see the Summary Tables of Changes. R74.
Errata R R76. L-bit of the CS and LMA bit of the IA32_EFER Register May Have an Erroneous Value For One Instruction Following a Mode Transition in a Hyper-Threading Enabled Processor Supporting Intel® Extended Memory 64 Technology (Intel® EM64T) Problem: In an Intel® EM64T enabled Processor, the L-bit of the Code Segment (CS) descriptor may not update with the correct value in an HT environment.
Errata R R78. Control Register 2 (CR2) Can be Updated during a REP MOVS/STOS Instruction with Fast Strings Enabled Problem: Under limited circumstances while executing a REP MOVS/STOS string instruction, with fast strings enabled, it is possible for the value in CR2 to be changed as a result of an interim paging event, normally invisible to the user. Any higher priority architectural event that arrives and is handled while the interim paging event is occurring may see the modified value of CR2.
Errata R R81. An REP MOVS or an REP STOS Instruction with RCX >= 2^32 May Fail to Execute to Completion or May Write to Incorrect Memory Locations on Processors Supporting Intel® Extended Memory 64 Technology (Intel® EM64T) Problem: In IA-32e mode using Intel EM64T-enabled processors, an REP MOVS or an REP STOS instruction executed with the register RCX >= 2^32, may fail to execute to completion or may write data to incorrect memory locations.
Errata R R84. Running in SMM (System Management Mode) And L1 Data Cache Adaptive Mode May Cause Unexpected System Behavior when SMRAM is Mapped to Cacheable Memory Problem: In a Hyper-Threading Technology-enabled system, unexpected system behavior may occur if a change is made to the value of the CR3 result from an RSM (Resume From System Management) instruction while in L1 data cache adaptive mode (IA32_MISC_ENABLES MSR 0x1a0, bit 24).
Errata R R87. FXSAVE Instruction May Result in Incorrect Data on Processors Supporting Intel® Extended Memory 64 Technology (Intel® EM64T) Problem: In IA-32e mode of the Intel EM64T processor, the upper 32 bits of the FDP value written out to memory by the FXSAVE instruction may be incorrect. Implication: This erratum may cause incorrect data to be saved into the memory. Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Errata R R91. A 64-Bit Value of Linear Instruction Pointer (LIP) May be Reported Incorrectly in the Branch Trace Store (BTS) Memory Record or in the Precise Event Based Sampling (PEBS) Memory Record Problem: On a processor supporting Intel® EM64T, • If an instruction fetch wraps around the 4G boundary in Compatibility Mode, the 64-bit value of LIP in the BTS memory record will be incorrect (upper 32 bits will be set to FFFFFFFFh when they should be 0).
Errata R R94. The Processor May Issue Front Side Bus Transactions up to 6 Clocks after RESET# is Asserted Problem: The processor may issue transactions beyond the documented 3 Front Side Bus (FSB) clocks and up to 6 FSB clocks after RESET# is asserted in the case of a warm reset. A warm reset is where the chipset asserts RESET# when the system is running. Implication: The processor may issue transactions up to 6 FSB clocks after the RESET# is asserted Workaround: None identified.
Errata R R97. The Processor May Issue Multiple Code Fetches to the Same Cache Line for Systems with Slow Memory Problem: Systems with long latencies on returning code fetch data from memory e.g. BIOS ROM, may cause the processor to issue multiple fetches to the same cache line, once per each instruction executed. Implication: This erratum may slow down system boot time. Intel has not observed a failure, as a result of this erratum, in a commercially available system.
Errata R R100. VM Exit Due to a MOV from CR8 May Cause an Unexpected Memory Access Problem: In a system supporting Intel® Virtualization Technology and Intel® Extended Memory 64 Technology, if the "CR8-store exiting" bit in the processor-based VM-execution control field is set and the "use TPR shadow" bit is not set, a MOV from CR8 instruction executed by a Virtual Machine Extensions (VMX) guest that causes a VM exit may generate an unexpected memory access.
Errata R R103.
Errata R R105. VM Entry/Exit Writes to LSTAR/SYSCALL_FLAG MSR's May Cause Incorrect Data to be Written to Bits [63:32] Problem: Incorrect MSR data in bits [63:32] may be observed in the following two cases; 1. When ECX contains 0xC0000084 and a VM entry/exit writes the IA32_CR_LSTAR MSR (MSR Address 0xC0000082) bits [63:32] of the data may be zeroed. 2.
Errata R R108. The Execution of a VMPTRLD Instruction May Cause an Unexpected Memory Access Problem: In a system supporting Intel® Virtualization Technology, executing VMPTRLD may cause a memory access to an address not referenced by the memory operand. Implication: This erratum may cause unpredictable system behavior including system hang. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. R109.
Errata R R111. FS/GS Base MSRs can be Loaded from MSR-Load Areas during VM Entry or VM Exit Problem: If the VM Exit or VM Entry MSR load area contains references to the FS or GS Base MSRs, the VM Exit and VM Entry transitions should fail. Instead, the operation will load the MSRs with the value in the corresponding MSR-load area entry. Implication: VM Entries and VM Exits that should fail will complete successfully in this situation.
Errata R R114. Upper 32 bits of ‘From’ Address Reported through LBR or LER MSRs, BTMs or BTSs May be Incorrect Problem: When a far transfer switches the processor from IA-32e mode to 32-bit mode, the upper 32 bits of the ‘From’ (source) addresses reported through the LBR (Last Branch) or LER (Last Exception Record) MSRs (Model-Specific Registers), BTMs (Branch Trace Messages) or BTSs (Branch Trace Stores) may be incorrect.
Errata R R117. VMExit after MOV SS and a Waiting x87 Instruction May not Clear the Interruptibility State in the VMM’s Working VMCS Problem: When Guest software executes a waiting x87 instruction, after an interrupt window which was closed due to blocking by MOVSS, a VM exit may occur due to Interrupt Window exiting = 1 in the Processor-Based VM-Execution Controls of the Controlling VMCS. This causes blocking by MOVSS bit in Interruptibility State to be incorrectly set in the VMM’s Working VMCS.
Errata R R119. Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address Translations Problem: An external A20M# pin if enabled forces address bit 20 to be masked (forced to zero) to emulates real-address mode address wraparound at 1 megabyte.
Errata R R121. The IA32_MC0_STATUS and IA32_MC1_STATUS Overflow Bit is not set when Multiple Un-correctable Machine Check Errors Occur at the Same Time Problem: When two enabled MC0/MC1 un-correctable machine check errors are detected in the same bank in the same internal clock cycle, the highest priority error will be logged in IA32_MC0_STATUS / IA32_MC1_STATUS register, but the overflow bit may not be set.
Specification Changes R Specification Changes The Specification Changes listed in this section apply to the following documents: • Intel® Pentium® 4 Processor 670, 660, 650, 640, and 630Δ and Intel® Pentium® 4 Processor Extreme Edition Datasheet • Intel® Pentium ® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531 and 520/521Δ Supporting Hyper-Threading Technology1 Datasheet All Specification Changes will be incorporated into a future version of the appropriate Pentium 4 processor documentation. R1.
Specification Clarifications R Specification Clarifications The Specification Clarifications listed in this section apply to the following documents: • Intel® Pentium® 4 Processor 670, 660, 650, 640, and 630Δ and Intel® Pentium® 4 Processor Extreme Edition Datasheet • Intel® Pentium® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531 and 520/521Δ Supporting Hyper-Threading Technology1 Datasheet All Specification Clarifications will be incorporated into a future version of the appropriate Pentium 4 pr
Documentation Changes R Documentation Changes The Documentation Changes listed in this section apply to the following documents: • Intel® Pentium® 4 Processor 670, 660, 650, 640, and 630Δ and Intel® Pentium® 4 Processor Extreme Edition Datasheet • Intel® Pentium® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531 and 520/521 Δ Supporting Hyper-Threading Technology1 Datasheet All Documentation Changes will be incorporated into a future version of the appropriate Pentium 4 processor documentation.
