Intel® Pentium® 4 Processor Extreme Edition on 0.
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Contents 1 Introduction....................................................................................................................... 11 1.1 1.2 2 Electrical Specifications.................................................................................................... 15 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 3 Processor Land Assignments.............................................................................. 37 Alphabetical Signals Reference .........................
5.2.4 5.2.5 6 Features ........................................................................................................................... 75 6.1 6.2 7 7.2 7.3 Mechanical Specifications ................................................................................... 80 7.1.1 Boxed Processor Cooling Solution Dimensions ..................................... 80 7.1.2 Boxed Processor Fan Heatsink Weight.................................................. 82 7.1.
Figures 2-1 2-2 3-1 3-2 3-3 3-4 3-5 3-6 4-1 4-2 5-1 6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 Datasheet VCC Static and Transient Tolerance, , , .............................................................. 24 VCC Overshoot Example Waveform.................................................................... 27 Processor Package Assembly Sketch.................................................................29 Processor Package Drawing Sheet 1 of 3...........................................................
Tables 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 3-1 3-2 3-3 4-1 4-2 4-3 5-1 5-2 5-3 6-1 7-1 7-2 6 References.......................................................................................................... 14 Voltage Identification Definition........................................................................... 16 FSB Signal Groups ............................................................................................. 19 BSEL[2:0] FSB Frequency Selections ...........
Revision History Revision No. -001 Description • Initial release Date June 2004 • Added 3.
Datasheet
Intel® Pentium® 4 Processor Extreme Edition on 0.13 Micron Process in the 775-land Package Features Available at 3.40 GHz and 3.
Datasheet
Introduction 1 Introduction The Intel® Pentium® 4 processor Extreme Edition on 0.13 micron process in 775-land package is a follow on to the Intel® Pentium® 4 processor Extreme Edition in the 478-pin package with Intel NetBurst® microarchitecture. The Pentium 4 processor Extreme Edition on 0.13 micron process in 775-land package uses Flip-Chip Land Grid Array (FC-LGA4) package technology, and plugs into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the LGA775 socket.
Introduction The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition. The new packed double-precision floating-point instructions enhance performance for applications that require greater range and precision, including scientific and engineering applications and advanced 3-D geometry techniques, such as ray tracing.
Introduction 1.1.1 Processor Packaging Terminology Commonly used terms are explained here for clarification: • Intel® Pentium® 4 processor Extreme Edition on 0.13 micron process in 775-land package — Processor in the FC-LGA4 package with a 2 MB L3 cache and 512-KB L2 cache. • Processor — For this document, the term processor is the generic form of the Pentium 4 processor Extreme Edition on 0.13 micron process in 775-land package.
Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document: Table 1-1. References Document Doc Number / Location Intel® Pentium® 4 Processor Specification Update http://intel.com/design/ Pentium4/specupdt/ 249199.htm Voltage Regulator-Down (VRD) 10.1 Design Guide for Desktop and Transportable Socket 775 http://intel.com/design/ Pentium4/guides/ 302356.
Electrical Specifications 2 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided. 2.1 FSB and GTLREF0 Most processor FSB signals use Gunning Transceiver Logic (GTL+) signaling technology. Pentium 4 processor Extreme Edition in the 775-land package terminates all on-die terminations to VCC. VTT must be provided via a separate voltage source and not be connected to VCC.
Electrical Specifications 2.3.1 VCC Decoupling Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the large current swings when the part is powering on, or entering/exiting low power states, must be provided by the voltage regulator solution (VR).
Electrical Specifications 2.4.1 Phase Lock Loop (PLL) Power and Filter VCCA and VCCIOPLL are power sources required by the PLL clock generators on the Pentium 4 processor Extreme Edition in the 775-land package. Since these PLLs are analog, they require low noise power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e., maximum frequency). To prevent this degradation, these supplies must be low pass filtered from VCC.
Electrical Specifications The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below. A matched resistor must be used for each group: • • • • • • • • 2.
Electrical Specifications Table 2-2. FSB Signal Groups Signal Group Signals1 Type GTL+ Common Clock Input Synchronous to BCLK[1:0] BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY# GTL+ Common Clock I/O Synchronous to BCLK[1:0] AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#, BR0#, DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, MCERR# Signals Associated Strobe REQ[4:0]#, A[16:3]#2, ADSTB0# GTL+ Source Synchronous I/O A[35:17]#2ADSTB1# Synchronous to assoc.
Electrical Specifications 2.7 GTL+ Asynchronous Signals The Pentium 4 processor Extreme Edition in the 775-land package does not use CMOS voltage levels on any signals that connect to the processor. As a result, legacy input signals such as A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK# use GTL+ input buffers. Legacy output FERR# and other non-AGTL+ signals (THERMTRIP#) use GTL+ output buffers. PROCHOT# uses a GTL+ input/output buffer.
Electrical Specifications 2.10 Absolute Maximum and Minimum Ratings Table 2-4 specifies absolute maximum and minimum ratings. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected.
Electrical Specifications 2.11 Processor DC Specifications The processor DC specifications in this section are defined at the processor core silicon and not at the package lands unless noted otherwise. See Chapter 4 for the signal definitions and signal assignments. Most of the signals on the processor FSB are in the GTL+ signal group. The DC specifications for these signals are listed in Table 2-7.
Electrical Specifications Table 2-6. VCC Static and Transient Tolerance Voltage Deviation from VID Setting (V)1, 2, 3, 4, 5 Icc (A) Maximum Voltage Typical Voltage Minimum Voltage 0A 0.000 V -0.019 V -0.038 V 10 A -0.014 V -0.033 V -0.053 V 20 A -0.028 V -0.048 V -0.067 V 30 A -0.042 V -0.062 V -0.082 V 40 A -0.056 V -0.076 V -0.096 V 50 A -0.070 V -0.090 V -0.111 V 60 A -0.084 V -0.105 V -0.125 V 70 A -0.098 V -0.119 V -0.140 V 80 A -0.112 V -0.133 V -0.
Electrical Specifications Figure 2-1. VCC Static and Transient Tolerance1, 2, 3, 4 0A 0.000 V 20 A 40 A 60 A 80 A 100 A 120 A -0.050 V -0.100 V -0.150 V -0.200 V -0.250 V Vccmax Vcctyp Vccmin NOTES: 1. 2. 3. 4. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.12. This loadline specification shows the deviation from the VID set point.
Electrical Specifications Table 2-8. Asynchronous GTL+ Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 2,3,4 VIH Input High Voltage, Asynch GTL+ 1.10*GTLREF0 VCC V VIL Input Low Voltage, Asynch. GTL+ 0 0.9*GTLREF0 V 4 VOH Output High Voltage N/A VCC V 2,3,5 IOL Output Low Current N/A 50 mA 6 IHI Land Leakage High N/A 100 µA 7 ILO Land Leakage Low N/A 500 µA 8 RON Buffer On Resistance, Asynch GTL+ 8.4 13.2 Ω 4 NOTES: 1.
Electrical Specifications Table 2-10. VTTPWRGD DC Specifications Symbol Parameter Min Typ Max Unit VIL Input Low Voltage — — 0.3 V VIH Input High Voltage 0.9 — — V Notes1 NOTES: 1. VTTPWRGD is not a feature of the Pentium 4 processor Extreme Edition in the 775-land package. This pin is used by compatible processors. This pin is required for compatibility with Voltage Regulator Down (VRD) 10.1 Design Guide standards. Table 2-11.
Electrical Specifications Figure 2-2. VCC Overshoot Example Waveform Example Overshoot Waveform Voltage (V) VID + 0.050 VOS VID TOS Time TOS: Overshoot time above VID VOS: Overshoot above VID NOTES: 1. VOS is measured overshoot voltage. 2. TOS is measured time duration above VID. 2.12.1 Die Voltage Validation Overshoot events from application testing on real processors must meet the specifications in Table 2-12 when measured across the VCC_SENSE and VSS_SENSE lands.
Electrical Specifications Table 2-13. GTL+ Bus Voltage Definitions Symbol Parameter Min Typ Max Units Notes1 GTLREF0 Bus Reference Voltage (0.0986VCC+ 0.6106VTT) – 10.21% (0.0986VCC +0.6106VTT) (0.0986VCC+ 0.6106VTT) + 4.6% V RTT Termination Resistance 54 60 66 Ω 6 COMP[1:0] COMP Resistance 59.8 60.4 61 Ω 7 2,3,4,5 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and voltages. 2.
Package Mechanical Specifications 3 Package Mechanical Specifications The Pentium 4 processor Extreme Edition in the 775-land package is packaged in a Flip-Chip Land Grid Array (FC-LGA4) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications Note: Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor thermal/mechanical design guidelines. Figure 3-2.
Package Mechanical Specifications Figure 3-3.
Package Mechanical Specifications Figure 3-4. Processor Package Drawing Sheet 3 of 3 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep-out zone requirements. A thermal and mechanical solution design must not intrude into the required keepout zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 3-4 for keep-out zones.
Package Mechanical Specifications 3.3 Package Loading Specifications Table 3-1 provides dynamic and static load specifications for the processor package. These mechanical maximum load limits should not be exceeded during heatsink assembly, shipping conditions, or standard use condition. Also, any mechanical system or component testing should not exceed the maximum limits.
Package Mechanical Specifications 3.6 Processor Mass Specification The typical mass of the Pentium 4 processor Extreme Edition in the 775-land package is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package. 3.7 Processor Materials Table 3-3 lists some of the package components and associated materials. Table 3-3. Processor Materials 3.
Package Mechanical Specifications 3.9 Processor Land Coordinates Figure 3-6 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. . Figure 3-6.
Package Mechanical Specifications 36 Datasheet
Land Listing and Signal Descriptions 4 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for the Pentium 4 processor Extreme Edition in the 775-land package. The landout footprint is shown in Figure 4-1 and Figure 4-2. These figures represent the landout arranged by land number and they show the physical location of each signal on the package land array (top view).
Land Listing and Signal Descriptions Figure 4-1.
Land Listing and Signal Descriptions Figure 4-2.
Land Listing and Signal Descriptions Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name Datasheet Land # Signal Buffer Type Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name 42 Land # HITM# E4 IERR# AB2 IGNNE# N2 INIT# P3 ITP_CLK0 AK3 ITP_CLK1 AJ3 LINT0 K1 LINT1 L1 Signal Buffer Type Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Datasheet Land Name Land # Signal Buffer Type VCC AC26 VCC AC27 VCC VCC Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments 44 Land Name Land # Signal Buffer Type VCC AK12 VCC AK14 VCC VCC Table 4-1.
Land Listing and Signal Descriptions Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments 46 Land Name Land # Signal Buffer Type VSS AA24 VSS AA25 VSS VSS Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Datasheet Land Name Land # Signal Buffer Type VSS AJ23 VSS AJ24 VSS VSS Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name 48 Land # Signal Buffer Type Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Datasheet Land Name Land # Signal Buffer Type VSS R30 VSS R5 VSS VSS Table 4-1.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # 50 Land Name Signal Buffer Type Direction Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # Datasheet Land Name Signal Buffer Type Direction Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # 52 Land Name Signal Buffer Type Direction Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # Datasheet Land Name Signal Buffer Type Direction Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # 54 Land Name Signal Buffer Type Direction Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # Datasheet Land Name Signal Buffer Type Direction Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # 56 Land Name Signal Buffer Type Direction Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # Datasheet Land Name Signal Buffer Type Direction Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # 58 Land Name Signal Buffer Type Direction Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # Datasheet Land Name Signal Buffer Type Direction Table 4-2.
Land Listing and Signal Descriptions 4.2 Alphabetical Signals Reference Table 4-3. Signal Description (Sheet 1 of 9) Name Type Description 236-byte A[35:3]# Input/ Output A[35:3]# (Address) define a physical memory address space. In subphase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 1 of 9) Name Type Description BINIT# (Bus Initialization) may be observed and driven by all processor FSB agents and if used, must connect the appropriate pins/lands of all such agents. If the BINIT# driver is enabled during power-on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 1 of 9) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins/ lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will, thus, be driven four times in a common clock period.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 1 of 9) Name DRDY# Type Description Input/ Output DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be de-asserted to insert idle clocks. This signal must connect the appropriate pins/lands of all processor FSB agents. DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 1 of 9) Name IERR# Type Output Description IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 1 of 9) Name Type Description MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor FSB agents. MCERR# assertion conditions are configurable at a system level. Assertion options are defined by the following options: • Enabled or disabled. MCERR# Input/ Output • Asserted, if configured, for internal errors along with IERR#.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 1 of 9) Name SKTOCC# SLP# SMI# Type Description Output SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System board designers may use this signal to determine if the processor is present. Input SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 1 of 9) Name Type Description TRST# Input TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. Contact your Intel representative for complete implementation details. VCC Input VCC are the power pins for the processor. The voltage supplied to these pins is determined by the VID[5:0] pins. VCCA provides isolated power for the internal processor core PLLs.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 1 of 9) Name Type Description The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to provide a voltage supply for some signals that require termination to VTT on the motherboard. Contact your Intel representative for further details and documentation. For future processor compatibility some signals are required to be pulled up to VTT_OUT_LEFT or VTT_OUT_RIGHT.
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The Pentium 4 processor Extreme Edition in the 775-land package requires a thermal solution to maintain temperatures within operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
Thermal Specifications and Design Considerations Table 5-1. Processor Thermal Specifications Core Frequency (GHz) Thermal Design Power (W) Minimum TC (°C) Maximum TC (°C) Notes 3.40 109.6 5 66 1, 2 3.46 110.7 5 66 1, 2 NOTES: 1. These values are specified at Vcc_max for the processor. Systems must be designed to ensure that the processor is not subjected to any static VCC and ICC combination wherein VCC exceeds Vcc_max at specified ICC. Refer to loadline specification in Chapter 2. 2.
Thermal Specifications and Design Considerations 5.2 Processor Thermal Features 5.2.1 Thermal Monitor The Thermal Monitor feature helps control the processor temperature by activating the TCC when the processor silicon reaches its maximum operating temperature. The TCC reduces processor power consumption as needed by modulating (starting and stopping) the internal processor core clocks. The Thermal Monitor feature must be enabled for the processor to be operating within specifications.
Thermal Specifications and Design Considerations programmable via bits 3:1 of the same ACPI P_CNT Control Register. In On-Demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-Demand mode may be used in conjunction with the Thermal Monitor. If the system tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the On-Demand mode. 5.2.
Thermal Specifications and Design Considerations 5.2.5 Thermal Diode The processor incorporates an on-die thermal diode. A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management/long term die temperature change purposes. Table 5-2 and Table 5-3 provide the diode parameter and interface specifications. This thermal diode is separate from the Thermal Monitor’s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor.
Thermal Specifications and Design Considerations 74 Datasheet
Features 6 Features This chapter contains power-on configuration options and clock control/low power state descriptions. 6.1 Power-On Configuration Options Several configuration options can be configured by hardware. The Pentium 4 processor Extreme Edition in the 775-land package samples the hardware configuration at reset, on the active-toinactive transition of RESET#. For specifications on these options, refer to Table 6-1. The sampled information configures the processor for subsequent operation.
Features 6.2.2 AutoHALT Powerdown State—State 2 AutoHALT is a low power state entered when the processor executes the HALT instruction. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the AutoHALT Power Down state.
Features A transition to the HALT/Grant Snoop state occurs when the processor detects a snoop on the FSB (see Section 6.2.4). A transition to the Sleep state (see Section 6.2.5) occurs with the assertion of the SLP# signal. While in the Stop-Grant State, SMI#, INIT#, BINIT# and LINT[1:0] are latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state.
Features 78 Datasheet
Boxed Processor Specifications 7 Boxed Processor Specifications The Pentium 4 processor Extreme Edition in the 775-land package will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed Pentium 4 processor Extreme Edition in the 775-land package will be supplied with a cooling solution.
Boxed Processor Specifications 7.1 Mechanical Specifications 7.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed Pentium 4 processor Extreme Edition in the 775- land package fan heatsink. The boxed processor will be shipped with an unattached fan heatsink. Figure 7-2 shows a mechanical representation of the boxed Pentium 4 processor Extreme Edition in the 775-land package.
Boxed Processor Specifications Figure 7-3. Space Requirements for the Boxed Processor (Top View) 3.74 [95.0] 3.74 [95.0] NOTES: 1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. Figure 7-4.
Boxed Processor Specifications 7.1.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 450 grams. Refer to Chapter 5 and the Intel® Pentium® 4 Processor Extreme Edition on 0.13 Micron Process in the 775-land package Thermal Design Guide for details on the processor weight and heatsink requirements. 7.1.
Boxed Processor Specifications Figure 7-5. Boxed Processor Fan Heatsink Power Cable Connector Description Pin 1 2 3 4 Signal GND +12 V SENSE CONTROL Straight square pin, 4-pin terminal housing with polarizing ribs and friction locking ramp. 0.100" pitch, 0.025" square pin width. Match with straight pin, friction lock header on mainboard. 1 2 3 4 Table 7-1. Fan Heatsink Power and Signal Specifications Description Min Typ Max Unit Notes +12 V: 12 volt fan power supply 10.2 12 13.
Boxed Processor Specifications Figure 7-6. Baseboard Power Header Placement Relative to Processor Socket B R4.33 [110] C 7.3 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. 7.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink.
Boxed Processor Specifications Figure 7-7. Boxed Processor Fan Heatsink Airspace Keep-out Requirements (Top View) Figure 7-8.
Boxed Processor Specifications 7.3.2 Variable Speed Fan The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low. If internal chassis temperature increases beyond a lower set point, the fan speed will rise linearly with the internal temperature until the higher set point is reached. At that point, the fan speed is at its maximum.
Boxed Processor Specifications Table 7-2. Boxed Processor Fan Heatsink Set Points Boxed Processor Fan Heatsink Set Point (ºC) Boxed Processor Fan Speed Notes X ≤ 30 When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. Recommended maximum internal chassis temperature for nominal operating environment. 1 Y = 34 When the internal chassis temperature is at this point, the fan operates between its lowest and highest speeds.
Boxed Processor Specifications 88 Datasheet
Debug Tools Specifications 8 Debug Tools Specifications Refer to the ITP700 Debug Port Design Guide for information regarding debug tools specifications. The ITP700 Debug Port Design Guide is located on http://developer.intel.com. 8.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Pentium 4 processor Extreme Edition in the 775-land package systems.
Debug Tools Specifications 90 Datasheet
