Intel® Pentium® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531 and 520/521∆ Supporting Hyper-Threading Technology1 Datasheet On 90 nm Process in 775-land LGA Package and supporting Intel® Extended Memory 64 TechnologyΦ May 2005 Document Number: 302351-004
Contents INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
Contents Contents 1 Introduction.................................................................................................................................... 11 1.1 1.2 2 Electrical Specifications ................................................................................................................. 15 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 3 Package Mechanical Drawing ............................................................................................
Contents 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 6 Features ........................................................................................................................................ 85 6.1 6.2 7 Power-On Configuration Options........................................................................................ 85 Clock Control and Low Power States ................................................................................. 85 6.2.1 Normal State................................................
Contents Figures 2-1 2-2 2-3 2-4 3-1 3-2 3-3 3-4 3-5 3-6 3-7 4-1 4-2 5-1 5-2 5-3 5-4 6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 Phase Lock Loop (PLL) Filter Requirements.............................................................................. 19 VCC Static and Transient Tolerance for 775_VR_CONFIG_04A............................................... 28 VCC Static and Transient Tolerance for 775_VR_CONFIG_04B............................................... 30 VCC Overshoot Example Waveform .................
Contents Tables 1-1 References ................................................................................................................................. 13 2-1 Core Frequency to FSB Multiplier Configuration ........................................................................ 16 2-2 Voltage Identification Definition .................................................................................................. 18 2-3 FSB Signal Groups...........................................................
Contents Revision History Revision No. -001 Description • Initial release Date of Release June 2004 • Added specifications for processor number 550 with PRB = 0 -002 • Added support for Execute Disable Bit capability • Added Icc Enhanced Auto Halt specifications September 2004 • Added support for Thermal Monitor 2 -003 • Added specifications for processor number 570 with PRB = 1 November 2004 • Added specifications for processor numbers 571, 561, 551, 541, 531, and 521.
Contents 8 Datasheet
Contents Intel® Pentium® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531, and 520/521 • Available at 3.80 GHz, 3.60 GHz, 3.40 GHz, • 16-KB Level 1 data cache • 1-MB Advanced Transfer Cache (on-die, full- 3.20 GHz, 3 GHz, and 2.
Contents 10 Datasheet
Introduction 1 Introduction The Intel® Pentium® 4 processor on 90 nm process in the 775-land package is a follow on to the Pentium 4 processor in the 478-pin package with enhancements to the Intel NetBurst® microarchitecture. The Pentium 4 processor on 90 nm process in the 775-land package uses FlipChip Land Grid Array (FC-LGA4) package technology, and plugs into a 775LGA socket.
Introduction The Pentium 4 processor on 90 nm process in the LGA775-land package will also include the Execute Disable Bit capability previously available in Intel® Itanium® processors. This feature combined with a support operating system allows memory to be marked as executable or nonexecutable. If code attempts to run in non-executable memory the processor raises an error to the operating system.
Introduction • Retention mechanism (RM)—Since the LGA775 socket does not include any mechanical features for heatsink attach, a retention mechanism is required. Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket. • Storage conditions—Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air.
Introduction 14 Datasheet
Electrical Specifications 2 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided. 2.1 FSB and GTLREF Most processor FSB signals use Gunning Transceiver Logic (GTL+) signaling technology. Platforms implement a termination voltage level for GTL+ signals defined as VTT. VTT must be provided via a separate voltage source and not be connected to VCC.
Electrical Specifications 2.3.1 VCC Decoupling Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the large current swings when the part is powering on, or entering/exiting low power states, must be provided by the voltage regulator solution (VR). For more details on this topic, refer to the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket. 2.
Electrical Specifications 2.4 Voltage Identification The VID specification for the Pentium 4 processor in the 775-land package is supported by the Voltage Regulator Down (VRD) 10.1 Design Guide For Desktop LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor VCC pins. A minimum voltage is provided in Table 2-8 and changes with frequency. This allows processors running at a higher frequency to have a relaxed minimum voltage specification.
Electrical Specifications Table 2-2. Voltage Identification Definition VID5 VID4 VID3 VID2 VID1 VID0 VID VID5 VID4 VID3 VID2 VID1 VID0 VID 0 0 1 0 1 0 0.8375 0 1 1 0 1 0 1.2125 1 0 1 0 0 1 0.8500 1 1 1 0 0 1 1.2250 0 0 1 0 0 1 0.8625 0 1 1 0 0 1 1.2375 1 0 1 0 0 0 0.8750 1 1 1 0 0 0 1.2500 0 0 1 0 0 0 0.8875 0 1 1 0 0 0 1.2625 1 0 0 1 1 1 0.9000 1 1 0 1 1 1 1.2750 0 0 0 1 1 1 0.
Electrical Specifications 2.4.1 Phase Lock Loop (PLL) Power and Filter VCCA and VCCIOPLL are power sources required by the PLL clock generators for the Pentium 4 processor in the 775-land package. Since these PLLs are analog, they require low noise power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core timings (i.e., maximum frequency). To prevent this degradation, these supplies must be low pass filtered from VTT.
Electrical Specifications 2.5 Reserved, Unused, FC and TESTHI Signals All RESERVED signals must remain unconnected. Connection of these signals to VCC, VSS, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED signals. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level.
Electrical Specifications 2.6 FSB Signal Groups The FSB signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term "GTL+ Input" refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, "GTL+ Output" refers to the GTL+ output group as well as the GTL+ I/O group when driving.
Electrical Specifications NOTES: 1. Refer to Section 4.2 for signal descriptions. 2. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects. 3. The value of these signals during the active-to-inactive edge of RESET# defines the processor configuration options. See Section 6.1 for details. Table 2-4.
Electrical Specifications 2.8 Test Access Port (TAP) Connection Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the Pentium 4 processor in the 775-land package be first in the TAP chain and followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage level.
Electrical Specifications 2.10 Absolute Maximum and Minimum Ratings Table 2-7 specifies absolute maximum and minimum ratings. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected.
Electrical Specifications Table 2-8. Voltage and Current Specifications (Sheet 1 of 2) Symbol VID range Parameter VID Processor Number Min Typ Max Unit Notes1 1.200 — 1.425 V 2 Refer to Table 2-10 and Figure 2-3 V 3, 4, 5, 6 Refer to Table 2-9 and Figure 2-2 V 3, 4, 6, 7, 8 A 9 A 10, 11, 15 A 11, 15 Core Frequency VCC for 775_VR_CONFIG_04B processors VCC 570/571 3.80 GHZ (PRB = 1) 560/561 3.60 GHz (PRB = 1) 550 3.
Electrical Specifications Table 2-8. Voltage and Current Specifications (Sheet 2 of 2) Symbol Parameter Min Typ Max Unit Notes1 ICC_VCCA ICC FOR PLL LANDS — — 120 mA 15 ICC_VCCIOPLL ICC FOR I/O PLL LAND — — 100 mA 15 ICC_GTLREF ICC for GTLREF — — 200 µA 15 NOTES: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 26 Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data.
Electrical Specifications Table 2-9. VCC Static and Transient Tolerance for 775_VR_CONFIG_04A Processors Voltage Deviation from VID Setting (V)1, 2, 3, 4 ICC (A) Maximum Voltage 1.70 mΩ Typical Voltage 1.75 mΩ Minimum Voltage 1.80 mΩ 0 0.000 -0.025 -0.050 5 -0.009 -0.034 -0.059 10 -0.017 -0.043 -0.068 15 -0.026 -0.051 -0.077 20 -0.034 -0.060 -0.086 25 -0.043 -0.069 -0.095 30 -0.051 -0.078 -0.104 35 -0.060 -0.086 -0.113 40 -0.068 -0.095 -0.122 45 -0.077 -0.104 -0.
Electrical Specifications Figure 2-2. VCC Static and Transient Tolerance for 775_VR_CONFIG_04A Icc [A] 0 10 20 30 40 50 60 70 VID - 0.000 VID - 0.025 Vcc Maximum VID - 0.050 Vcc [V] VID - 0.075 VID - 0.100 Vcc Typical VID - 0.125 Vcc Minimum VID - 0.150 VID - 0.175 VID - 0.200 NOTES: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.12. 2. This loadline specification shows the deviation from the VID set point. 3.
Electrical Specifications Table 2-10. VCC Static and Transient Tolerance for 775_VR_CONFIG_04B Processors Voltage Deviation from VID Setting (V)1, 2, 3, 4 ICC (A) Maximum Voltage 1.30 mΩ Typical Voltage 1.35 mΩ Minimum Voltage 1.40 mΩ 0 0.000 -0.019 -0.038 5 -0.007 -0.026 -0.045 10 -0.013 -0.033 -0.052 15 -0.020 -0.039 -0.059 20 -0.026 -0.046 -0.066 25 -0.033 -0.053 -0.073 30 -0.039 -0.060 -0.080 35 -0.046 -0.066 -0.087 40 -0.052 -0.073 -0.094 45 -0.059 -0.080 -0.
Electrical Specifications Figure 2-3. VCC Static and Transient Tolerance for 775_VR_CONFIG_04B Icc [A] 0 10 20 30 40 50 60 70 80 90 100 110 120 VID - 0.000 VID - 0.019 VID - 0.038 Vcc Maximum VID - 0.057 VID - 0.076 Vcc [V] VID - 0.095 Vcc Typical VID - 0.114 VID - 0.133 Vcc Minimum VID - 0.152 VID - 0.171 VID - 0.190 VID - 0.209 VID - 0.228 NOTES: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.12. 2.
Electrical Specifications Table 2-11. GTL+ Asynchronous Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 VIL Input Low Voltage 0.0 VTT/2 – (0.10 * VTT) V 2, 3 VIH Input High Voltage VTT/2 + (0.10 * VTT) VTT V 3, 4, 5, 6 VOH Output High Voltage 0.90*VTT VTT V 5, 6, 7 IOL Output Low Current — VTT/[(0.
Electrical Specifications Table 2-13. PWRGOOD and TAP Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1, VHYS Input Hysteresis 200 350 mV 3 VT+ Input low to high threshold voltage 0.5 * (VTT + VHYS_MIN) 0.5 * (VTT + VHYS_MAX) V 4 VT- Input high to low threshold voltage 0.5 * (VTT – VHYS_MAX) 0.
Electrical Specifications 2.12 VCC Overshoot Specification The Pentium 4 processor in the 775-land package can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high to low current load condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot voltage). The time duration of the overshoot event must not exceed TOS_MAX (TOS_MAX is the maximum allowable time duration above VID).
Electrical Specifications 2.13 GTL+ FSB Specifications Termination resistors are not required for most GTL+ signals, as these are integrated into the processor silicon.Valid high and low levels are determined by the input buffers which compare a signal’s voltage with a reference voltage called GTLREF. Table 2-18 lists the GTLREF specifications. The GTL+ reference voltage (GTLREF) should be generated on the system board using high precision voltage divider circuits. Table 2-18.
Package Mechanical Specifications 3 Package Mechanical Specifications The Pentium 4 processor in the 775-land package is packaged in a Flip-Chip Land Grid Array (FC-LGA4) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications Figure 3-2.
Package Mechanical Specifications Figure 3-3.
Package Mechanical Specifications Figure 3-4.
Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep-out zone requirements. A thermal and mechanical solution design must not intrude into the required keepout zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 3-2 and Figure 3-3 for keep-out zones.
Package Mechanical Specifications 3.5 Package Insertion Specifications The Pentium 4 processor in the 775-land package can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide. 3.6 Processor Mass Specification The typical mass of the Pentium 4 processor in the 775-land package is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package. 3.
Package Mechanical Specifications Figure 3-6. Processor Top-Side Marking Example for Processors Supporting Intel® EM64T ProcessorNumber/S-Spec/ CountryofAssy Frequency/L2Cache/Bus/ 775_VR_CONFIG_04x FPO INTEL m © ‘04 Pentium ® 4 571 SLxxx [COO] 3.80GHZ/1M/800/04B [FPO] UniqueUnit Identifier ATPO Serial # 2-D MatrixMark ATPO S/N 3.9 Processor Land Coordinates Figure 3-7 shows the top view of the processor land coordinates.
Package Mechanical Specifications . Figure 3-7.
Land Listing and Signal Descriptions 4 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for the Pentium 4 processor in the 775-land package. The landout footprint is shown in Figure 4-1 and Figure 4-2. These figures represent the landout arranged by land number and they show the physical location of each signal on the package land array (top view).
Land Listing and Signal Descriptions Figure 4-1.
Land Listing and Signal Descriptions Figure 4-2.
Land Listing and Signal Descriptions Table 4-1.
Land Listing and Signal Descriptions Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments 48 Land Name Land # ITP_CLK1 LINT0 Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Datasheet Land Name Land # Signal Buffer Type VCC AC26 VCC AC27 VCC VCC Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments 50 Land Name Land # Signal Buffer Type VCC AK12 VCC AK14 VCC VCC Table 4-1.
Land Listing and Signal Descriptions Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments 52 Land Name Land # Signal Buffer Type VSS AA24 VSS AA25 VSS VSS Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Datasheet Land Name Land # Signal Buffer Type VSS AJ23 VSS AJ24 VSS VSS Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Land Name 54 Land # Signal Buffer Type Table 4-1.
Land Listing and Signal Descriptions Table 4-1. Alphabetical Land Assignments Datasheet Land Name Land # Signal Buffer Type VSS R30 VSS R5 VSS VSS Table 4-1.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # 56 Land Name Signal Buffer Type Direction Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Datasheet Land # Land Name Signal Buffer Type C24 VSS C25 VTT C26 C27 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Land # 58 Land Name Signal Buffer Type Direction Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Datasheet Land # Land Name Signal Buffer Type J13 VCC J14 VCC Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment 60 Land # Land Name P1 P2 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Datasheet Land # Land Name W3 W4 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment 62 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Datasheet Land # Land Name Signal Buffer Type AG12 VCC AG13 VSS AG14 AG15 Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment 64 Land # Land Name AK4 AK5 AK6 RESERVED AK7 VSS Power/Other AK8 VCC AK9 VCC Table 4-2.
Land Listing and Signal Descriptions Table 4-2. Numerical Land Assignment Datasheet Land # Land Name Signal Buffer Type AM27 VSS AM28 VSS AM29 AM30 Table 4-2.
Land Listing and Signal Descriptions 4.2 Alphabetical Signals Reference Table 4-3. Signal Description (Sheet 1 of 8) Name A[35:3]# Type Input/ Output Description A[35:3]# (Address) define a 236-byte physical memory address space. In subphase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 2 of 8) Name Type Description BINIT# (Bus Initialization) may be observed and driven by all processor FSB agents and if used, must connect the appropriate pins/lands of all such agents. If the BINIT# driver is enabled during power-on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 3 of 8) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins/ lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will, thus, be driven four times in a common clock period.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 4 of 8) Name DRDY# Type Description Input/ Output DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be de-asserted to insert idle clocks. This signal must connect the appropriate pins/lands of all processor FSB agents. DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 5 of 8) Name IGNNE# Type Description Input IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is de-asserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 6 of 8) Name PROCHOT# PWRGOOD REQ[4:0]# RESET# Type Input/ Output Description As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 7 of 8) Name Type Description STPCLK# Input STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state.
Land Listing and Signal Descriptions Table 4-3. Signal Description (Sheet 8 of 8) Name VID[5:0] Type Description Output VID[5:0] (Voltage ID) signals are used to support automatic selection of power supply voltages (VCC). These are open drain signals that are driven by the processor and must be pulled up on the motherboard. Refer to the Voltage Regulator-Down (VRD) 10.1 Design Guide for Desktop Socket 775 for more information.
Land Listing and Signal Descriptions 74 Datasheet
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The Pentium 4 processor in the 775-land package requires a thermal solution to maintain temperatures within operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
Thermal Specifications and Design Considerations The case temperature is defined at the geometric top center of the processor IHS. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained periods of time. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 5-1 instead of the maximum processor power consumption.
Thermal Specifications and Design Considerations Table 5-2. Thermal Profile for Processors with PRB = 1 Power (W) Maximum TC (°C) Power (W) Maximum TC (°C) Power (W) Maximum TC (°C) Power (W) Maximum TC (°C) 0 44.0 30 51.5 60 59.0 90 66.5 2 44.5 32 52.0 62 59.5 92 67.0 4 45.0 34 52.5 64 60.0 94 67.5 6 45.5 36 53.0 66 60.5 96 68.0 8 46.0 38 53.5 68 61.0 98 68.5 10 46.5 40 54.0 70 61.5 100 69.0 12 47.0 42 54.5 72 62.0 102 69.5 14 47.5 44 55.
Thermal Specifications and Design Considerations Table 5-3. Thermal Profile for Processors with PRB = 0 Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 44.2 30 52.6 60 61.0 2 44.8 32 53.2 62 61.6 4 45.3 34 53.7 64 62.1 6 45.9 36 54.3 66 62.7 8 46.4 38 54.8 68 63.2 10 47.0 40 55.4 70 63.8 12 47.6 42 56.0 72 64.4 14 48.1 44 56.5 74 64.9 16 48.7 46 57.1 76 65.5 18 49.2 48 57.6 78 66.0 20 49.8 50 58.2 80 66.
Thermal Specifications and Design Considerations 5.1.2 Thermal Metrology The maximum and minimum case temperatures (TC) are specified in Table 5-1. These temperature specifications are meant to help ensure proper operation of the processor. Figure 5-3 illustrates where Intel recommends TC thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the Intel® Pentium® 4 Processor on 90 nm Process in the 775-Land Package Thermal Design Guidelines.
Thermal Specifications and Design Considerations With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable.
Thermal Specifications and Design Considerations Figure 5-4. Thermal Monitor 2 Frequency and Voltage Ordering TTM2 fMAX fTM2 Temperature Frequency VID VIDTM2 VID PROCHOT# Time The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled. It should be noted that the Thermal Monitor 2 TCC can not be activated via the on demand mode.
Thermal Specifications and Design Considerations 5.2.4 PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or de-assertion of PROCHOT#.
Thermal Specifications and Design Considerations 5.2.7 Thermal Diode The processor incorporates an on-die thermal diode. A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management/long term die temperature change purposes. Table 5-4 and Table 5-5 provide the diode parameter and interface specifications. This thermal diode is separate from the Thermal Monitor’s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor.
Thermal Specifications and Design Considerations 84 Datasheet
Features 6 Features 6.1 Power-On Configuration Options Several configuration options can be configured by hardware. The Pentium 4 processor in the 775land package samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 6-1. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features 6.2.1 Normal State This is the normal operating state for the processor. 6.2.2 HALT and Enhanced HALT Powerdown States The Prescott processor supports the HALT or Enhanced HALT powerdown state. The Enhanced HALT powerdown state is configured and enabled via the BIOS. The Enhanced HALT state is a lower power state as compared to the Stop Grant State. If Enhanced HALT is not enabled, the default powerdown state entered will be HALT.
Features Figure 6-1.
Features 6.2.4 Enhanced HALT Snoop or HALT Snoop State, Grant Snoop State The Enhanced HALT Snoop State is used in conjunction with the new Enhanced HALT state. If Enhanced HALT state is not enabled in the BIOS, the default Snoop State entered will be the HALT Snoop State. Refer to the sections below for details on HALT Snoop State, Grant Snoop State and Enhanced HALT Snoop State. 6.2.4.
Boxed Processor Specifications 7 Boxed Processor Specifications The Pentium 4 processor on 90 nm process in the 775-land package will also be offered as a boxed Intel processor. Boxed Intel processors are intended for system integrators who build systems from baseboards and standard components. The boxed Pentium 4 processor in the 775-land package will be supplied with a cooling solution.
Boxed Processor Specifications 7.1 Mechanical Specifications 7.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed Pentium 4 processor on 90 nm process in the 775-land package. The boxed processor will be shipped with an unattached fan heatsink. Figure 7-1 shows a mechanical representation of the boxed Pentium 4 processor in the 775-land package. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.
Boxed Processor Specifications Figure 7-4. Space Requirements for the Boxed Processor (Overall View) 7.1.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5 and the Intel® Pentium® 4 Processor on 90 nm Process in the 775-Land Package Thermal Design Guidelines for details on the processor weight and heatsink requirements. 7.1.
Boxed Processor Specifications The fan heatsink outputs a SENSE signal that is an open-collector output that pulses at a rate of 2 pulses per fan revolution. A baseboard pull-up resistor provides VOH to match the system boardmounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND. The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the connector labeled as CONTROL.
Boxed Processor Specifications Figure 7-6. Baseboard Power Header Placement Relative to Processor Socket B R4.33 [110] C 7.3 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. 7.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink.
Boxed Processor Specifications Figure 7-7. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Top View) Figure 7-8.
Boxed Processor Specifications 7.3.2 Variable Speed Fan If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header it will operate as follows: The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low.
Boxed Processor Specifications Table 7-2. Fan Heatsink Power and Signal Specifications Boxed Processor Fan Heatsink Set Point (ºC) Boxed Processor Fan Speed Notes X ≤ 30 When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. Recommended maximum internal chassis temperature for nominal operating environment. 1 Y = 34 When the internal chassis temperature is at this point, the fan operates between its lowest and highest speeds.
