Technical Product Specification

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Intel

Server Board S1600JP

Intel order number G68018-010

Revision 1.9

April 2014

Summary of content (245 pages)

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Intel® Server Board S1600JP Technical Product Specification Intel order number G68018-010 Revision 1.
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Revision History Intel® Server Board S1600JP TPS Revision History Date Modifications May 2012 0.5 Initial release. June 2012 0.6   Updated Memory Support Guidelines. Updated Processor Information. July 2012 1.0          Updated All Block Diagrams. October 2012 January 2013 ii Revision Number 1.1 1.2 Updated Risers Information. Updated BIOS Setup Interface. Updated Connector and Header Location and Pin-out. Updated Power Supply Specific Guidelines. Updated BIOS Setup Interface.
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Intel® Server Board S1600JP TPS Disclaimers Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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Table of Contents Intel® Server Board S1600JP TPS Table of Contents 1. Introduction ........................................................................................................................1 1.1 Section Outline .......................................................................................................1 1.2 Server Board Use Disclaimer .................................................................................2 2. Server Board Overview .......................................
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Intel® Server Board S1600JP TPS Table of Contents 4.1 4.1.1 4.1.2 4.1.3 4.2 4.3 4.4 4.5 4.6 4.6.1 4.6.2 4.6.3 4.6.4 4.6.5 4.7 4.7.1 4.7.2 4.7.3 4.7.4 4.8 4.9 4.10 4.11 4.12 4.12.1 4.12.2 4.12.3 4.12.4 4.12.5 4.12.6 4.12.7 4.13 4.13.1 4.13.2 4.14 4.14.1 4.14.2 4.14.3 4.14.4 4.14.5 4.14.6 Baseboard Management Controller (BMC) Firmware Feature Support................. 35 IPMI 2.0 Features.................................................................................................35 Non-IPMI Features ...
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Table of Contents Intel® Server Board S1600JP TPS 4.15 Other Platform Management ................................................................................60 4.15.1 Wake On LAN (WOL) ...........................................................................................60 4.15.2 PCI Express* Power management .......................................................................60 4.15.3 PMBus* ......................................................................................................
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Intel® Server Board S1600JP TPS Table of Contents 7.3.12 TPM Connector ..................................................................................................168 7.3.13 SSI Front Panel Header .....................................................................................169 7.3.14 SMB PMBus* Connector ....................................................................................169 7.3.15 HSBP I2C Connector ............................................................................
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List of Figures Intel® Server Board S1600JP TPS List of Figures Figure 1. Intel® Server Board S1600JP (4NIC SKU)....................................................................3 Figure 2. Intel® Server Board S1600JP Components ..................................................................5 Figure 3. Rear Panel Connector Placement ................................................................................6 Figure 4. Baseboard and Mounting Holes .................................................
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Intel® Server Board S1600JP TPS List of Figures Figure 40. BMC LAN Configuration Screen ............................................................................. 129 Figure 41. Boot Options Screen ..............................................................................................137 Figure 42. Hard Disk Order Screen .........................................................................................140 Figure 43. Network Device Order Screen .............................................
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List of Tables Intel® Server Board S1600JP TPS List of Tables Table 1. Intel® Server Board S1600JP Feature Set .....................................................................3 Table 2. Intel® Server Board S1600JP Features .........................................................................8 Table 3. Intel® Xeon® processor E5-2600, E5-2600 v2, E5-1600, and E5-1600 v2 product family UDIMM Support Guidelines ..........................................................................................
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Intel® Server Board S1600JP TPS List of Tables Table 37. Setup Utility – Processor PCIe Link Speed Configuration Screen Detail Fields ....... 105 Table 38. Setup Utility – Serial Ports Configuration Screen Fields .......................................... 105 Table 39. Setup Utility – USB Controller Configuration Screen Fields ..................................... 108 Table 40. Setup Utility – System Acoustic and Performance Configuration Screen Fields ...... 111 Table 41.
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List of Tables Intel® Server Board S1600JP TPS Table 78. SSI Front Panel Header Pin-Out (J6H1) .................................................................. 169 Table 79. PMBus* Connector Pin-Out (J6H2) ......................................................................... 169 Table 80. HSBP I2C Connector Pin-Out (J1E2) ....................................................................... 169 Table 81. Baseboard Fan Connector Pin-Out (J1K1, J1K2, J3K1, J4K2, J6K2, and J6K3) ..... 170 Table 82.
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Revision 1.
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Intel® Server Board S1600JP TPS 1. Introduction Introduction The Intel® Server Board S1600JP is a half width, single socket server board using the Intel® Xeon® processor E5-2600 and Intel® Xeon® processor E5-2600 v2 series or Intel® Xeon® processor E5-1600 and Intel® Xeon® processor E5-1600 v2, in combination with Intel® C600 chipset to provide a balance feature set between technology leadership and cost.
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Introduction 1.2 Intel® Server Board S1600JP TPS Server Board Use Disclaimer Intel Corporation server boards contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel® ensures through its own chassis development and testing, that when Intel® server building blocks are used together, the fully integrated system will meet the intended thermal requirements of these components.
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Intel® Server Board S1600JP TPS 2. Server Board Overview Server Board Overview The Intel® Server Board S1600JP is a monolithic Printed Circuit Board (PCB) with features designed to support the high performance and high density computing markets. This server board is designed to support the Intel® Xeon® processor E5-2600 and E5-2600 v2 or Intel® Xeon® processor E5-1600 and E5-1600 v2 product family. Previous generation Intel® Xeon® processors are not supported.
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Server Board Overview Intel® Server Board S1600JP TPS Feature Memory Chipset Intel C600-A Platform Controller Hub (PCH) with support for optional Storage Upgrade Key.  DB-15 Video connectors  Four RJ-45 Network Interface for 10/100/1000 LAN (SKU: S1600JP4)  Two RJ-45 Network Interface for 10/100/1000LAN (SKU: S1600JP2)  Two USB 2.
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Intel® Server Board S1600JP TPS 2.1 Server Board Overview Server Board Connector and Component Layout The following illustration provides a general overview of the server board, identifying key feature and component locations. The majority of the items identified are common in the Intel® Server Board S1600JP family. The accompanying table will identify variations when present.
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Server Board Overview 2.1.1 Intel® Server Board S1600JP TPS Board Rear Connector Placement ® The Intel Server Board S1600JP has the following board rear connector placement: Description A B C D E ID LED 5V standby LED DB15 Video out Two NIC ports (RJ45) System status LED Description F G H I Two NIC ports (RJ45) USB connector Diagnostic LED USB connector Figure 3. Rear Panel Connector Placement 6 Revision 1.
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Intel® Server Board S1600JP TPS 2.1.2 Server Board Overview Server Board Mechanical Drawings The following figures are mechanical drawings for the Intel® Server Board S1600JP: Figure 4. Baseboard and Mounting Holes Revision 1.
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Product Architecture Overview 3. Intel® Server Board S1600JP TPS Product Architecture Overview The Intel® Server Board S1600JP is a purpose build, rack-optimized server board used in a high-density rack system.
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Intel® Server Board S1600JP TPS Product Architecture Overview ® Figure 5. Intel Server Board S1600JP Functional Block Diagram Revision 1.
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Product Architecture Overview 3.2 Intel® Server Board S1600JP TPS Processor Support The server board includes one Socket-R (LGA2011) processor socket and can support the Intel® Xeon® processor E5-2600 and E5-2600 v2 or Intel® Xeon® processor E5-1600 and E51600 v2 product family, with a Thermal Design Power (TDP) of up to 135W for Intel® Xeon® processor E5-2600 and E5-2600 v2 product family or up to 130W for Intel® Xeon® processor E5-1600 and E5-1600 v2 product family.
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Intel® Server Board S1600JP TPS Product Architecture Overview The linked image cannot be displayed. The file may have been moved, renamed, or deleted. Verify that the link points to the correct file and location. Figure 7. Processor Socket ILM Variations The square ILM has an 94x56mm heatsink mounting hole pattern and is used on the Intel® Server Board S1600JP. 3.
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Product Architecture Overview    Intel® Server Board S1600JP TPS A 32-KB instruction and 32-KB data first-level cache (L1) for each core. A 256-KB shared instruction/data mid-level (L2) cache for each core. Up to 20 MB last level cache (LLC): up to 2.5 MB per core instruction/data last level cache (LLC), shared among all cores. Supported Technologies:              3.3.
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Intel® Server Board S1600JP TPS    Product Architecture Overview Command launch modes of 1n/2n. RAS Support: o Rank Level Sparing and Device Tagging. o Demand and Patrol Scrubbing. o DRAM Single Device Data Correction (SDDC) for any single x4 or x8 DRAM device. Independent channel mode supports x4 SDDC. x8 SDDC requires lockstep mode. o Lockstep mode where channels 0 and 1 and channels 2 and 3 are operated in lockstep mode.
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Product Architecture Overview 1. 2. Intel® Server Board S1600JP TPS ® Supported DRAM Densities are 1Gb, 2Gb, and 4Gb. Only 2Gb and 4Gb are validated by Intel . Command Address Timing is 1N for 1DPC and 2N for 2DPC. ® ® Table 4.
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Intel® Server Board S1600JP TPS 5. Product Architecture Overview QDP – Quad Die Package DRAM Stacking; DDP – Dual Die Package DRAM stacking; P – Planer monolithic DRAM Die. 3.3.1.2 Memory Population Rules Note: All memory on Intel® Server Board S1600JP is expected to match in all respects, including the memory vendor. S1600JP does not support any mix of memory parts, whether or not a mixed configuration may be able to operate successfully in a particular instance.
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Product Architecture Overview Intel® Server Board S1600JP TPS  All DIMMs must be DDRIII DIMMs.  Unbuffered DIMMs can be ECC.  Mixing of Registered and Unbuffered DIMMs is not allowed per platform.  Mixing of LRDIMM with any other DIMM type is not allowed per platform.  Mixing of DDRIII voltages is not validated within a socket or across sockets by Intel®. If 1.35V (DDRIIIL) and 1.50V (DDRIII) DIMMs are mixed, the DIMMs will run at 1.50V.
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Intel® Server Board S1600JP TPS 3.3.1.4.2 Product Architecture Overview Rank Sparing Mode In Rank Sparing Mode, one rank is a spare of the other ranks on the same channel. The spare rank is held in reserve and is not available as system memory. The spare rank must have identical or larger memory capacity than all the other ranks (sparing source ranks) on the same channel. After sparing, the sparing source rank will be lost. 3.3.1.4.
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Product Architecture Overview Intel® Server Board S1600JP TPS ® Figure 9. Intel Server Board S1600JP PCI Layout 3.3.2.1 Riser Types There are three PCIe riser slots on the server board, and they are customized on pin definition. The riser slot 1 is a standard 164-pin x 16 connector but it is not compatible with standard PCIe pinout. It has a x16 PCIe GenIII electrical interface. It can be configured as a single x16, dual x8, or dual x4 plus single x8 (with different risers) if required.
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Intel® Server Board S1600JP TPS  Product Architecture Overview 1U low profile Riser slot 1 with one PCIe slot – It provides electrical connectivity for a PCIe x16 GenIII low profile adapter card. It supports a PCIe GenIII X16 card edge connection and a x16/x16 mech PCIe connector. The X16 PCIe card edge connection are not compatible with the standard PCIe pinout but the x16 PCIe connector is compatible. Product Code: F1UJP1X16RISER. Figure 10.
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Product Architecture Overview Intel® Server Board S1600JP TPS Figure 11. PCIe Riser for Slot 2 Figure 12. Riser Carrier Board  20 1U PCIe double width PCI Express* card Riser for slot 3 with one PCIe slot - It provides electrical connectivity for a PCIe x16 GenIII double width PCI Express* card. It supports a PCIe GenIII 2X60pin card edge connection and a x16/x16 mech PCIe connector.
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Intel® Server Board S1600JP TPS Product Architecture Overview Figure 13. 1U PCIe Double Width PCI Express* Card Riser for Slot3  1U PCIe FHFL Riser for slot 3 with two PCIe slots - It provides electrical connectivity for two standard PCIe x8 GenIII FHFL PCIE card. It supports x2 60 pin PCIE card edge and one GenIII x8/x16 mech PCIE connector and one GenIII x8/x8 mech PCIE connector.
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Product Architecture Overview 3.3.2.3 Intel® Server Board S1600JP TPS I/O Module Support To broaden the standard on-board feature set, the server board supports the option of adding a single I/O module providing external ports for a variety of networking interfaces. The I/O module attaches to a high density 80-pin connector of I/O module carrier on the Riser 2. 3.
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Intel® Server Board S1600JP TPS Product Architecture Overview  Supports Intel® Virtualization Technology for Directed I/O (Intel® VT-d)  Supports Intel® Trusted Execution Technology (Intel® TXT)  Low Pin Count (LPC) interface  Firmware Hub (FWH) interface support  Serial Peripheral Interface (SPI) support  Intel® Anti-Theft Technology (Intel® AT)  JTAG Boundary Scan support 3.4.
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Product Architecture Overview Intel® Server Board S1600JP TPS ® Table 8.
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Intel® Server Board S1600JP TPS 3.4.4 Product Architecture Overview PCI Interface ® The Intel C600 PCH PCI Interface provides a 33 MHz, Revision 2.3 implementation. It integrates a PCI arbiter that supports up to four external PCI bus masters in addition to the PCH internal requests. This allows for combinations of up to four PCI down devices and PCI slots. 3.4.5 Low Pin Count (LPC) Interface ® The Intel C600 PCH implements an LPC Interface as described in the LPC 1.1 Specification.
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Product Architecture Overview 3.4.9 Intel® Server Board S1600JP TPS Advanced Programmable Interrupt Controller (APIC) In addition to the standard ISA compatible Programmable Interrupt Controller (PIC) described in the previous section, the Intel® C600 PCH incorporates the Advanced Programmable Interrupt Controller (APIC). 3.4.10 Real Time Clock (RTC) ® The Intel C600 PCH contains a Motorola* MC146818B-compatible real-time clock with 256 bytes of battery-backed RAM.
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Intel® Server Board S1600JP TPS 3.4.15 Product Architecture Overview KVM/Serial Over LAN (SOL) Function These functions support redirection of keyboard, mouse, and text screen to a terminal window on a remote console. The keyboard, mouse, and text redirection enables the control of the client machine through the network without the need to be physically near that machine. Text, mouse, and keyboard redirection allows the remote machine to control and configure the client by entering BIOS setup.
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Product Architecture Overview Intel® Server Board S1600JP TPS C600 PCH can be programmed to generate either SMI# or TCO interrupt due to an active INTRUDER# signal. 3.4.18 System Management Bus (SMBus* 2.0) ® The Intel C600 PCH contains a SMBus* Host interface that allows the processor to communicate with SMBus* slaves. This interface is compatible with most I2C devices. Special I2C commands are implemented.
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Intel® Server Board S1600JP TPS Product Architecture Overview Figure 16. 1GbE NIC port LED Table 10. NIC Status LED LED Color Green/Amber (B) Green (A) 3.4.19.1 LED State NIC State Off 10 Mbps Amber 100 Mbps Green 1000 Mbps On Active Connection Blinking Transmit/Receive activity MAC Address Definition ® The Intel Server Board S1600JP2 has the following four MAC addresses assigned to it at the Intel® factory.
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Product Architecture Overview Intel® Server Board S1600JP TPS EEPROM is programmed to turn off this feature from the other ports in order to maximize power savings during sleep states. 3.4.19.3 Wake-On-LAN WOL is supported on the Intel® I350 LAN controller for all supported Sleep states. 3.4.19.4 Intel® i350 Thermal Sensor Intel® i350 NIC will have an integrated digital thermal sensor accessible through CSR and manageability registers.
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Intel® Server Board S1600JP TPS Product Architecture Overview Figure 18. Integrated BMC Functional Block Diagram The Integrated BMC is provided by an embedded ARM9 controller and associated peripheral functionality that is required for IPMI-based server management. Firmware usage of these hardware features is platform dependent.
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Product Architecture Overview               Intel® Server Board S1600JP TPS Serial general-purpose I/O Ports (80 in and 80 out) Three UARTs Platform Environmental Control Interface (PECI) Six general-purpose timers Interrupt controller Multiple SPI flash interfaces NAND/Memory interface Sixteen mailbox registers for communication between the BMC and host LPC ROM interface BMC watchdog timer capability SD/MMC card controller with DMA support LED support with programmable blink rate controls
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Intel® Server Board S1600JP TPS Product Architecture Overview  DDR-II/III memory interface supports up to 256MB of memory  Supports all display resolutions up to 1600 x 1200 16bpp @ 60Hz  High speed Integrated 24-bit RAMDAC The integrated video controller supports all standard IBM VGA modes. The following table shows the 2D modes supported for both CRT and LCD: Table 11.
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Product Architecture Overview 3.5.3 Intel® Server Board S1600JP TPS Remote KVM The Integrated BMC contains a remote KVMS subsystem with the following features:  USB 2.0 interface for Keyboard, Mouse, Video, and Remote storage such as CD/DVD ROM and floppy  USB 1.1/USB 2.
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Platform Management Functional Overview 4. Intel® Server Board S1600JP TPS Platform Management Functional Overview Platform management functionality is supported by several hardware and software components integrated on the server board that work together to control system functions, monitor and report system health, and control various thermal and performance features in order to maintain (when possible) server functionality in the event of component failure and/or environmentally stressed conditions.
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Intel® Server Board S1600JP TPS Platform Management Functional Overview  BMC self-test: The BMC performs initialization and run-time self-tests and makes results available to external entities. See also the Intelligent Platform Management Interface Specification Second Generation v2.0. 4.1.2 Non-IPMI Features The BMC supports the following non-IPMI features. This list does not preclude support for future enhancements or additions.
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Platform Management Functional Overview               Power fault analysis Intel® Light-Guided Diagnostics Address Resolution Protocol (ARP): The BMC sends and responds to ARPs (supported on embedded NICs) Dynamic Host Configuration Protocol (DHCP): The BMC performs DHCP (supported on embedded NICs) E-mail alerting Embedded web server o Support for embedded web server UI in Basic Manageability feature set o Human-readable SEL o Additional system configurability o Additional system moni
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Intel® Server Board S1600JP TPS                     4.2 Platform Management Functional Overview o Signed Firmware (improved security) o Inventory data/system information export (partial SMBIOS table) Enhancements to fan speed control DCMI 1.
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Platform Management Functional Overview State Supported Intel® Server Board S1600JP TPS Description S1 Yes Sleeping. Hardware context is maintained; equates to processor and chipset clocks being stopped.  The front panel power LED blinks at a rate of 1 Hz with a 50% duty cycle (not controlled by the BMC).  The watchdog timer is stopped.  The power, reset, front panel NMI, and ID buttons are unprotected.  Fan speed control is determined by available SDRs.
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Intel® Server Board S1600JP TPS Platform Management Functional Overview system is reset or powered-on and POST completes, as indicated by the assertion of the POSTcomplete signal. Additionally, the BMC should cancel any pending reads of the RTC if the POST-complete signal deasserts (for example, due to a reset). Normally the BMC reads the RTC when AC power is first applied and before the system is powered-on, so this is not a concern.
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Platform Management Functional Overview Channel ID Intel® Server Board S1600JP TPS Interface Supports Sessions 4 Reserved Yes 5 USB No 6 Secondary IPMB No 7 SMM No 8 – 0Dh Reserved – 0Eh Self 2 – 0Fh SMS/Receive Message Queue Notes: 1. 2. No Optional hardware supported by the server system. Refers to the actual channel used to send the request. 4.6.2 User Model The BMC supports the IPMI 2.0 user model including User ID 1 support. 15 user IDs are supported.
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Intel® Server Board S1600JP TPS Users Platform Management Functional Overview User name Password Status Default Privilege Characteristics User 3 test1 superuser Disabled Admin User name and password can be changed. User 4 test2 superuser Disabled Admin User name and password can be changed. User 5 test3 superuser Disabled Admin User name and password can be changed. User 6-15 undefined undefined Disabled Admin User name and password can be changed. 4.6.
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Platform Management Functional Overview Intel® Server Board S1600JP TPS Note: The number of possible active session values returned by Get Session Info is the total number of allocated memory session slots in BMC firmware for IPMI Sessions. The actual number of IPMI sessions that can be established at any time is dependent on Channel and User IPMI configuration parameters and in compliance with the IPMI Specification, which is always less than the total available slots. 4.6.
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Intel® Server Board S1600JP TPS 4.6.4.
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Platform Management Functional Overview Intel® Server Board S1600JP TPS  The IPv6 Enable parameter must be set before any IPv6 packets will be sent or received on that channel.  There are two variants of automatic IP Address Source configuration versus just DHCP for IPv4. The three possible IPv6 IP Address Sources for configuring the BMC are:  Static (Manual): The IP, Prefix, and Gateway parameters are manually configured by the user.
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Intel® Server Board S1600JP TPS Platform Management Functional Overview The BMC allocates 65,502 bytes (approximately 64 KB) of non-volatile storage space to store system events. The SEL timestamps may not be in order. Up to 3,639 SEL records can be stored at a time. Any command that results in an overflow of the SEL beyond the allocated space is rejected with an “Out of Space” IPMI completion code (C4h). 4.7.1 Servicing Events Events can be received while the SEL is being cleared.
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Platform Management Functional Overview Intel® Server Board S1600JP TPS BMC’s in-band and out-of-band interfaces regardless of the system power state. The BMC allocates 65,519 bytes of non-volatile storage space for the SDR. 4.9 Field Replaceable Unit (FRU) Inventory Device The BMC implements the interface for logical FRU inventory devices as specified in the Intelligent Platform Management Interface Specification, Version 2.0.
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Intel® Server Board S1600JP TPS Platform Management Functional Overview 4.11 Diagnostics Interrupt (NMI) The BMC generates an NMI pulse under certain conditions. The BMC-generated NMI pulse duration is at least 30ms. Once an NMI has been generated by the BMC, the BMC does not generate another NMI until the system has been reset or powered down. The following actions cause the BMC to generate an NMI pulse: a. Receiving a Chassis Control command to pulse the diagnostic interrupt.
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Platform Management Functional Overview Intel® Server Board S1600JP TPS Feature Basic* Advanced** PECI Thermal Management Support X X E-mail Alerting X X Embedded Web Server X X SSH Support X X Integrated KVM X Integrated Remote Media Redirection X Local Directory Access Protocol (LDAP) X X Intel Intelligent Power Node Manager Support*** X X SMASH CLP X X ® * Basic management features provided by Integrated BMC.
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Intel® Server Board S1600JP TPS Platform Management Functional Overview The Integrated BMC supports an embedded KVM application (Remote Console) that can be launched from the embedded web server from a remote console. USB1.1 or USB 2.0 based mouse and keyboard redirection are supported. It is also possible to use the KVM-redirection (KVM-r) session concurrently with media-redirection (media-r).
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Platform Management Functional Overview Intel® Server Board S1600JP TPS An Integrated BMC reset (for example, due to an Integrated BMC Watchdog initiated reset or Integrated BMC reset after Integrated BMC firmware update) will require the session to be reestablished. KVM sessions persist across system reset, but not across an AC power loss. 4.12.1.6 Timeout The remote KVM session will automatically timeout after a configurable amount of time (30 minutes is the default).
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Intel® Server Board S1600JP TPS Platform Management Functional Overview on/off. An Integrated BMC reset (for example, due to an Integrated BMC reset after Integrated BMC firmware update) will require the session to be re-established.  The mounted device is visible to (and useable by) the managed system’s OS and BIOS in both pre-boot and post-boot states.  The mounted device shows up in the BIOS boot order and it is possible to change the BIOS boot order to boot from this remote device.
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Platform Management Functional Overview  Intel® Server Board S1600JP TPS Mozilla Firefox 3.6* The embedded web user interface supports strong security (authentication, encryption, and firewall support) since it enables remote server configuration and control. The user interface presented by the embedded web user interface shall authenticate the user before allowing a web session to be initiated. Encryption using 128-bit SSL is supported. User authentication is based on user id and password.
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Intel® Server Board S1600JP TPS Platform Management Functional Overview based standard that builds upon a set of required IPMI standard commands by adding a set of DCMI-specific IPMI OEM commands. 4.12.5 Lightweight Directory Authentication Protocol (LDAP) The Lightweight Directory Access Protocol (LDAP) is an application protocol supported by the Integrated BMC for the purpose of authentication and authorization. The Integrated BMC user connects with an LDAP server for login authentication.
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Platform Management Functional Overview Intel® Server Board S1600JP TPS The following terminology is used for the various memory throttling options:  Static Open Loop Thermal Throttling (Static-OLTT): OLTT control registers are configured by BIOS MRC remain fixed after post. The system does not change any of the throttling control registers in the embedded memory controller during runtime.
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Intel® Server Board S1600JP TPS Platform Management Functional Overview allows the user to select which supported chassis (Intel® or Non-Intel®) and platform chassis configuration is used. Based on the input provided, the FRUSDR writes sensor data specific to the configuration to NVRAM for the BMC controller to read each time the system is powered on. 4.13 Intel® Intelligent Power Node Manager 4.13.
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Platform Management Functional Overview Intel® Server Board S1600JP TPS 4.14 Management Engine (ME) 4.14.1 Overview ® The Intel Server Platform Services (SPS) is a set of manageability services provided by the firmware executing on an embedded ARC controller within the IOH. This management controller is also commonly referred to as the Management Engine (ME).
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Intel® Server Board S1600JP TPS Platform Management Functional Overview Figure 19. Management Engine Distribution Model 4.14.3 ME System Management Bus (SMBus*) Interface  The ME uses the SMLink0 on the SSB in multi-master mode as a dedicated bus for communication with the BMC using the IPMB protocol. The BMC FW considers this a secondary IPMB bus and runs at 400 kHz.
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Platform Management Functional Overview  Intel® Server Board S1600JP TPS BMC may be queried by the ME for inlet temperature readings. 4.14.5 ME Power and Firmware Startup ® On Intel Server Board S1600JP, the ME is on standby power. The ME FW will begin its startup sequence at the same time that the BMC FW is booting. As the BMC FW is booting to a Linux* kernel and the ME FW uses an RTOS, the ME FW should always complete its basic initialization before the BMC.
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Intel® Server Board S1600JP TPS Platform Management Functional Overview however, this may need to be comprehended by the fan monitoring FW if it does have this sideeffect. 4.15 Other Platform Management The platform supports the following sleep states, S1 and S5. Within S0, the platform supports additional lower power states, such as C1e and C6, for the CPU. 4.15.1 4.15.2 Wake On LAN (WOL)  Wake On LAN (WOL) is supported on both LAN ports and IOM LAN modules for all supported Sleep states.
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Intel® Server Board S1600JP TPS BIOS Setup Interface 5. BIOS Setup Interface 5.1 HotKeys Supported During POST Certain “HotKeys” are recognized during POST. A HotKey is a key or a key combination that is recognized as an unprompted command input, that is, the operator is not prompted to press the HotKey and typically the HotKey will be recognized even while other processing is in progress. The Intel® Server Board S1600JP Family BIOS recognizes a number of HotKeys during POST.
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BIOS Setup Interface Intel® Server Board S1600JP TPS  Mouse devices detected, if any attached  Instructions showing HotKeys for going to Setup, going to popup Boot Menu, starting Network Boot 5.3 BIOS Boot Pop-up Menu The BIOS Boot Specification (BBS) provides a Boot Pop-up menu that can be invoked by pressing the key during POST. The BBS Pop-up menu displays all available boot devices. The boot order in the pop-up menu is not the same as the boot order in the BIOS setup.
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Intel® Server Board S1600JP TPS BIOS Setup Interface Note: If an Administrative Password has not been set, anyone who boots the system to Setup has access to all selection and data entry fields in Setup and can change any of them. 5.4.1.1 Setup Page Layout The Setup page layout is sectioned into functional areas. Each occupies a specific area of the screen and has dedicated functionality. The following table lists and describes each functional area.
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BIOS Setup Interface Functional Area Description Keyboard Command Area 5.4.1.2 Intel® Server Board S1600JP TPS The Keyboard Command Area is located at the bottom right of the screen and continuously displays help for keyboard special keys and navigation keys. Entering BIOS Setup To enter the BIOS Setup using a keyboard (or emulated keyboard), press the function key during boot time when the OEM or Intel® logo is displayed.
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Intel® Server Board S1600JP TPS Key Option BIOS Setup Interface Description Select Field The key is used to move between fields. For example, can be used to move from hours to minutes in the time item in the main menu. - Change Value The minus key on the keypad is used to change the value of the current item to the previous value. This key scrolls through the values in the associated pick list without displaying the full list.
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BIOS Setup Interface Intel® Server Board S1600JP TPS  The text shown in the Option Values and Help Text entries in each Field Description are the actual text and values are displayed on the BIOS Setup screens.  In the Option Values entries, the text for default values is shown with an underline. These values do not appear underline on the BIOS Setup screen. The underlined text in this document is to serve as a reference to which value is the default value.
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Intel® Server Board S1600JP TPS BIOS Setup Interface Categories (Top Tabs) 2nd Level Screens 3rd Level Screens  NIC Configuration  UEFI Network Stack  UEFI Option ROM Control  Processor PCIe Link Speed  Serial Port Configuration  USB Configuration  System Acoustic and Performance Configuration Security Screen (Tab) Server Management Screen (Tab)  Console Redirection  System Information  BMC LAN Configuration Boot Options Screen (Tab)  Hard Disk Order  Network Device O
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BIOS Setup Interface 5.4.2.2 Intel® Server Board S1600JP TPS Main Screen (Tab) The Main Screen is the first screen that appears when the BIOS Setup configuration utility is entered, unless an error has occurred. If an error has occurred, the Error Manager Screen appears instead. Main Advanced Security Server Management Boot Options Logged in as: Administrator/User Platform ID Boot Manager System BIOS BIOS Version
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Intel® Server Board S1600JP TPS BIOS Setup Interface Table 26. Setup Utility – Main Screen Fields Setup Item Options Help Text Comments Logged in as Administrator / User None Information only. Displays password level that setup is running in: Administrator or User. With no passwords set, Administrator is the default mode. Platform ID Platform ID None Information only. Displays the Platform ID: S1600JP. None Information only.
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BIOS Setup Interface Setup Item POST Error Pause Options Enabled Disabled Intel® Server Board S1600JP TPS Help Text [Enabled] – Go to the Error Manager for critical POST errors. Comments If enabled, the POST Error Pause option takes the system to the error manager to review the errors when major errors occur. Minor and fatal error displays are not affected by this setting. [Disabled] – Attempt to boot and do not go to the Error Manager for critical POST errors.
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Intel® Server Board S1600JP TPS Main Advanced BIOS Setup Interface Security Server Management Boot Options Boot Manager ► Processor Configuration ► Power & Performance ► Memory Configuration ► Mass Storage Controller Configuration ► PCI Configuration ► Serial Port Configuration ► USB Configuration ► System Acoustic and Performance Configuration Figure 21. Advanced Screen Table 27.
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BIOS Setup Interface Setup Item Intel® Server Board S1600JP TPS Options Selection only. Select this line and press the key to go to the PCI Configuration group of configuration settings. None View/Configure serial port information and settings. Selection only. Select this line and press the key to go to the Serial Port Configuration group of configuration settings. None View/Configure USB information and settings. Selection only.
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Intel® Server Board S1600JP TPS 5.4.2.4 BIOS Setup Interface Processor Configuration The Processor Configuration screen displays the processor identification and microcode level, core frequency, cache sizes for all processors currently installed. It also allows the user to enable or disable a number of processor options. To access this screen from the Main screen, select Advanced > Processor Configuration.
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BIOS Setup Interface Intel® Server Board S1600JP TPS Intel(R) VT for Directed I/O Enabled/Disabled Interrupt Remapping Enabled/Disabled Coherency Support Enabled/Disabled ATS Support Enabled/Disabled Pass-through DMA Support Enabled/Disabled Intel(R) TXT Enabled/Disabled Enhanced Error Containment Mode Enabled/Disabled MLC Streamer Enabled/Disabled MLC Spatial Prefetcher Enabled/Disabled DCU Data Prefetcher Enabled/Disabled DCU Instruction Prefetcher Enabled/Disabled Direct Cache Acc
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Intel® Server Board S1600JP TPS Setup Item BIOS Setup Interface Options Help Text Comments L1 Cache RAM L1 cache size None Information only. Displays size in KB of the processor L1 Cache. Since L1 cache is not shared between cores, this is shown as the amount of L1 cache per core. There are two types of L1 cache, so this amount is the total of L1 Instruction Cache plus L1 Data Cache for each core. L2 Cache RAM L2 cache size None Information only. Displays size in KB of the processor L2 Cache.
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BIOS Setup Interface Intel® Server Board S1600JP TPS Setup Item Processor C3 Options Help Text This is normally Disabled, but can be Enabled for improved performance on certain benchmarks and in certain situations. Enabled Disabled Enable/Disable Processor C6 (ACPI C3) report to OS This is normally Enabled but can be Disabled for improved performance on certain benchmarks and in certain situations.
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Intel® Server Board S1600JP TPS Setup Item BIOS Setup Interface Options Execute Disable Enabled Disabled Bit Help Text Execute Disable Bit can help prevent certain classes of malicious buffer overflow attacks. Contact your OS vendor regarding OS support of this feature. ® Intel Virtualization Technology Enabled Disabled ® Intel Virtualization Technology allows a platform to run multiple operating systems and applications in independent partitions.
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BIOS Setup Interface Intel® Server Board S1600JP TPS Setup Item MLC Streamer Options Enabled Disabled Help Text MLC Streamer is a speculative prefetch unit within the processor(s) Note: Modifying this setting may affect performance. MLC Spatial Prefetcher Enabled Disabled [Enabled] – Fetches adjacent cache line (128 bytes) when required data is not currently in cache. [Disabled] – Only fetches cache line with data required by the processor (64 bytes).
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Intel® Server Board S1600JP TPS 5.4.2.5 BIOS Setup Interface Power and Performance policy The Power and Performance screen allows the user to specify a profile which is optimized in the direction of either reduced power consumption or increased performance. To access this screen from the Main screen, select Advanced > Power and Performance. To move to another screen, press the key to return to the Advanced screen, then select the desired screen.
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BIOS Setup Interface Intel® Server Board S1600JP TPS When the user selects a Power and Performance Policy in Setup, there is a list of complementary settings which are made. These can be individually overridden after the policy setting has been selected and the profile settings performed. The profile settings are listed in the following table. Table 30.
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Intel® Server Board S1600JP TPS BIOS Features BIOS Setup Interface Available Settings Performance Balanced Performance Balanced Power Power Setup: Advanced > Memory Configuration Memory Operating Speed Selection Auto/800/1067 /1333/1600 (Auto) (Auto) (Auto) (Auto) Patrol Scrub Enabled/Disabled (Enabled) (Enabled) (Enabled) (Enabled) Demand Scrub Enabled/Disabled (Enabled) (Enabled) (Enabled) (Enabled) Setup: Advanced > System Acoustic and Performance Configuration Set Throttling Mo
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BIOS Setup Interface Intel® Server Board S1600JP TPS BIOS Features Available Settings Performance/Bala nced Performance/Bala nced Power/Power ENERGY_PERF _BIAS mode 5.4.2.6 Performance Performance Balanced Performance Balanced Power (Balanced Performance) Balanced Power Power Power Memory Configuration The Memory Configuration screen allows the user to view details about the DDRIII DIMMs that are installed as system memory, and alter BIOS Memory Configuration settings where appropriate.
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Intel® Server Board S1600JP TPS BIOS Setup Interface DIMM Information DIMM_A1 DIMM_A2 DIMM_B1 DIMM_B2 DIMM_C1 DIMM_C2 DIMM_D1 DIMM_D2 Figure 24. Memory Configuration Screen Table 31.
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BIOS Setup Interface Setup Item Current Configuration Intel® Server Board S1600JP TPS Options Independent Channel Help Text None Comments Information only: Displays one of the following: Independent Channel – DIMMs are operating in Independent Channel Mode, the default configuration when there is no RAS Mode configured. Mirror Rank Sparing Lockstep Mirror – Mirroring RAS Mode has been configured and is operational. Rank Sparing – Rank Sparing RAS Mode has been configured and is operational.
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Intel® Server Board S1600JP TPS Setup Item Options BIOS Setup Interface Help Text Comments Demand Scrub Enabled Disabled When enabled, executes when an ECC error is encountered during a normal read/write of data and corrects that data. When enabled, Demand Scrub automatically corrects a Correctable ECC Error encountered during a fetch from memory by writing back the corrected data to memory.
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BIOS Setup Interface Setup Item Intel® Server Board S1600JP TPS Options Help Text Comments Memory RAS and Performance Configuration None Configure memory RAS (Reliability, Availability, and Serviceability) and view current memory performance information and settings. Selection only. Select this line and press the key to go to the Memory RAS and Performance Configuration group of configuration settings.
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Intel® Server Board S1600JP TPS BIOS Setup Interface Advanced Memory RAS and Performance Configuration Capabilities Memory Mirroring Possible Yes/No Memory Rank Sparing Possible Yes/No Memory Lockstep Possible Yes/No Select Memory RAS Configuration Maximum Performance/Mirroring/Lockstep Figure 25. Memory RAS and Performance Configuration Screen Table 32.
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BIOS Setup Interface Setup Item Intel® Server Board S1600JP TPS Options Memory Lockstep Possible Yes Select Memory RAS Configuration Maximum Performance Help Text Information only. Displays whether the current DIMM configuration is capable of Memory Lockstep. For Memory Lockstep to be possible, DIMM configurations on all paired channels must be identical between the channel pair. Allows the user to select the memory RAS Configuration to be applied for the next boot.
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Intel® Server Board S1600JP TPS BIOS Setup Interface To access this screen from the Main screen, select Advanced > Mass Storage Controller Configuration. To move to another screen, press the key to return to the Advanced screen, then select the desired screen.
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BIOS Setup Interface Intel® Server Board S1600JP TPS Table 33. Mass Storage Controller Configuration Fields Setup Item Options Help Text Comments AHCI Controller Configuration AHCI Port Configuration None Information only. This is a display showing which ports are available through the onboard AHCI capable SATA controller, if the controller is enabled. SATA/SAS Controller Configuration SCU SAS/SATA Port Configuration None Information only.
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Intel® Server Board S1600JP TPS Setup Item AHCI Capable RAID Options Options ® Intel ESRT2 (LSI*) ® Intel RSTe BIOS Setup Interface Help Text This option only appears when the SATA Controller is enabled, and RAID Mode has been selected as the operational SATA Mode. This setting selects the RAID stack to be used for SATA RAID with the onboard AHCI SATA controller.
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BIOS Setup Interface Setup Item RSTe Boot Configuration Intel® Server Board S1600JP TPS Options Neither AHCI Capable Ctrlr SAS/SATA Capable Ctrlr Help Text This selects the device that will support Bootable Drives, whether they are in RAID arrays or individual passthrough SAS/SATA drives. Once selected and set up (if necessary), individual bootable devices will be listed in the Bootable Devices menu display.
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Intel® Server Board S1600JP TPS BIOS Setup Interface Advanced PCI Configuration Maximize Memory below 4GB Enabled / Disabled Memory Mapped I/O above 4 GB Enabled / Disabled Memory Mapped I/O Size Auto/1G/2G/4G/8G/16G/32G/64G/128G/256G/512G/ 1024G Onboard Video Enabled / Disabled Dual Monitor Video Enabled / Disabled NTB PCIe Port on CPU socket 1 Transparent Bridge/NTB to NTB/NTB to RP Enable NTB Bars Crosslink control override Enabled/ Disabled DSD/USP / USD/DSP ► NIC Configuration ► UEFI N
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BIOS Setup Interface Intel® Server Board S1600JP TPS Table 34. Setup Utility – PCI Configuration Screen Fields Setup Item Options Maximize Memory below 4GB Enabled Memory Mapped I/O above 4GB Memory Mapped I/O Size Help Text Comments BIOS maximizes memory usage below 4GB for an OS without PAE support, depending on the system configuration. Only enable for an OS without PAE support.
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Intel® Server Board S1600JP TPS Setup Item Options Enable NTB Bars Disabled Enabled BIOS Setup Interface Help Text Comments If disabled, BIOS will not program NTB BAR size registers. This option allow BIOS to program NTB BAR registers with default values when Enabled. If disabled, BIOS will not program NTB BARs registers and the task is left to drivers. This option only appears when NTB PCIe Port on CPU socket1 is not configured as ‘Transparent Bridge’.
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BIOS Setup Interface PXE 10GbE Option ROM Enabled / Disabled FCoE 10GbE Option ROM Enabled / Disabled iSCSI 1GbE/10GbE Option ROM Enabled / Disabled Onboard NIC1 Type NIC1 Controller Enabled / Disabled NIC1 Port1 Enabled / Disabled NIC1 Port2 Enabled / Disabled NIC1 Port3 Enabled / Disabled NIC1 Port4 Enabled / Disabled NIC1 Port1 PXE Enabled / Disabled NIC1 Port2 PXE Enabled / Disabled NIC1 Port3 PXE Enabled / Disabled NIC1 Port4 PXE Enab
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Intel® Server Board S1600JP TPS BIOS Setup Interface IOM1 Port3 MAC Address IOM1 Port4 MAC Address IO Module 1 Type IOM1 InfiniBand* Option ROM Enabled / Disabled IOM1 Port1 GUID IOM1 Port1 MAC Address Figure 28. NIC Configuration Screen Table 35.
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BIOS Setup Interface Intel® Server Board S1600JP TPS Setup Item Options PXE 10GbE Option ROM Enabled Disabled Help Text Enable/Disable Onboard/IOM NIC PXE Option ROM Load. Comments This selection is to enable/disable the 10GbE PXE Option ROM that is used by all Onboard and IO Module 10 GbE controllers. This option is grayed out and not accessible if the iSCSI Option ROM is enabled or the 10 GbE FCoE Option ROM is enabled.
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Intel® Server Board S1600JP TPS BIOS Setup Interface Setup Item Options Onboard NIC1 Type Onboard NIC Description None. Help Text Information only. This is a display showing which NIC is available as Network Controllers integrated into the baseboard. Onboard NIC will be followed by a section including a group of options that are specific to the type of NIC. Comments NIC1 Controller Enabled Disabled Enable/Disable Onboard Network Controller.
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BIOS Setup Interface Setup Item NIC1 Port x PXE Intel® Server Board S1600JP TPS Options Enable Help Text Enable/Disable NIC 1 Port x PXE Boot Disable Comments This will enable or disable PXE Boot capability for Port of Onboard NIC 1. This option will not appear for ports on a NIC which is disabled, or for individual ports when the corresponding NIC Port is disabled. Only ports which actually exist for NIC1 will appear in this section.
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Intel® Server Board S1600JP TPS Setup Item IOM1 Portx PXE Options Enabled Disabled BIOS Setup Interface Help Text Enable/Disable IOM NIC Port PXE Boot Comments This will enable or disable PXE Boot capability for Port of IO Module 1. Only ports which actually exist for a particular IOM will appear in this section. That is, Port1-Port4 will appear for a quad-port NIC, Port1-Port2 will appear for a dual-port NIC, and only Port1 will appear for a single-port NIC.
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BIOS Setup Interface 5.4.2.11 Intel® Server Board S1600JP TPS UEFI Network Stack The UEFI Network Stack provides access to network devices while executing in the UEFI boot services environment. This screen allows the user to configure UEFI Network Stack Settings. Advanced UEFI Network Stack UEFI Network Stack Enabled/Disabled IPv4 PXE Support Enabled/Disabled Figure 29. UEFI Network Stack Screen Table 38.
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Intel® Server Board S1600JP TPS 5.4.2.12 BIOS Setup Interface UEFI Option ROM Control The UEFI Option ROM Control configuration screen is brought by the EFI PCI Option ROM compliant with the Human Interface Infrastruce Specification 2.3.1. Those configuration settings are provided by third-party PCI device provider and not controlled directly by the BIOS. The BIOS will parse the HII package provided by the EFI PCI Option ROM and group them into this screen.
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BIOS Setup Interface 5.4.2.13 Intel® Server Board S1600JP TPS Processor PCIe Link Speed Configuration The Processor PCIe Link Speed configuration screen allows the user to configure the PCIe Link Speed of the Processor IIO PCIe root port and the PCIe devices connected to this port. To access this screen from the Main screen, select Advanced > PCI Configuration > Processor PCIe Link Speed.
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Intel® Server Board S1600JP TPS BIOS Setup Interface Table 37. Setup Utility – Processor PCIe Link Speed Configuration Screen Detail Fields Setup Item Socket 1, DMI Options Gen2 (5GT/s) Help Text Comments DMI link speed selection. Gen1 (2.5GT/s) Socket 1, PCIe Port xx Gen3 (8GT/s) PCIe Port link speed selection. Gen2 (5GT/s) Gen1 (2.5GT/s) 5.4.2.14 Serial Port Configuration The Serial Port Configuration screen allows the user to configure the Serial A [COM 1] ports.
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BIOS Setup Interface Setup Item Address Options 3F8h 2F8h Intel® Server Board S1600JP TPS Help Text Comments Select Serial port A base I/O address. Legacy I/O port address. This field should not appear when Serial A port enable/disable does not appear. Select Serial port A interrupt request (IRQ) line. Legacy IRQ. This field should not appear when Serial A port enable/disable does not appear. 3E8h 2E8h IRQ 3 4 5.4.2.
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Intel® Server Board S1600JP TPS BIOS Setup Interface Advanced USB Configuration Detected USB Devices < Number of USB devices detected in system > USB Controller Enabled/Disabled Legacy USB Support Enabled/Disabled/Auto Port 60/64 Emulation Enabled/Disabled Make USB Devices Non-Bootable Enabled/Disabled USB Mass Storage Device Configuration Device Reset timeout 10 seconds/20 seconds/30 seconds/40 seconds Mass Storage Devices: Auto/Floppy/Forced FDD/Ha
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BIOS Setup Interface Intel® Server Board S1600JP TPS Table 39. Setup Utility – USB Controller Configuration Screen Fields Setup Item Options Detected USB Devices Number of USB devices detected in system Help Text None Comments Information only. Displays the total number of USB devices of all types which have been detected in POST. Note: There is one USB keyboard and one USB mouse detected from the BMC KVM function under this item, even if no USB devices are connected to the system.
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Intel® Server Board S1600JP TPS Setup Item Device Reset timeout Options 10 seconds 20 seconds 30 seconds BIOS Setup Interface Help Text USB Mass Storage device Start Unit command timeout. Setting to a larger value provides more time for a mass storage device to be ready, if needed. Comments If the USB controller setting is Disabled, this field is grayed out and inactive. 40 seconds Mass Storage Devices Auto Floppy ForcedFDD [Auto] - USB devices less than 530 MB are emulated as floppies.
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BIOS Setup Interface Intel® Server Board S1600JP TPS Advanced System Acoustic and Performance Configuration Set Throttling Mode Auto/DCLTT/SCLTT/SOLTT Altitude 300m or less/301m-900m/901m – 1500m/Higher than 1500m Set Fan Profile Performance, Acoustic Fan PWM Offset [0 – 100, 0 is default] Quiet Fan Idle Mode Enabled/Disabled Figure 35. System Acoustic and Performance Configuration 110 Revision 1.
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Intel® Server Board S1600JP TPS BIOS Setup Interface Table 40. Setup Utility – System Acoustic and Performance Configuration Screen Fields Setup Item Set Throttling Mode Options Auto DCLTT SCLTT SOLTT Help Text Sets Thermal Throttling mode for memory, to control fans and DRAM power as needed to control DIMM temperatures. [Auto] –BIOS selects mode.
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BIOS Setup Interface Setup Item Set Fan Profile Options Performance Acoustics Intel® Server Board S1600JP TPS Help Text Comments [Performance] - Fan control provides primary system cooling before attempting to throttle memory. This option allows the user to choose a Fan Profile that is optimized for maximizing performance or for minimizing acoustic noise. [Acoustic] - The system will favor using throttling of memory over boosting fans to cool the system if thermal thresholds are met.
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Intel® Server Board S1600JP TPS 5.4.2.17 BIOS Setup Interface Security Screen (Tab) The Security screen allows the user to enable and set the user and administrative password and to lock out the front panel buttons so that they cannot be used. This screen also allows the user to enable and activate the Trusted Platform Module (TPM) security settings on those boards that support TPM.
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BIOS Setup Interface Setup Item User Password Status Intel® Server Board S1600JP TPS Options Installed Help Text Comments None Information only. Indicates the status of the user password. Administrator password is used if Power On Password is enabled and to control change access in BIOS Setup. Length is 1-14 characters. Case sensitive alphabetic, numeric, and special characters !@#$%^&*()_+=? are allowed. Note: Administrator password must be set in order to use the User account.
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Intel® Server Board S1600JP TPS Setup Item Set User Password Options Entry Field – 0-14 characters BIOS Setup Interface Help Text User password is used if Power On Password is enabled and to allow restricted access to BIOS Setup. Length is 114 characters. Case sensitive alphabetic, numeric, and special characters !@#$%^&*()_+=? are allowed. Note: Removing the administrator password also removes the user password. Power ON Password Enabled Disabled Enable Power On Password support.
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BIOS Setup Interface Setup Item TPM State Intel® Server Board S1600JP TPS Options Help Text None May be: Comments Information only. Shows the current TPM device state. A Disabled TPM device does not execute commands that use the TPM functions and TPM security operations are not available.
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Intel® Server Board S1600JP TPS Main Advanced BIOS Setup Interface Security Server Management Boot Options Boot Manager Assert NMI on SERR Enabled / Disabled Assert NMI on PERR Enabled / Disabled PCIe AER Support Enabled / Disabled Log Correctable Errors Enabled / Disabled Reset on CATERR Enabled / Disabled Reset on ERR2 Enabled / Disabled Resume on AC Power Loss Stay Off / Last state / Power On Power Restore Delay Disabled/Auto/Fixed Power Restore Delay Value 25 Clear System Event
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BIOS Setup Interface Intel® Server Board S1600JP TPS ► System Information ► BMC LAN Configuration Figure 37. Server Management Screen Table 42. Setup Utility – Server Management Configuration Screen Fields Setup Item Assert NMI on SERR Options Enabled Disabled Help Text On SERR, generate an NMI and log an error. Note: [Enabled] must be selected for the Assert NMI on PERR setup option to be visible. Assert NMI on PERR Enabled Disabled On PERR, generate an NMI and log an error.
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Intel® Server Board S1600JP TPS Setup Item Reset on CATERR Options Enabled Disabled BIOS Setup Interface Help Text When enabled system gets reset upon encountering Catastrophic Error (CATERR); when disabled system does not get reset on CATERR. Comments This option controls whether the system will be reset when the “Catastrophic Error” CATERR# signal is held asserted, rather than just pulsed to generate an SMI. This indicates that the processor has encountered a fatal hardware error.
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BIOS Setup Interface Setup Item Resume on AC Power Loss Intel® Server Board S1600JP TPS Options Stay Off Last state Power on Help Text System action to take on AC power loss recovery. [Stay Off] - System stays off. [Last State] - System returns to the same state before the AC power loss. [Power On] - System powers on. Comments This option controls the policy that the BMC will follow when AC power is restored after an unexpected power outage.
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Intel® Server Board S1600JP TPS Setup Item Power Restore Delay Options Disabled Auto Fixed BIOS Setup Interface Help Text Allows a delay in powering up after a power failure, to reduce peak power requirements. The delay can be fixed or automatic between 25-300 seconds. Comments When the AC power resume policy (above) is either Power On or Last State, this option allows a delay to be taken after AC power is restored before the system actually begins to power up.
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BIOS Setup Interface Setup Item Power Restore Delay Value Intel® Server Board S1600JP TPS Options Help Text Comments Entry Field 25 Fixed time period 25-300 seconds for When the power restore policy is – 300, 25 is Power Restore Delay Power On or Last State, and the Power Restore Delay selection is default Fixed, this field allows for specifying how long in seconds that fixed delay will be. When the Power Restore Delay is Disabled or Auto, this field will be grayed out and unavailable.
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Intel® Server Board S1600JP TPS Setup Item O/S Boot Watchdog Timer Options Enabled Disabled BIOS Setup Interface Help Text Comments If enabled, the BIOS programs the watchdog timer with the timeout value selected. If the OS does not complete booting before the timer expires, the BMC resets the system and an error is logged. ® Requires OS support or Intel Management Software. This option controls whether the system will set the BMC Watchdog to detect an apparent hang during OS boot.
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BIOS Setup Interface Intel® Server Board S1600JP TPS Setup Item Options EuP LOT6 OffMode Enabled Disabled Help Text Comments Enable/disable Ecodesign EuP LOT6 “Deep Sleep” Off-Mode for near-zero energy use when powered off. This option controls whether the system goes into “Deep Sleep” or more conventional S5 “Soft-Off” when powered off. “Deep Sleep” state uses less energy than S5 but S5 can start up faster and can allow a Wake on LAN action (which cannot be done from a Deep Sleep state).
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Intel® Server Board S1600JP TPS BIOS Setup Interface Table 43. Setup Utility – Console Redirection Configuration Fields Setup Item Console Redirection Options Disabled Serial Port A Help Text Console redirection allows a serial port to be used for server management tasks. [Disabled] - No console redirection. [Serial Port A] - Configure serial port A for console redirection. Enabling this option disables the display of the Quiet Boot logo screen during POST.
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BIOS Setup Interface Intel® Server Board S1600JP TPS Server Management System Information Board Part Number Board Serial Number System Part Number System Serial Number Chassis Part Number Chassis Serial Number Asset Tag BMC Firmware Revision ME Firmware Revision SDR Revision
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Intel® Server Board S1600JP TPS Setup Item BIOS Setup Interface Options Help Text Comments BMC Firmware Revision BMC FW Rev display None Information only ME Firmware Revision ME FW Rev display None Information only SDR Revision SDR Rev display None Information only UUID UUID display None Information only 5.4.2.
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BIOS Setup Interface Intel® Server Board S1600JP TPS Server Management BMC LAN Configuration Baseboard LAN configuration IP Source Static/Dynamic IP Address [0.0.0.0] Subnet Mask [0.0.0.0] Gateway IP [0.0.0.
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Intel® Server Board S1600JP TPS BIOS Setup Interface IPv6 Prefix Length [0 – 128, 64 is default] BMC DHCP Host Name [DHCP Host Name display/edit] User Configuration User ID anonymous/root/User3/User4/User5 Privilege Callback/ User/Operator/Administrator User status Disable/Enable User Name [User Name display/edit] User Password. Figure 40. BMC LAN Configuration Screen Table 45. Setup Utility – BMC configuration Screen Fields Setup Item IP source Options Static Dynamic Revision 1.
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BIOS Setup Interface Setup Item IP address Options Entry Field 0.0.0.0, 0.0.0.0 is default Intel® Server Board S1600JP TPS Help Text View/Edit IP address. Press to edit. Comments This specifies the IPv4 Address for the Baseboard LAN. There is a separate ® IPv4 Address field for the Intel RMM4 LAN configuration. When IPv4 addressing is used, the initial value for this field is acquired from the BMC.
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Intel® Server Board S1600JP TPS Setup Item Options BIOS Setup Interface Help Text Comments other IPv6 fields will not be visible for the ® Baseboard LAN and Intel RMM4 DMN (if installed). When IPv6 addressing is Enabled, all IPv6 fields for the ® Baseboard LAN and Intel RMM4 DMN will become visible, and all IPv4 fields will be grayed out and inactive. IPv6 Source Static Dynamic Auto Select BMC IPv6 source: If [Static], IPv6 parameters may be edited.
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BIOS Setup Interface Setup Item Options Intel® Server Board S1600JP TPS Help Text 0000:0000 0000:0000 Comments value for this field is acquired from the BMC. The setting of IPv6 Source determines whether this field is displayonly (when Dynamic or Auto) or can be edited (when Static). 0000:0000 0000:0000 is default IPv6 Prefix Length Entry Field 0 – 128, 64 is default View/Edit IPv6 Prefix Length from zero to 128 (default 64). Press to edit.
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Intel® Server Board S1600JP TPS Setup Item IP source Options Static Dynamic BIOS Setup Interface Help Text Select RMM4 IP source: If [Static], IP parameters may be edited. If [Dynamic], these fields are displayonly and IP address is acquired automatically (DHCP). Comments This specifies the IP Source for IPv4 ® addressing for the Intel RMM4 DMN LAN connection. There is a separate IP Source field for the Baseboard LAN configuration.
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BIOS Setup Interface Setup Item Options Intel® Server Board S1600JP TPS Help Text Comments When IPv4 addressing is used, the initial value for this field is acquired from the BMC. The setting of IP Source determines whether this field is displayonly (when Dynamic) or can be edited (when Static). When IPv6 addressing is enabled, this field is grayed out and inactive. IPv6 Source Static Dynamic Auto ® Select Intel RMM4 IPv6 source: If [Static], IPv6 parameters may be edited.
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Intel® Server Board S1600JP TPS Setup Item Options BIOS Setup Interface Help Text Comments 0000:0000 option is set to Enabled. 0000:0000 0000:0000 When IPv6 addressing is used, the initial value for this field is acquired from the BMC. The setting of IPv6 Source determines whether this field is displayonly (when Dynamic or Auto) or can be edited (when Static).
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BIOS Setup Interface Setup Item Privilege Options Callback User Intel® Server Board S1600JP TPS Help Text Comments View/Select user privilege. User2 (root) privilege is "Administrator" and cannot be changed. The level of privilege that is assigned for a User ID affects which functions that user may perform. Enable/Disable LAN access for selected user. Also enables/disables SOL and KVM media redirection. Note that status setting is Disabled by default until set to Enabled.
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Intel® Server Board S1600JP TPS Main Advanced BIOS Setup Interface Security Server Management Boot Options System Boot Timeout <0 – 65535, 0 is default> Boot Option #1 Boot Option #2 Boot Option #n Boot Manager ► Hard Disk Order ► Network Device Order EFI Optimized Boot Enabled/Disabled Use Legacy Video for EFI OS Enabled/Disabled Boot Option Retry Enabled/Disabled USB Boot Priority Enabled/Disabled Static Bo
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BIOS Setup Interface Setup Item Intel® Server Board S1600JP TPS Options Help Text Boot Manager menu and wait for user input for every system boot. Comments the FRB2 setting for BIOS boot failure protection. The FBR2 countdown will be suspended during the time that the Boot Timeout countdown is active.
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Intel® Server Board S1600JP TPS Setup Item Options BIOS Setup Interface Help Text Comments available in the system. EFI Optimized Boot Enabled Disabled Use Legacy Video for EFI OS Enabled Disabled Boot Option Retry Enabled Disabled USB Boot Priority Enabled Disabled Static Boot Ordering Enabled Disabled If enabled, the BIOS only loads modules required for booting EFI-aware Operating Systems. If this option is enabled, the system will not boot successfully to a non-EFI-aware OS.
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BIOS Setup Interface Setup Item Intel® Server Board S1600JP TPS Options Help Text Comments Select Yes to take a snapshot of the current Boot Options list into the Static Boot Options list on the next boot. After saving Static Boot Options list, this option will change back to No Action automatically. This option is available only when the Static Boot Order option is Enabled. Otherwise it will be grayed out and unavailable. 5.4.2.
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Intel® Server Board S1600JP TPS Setup Item Hard Disk #2 5.4.2.24 Options BIOS Setup Interface Help Text Available Hard Disk devices. Comments Set system boot order by selecting the boot option for this position. Choose the order of booting among Hard Disk devices by choosing which available Hard Disk device should be in each position in the order.
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BIOS Setup Interface 5.4.2.25 Intel® Server Board S1600JP TPS Boot Manager Screen (Tab) The Boot Manager screen allows the user to view a list of devices available for booting, and to select a boot device for immediately booting the system. There is no predetermined order for listing bootable devices. They are simply listed in order of discovery. Regardless of whether any other bootable devices are available, the “Internal EFI Shell” will always be available.
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Intel® Server Board S1600JP TPS Setup Item Boot Device #n BIOS Setup Interface Options Help Text None Comments Select this option to boot now. Note: This list is not the system boot option order. Use the Boot Options menu to view and configure the system boot option order. These are names of bootable devices discovered in the system.
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BIOS Setup Interface Setup Item SEVERITY Intel® Server Board S1600JP TPS Options Minor Help Text Comments None Each POST Error Code has a Severity associated with it. Major Fatal INSTANCE Depend on Error Code None Where applicable, this field shows a value indicating which one of a group of components was responsible for generating the POST Error Code that is being reported.
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Intel® Server Board S1600JP TPS Error Manager BIOS Setup Interface Save & Exit Save Changes and Exit Discard Changes and Exit Save Changes Discard Changes Load Default Values Save as User Default Values Load User Default Values *Certain brands and names may be claimed as the property of others. Figure 46. Save & Exit Screen Table 51. Setup Utility – Exit Screen Fields Setup Item Save Changes and Exit Options None Help Text Exit the BIOS Setup utility after saving changes.
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BIOS Setup Interface Setup Item Discard Changes and Exit Intel® Server Board S1600JP TPS Options None Help Text Exit the BIOS Setup utility without saving changes. The [Esc] key can also be used. Comments Selection only. Select this line and press the key to exit Setup without saving any changes in BIOS settings. If there have been no changes made in the settings, the BIOS will resume executing POST. If changes have been made in BIOS settings, a confirmation pop-up will appear.
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Intel® Server Board S1600JP TPS Setup Item Load Default Values Options None BIOS Setup Interface Help Text Load Defaults Values for all the setup options. Comments Selection only. Select this line and press the key to load default values for all BIOS settings. These are the initial factory settings (“failsafe” settings) for all BIOS parameters. There will be a confirmation popup to verify that the user really meant to take this action.
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BIOS Setup Interface Setup Item Load User Default Values Intel® Server Board S1600JP TPS Options None Help Text Load user default values to all the set options. Comments Selection only. Select this line and press the key to load User Default Values for all BIOS settings. These are user-customized BIOS default settings for all BIOS parameters, previously established by doing a “Save User Defaults” action (see above).
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Intel® Server Board S1600JP TPS 6. Configuration Jumpers Configuration Jumpers The following table provides a summary and description of configuration, test, and debug jumpers on the Intel® Server Board S1600JP. The server board has several 3-pin jumper blocks that can be used. Pin 1 on each jumper block can be identified by the following symbol on the silkscreen: Figure 47. Jumper Blocks (J2B1, J2B3, J2B5, J2B6, J2B4, and J2B2) Table 52.
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Configuration Jumpers Intel® Server Board S1600JP TPS Jumper Name Mode of Operation Jumper Position J2B6: Password Clear Note 1-2 Normal Normal mode, password in protection. 2-3 Clear Password BIOS password is cleared. J2B3: BIOS Recovery Mode 1-2 Normal Normal mode. 2-3 Recovery BIOS in recovery mode. J2B2: CPLD Update 1-2 Normal Normal mode. 2-3 Update 1-2 Normal Normal mode. 2-3 Clear BIOS Settings BIOS settings are reset to factory default. J2B5: BIOS Default 6.
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Intel® Server Board S1600JP TPS Configuration Jumpers Note: Normal BMC functionality is disabled with the Force BMC Update jumper is set to the enabled position. You should never run the server with the BMC Force Update jumper set in this position. You should only use this jumper setting when the standard firmware update process fails. This jumper should remain in the default/disabled position when the server is running normally.
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Configuration Jumpers Intel® Server Board S1600JP TPS Table 54. Password Clear Jumper Jumper Position Mode of Operation Note 1-2 Normal Normal mode, password in protection. 2-3 Clear Password BIOS password is cleared. Steps to clear the BIOS password: 1. Power down server. Do not unplug the power cord. 2. Open the chassis. For instructions, see your Server Chassis Documentation. 3.
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Intel® Server Board S1600JP TPS Configuration Jumpers before any video or console is available. Once the system boots to this recovery image file (FVMAIN.FV), it boots automatically into the EFI Shell to invoke the Startup.nsh script and start the flash update application (IFlash32.efi). IFlash32.efi requires the supporting BIOS Capsule image file (*Rec.CAP). After the update is complete, a message displays, stating the BIOS has been updated successfully. This indicates the recovery process is finished.
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Configuration Jumpers 5. 6. 7. 8. Intel® Server Board S1600JP TPS Remove AC power. Move the jumper back to default position, covering pins 1 and 2. Close the server chassis. Power up the server. The BIOS settings are now cleared and you can reset it by going into the BIOS setup. Note: Removing AC Power before performing the BIOS settings Clear operation causes the system to automatically power up and immediately power down, after the procedure is followed and AC power is re-applied.
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Intel® Server Board S1600JP TPS Connector/Header Locations and Pin-out 7. Connector/Header Locations and Pin-out 7.1 Power Connectors To facilitate customers who want to cable to this board from a power supply, the power connectors are implemented through one 10-pin connector and one 8-pin connector. Table 55. Main Power Supply Connector 10-pin 2x5 Connector Pin-Out (J4K1) Pin 1 2 3 4 5 Signal Name PSON GND GND GND 5V Pin Signal Name 6 7 8 9 10 5VSB PWROK 3.3V 3.3V Reserved Table 56.
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Connector/Header Locations and Pin-out 7.2.2 Intel® Server Board S1600JP TPS IPMB Header Table 58. IPMB Header Pin-Out (J6A4) Pin 1 2 3 4 7.2.3 Signal Name SMB_IPMB_5VSB_DAT GND SMB_IPMB_5VSB_CLK P5V_STBY Power Button The BIOS supports a front control panel power button. Pressing the power button initiates a request that the Integrated BMC forwards to the ACPI power state machines in the chipset. It is monitored by the Integrated BMC and does not directly control power on the power supply.
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Intel® Server Board S1600JP TPS 7.2.6 Connector/Header Locations and Pin-out Power LED The green power LED is active when the system DC power is on. The power LED is controlled by the BIOS. The power LED reflects a combination of the state of system (DC) power and the system ACPI state. The following table identifies the different states that the power LED can assume. Table 59. Power LED Indicator States State Power off Power on S5 S1 Sleep S0 7.2.
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Connector/Header Locations and Pin-out Intel® Server Board S1600JP TPS Table 60. System Status LED Color State System Status Green Green Solid on ~1 Hz blink Ok Degraded Amber ~1 Hz blink Non-Fatal Amber Solid on Fatal Off N/A Not ready Description System ready BIOS detected  Unable to use all of the installed memory (more than one 1 DIMM installed).  In a mirrored configuration, when memory mirroring takes place and system loses memory redundancy. This is not 1 covered by (2).
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Intel® Server Board S1600JP TPS 7.2.8 Connector/Header Locations and Pin-out Chassis ID LED The chassis ID LED provides a visual indication of a system being serviced. The state of the chassis ID LED is affected by the following:  Toggled by the chassis ID button  Controlled by the Chassis Identify command (IPMI)  Controlled by the Chassis Identify LED command (OEM) Table 61.
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Connector/Header Locations and Pin-out Pin B9 B10 B11 Pin Name Spare 3.3VAUX WAKE# Description For wake on LAN For wake on LAN Intel® Server Board S1600JP TPS Pin Pin Name A9 A10 A11 3.3V 3.3V PERST# A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 GND REFCLK1+ REFCLK1GND PERxP0 PERxN0 GND 3.
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Intel® Server Board S1600JP TPS Pin B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 Connector/Header Locations and Pin-out Pin Name Description PETxN10 GND GND PETxP11 PETxN11 GND GND PETxP12 PETxN12 GND GND PETxP13 PETxN13 GND GND PETxP14 PETxN14 GND GND PETxP15 PETxN15 GND REFCLK3+ REFCLK3- Tx Lane 10- Pin A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 Tx Lane 11+ Tx Lane 11- Tx Lane 12+ Tx Lane 12-
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Connector/Header Locations and Pin-out Pin B15 B16 B17 B18 B19 Pin Name Intel® Server Board S1600JP TPS Description Pin Pin Name MDIO PERST# WAKE# PETxP0 PETxN0 A15 A16 A17 A18 A19 MDC GND REFCLK+ REFCLKGND B20 B21 B22 GND GND PETxP1 A20 A21 A22 PERxP0 PERxN0 GND B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 PETxN1 GND GND PETxP2 PETxN2 GND GND PETxP3 PETxN3 GND GND PETxP4 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 GND PERxP1 PERxN1 GND GND PERxP2 PERxN2 GND GND PERxP3 PERxN3 GND B3
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Intel® Server Board S1600JP TPS Side Even 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 Revision 1.9 Connector/Header Locations and Pin-out Pin Name PETxN0 GND PETxP1 PETxN1 GND PETxP2 PETxN2 GND PETxP3 PETxN3 GND PETxP4 PETxN4 GND PETxP5 PETxN5 GND PETxP6 PETxN6 GND PETxP7 PETxN7 GND 3.
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Connector/Header Locations and Pin-out Intel® Server Board S1600JP TPS Side Even Pin Name Side Odd Pin Name 15 13 11 9 7 PERxP14 PERxN14 6 PETxN14 GND PETxP15 PETxN15 GND SMBUS_R4 CLK 5 4 2 Spare Spare 3 1 GND SMBUS_R4 DAT Riser ID 16 14 12 10 8 GND PERxP15 PERxN15 Notes: There are 2 PCIe clock references from the riser slot: REFCLK1 and REFCLK2. If the riser is designed as 1 x16 PCIe, BIOS will only enable REFCLK1 and disable REFCLK2.
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Intel® Server Board S1600JP TPS Pin 7.3.4 Connector/Header Locations and Pin-out Signal Name Pin Signal Name 3 Green 4 G_RTN (Green Return) 5 Blue 6 B_RTN (Blue Return) 7 Vsync 8 GND 9 Hsync 10 KEY 11 DDC_SDA 12 VIDEO_IN_USE signal 13 DDC_SCL 14 +5V (fused, not populated) NIC Connectors The server board provides four RJ-45 connectors on the back edge of the board (JA4A1 and JA3A1). The pin-out for NIC connectors are identical and are defined in the following table. Table 67.
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Connector/Header Locations and Pin-out Intel® Server Board S1600JP TPS Pin 2 3 4 5 6 7 7.3.6 Signal Name SATA_TX_DP SATA_TX_DN GND SATA_RX_DN SATA_RX_DP GND Mini SAS Connector The server board provides one mini SAS port connector (J2D2). Table 69. Mini SAS Connector Pin-Out (J2D2) Pin 7.3.
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Intel® Server Board S1600JP TPS 7.3.8 Connector/Header Locations and Pin-out Hard Drive Activity (Input) LED Header Table 71. SATA HDD Activity (Input) LED Header (J6F1) Pin Description 1 2 7.3.9 LED_HD_ACTIVE_L NC Storage Upgrade Key Connector The server board provides one SATA/SAS storage upgrade key connector (J3E1) on board.
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Connector/Header Locations and Pin-out Intel® Server Board S1600JP TPS Pin 4 Signal Name GND One Type A USB connector on the server board provide an option to support UBS device. The pin-out is detailed in the following table. Table 75. Type A USB connector Pin-Out (J1D2) Pin Signal Name 1 2 3 4 +5V USB_N USB_P GND Two 2x5 connectors on the server board provide an option to support four additional internal USB ports (J6E2 and J2D1). The pin-out is detailed in the following table and so on. Table 76.
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Intel® Server Board S1600JP TPS 7.3.13 Connector/Header Locations and Pin-out SSI Front Panel Header The server board provides one front panel header (J6H1) to support the standard Scythe pin-out is defined in the following table and so on. Table 78. SSI Front Panel Header Pin-Out (J6H1) Pin 7.3.14 SSI Signal name Pin SSI Signal Name 1 3 5 7 9 11 13 15 17 19 21 23 SB3.3V Key Power LED Cathode 3.
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Connector/Header Locations and Pin-out 7.4 Intel® Server Board S1600JP TPS Fan Headers The server board provides six 8 pin fan headers (J1K1, J1K2, J3K1, J4K2, J6K2, and J6K3). The following table defined the pin-out. Table 81. Baseboard Fan Connector Pin-Out (J1K1, J1K2, J3K1, J4K2, J6K2, and J6K3) Pin 7.5 Signal Name 1 GND 2 12V 3 Tachx 4 PWMy 5 GND 6 12V 7 Tachz 8 PWMy Fan Domain Mapping S1600JP has six system fan connector can connector 12 fans.
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Intel® Server Board S1600JP TPS 7.6 Connector/Header Locations and Pin-out Chassis Intrusion The Chassis Intrusion header is connected through a two wire cable to a switch assembly that is mounted just under the chassis cover on systems that support this feature. When the chassis cover is removed, the switch and thus the electrical connection between the pins on this header become open allowing the Emulex* PILOT III BMC’s CHASIS_N pin to be pulled LOW.
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Intel® Light-Guided Diagnostics 8. Intel® Server Board S1600JP TPS Intel® Light-Guided Diagnostics Intel® Server Board S1600JP has several onboard diagnostic LEDs to assist in troubleshooting board-level issues. This section provides a description the location and function of each LED on the server board. 8.1 Front Panel Support The Intel® Server Board S1600JP supports the front panel and control signals which are provided through bridge board.
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Intel® Server Board S1600JP TPS 8.1.3 Intel® Light-Guided Diagnostics Network Link/Activity LED The server board provides LED on the front panel for Network Link/Activity. The following table shows the LED details: Table 84. Network link/activity LED LED Color LAN Link/Activity 8.
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Environmental Limits Specifications 9. Intel® Server Board S1600JP TPS Environmental Limits Specifications Operation of the server board at conditions beyond those shown in the following table may cause permanent damage to the system. Exposure to absolute maximum rating conditions for extended periods may affect long term system reliability. Note: The Energy Star compliance is at the systems level and not the board level. Use of Intel® boards alone does not guarantee Energy Star compliance. Table 85.
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Intel® Server Board S1600JP TPS 9.1 Environmental Limits Specifications Processor Thermal Design Power (TDP) Support To allow optimal operation and long-term reliability of Intel® processor-based systems, the processor must remain within the defined minimum and maximum case temperature (TCASE) specifications. Thermal solutions not designed to provide sufficient thermal capability may affect the long-term reliability of the processor and system.
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Power Supply Specification Guidelines Intel® Server Board S1600JP TPS 10. Power Supply Specification Guidelines This section provides power supply specification guidelines recommended for providing the specified server platform with stable operating power requirements. And the introduction of how to power ON the server with standard SSI ATX or EPS power supply. Note: The power supply data provided in this section is for reference purposes only.
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Intel® Server Board S1600JP TPS 2. Power Supply Specification Guidelines Length of time peak power can be supported is based on thermal sensor and assertion of the SMBAlert# signal. Minimum peak power duration shall be 20 seconds without asserting the SMBAlert# signal at maximum operating temperature. 10.2.2 Standby Output The standby output shall be present when an AC input greater than the power supply turn on voltage is applied. There should be load sharing in the standby rail. 10.2.
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Power Supply Specification Guidelines Intel® Server Board S1600JP TPS The power supply shall be provided with a reliable protective earth ground. All secondary circuits shall be connected to protective earth ground. Resistance of the ground returns to chassis shall not exceed 1.0 mΩ. This path may be used to carry DC current. 10.2.7 Closed loop stability The power supply shall be unconditionally stable under all line/load/transient load conditions including specified capacitive load ranges.
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Intel® Server Board S1600JP TPS Power Supply Specification Guidelines between power supplies (passive sharing). The 12VSB output of the power supplies are connected together in the system so that a failure or hot swap of a redundant power supply does not cause these outputs to go out of regulation in the system. 10.2.14 Ripple/Noise The maximum allowed ripple/noise output of the power supply is defined in the following table.
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Power Supply Specification Guidelines Intel® Server Board S1600JP TPS AC Input Tvout_holdup Vout Tpwok_low TAC_on_delay Tsb_on_delay Tpwok_on PWOK 12Vsb Tpwok_off Tsb_on_delay Tpwok_on Tpwok_holdup Tsb_vout Tpwok_off Tpson_pwok T5Vsb_holdup Tpson_on_delay PSON AC turn on/off cycle PSON turn on/off cycle Figure 50. 750W Turn On/Off Timing (Power Supply Signals) 10.
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Intel® Server Board S1600JP TPS Power Supply Specification Guidelines power supply P1 Conn(2X12pin baseboard power connector) to 2X5 pin connector which can be connected to S1600JP main power connector 1. The other 2X4 pin power connector from power supply can connect to S1600JP main power connector 2 directly. Figure 52. 2X12pin to 2X5 pin Power Adapter Cable  2X12 pin connector pin-out Figure 53. 2X12 Power Connector Pin Number Revision 1.
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Power Supply Specification Guidelines Intel® Server Board S1600JP TPS Table 94. 2X12 Pin Power Connector Pin-Out Pin Signal Name 18 AWG Color 12 24 11 23 10 22 9 5VSB Purple 21 8 PWROK Gray 20 7 GND Black 19 6 Signal Name 18 AWG Color PSON Green +3.3V Orange 18 5 GND Black 17 4 +5V Red 16 3 GND Black 15 2 +3.3V Orange 14 1  Pin 13 2X5 pin connector pin-out Figure 54. 2X5 Pin Number Table 95.
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Intel® Server Board S1600JP TPS  Power Supply Specification Guidelines 2X12 connector to 2X5 connector mapping tab Table 96. 2X12 Pin to 2X5 Pin Connector Mapping Table Connect the power adapter cable 2X12 pin connector to power supply P1 Conn(2X12pin baseboard power connector) and connect the other side to S1600JP main power 1. Connect power supply P2 Conn (2X4 pin processor/memory power connector) to S1600JP main power 2, and then the server board is ready to be power ON.
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Appendix A: Integration and Usage Tips Intel® Server Board S1600JP TPS Appendix A: Integration and Usage Tips  When adding or removing components or peripherals from the server board, AC power must be removed. With AC power plugged into the server board, 5-V standby is still present even though the server board is powered off.
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Intel® Server Board S1600JP TPS Appendix B: Integration BMC Sensor Tables Appendix B: Integrated BMC Sensor Tables This appendix lists the sensor identification numbers and information about the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 2.0, for sensor and event/reading-type table information.
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Appendix B: Integration BMC Sensor Tables  Intel® Server Board S1600JP TPS Rearm Sensors The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states. Rearming the sensors can be done manually or automatically. This column indicates the type supported by the sensor.
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Intel® Server Board S1600JP TPS Appendix B: Integration BMC Sensor Tables Note: All sensors listed as follows may not be present on all platforms. Please check platform EPS section for platform applicability and platform chassis section for chassis specific sensors. Redundancy sensors will be only present on systems with appropriate hardware to support redundancy (for instance, fan or power supply). Table 97.
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Appendix B: Integration BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Sensor # Security (Physical Scrty) Intel® Server Board S1600JP TPS Platform Applicability Sensor Type Event/ Reading Type Intrusion is chassisspecific Security 05h Specific 6Fh 04 - LAN leash lost OK De OK As – Fatal As and De 02 - Log area reset/cleared OK 04 – PEF action Event Offset Triggers FP Interrupt (FP NMI Diag Int) 05h Chassis specific Critical Interrupt 13h Sensor Specific 6Fh 00 - Front pa
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Intel® Server Board S1600JP TPS Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Appendix B: Integration BMC Sensor Tables Sensor Type Event/ Reading Type Redundancy) SSB Thermal Trip (SSB Therm Trip) IO Module Presence (IO Mod Presence) 0Dh All Temperat ure Digital Discrete 01h 03h Event Offset Triggers Contrib. To System Status Assert/ De-assert Readable Value/ Offsets Event Data Rearm Standby 03 - Non-redundant: Sufficient resources.
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Appendix B: Integration BMC Sensor Tables Full Sensor Name (Sensor name in SDR) FW Update Status IO Module2 Presence (IO Mod2 Presence) Baseboard Temperature 5 (Platform Specific) Baseboard Temperature 6 (Platform Specific) IO Module2 Temperature (I/O Mod2 Temp) PCI Riser 3 Temperature (PCI Riser 5 Temp) PCI Riser 4 Temperature (PCI Riser 4 Temp) Baseboard +1.05V Processor3 Vccp (BB +1.
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Intel® Server Board S1600JP TPS Full Sensor Name (Sensor name in SDR) Baseboard +1.05V Processor4 Vccp (BB +1.05Vccp P4) Baseboard Temperature 1 (Platform Specific) Front Panel Temperature (Front Panel Temp) SSB Temperature (SSB Temp) Baseboard Temperature 2 (Platform Specific) Baseboard Temperature 3 (Platform Specific) Baseboard Temperature 4 (Platform Specific) IO Module Temperature (I/O Mod Temp) Revision 1.
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Appendix B: Integration BMC Sensor Tables Full Sensor Name (Sensor name in SDR) PCI Riser 1 Temperature (PCI Riser 1 Temp) IO Riser Temperature (IO Riser Temp) Hot-swap Backplane 1 Temperature (HSBP 1 Temp) Hot-swap Backplane 2 Temperature (HSBP 2 Temp) Hot-swap Backplane 3 Temperature (HSBP 3 Temp) PCI Riser 2 Temperature (PCI Riser 2 Temp) SAS Module Temperature (SAS Mod Temp) Exit Air Temperature (Exit Air Temp) 192 Sensor Type Event/ Reading Type 27h Platformspecific Temperat ure 01h Threshold 0
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Intel® Server Board S1600JP TPS Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Appendix B: Integration BMC Sensor Tables Sensor Type Event/ Reading Type Threshold 01h Network Interface Controller Temperature (LAN NIC Temp) 2Fh All Temperat ure 01h Fan Tachometer Sensors (Chassis specific sensor names) 30h– 3Fh Chassis and Platform Specific Fan 04h Fan Present Sensors (Fan x Present) 40h– 4Fh Chassis and Platform Specific Fan 04h Power Supply 1 Note2 Status 50h (PS1
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Appendix B: Integration BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Intel® Server Board S1600JP TPS Sensor Type Event/ Reading Type Power Supply 1 +12V % of Maximum Current Output 58h (PS1 Curr Out %) Chassisspecific Current 03h Threshold 01h Power Supply 2 +12V % of Maximum Current Output 59h (PS2 Curr Out %) Chassisspecific Current 03h Threshold 01h Power Supply 1 Temperature 5Ch (PS1 Temperature) Chassisspecific Temperat ure 01h Threshold 01h
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Intel® Server Board S1600JP TPS Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Appendix B: Integration BMC Sensor Tables Sensor Type Event/ Reading Type Event Offset Triggers Contrib.
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Appendix B: Integration BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Processor 3 Thermal Control % (P3 Therm Ctrl %) Sensor # 7Ah Platform Applicability Intel® Server Board S1600JP TPS Sensor Type Event/ Reading Type Event Offset Triggers Platformspecific Temperat ure 01h Threshold 01h [u] [c,nc] Threshold 01h [u] [c,nc] Contrib.
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Intel® Server Board S1600JP TPS Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Appendix B: Integration BMC Sensor Tables Sensor Type Event/ Reading Type Event Offset Triggers Contrib.
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Appendix B: Integration BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Processor 3 VRD Temperature Sensor # Platform Applicability Processor 1 Memory VRD Hot 2-3 (P1 Mem23 VRD Hot) Processor 2 Memory VRD Hot 0-1 (P2 Mem01 VRD Hot) Processor 2 Memory VRD Hot 2-3 (P2 Mem23 VRD Hot) 198 Event/ Reading Type Event Offset Triggers Contrib.
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Intel® Server Board S1600JP TPS Full Sensor Name (Sensor name in SDR) Processor 3 Memory VRD Hot 0-1 (P3 Mem01 VRD Hot) Processor 3 Memory VRD Hot 2-3 (P4 Mem23 VRD Hot) Processor 4 Memory VRD Hot 0-1 (P4 Mem01 VRD Hot) Processor 4 Memory VRD Hot 2-3 (P4 Mem23 VRD Hot) Sensor # Sensor Type Event/ Reading Type Event Offset Triggers Contrib.
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Appendix B: Integration BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Sensor # Power Supply 2 Fan A5h Tachometer 2 (PS2 Fan Tach 2) Processor 1 DIMM Aggregate Thermal Margin B0h 1 (P1 DIMM Thrm Mrgn1) Processor 1 DIMM Aggregate Thermal Margin B1h 2 (P1 DIMM Thrm Mrgn2) Processor 2 DIMM Aggregate Thermal Margin B2h 1 (P2 DIMM Thrm Mrgn1) Processor 2 DIMM Aggregate Thermal Margin B3h 2 (P2 DIMM Thrm Mrgn2) 200 Platform Applicability Intel® Server Board S1600JP TPS Sensor Type Event/ Reading
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Intel® Server Board S1600JP TPS Full Sensor Name (Sensor name in SDR) Sensor # Processor 3 DIMM Aggregate Thermal Margin B4h 1 (P3 DIMM Thrm Mrgn1) Processor 3 DIMM Aggregate Thermal Margin B5h 2 (P3 DIMM Thrm Mrgn2) Processor 4 DIMM Aggregate Thermal Margin B6h 1 (P4 DIMM Thrm Mrgn1) Platform Applicability Platform Specific Platform Specific Platform Specific Appendix B: Integration BMC Sensor Tables Sensor Type Temperat ure 01h Temperat ure 01h Temperat ure 01h Event/ Reading Type Threshold
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Appendix B: Integration BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Processor 1 DIMM Thermal Trip (P1 Mem Thrm Trip) Processor 2 DIMM Thermal Trip (P2 Mem Thrm Trip) Processor 3 DIMM Thermal Trip (P3 Mem Thrm Trip) Processor 4 DIMM Thermal Trip (P4 Mem Thrm Trip) Global Aggregate Temperature Margin 1 (Agg Therm Mrgn 1) 202 Sensor # Platform Applicability Intel® Server Board S1600JP TPS Sensor Type Event/ Reading Type Event Offset Triggers Contrib.
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Intel® Server Board S1600JP TPS Full Sensor Name (Sensor name in SDR) Global Aggregate Temperature Margin 2 (Agg Therm Mrgn 2) Global Aggregate Temperature Margin 3 (Agg Therm Mrgn 3) Global Aggregate Temperature Margin 4 (Agg Therm Mrgn 4) Global Aggregate Temperature Margin 5 (Agg Therm Mrgn 5) Global Aggregate Temperature Margin 6 (Agg Therm Mrgn 6) Revision 1.
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Appendix B: Integration BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Global Aggregate Temperature Margin 7 (Agg Therm Mrgn 7) Global Aggregate Temperature Margin 8 (Agg Therm Mrgn 8) Baseboard +12V (BB +12.0V) Baseboard +5V (BB +5.0V) Baseboard +3.3V (BB +3.3V) Baseboard +5V Stand-by (BB +5.0V STBY) Baseboard +3.3V Auxiliary (BB +3.3V AUX) 204 Sensor # Platform Applicability Intel® Server Board S1600JP TPS Sensor Type Event/ Reading Type Event Offset Triggers Contrib.
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Intel® Server Board S1600JP TPS Full Sensor Name (Sensor name in SDR) Baseboard +1.05V Processor1 Vccp (BB +1.05Vccp P1) Baseboard +1.05V Processor2 Vccp (BB +1.05Vccp P2) Baseboard +1.5V P1 Memory AB VDDQ (BB +1.5 P1MEM AB) Baseboard +1.5V P1 Memory CD VDDQ (BB +1.5 P1MEM CD) Baseboard +1.5V P2 Memory AB VDDQ (BB +1.5 P2MEM AB) Baseboard +1.5V P2 Memory CD VDDQ (BB +1.5 P2MEM CD) Revision 1.
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Appendix B: Integration BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Baseboard +1.8V Aux (BB +1.8V AUX) Baseboard +1.1V Stand-by (BB +1.1V STBY) Baseboard CMOS Battery (BB +3.3V Vbat) Baseboard +1.35V P1 Low Voltage Memory AB VDDQ (BB +1.35 P1LV AB) Baseboard +1.35V P1 Low Voltage Memory CD VDDQ (BB +1.35 P1LV CD) Baseboard +1.35V P2 Low Voltage Memory AB VDDQ (BB +1.
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Intel® Server Board S1600JP TPS Full Sensor Name (Sensor name in SDR) Baseboard +1.35V P2 Low Voltage Memory CD VDDQ (BB +1.35 P2LV CD) Sensor # Platform Applicability Appendix B: Integration BMC Sensor Tables Sensor Type Event/ Reading Type E7h All Voltage 02h EAh Platform Specific Voltage 02h EBh Platform Specific Voltage 02h Threshold 01h ECh Platform Specific Voltage 02h Threshold 01h EDh Platform Specific Voltage 02h Threshold 01h Baseboard +1.1V EEh (BB 1.
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Appendix B: Integration BMC Sensor Tables Full Sensor Name (Sensor name in SDR) (HDD 0 - 14 Status) Sensor # FEh Platform Applicability Intel® Server Board S1600JP TPS Sensor Type Event/ Reading Type 6Fh Event Offset Triggers 07 - Rebuild/Remap in progress Contrib. To System Status Assert/ De-assert Readable Value/ Offsets Event Data Rearm Standby Degraded Notes: 1. 2. 3.
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Intel® Server Board S1600JP TPS Appendix C: BIOS Sensors and SEL Data Appendix C: BIOS Sensors and SEL Data BIOS owns a set of IPMI-compliant Sensors. These are actually divided in ownership between BIOS POST (GID = 01) and BIOS SMI Handler (GID = 33). The SMI Handler Sensors are typically for logging runtime error events, but they are active during POST and may log errors such as Correctable Memory ECC Errors if they occur.
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Appendix C: BIOS Sensors and SEL Data Sensor Name Memory RAS Configuration Status Sensor Number 02h Sensor Owner (GID) 01h (BIOS POST) Intel® Server Board S1600JP TPS Sensor Type 0Ch (Memory) Event/Reading Type Event Data 2 Offset Values Event Data 3 09h (Digital Discrete) 0h = RAS Configuration Disabled 1h = RAS Configuration Enabled ED2 = [7:4] = Reserved [3:0] Config Err 0 = None 3 = Invalid DIMM Config for RAS Mode ED3 = [7:4] = Reserved [3:0] = RAS Mode 0 = None 1 = Mirroring 2 = Lockstep
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Intel® Server Board S1600JP TPS Sensor Name Sensor Number PCIe Fatal Error (Standard AER Errors) (see Sensor 14h for continuation) 04h PCIe Correctable Error (Standard AER Errors) 05h BIOS POST Error 06h Revision 1.
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Appendix C: BIOS Sensors and SEL Data Sensor Name QPI Correctable Errors (reserved for Validation) Sensor Number 06h Sensor Owner (GID) 33h (SMI Handler) Intel® Server Board S1600JP TPS Sensor Type 13h (Critical Interrupt) Event/Reading Type Event Data 2 Offset Values Event Data 3 72h (OEM Discrete) Offset Reserved ED2 = [7:0] = Node ID 0-3 = CPU1-4 ED3 = Reserved QPI Fatal Error (see Sensor 17h for continuation) 07h Chipset Proprietary (reserved for Validation) 08h QPI Link Width Reduced
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Intel® Server Board S1600JP TPS Sensor Name Sparing Redundancy State Sensor Number 11h Appendix C: BIOS Sensors and SEL Data Sensor Owner (GID) 33h (SMI Handler) Sensor Type 0Ch (Memory) Event/Reading Type Event Data 2 Offset Values Event Data 3 0Bh (Discrete, Redundancy State) 0h = Fully Redundant 2h = Redundancy Degraded ED2 = [7:4] = Sparing Domain 0-3 = Channel A-D for Socket [3:2] = Reserved [1:0] = Rank on DIMM 0-3 = Rank Number ED3 = [7:5]= Socket ID 0-3 = CPU1-4 [4:3] = Channel 0-3 = Ch
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Appendix C: BIOS Sensors and SEL Data Sensor Name Memory Parity Error Sensor Number 13h Sensor Owner (GID) 33h (SMI Handler) Intel® Server Board S1600JP TPS Sensor Type 0Ch (Memory) Event/Reading Type Event Data 2 Offset Values Event Data 3 6Fh (Sensor Specific Offset) 2h = Address Parity Error ED2 = Validity [7:5] = Reserved [4] = Channel Validity Check 0 = ED3 Chan # Not Valid 1 = ED3 Chan # Is Valid [3] = DIMM Validity Check 0 = ED3 DIMM # Not Valid 1 = ED3 DIMM # Is Valid [2:0] = Error Type
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Intel® Server Board S1600JP TPS Sensor Name QPI Fatal Error (continuation of Sensor 07h) System Event Sensor Number 17h 83h Appendix C: BIOS Sensors and SEL Data Sensor Owner (GID) 33h (SMI Handler) 01h (BIOS POST) Sensor Type 13h (Critical Interrupt) 12h (System Event) Event/Reading Type Event Data 2 Offset Values Event Data 3 74h (OEM Discrete) 0h = Illegal inbound request 1h = IIO Write Cache Uncorrectable Data ECC Error 2h = IIO CSR crossing 32-bit boundary Error 3h = IIO Received XPF ph
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Appendix D: POST Code LED Decoder Intel® Server Board S1600JP TPS Appendix D: POST Code LED Decoder During the system boot process, the BIOS executes several platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the POST code on the POST code diagnostic LEDs found on the back edge of the server board.
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Intel® Server Board S1600JP TPS Appendix D: POST Code LED Decoder MSB LSB LED #7 LED #6 LED #5 LED #4 LED #3 LED #2 LED #1 LED #0 8h 4h 2h 1h 8h 4h 2h 1h Status ON OFF ON OFF ON ON OFF OFF Results 1 Ah 0 1 0 1 Ch 1 0 0 Upper nibble bits = 1010b = Ah; Lower nibble bits = 1100b = Ch; the two are concatenated as ACh. Table 100.
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Appendix D: POST Code LED Decoder Intel® Server Board S1600JP TPS Table 101.
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Intel® Server Board S1600JP TPS Appendix D: POST Code LED Decoder Progress Code Description 0x09 End Of Sec Phase 0x0E Microcode Not Found 0x0F Microcode Not Loaded PEI Phase 0x10 PEI Core 0x11 CPU PEIM 0x15 NB PEIM 0x19 SB PEIM MRC Progress Codes At this point the MRC Progress Code sequence is executed See Table 101 0x31 Memory Installed 0x32 CPU PEIM (CPU Init) 0x33 CPU PEIM (Cache Init) 0x34 CPU PEIM (BSP Select) 0x35 CPU PEIM (AP Init) 0x36 CPU PEIM (CPU SMM Init) 0x4F Dxe
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Appendix D: POST Code LED Decoder Intel® Server Board S1600JP TPS Progress Code 220 Description 0x90 DXE BDS Started 0x91 DXE BDS connect drivers 0x92 DXE PCI Bus begin 0x93 DXE PCI Bus HPC Init 0x94 DXE PCI Bus enumeration 0x95 DXE PCI Bus resource requested 0x96 DXE PCI Bus assign resource 0x97 DXE CON_OUT connect 0x98 DXE CON_IN connect 0x99 DXE SIO Init 0x9A DXE USB start 0x9B DXE USB reset 0x9C DXE USB detect 0x9D DXE USB enable 0xA1 DXE IDE begin 0xA2 DXE IDE reset
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Intel® Server Board S1600JP TPS Appendix D: POST Code LED Decoder Progress Code Description 0xB3 DXE Reset system 0xB4 DXE USB Hot plug 0xB5 DXE PCI BUS Hot plug 0xB6 DXE NVRAM cleanup 0xB7 DXE Configuration Reset 0x00 INT19 S3 Resume 0xE0 S3 Resume PEIM (S3 started) 0xE1 S3 Resume PEIM (S3 boot script) 0xE2 S3 Resume PEIM (S3 Video Repost) 0xE3 S3 Resume PEIM (S3 OS wake) BIOS Recovery Revision 1.
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Appendix E: Video POST Code Errors Intel® Server Board S1600JP TPS Appendix E: Video POST Code Errors Whenever possible, the BIOS outputs the current boot progress codes on the video screen. Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. The class and subclass fields point to the type of hardware being initialized. The operation field represents the specific initialization activity.
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Intel® Server Board S1600JP TPS Appendix E: Video POST Code Errors Error Code 8161 Error Message Processor 02 unable to apply microcode update Response Major 8162 Processor 03 unable to apply microcode update Major 8163 Processor 04 unable to apply microcode update Major 8170 Processor 01 failed Self Test (BIST) Major 8171 Processor 02 failed Self Test (BIST) Major 8172 Processor 03 failed Self Test (BIST) Major 8173 Processor 04 failed Self Test (BIST) Major 8180 Processor 01 microc
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Appendix E: Video POST Code Errors Intel® Server Board S1600JP TPS Error Code 8536 DIMM_H2 failed test/initialization Response Major 8537 DIMM_H3 failed test/initialization Major 8538 DIMM_J1 failed test/initialization Major 8539 DIMM_J2 failed test/initialization Major 853A DIMM_J3 failed test/initialization Major 853B DIMM_K1 failed test/initialization Major 853C DIMM_K2 failed test/initialization Major 853D DIMM_K3 failed test/initialization Major 853E DIMM_L1 failed test/initi
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Intel® Server Board S1600JP TPS Appendix E: Video POST Code Errors Error Code 8560 Error Message DIMM_A1 encountered a Serial Presence Detection (SPD) failure Response Major 8561 DIMM_A2 encountered a Serial Presence Detection (SPD) failure Major 8562 DIMM_A3 encountered a Serial Presence Detection (SPD) failure Major 8563 DIMM_B1 encountered a Serial Presence Detection (SPD) failure Major 8564 DIMM_B2 encountered a Serial Presence Detection (SPD) failure Major 8565 DIMM_B3 encountered a S
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Appendix E: Video POST Code Errors Intel® Server Board S1600JP TPS Error Code 85CB DIMM_R2 failed test/initialization Response Major 85CC DIMM_R3 failed test/initialization Major 85CD DIMM_T1 failed test/initialization Major 85CE DIMM_T2 failed test/initialization Major 85CF DIMM_T3 failed test/initialization Major 85D0 DIMM_L3 disabled Major 85D1 DIMM_M1 disabled Major 85D2 DIMM_M2 disabled Major 85D3 DIMM_M3 disabled Major 85D4 DIMM_N1 disabled Major 85D5 DIMM_N2 disabled
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Intel® Server Board S1600JP TPS Appendix E: Video POST Code Errors Error Code A002 TPM device failure. Response Minor A003 TPM device failed self test. Minor A100 BIOS ACM Error Major A421 PCI component encountered a SERR error Fatal A5A0 PCI Express component encountered a PERR error Minor A5A1 PCI Express component encountered an SERR error Fatal A6A0 DXE Boot Services driver: Not enough memory available to shadow a Legacy Option ROM. Minor Revision 1.
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Glossary Intel® Server Board S1600JP TPS Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (for example, “82460GX”) with alpha entries following (for example, “AGP 4x”). Acronyms are then entered in their respective place, with non-acronyms following. Table 104.
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Intel® Server Board S1600JP TPS Term Definition HPA Host Physical Address Hz Hertz (1 cycle/second) 2 IC Inter-Integrated Circuit Bus IA Intel Architecture IBF Input Buffer ICH I/O Controller Hub IC MB Intelligent Chassis Management Bus IFB I/O and Firmware Bridge ILM Independent Loading Mechanism IMC Integrated Memory Controller INTR Interrupt IP Internet Protocol IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface IR Infrared ITP In-Ta
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Glossary Term Intel® Server Board S1600JP TPS Definition PSMI Power Supply Management Interface PWM Pulse-Width Modulation QPI QuickPath Interconnect RAM Random Access Memory RASUM Reliability, Availability, Serviceability, Usability, and Manageability RISC Reduced Instruction Set Computing ROM Read Only Memory RTC Real-Time Clock (Component of ICH peripheral chip on the server board) RMM3 Remote Management Module 3 SDR Sensor Data Record SECC Single Edge Connector Cartridge SEEPRO
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Intel® Server Board S1600JP TPS Reference Documents Reference Documents  ACPI 3.0: http://www.acpi.info/spec.htm  IPMI 2.0  Data Center Management Interface Specification v1.0, May 1, 2008: www.intel.com/go/dcmi  PCI Bus Power Management Interface Specification 1.1: http://www.pcisig.com/  PCI Express* Base Specification Rev 2.0 Dec 06: http://www.pcisig.com/  PCI Express* Card Electromechanical Specification Rev 2.0: http://www.pcisig.com/  PMBus*: http://pmbus.org  SATA 2.