Technical Product Specification

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Intel

Server Board S1400SP

Intel order number G64248-003

Revision 2.1

May, 2014

Summary of content (162 pages)

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Intel® Server Board S1400SP Technical Product Specification Intel order number G64248-003 Revision 2.
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Revision History Intel® Server Board S1400SP TPS Revision History Date September, 2012 Revision Number 1.0 December, 2013 2.0  In Table 1, add a note that SAS Module and eUSB SSD can’t be supported at the same time. ® ®  Added support for Intel Xeon processor E5-2400 v2 product family May, 2014 2.1 Added PCI Express* Lane Mapping. ii Modifications Initial release. Intel order number G64248-003 Revision 2.
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Intel® Server Board S1400SP TPS Disclaimers Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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Table of Contents Intel® Server Board S1400SP TPS Table of Contents 1. Introduction .......................................................................................................................... 1 1.1 Chapter Outline........................................................................................................ 1 1.2 Server Board Use Disclaimer .................................................................................. 1 2. Overview .............................................
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Intel® Server Board S1400SP TPS 6.1.1 6.1.2 6.1.3 6.2 6.3 6.3.1 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.11.1 6.11.2 6.11.3 6.11.4 6.11.5 6.11.6 6.11.7 6.11.8 6.11.9 6.12 6.12.1 6.12.2 6.12.3 6.12.4 6.12.5 6.12.6 6.12.7 6.12.8 6.12.9 6.12.10 6.12.11 6.12.12 6.12.13 6.12.14 6.12.15 6.12.16 6.12.17 Revision 2.1 Table of Contents IPMI 2.0 Features .................................................................................................. 47 Non IPMI Features ..............................................
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Table of Contents Intel® Server Board S1400SP TPS 7. Advanced Management Feature Support (RMM4)........................................................... 75 7.1 Keyboard, Video, Mouse (KVM) Redirection ......................................................... 76 7.1.1 Remote Console .................................................................................................... 77 7.1.2 Performance ......................................................................................................
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Intel® Server Board S1400SP TPS Table of Contents 10.2 System Status LED ................................................................................................ 97 10.3 BMC Boot/Reset Status LED Indicators ................................................................ 99 10.4 Post Code Diagnostic LEDs .................................................................................. 99 10.5 5 Volt Stand-By Present LED .............................................................................
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List of Figures Intel® Server Board S2400SC TPS List of Figures Figure 1. Intel® Server Board S1400SP4 Layout .......................................................................... 4 Figure 2. Intel® Server Board S1400SP Layout ............................................................................ 5 Figure 3. Jumper Block Identification ............................................................................................ 5 Figure 4.
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Intel® Server Board S1400SP TPS List of Tables List of Tables Table 1. Intel® Server Board S1400SP Feature Set ..................................................................... 2 Table 2. UDIMM Support Guidelines .......................................................................................... 18 Table 3. RDIMM Support Guidelines .......................................................................................... 18 Table 4. Intel® Server Board S1400SP DIMM Nomenclature ................
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List of Tables Intel® Server Board S1400SP TPS Table 40. SGPIO Header Pin-out ............................................................................................... 89 Table 41. VGA Connector Pin-out .............................................................................................. 89 Table 42. RJ-45 10/100/1000 NIC Connector Pin-out ................................................................ 90 Table 43. External USB Connector Pin-out ............................................
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Intel® Server Board S1400SP TPS List of Tables Revision 2.
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Intel® Server Board S1400SP TPS 1. Introduction Introduction This Technical Product Specification (TPS) provides board specific information detailing the features, functionality, and high-level architecture of the Intel® Server Board S1400SP. In addition, you can obtain design-level information for specific subsystems by ordering the External Product Specifications (EPS) or External Design Specifications (EDS) for a given subsystem.
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Overview 2. Intel® Server Board S1400SP TPS Overview The Intel® Server Board S1400SP is monolithic printed circuit boards (PCBs) with features designed to support the 1U rack server markets. This server board is designed to support the Intel® Xeon® processor E5-2400 product family. Previous generation Intel® Xeon® processors are not supported. 2.1 Intel® Server Boards S1400SP Feature Set Table 1.
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Intel® Server Board S1400SP TPS Feature Overview Description  Dual SFP+ port 10GbE module based on Intel® 82599 10 GbE controller – AXX10GBNIAIOM  Single Port FDR 56GT/S speed InfiniBand* module with QSFP connector – AXX1FDRIBIOM  Dual port FDR 56GT/S speed InfiniBand* module with QSFP connector – AXX2FDRIBIOM Hard Drive and Optical Drive Support     RAID Support  Intel ® RSTe SW RAID 0/1/10/5  LSI* SW RAID 0/1/10/5 Video Support  Integrated 2D video controller.
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Overview 2.2 Intel® Server Board S1400SP TPS Server Board Layout Figure 1. Intel® Server Board S1400SP4 Layout 4 Intel order number G64248-003 Revision 2.
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Intel® Server Board S1400SP TPS 2.2.1 Overview Server Board Connector and Component Layout The following figures show the layout of the server board. Figure 2. Intel® Server Board S1400SP Layout Figure 3. Jumper Block Identification Revision 2.
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Overview 2.2.2 Intel® Server Board S1400SP TPS Server Board Mechanical Drawings Figure 4. Intel® Server Board S1400SP – Mounting Hole Locations (1 of 2) 6 Intel order number G64248-003 Revision 2.
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Intel® Server Board S1400SP TPS Overview Figure 5. Intel® Server Board S1400SP – Mounting Hole Locations (2 of 2) Revision 2.
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Overview Intel® Server Board S1400SP TPS Figure 6. Intel® Server Boards S1400SP – Major Connector Pin-1 Locations (1 of 2) 8 Intel order number G64248-003 Revision 2.
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Intel® Server Board S1400SP TPS Overview Figure 7. Intel® Server Boards S1400SP – Major Connector Pin-1 Locations (2 of 2) Revision 2.
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Overview Intel® Server Board S1400SP TPS Figure 8. Intel® Server Boards S1400SP – Primary Side Keepout Zone 10 Intel order number G64248-003 Revision 2.
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Intel® Server Board S1400SP TPS Overview Figure 9. Intel® Server Boards S1400SP – Primary Side Card Side Keepout Zone Figure 10. Intel® Server Boards S1400SP – Primary Side Air Duct Keepout Zone Revision 2.
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Overview Intel® Server Board S1400SP TPS Figure 11. Intel® Server Boards S1400SP – Second Side Keepout Zone 2.2.3 Server Board Rear I/O Layout The following drawings show the layout of the rear I/O components for the server board. Figure 12. Intel® Server Boards S1400SP2 Rear I/O Layout 12 Intel order number G64248-003 Revision 2.
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Intel® Server Board S1400SP TPS Overview Figure 13. Intel® Server Boards S1400SP4 Rear I/O Layout Revision 2.
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Functional Architecture 3. Intel® Server Board S1400SP TPS Functional Architecture The architecture and design of the Intel® Server Board S1400SP is based on the Intel® C600 chipset family. The chipset is designed for systems based on the Intel® Xeon® processor in an FC-LGA 1356 Socket B2 package with Intel® QuickPath Interconnect (Intel® QPI).
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Intel® Server Board S1400SP TPS Functional Architecture Note: Previous generation Intel® Xeon® processors are not supported on the Intel® server board described in this document. Visit the Intel® website for a complete list of supported processors. 3.1.1 Processor Socket Assembly Each processor socket of the server board is pre-assembled with an Independent Latching Mechanism (ILM) and Back Plate which allow for secure placement of the processor and processor heat to the server board.
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Functional Architecture Intel® Server Board S1400SP TPS The following sections will provide an overview of the key processor features and functions that help to define the performance and architecture of the server board.
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Intel® Server Board S1400SP TPS Functional Architecture links to complete the connection between two components. This supports traffic in both directions simultaneously. To facilitate flexibility and longevity, the interconnect is defined as having five layers: Physical, Link, Routing, Transport, and Protocol. The Intel® QuickPath Interconnect includes a cache coherency protocol to keep the distributed memory and caching structures coherent during system operation.
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Functional Architecture  Intel® Server Board S1400SP TPS Memory thermal monitoring support for DIMM temperature 3.2.2.1 Supported Memory Table 2. UDIMM Support Guidelines Ranks Per DIMM and Data Width SRx8 NonECC DRx8 NonECC SRx16 NonECC SRx8 ECC DRx8 ECC Speed (MT/s) and Voltage Validated by Slot per Channel (SPC) and DIMM Per Channel (DPC)2,3 Memory Capacity Per DIMM1 1 Slot per Channel 1DPC 1.35V 1.5V 2 Slots per Channel 1DPC 1.35V 1.5V 1.35V 2DPC 1.
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Intel® Server Board S1400SP TPS Functional Architecture Notes: 1. Supported DRAM Densities are 1Gb, 2Gb and 4Gb. Only 2Gb and 4Gb are validated by Intel®. 2. Command Address Timing is 1N. Supported and Validated Supported but not Validated 3.2.2.2 Memory Slot Identification and Population Rules Note: Although mixed DIMM configurations may be functional, Intel only performs platform validation on systems that are configured with identical DIMMs installed.
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Functional Architecture Intel® Server Board S1400SP TPS The following are generic DIMM population requirements that generally apply to the Intel® Server Board S1400SP.  All DIMMs must be DDR3 DIMMs.  Registered DIMMs must be ECC only; unbuffered DIMMs can be ECC or non-ECC. However, Intel® only validates and supports ECC memory for its server products. Mixing of Registered and Unbuffered DIMMs is not allowed per platform.
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Intel® Server Board S1400SP TPS Functional Architecture Note: Some server operating systems do not display the total physical memory installed. What is displayed is the amount of physical memory minus the approximate memory space used by system BIOS components. These BIOS components include, but are not limited to: 1. ACPI (may vary depending on the number of PCI devices detected in the system) 2. ACPI NVS table 3. Processor microcode 4. Memory Mapped I/O (MMIO) 5. Manageability Engine (ME) 6.
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Functional Architecture Intel® Server Board S1400SP TPS Rank Sparing Mode enhances the system’s RAS capability by “swapping out” failing ranks of DIMMs. Rank Sparing is strictly channel and rank oriented. Each memory channel is a Sparing Domain. For Rank Sparing to be available as a RAS option, there must be 2 or more single rank or dual rank DIMMs, or at least one quad rank DIMM installed on each memory channel.
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Intel® Server Board S1400SP TPS Functional Architecture When Mirroring Mode is operational, the system treats Correctable Errors the same way as it would in Independent channel mode. There is a correctable error threshold. Correctable error counts accumulate by rank, and the first event is logged. What Mirroring primarily protects against is the possibility of an Uncorrectable ECC Error occurring with critical data “in process”.
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Functional Architecture 3.2.2.4.5 Intel® Server Board S1400SP TPS Single Device Data Correction (SDDC) SDDC – Single Device Data Correction is a technique by which data can be replaced by the IMC from an entire x4 DRAM device which is failing, using a combination of CRC plus parity. This is an automatic IMC driven hardware. It can be extended to x8 DRAM technology by placing the system in Channel Lockstep Mode. 3.2.2.4.
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Intel® Server Board S1400SP TPS 3.2.2.4.7 Functional Architecture Demand Scrubbing for ECC Memory Demand scrubbing is the ability to write corrected data back to the memory once a correctable error is detected on a read transaction. This allows for correction of data in memory at detect, and decrease the chances of a second error on the same address accumulating to cause a multi-bit error (MBE) condition.
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Functional Architecture Intel® Server Board S1400SP TPS Figure 17. Functional Block Diagram of Processor IIO Sub-system The following sub-sections will describe the server board features that are directly supported by the processor IIO module. These include the Riser Card Slots, Network Interface, and connectors for the optional I/O modules and SAS Module. Features and functions of the Intel® C600 Series chipset will be described in its own dedicated section. 3.2.3.
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Intel® Server Board S1400SP TPS Functional Architecture PCIe Port0/DMI2 PCIe Port 1a PCIe Port 1b PCIe Port 2a PCIe Port 2b PCIe Port 2c PCIe Port 2d PCIe Port 3a PCIe Port 3b PCIe Port 3c PCIe Port 3d CPU0 B0,D0,F0 PCH B0,D0,F1 ROC module conn B0,D3,F0 B0,D3,F1 B0,D3,F1 IO module conn Slot6 x16conn Figure 18. PCI Express* Lane Mapping 3.2.3.2 Riser Card Support The server board includes one riser card slot labeled SLOT_6 (PCIe_x16).
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Functional Architecture Intel® Server Board S1400SP TPS Supported I/O modules include: Table 5. Supported Intel® I/O Module Options Descritpion 4-port 1Gb Ethernet Networking IO Module 2-port 10Gb Ethernet Networking IO Module 2-port 10Gb Ethernet SFP IO Module FDR InfiniBand* IO Module 3.2.3.
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Intel® Server Board S1400SP TPS Functional Architecture Figure 20. Functional Block Diagram – Chipset Supported Features and Functions On the Intel® Server Boards S1400SP, the chipset provides support for the following on-board functions:       PCI Express* root ports Low Pin Count (LPC) interface Universal Serial Bus (USB) Controller Serial Attached SCSI (SAS)/Serial ATA (SATA) Support Intel® Rapid Storage Technology Manageability Features 3.3.
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Functional Architecture 3.3.3 Intel® Server Board S1400SP TPS On-board Serial Attached SCSI (SAS)/Serial ATA (SATA) Support and Options ® The Intel C600-A chipset provides storage support from two integrated controllers: AHCI and SCU.
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Intel® Server Board S1400SP TPS Product Code Color Functional Architecture On-Server Board SATA/SAS Capable Controller On-Server Board AHCI Capable SATA Controller No Key N/A Intel® RSTE 4 ports SATA R0,1,10,5 ® or Intel ESRT2 4 ports SATA R0,1,10 Intel® RSTE SATA R0,1,10,5 ® or Intel ESRT2 SATA R0,1,10 RKSATA4R5 Black Intel® RSTE 4 ports SATA R0,1,10,5 ® or Intel ESRT2 4 ports SATA R0,1,10,5 Intel® RSTE SATA R0,1,10,5 ® or Intel ESRT2 SATA R0,1,10,5 RKSATA8 Blue Intel® RSTE 8 ports SATA R0,
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Functional Architecture Intel® Server Board S1400SP TPS 4 and 8 Port SAS RAID 5 support provided with appropriate Intel® RAID C600 Upgrade Key. Maximum drive support = Eight (with or without SAS expander option installed). Open Source Compliance = Binary Driver (includes Partial Source files) or Open Source using MDRAID layer in Linux*. OS Support = Microsoft Windows 7*, Microsoft Windows 2008*, Microsoft Windows 2003*, RHEL*, SLES*, other Linux* variants using partial source builds.
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Intel® Server Board S1400SP TPS Functional Architecture  ECC Error Reporting. When detecting an ECC error, the host controller has the ability to send one of several messages to the chipset. The host controller can instruct the chipset to generate SMI #, NMI, SERR#, or TCO interrupt.  Function Disable. The chipset provides the ability to disable the following integrated functions: LAN, USB, LPC, SATA, PCI Express* or SMBus*.
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Functional Architecture Intel® Server Board S1400SP TPS Figure 23. Integrated BMC Hardware 3.4.
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Intel® Server Board S1400SP TPS 3.4.1.2 Functional Architecture Wake-up Control The super I/O contains functionality that allows various events to power on and power off the system. 3.4.
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Functional Architecture Intel® Server Board S1400SP TPS Table 9. Video mode On-board Video Dual Monitor Video 3.4.3 Enabled Disabled Enabled Disabled Shaded if on-board video is set to "Disabled" Baseboard Management Controller The server board utilizes the following features of the embedded baseboard management controller.  IPMI 2.
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Intel® Server Board S1400SP TPS Functional Architecture  Hardware Based Video Compression and Redirection Logic  Supports both text and Graphics redirection  Hardware assisted Video redirection using the Frame Processing Engine  Direct interface to the Integrated Graphics Controller registers and Frame buffer  Hardware-based encryption engine 3.4.3.2 Integrated BMC Embedded LAN Channel The Integrated BMC hardware includes two dedicated 10/100 network interfaces.
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System Security Intel® Server Board S1400SP TPS 4. System Security 4.1 BIOS Password Protection The BIOS uses passwords to prevent unauthorized tampering with the server setup. Passwords can restrict entry to the BIOS Setup, restrict use of the Boot Popup menu, and suppress automatic USB device reordering. There is also an option to require a Power On password entry in order to boot the system.
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Intel® Server Board S1400SP TPS System Security In addition to restricting access to most Setup fields to viewing only when a User password is entered, defining a User password imposes restrictions on booting the system. In order to simply boot in the defined boot order, no password is required. However, the F6 Boot popup prompts for a password, and can only be used with the Administrator password.
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System Security     Intel® Server Board S1400SP TPS Produces EFI and legacy interfaces to a TPM-enabled operating system for using TPM. Produces ACPI TPM device and methods to allow a TPM-enabled operating system to send TPM administrative command requests to the BIOS. Verifies operator physical presence. Confirms and executes operating system TPM administrative command requests. Provides BIOS Setup options to change TPM security states and to clear TPM ownership.
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Intel® Server Board S1400SP TPS 4.2.3.1 System Security Security Screen To enter the BIOS Setup, press the F2 function key during boot time when the OEM or Intel® logo displays. The following message displays on the diagnostics screen and under the Quiet Boot logo screen: Press to enter setup When the Setup is entered, the Main screen displays.
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System Security Intel® Server Board S1400SP TPS Table 10. TPM Setup Utility – Security Configuration Screen Fields Setup Item TPM State* Options Enabled and Activated Enabled and Deactivated Disabled and Activated Disabled and Deactivated Help Text Comments Information only. Shows the current TPM device state. A disabled TPM device will not execute commands that use TPM functions and TPM security operations will not be available.
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Intel® Server Board S1400SP TPS System Security processor, chipset and BIOS, Authenticated Code Modules, and an Intel® Trusted Execution Technology compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an application. In addition, Intel® Trusted Execution Technology requires the system to include a TPM v1.2, as defined by the Trusted Computing Group TPM PC Client Specification, Revision 1.2.
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Technology Support Intel® Server Board S1400SP TPS 5. Technology Support 5.1 Intel® Trusted Execution Technology The Intel® Xeon® Processor E5 4600/2600/2400/1600 and Intel® Xeon® Processor E5 4600/2600/2400/1600 v2 Product Families support Intel® Trusted Execution Technology (Intel® TXT), which is a robust security environment designed to help protect against software-based attacks.
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Intel® Server Board S1400SP TPS Technology Support For more information on the DMAR table and the DRHD entry format, refer to the Intel® Virtualization Technology for Directed I/O Architecture Specification. For more general information about VT-x, VT-d, and VT-c, a good reference is Enabling Intel® Virtualization Technology Features and Benefits White Paper. 5.
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Technology Support Intel® Server Board S1400SP TPS power information utilized by the NM algorithms and also exports ACPI Source Language (ASL) code used by OS-Directed Power Management (OSPM) for negotiating processor P and T state changes for power limiting. PMBus*-compliant power supplies provide the capability to monitoring input power consumption, which is necessary to support NM. Below are the some of the applications of Intel® Intelligent Power Node Manager technology.       5.3.
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Intel® Server Board S1400SP TPS 6. Platform Management Functional Overview Platform Management Functional Overview Platform management functionality is supported by several hardware and software components integrated on the server board that work together to control system functions, monitor and report system health, and control various thermal and performance features in order to maintain (when possible) server functionality in the event of component failure and/or environmentally stressed conditions.
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Platform Management Functional Overview Intel® Server Board S1400SP TPS BMC self test: The BMC performs initialization and run-time self-tests and makes results available to external entities. See also the Intelligent Platform Management Interface Specification Second Generation v2.0.  6.1.
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Intel® Server Board S1400SP TPS                    Platform Management Functional Overview Intel® Light-Guided Diagnostics Address Resolution Protocol (ARP): The BMC sends and responds to ARPs (supported on embedded NICs). Dynamic Host Configuration Protocol (DHCP): The BMC performs DHCP (supported on embedded NICs). E-mail alerting Embedded web server o Support for embedded web server UI in Basic Manageability feature set.
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Platform Management Functional Overview     Intel® Server Board S1400SP TPS Enhancements to fan speed control. DCMI 1.1 compliance (product-specific). Support for embedded web server UI in Basic Manageability feature set.
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Intel® Server Board S1400SP TPS Platform Management Functional Overview Feature Acoustic Management X X Diagnostic Beep Code Support X X Power State Retention X X ARP/DHCP Support X X Advanced PECI Thermal Management Support X X E-mail Alerting X X Embedded Web Server X X SSH Support X X Integrated KVM X Integrated Remote Media Redirection X Lightweight Directory Access Protocol (LDAP) ® 6.
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Platform Management Functional Overview   Intel® Server Board S1400SP TPS Port 80h snooping capability Secondary Service Processor (SSP), which provides the HW capability of offloading time critical processing tasks from the main ARM core. Emulex* Pilot III contains an integrated SIO, KVMS subsystem and graphics controller with the following features: 6.4 Advanced Configuration and Power Interface (ACPI) The server board has support for the following ACPI states: Table 13.
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Intel® Server Board S1400SP TPS Source Power state retention Chipset Platform Management Functional Overview External Signal Name or Internal Subsystem Implemented by means of BMC internal logic Sleep S4/S5 signal (same as POWER_ON) Capabilities Turns power on when AC power returns Turns power on or off CPU Thermal CPU Thermtrip Turns power off WOL(Wake On LAN) LAN Turns power on 6.
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Platform Management Functional Overview Intel® Server Board S1400SP TPS FRB2 refers to the FRB algorithm that detects system failures during POST. The BIOS uses the BMC watchdog timer to back up its operation during POST. The BIOS configures the watchdog timer to indicate that the BIOS is using the timer for the FRB2 phase of the boot operation. After the BIOS has identified and saved the BSP information, it sets the FRB2 timer use bit and loads the watchdog timer with the new timeout interval.
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Intel® Server Board S1400SP TPS Platform Management Functional Overview The BMC provides FRU device command access to its own FRU device and to the FRU devices throughout the server. The FRU device ID mapping is defined in the Platform Specific Information. The BMC controls the mapping of the FRU device ID to the physical device 6.10 System Event Log (SEL) The BMC implements the system event log as specified in the Intelligent Platform Management Interface Specification, Version 2.0.
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Platform Management Functional Overview Intel® Server Board S1400SP TPS This capability requires the BMC to access temperature sensors on the individual memory DIMMs. Additionally, closed-loop thermal throttling is only supported with buffered DIMMs. 6.11.2 Setting Throttling Mode Select the most appropriate memory thermal throttling mechanism for memory sub-system from [Auto], [DCLTT], [SCLTT] and [SOLTT].
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Intel® Server Board S1400SP TPS Platform Management Functional Overview 1. The above features may or may not be in effective depends on the actual thermal characters of a specific system. 2. Refer to the Intel® Server System TPS for the board in Intel® chassis thermal and acoustic management. 3. Refer to Fan Control Whitepaper for the board in 3rd party chassis fan speed control customization. 6.11.
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Platform Management Functional Overview              Intel® Server Board S1400SP TPS Front Panel Temperature Sensor1 Baseboard Temperature Sensor2 CPU Margin Sensors3,5,6 DIMM Thermal Margin Sensors3,5 Exit Air Temperature Sensor4, 8 PCH Temperature Sensor4,6 On-board Ethernet Controller Temperature Sensors4, 6 Add-In Intel® SAS/IO Module Temperature Sensors4,10 PSU Thermal Sensor4, 9 CPU VR Temperature Sensors4, 7 DIMM VR Temperature Sensors4, 7 Integrated BMC Temperature Sensor4, 7 Global
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Intel® Server Board S1400SP TPS 6.11.9 Platform Management Functional Overview Memory Thermal Throttling The server board provides support for system thermal management through open loop throttling (OLTT) and closed loop throttling (CLTT) of system memory. Normal system operation uses closed-loop thermal throttling (CLTT) and DIMM temperature monitoring as major factors in overall thermal and acoustics management.
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Platform Management Functional Overview Intel® Server Board S1400SP TPS Table 16. Messaging Interfaces Channel ID Interface 0 1 Primary IPMB LAN 1 Supports Sessions No Yes 2 3 LAN 2 LAN 3 1 (Provided by the Intel® Dedicated Server Management NIC) Reserved USB Secondary IPMB Yes Yes 4 5 6 7 SMM 8– 0Dh Reserved 0Eh Self 2 0Fh SMS/Receive Message Queue Notes: 1. Optional hardware supported by the server system. 2. Refers to the actual channel used to send the request. 6.12.
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Intel® Server Board S1400SP TPS Platform Management Functional Overview See the Intelligent Platform Management Interface Specification Second Generation v2.0 for details about the IPMI-over-LAN protocol. Run-time determination of LAN channel capabilities can be determined by both standard IPMI defined mechanisms. 6.12.3.1 RMCP/ASF Messaging The BMC supports RMCP ping discovery in which the BMC responds with a pong message to an RMCP/ASF ping request.
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Platform Management Functional Overview Intel® Server Board S1400SP TPS 6.12.3.2.3 Concurrent Server Management Use of Multiple Ethernet Controllers The BMC FW supports concurrent OOB LAN management sessions for the following combination:  2 on-board NIC ports  1 on-board NIC and the optional dedicated RMM4 add-in management NIC.  2 on-board NICs and optional dedicated RMM4 add-in management NIC. All NIC ports must be on different subnets for the above concurrent usage models.
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Intel® Server Board S1400SP TPS  Platform Management Functional Overview BMC LAN 3 (Dedicated NIC) ----- 1000Mb 6.12.3.3 IPV6 Support In addition to IPv4, the server board has support for IPv6 for manageability channels. Configuration of IPv6 is provided by extensions to the IPMI Set and Get LAN Configuration Parameters commands as well as through a Web Console IPv6 configuration web page.
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Platform Management Functional Overview Intel® Server Board S1400SP TPS The LAN Failover feature applies only to BMC LAN traffic. It bonds all available Ethernet devices but only one is active at a time. When enabled, If the active connection’s leash is lost, one of the secondary connections is automatically configured so that it has the same IP address. Traffic immediately resumes on the new active connection. The LAN Failover enable/disable command may be sent at any time.
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Intel® Server Board S1400SP TPS Platform Management Functional Overview When changing from DHCP to Static configuration, the initial values of these three parameters will be equivalent to the existing DHCP-set parameters. Additionally, the BMC observes the following network safety precautions: 1. The user may only set a subnet mask that is valid, per IPv4 and RFC 950 (Internet Standard Subnetting Procedure).
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Platform Management Functional Overview Intel® Server Board S1400SP TPS such circumstances has no effect, and the BMC returns error code 0xD5, “Cannot Execute command. Command, or request parameter(s) are not supported in present state.” 6.12.3.6 DHCP BMC Hostname The BMC allows setting a DHCP Hostname using the Set/Get LAN Configuration Parameters command.           DHCP Hostname can be set regardless of the IP Address source configured on the BMC.
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Intel® Server Board S1400SP TPS Platform Management Functional Overview members of the VLAN will be isolated from any other network traffic. Please note that VLAN does not change the behavior of the host network setting, it only affects the BMC LAN communication. LAN configuration options are now supported (by means of the Set LAN Config Parameters command, parameters 20 and 21) that allow support for 802.1Q VLAN (Layer 2). This allows VLAN headers/packets to be used for IPMI LAN sessions.
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Platform Management Functional Overview   Intel® Server Board S1400SP TPS Activating SOL: This command is not accepted by the BMC. It is sent by the BMC when SOL is activated to notify a remote client of the switch to SOL. Activating a SOL session requires an existing IPMI-over-LAN session. If encryption is used, it should be negotiated when the IPMI-over LAN session is established. 6.12.
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Intel® Server Board S1400SP TPS Platform Management Functional Overview the traps is provided with the BMC firmware to facilitate interpretation of the traps by external software. The format of the MIB file is covered under RFC 2578. 6.12.11 Alert Policy Table Associated with each PEF entry is an alert policy that determines which IPMI channel the alert is to be sent. There is a maximum of 20 alert policy entries.
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Platform Management Functional Overview Intel® Server Board S1400SP TPS The embedded web server is supported over any system NIC port that is enabled for server management capabilities. 6.12.13 Embedded Web Server BMC Base manageability provides an embedded web server and an OEM-customizable web GUI which exposes the manageability features of the BMC base feature set.
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Intel® Server Board S1400SP TPS               The GUI session automatically times-out after a user-configurable inactivity period. By default, this inactivity period is 30 minutes. Embedded Platform Debug feature - Allow the user to initiate a “diagnostic dump” to a file that can be sent to Intel® for debug purposes. Virtual Front Panel. The Virtual Front Panel provides the same functionality as the local front panel. The displayed LEDs match the current state of the local panel LEDs.
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Platform Management Functional Overview      Intel® Server Board S1400SP TPS There is no precedence or lock-out mechanism for the control sources. When a new request arrives, previous requests are terminated. For example, if the chassis ID button is pressed, then the chassis ID LED changes to solid on. If the button is pressed again, then the chassis ID LED turns off.
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Intel® Server Board S1400SP TPS    Platform Management Functional Overview o Capture of power supply “black box” data and power supply asset information – Power supply vendors are adding the capability to store debug data within the power supply itself. The platform debug feature provides a means to capture this data for each installed power supply. The data can be analyzed by Intel® for failure analysis and possibly provided to the power supply vendor as well.
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Platform Management Functional Overview Category External BIOS Data System Data Intel® Server Board S1400SP TPS Data Human-readable sensor listing BIOS configuration settings POST codes for the two most recent boots SMBIOS table for the current boot 256 bytes of PCI config data for each PCI device Memory Map (EFI and Legacy) for current boot Table 19. Additional Diagnostics on Error Category System Data 6.12.
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Intel® Server Board S1400SP TPS 7. Advanced Management Feature Support (RMM4) Advanced Management Feature Support (RMM4) The integrated baseboard management controller has support for advanced management features which are enabled when an optional Intel® Remote Management Module 4 (RMM4) is installed. RMM4 is comprised of two boards – RMM4 lite and the optional Dedicated Server Management NIC (DMN). Table 20.
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Advanced Management Feature Support (RMM4) Intel® Server Board S1400SP TPS Figure 27. Intel® RMM4 Dedicated Management NIC Installation Table 21. Enabling Advanced Management Features Manageability Hardware Benefits ® Intel Integrated BMC Comprehensive IPMI based base manageability features. Intel® Remote Management Module 4 – Lite Package contains one module – 1- Key for advance Manageability features. No dedicated NIC for management. Enables KVM and media redirection from onboard NIC.
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Intel® Server Board S1400SP TPS Advanced Management Feature Support (RMM4) KVM redirection console support the following keyboard layouts: English, Dutch, French, German, Italian, Russian, and Spanish. KVM redirection includes a “soft keyboard” function. The “soft keyboard” is used to simulate an entire keyboard that is connected to the remote system. The “soft keyboard” functionality supports the following layouts: English, Dutch, French, German, Italian, Russian, and Spanish.
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Advanced Management Feature Support (RMM4) Intel® Server Board S1400SP TPS For the best possible KVM performance, a 2Mb/sec link or higher is recommended. The redirection of KVM over IP is performed in parallel with the local KVM without affecting the local KVM operation. 7.1.3 Security The KVM redirection feature supports multiple encryption algorithms, including RC4 and AES. The actual algorithm that is used is negotiated with the client based on the client’s capabilities. 7.1.
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Intel® Server Board S1400SP TPS       Advanced Management Feature Support (RMM4) The media redirection feature supports multiple encryption algorithms, including RC4 and AES. The actual algorithm that is used is negotiated with the client based on the client’s capabilities. A remote media session is maintained even when the server is powered-off (in standby mode). No restart of the remote media session is required during a server reset or power on/off.
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On-board Connector/Header Overview 8. Intel® Server Board S1400SP TPS On-board Connector/Header Overview The following section provides detailed information regarding all connectors, headers, and jumpers on the server boards. 8.1 Board Connector Information The following table lists all connector types available on the board and the corresponding preference designators printed on the silkscreen. Table 22.
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Intel® Server Board S1400SP TPS On-board Connector/Header Overview Connector Quantity Reference Designators Connector Type Pin Count HDD LED 1 J1G2 Header 2 SATA 2 SATA_0: J2H3 SATA_1: J1J1 Connector 7 Mini-SAS 2 SCU_0: J1H1 SCU_1: J1H2 Connector 38 Mini-SATA 1 J2H1 Connector 38 HSBP_I2C 1 J2H2 Header 3 LCP 1 J2H8 Header 7 IPMB 1 J2H6 Header 4 Configuration jumpers 5 J2H5: BMC Force Update J2H7: BIOS Recovery J2H4: BIOS Default J1H4: ME Force Update J1H6: Password
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On-board Connector/Header Overview Intel® Server Board S1400SP TPS Table 24. CPU Power Connector Pin-out Pin 1 2 3 4 5 6 7 8 Signal GND of Pin 5 GND of Pin 6 GND of Pin 7 GND of Pin 8 +12 Vdc CPU1 +12 Vdc CPU1 +12 Vdc DDR3_CPU1 +12 Vdc DDR3_CPU1 Color Black Black Black Black Yellow/black Yellow/black Yellow/black Yellow/black Table 25. Power Supply Auxiliary Signal Connector Pin-out Pin 1 2 3 4 5 8.3 Signal SMB_CLK_FP_PWR_R SMB_DAT_FP_PWR_R SMB_ALRT_3_ESB_R 3.3 V SENSE3.
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Intel® Server Board S1400SP TPS On-board Connector/Header Overview Signal Description P3V3 LED_HDD_ACTIVITY_R_N FP_PWR_BTN_N GROUND FP_RST_BTN_R_N GROUND FP_ID_BTN_R_N PU_FM_SIO_TEMP_SENSOR FP_NMI_BTN_R_N KEY LED_NIC_LINK2_ACT_FP_N LED_NIC_LINK2_LNKUP_FP_N 8.3.1.
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On-board Connector/Header Overview Intel® Server Board S1400SP TPS The following actions cause the BMC to generate an NMI pulse:  Receiving a Chassis Control command to pulse the diagnostic interrupt. This command does not cause an event to be logged in the SEL.  Watchdog timer pre-timeout expiration with NMI/diagnostic interrupt pre-timeout action enabled. The following table describes behavior regarding NMI signal generation and event logging by the BMC. Table 28.
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Intel® Server Board S1400SP TPS On-board Connector/Header Overview Table 29. Front Panel USB Connector Pin-out Signal Description P5V_USB_FP USB2_P11_F_DN USB2_P11_F_DP GROUND 8.3.3 Pin# 1 3 5 7 Pin# 2 4 6 8 10 Signal Description P5V_USB_FP USB2_P13_F_DN USB2_P13_F_DP GROUND TP_USB2_FP_10 Intel® Local Control Panel Connector The server board includes a 7-pin connector that is used when the system is configured with the Intel® Local Control Panel with LCD support.
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On-board Connector/Header Overview Intel® Server Board S1400SP TPS transfer rates of up to 3Gb/s. The connector labeled “SCU_1” is only enabled when an optional 8-port SAS or SATA Intel® RAID C600 Upgrade Key is installed. See Table 7 for a complete list of supported storage upgrade keys. “SATA_2-5” connector supports up to four SATA ports capable of transfer rates of up to 3Gb/s. The following tables provide the pin-out for each connector. Table 32.
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Intel® Server Board S1400SP TPS On-board Connector/Header Overview Table 33. SSI 4-pin Fan Header Pin-out Pin 1 2 3 4 Signal Name Ground 12V Fan Tach Fan PWM Type GND Power In Out Description Ground is the power supply ground Power supply 12 V FAN_TACH signal is connected to the BMC to monitor the fan speed FAN_PWM signal to control fan speed Table 34.
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On-board Connector/Header Overview 8.7 Intel® Server Board S1400SP TPS System Management Headers 8.7.1 Intel® Remote Management Module 4 Connector A 40-pin Intel® RMM4 connector and a 7-pin Intel® RMM4 Lite connector are included on the server board to support the optional Intel® Remote Management Module 4 or Intel® Remote Management Module 4 Lite. This server board does not support third-party management cards.
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Intel® Server Board S1400SP TPS Pin 7 9 11 13 8.7.3 On-board Connector/Header Overview Signal Name P3V3 RST_IBMC_NIC_N LPC_LAD<3> GND Pin 8 10 12 14 Signal Name GND CLK_33M_TPM_CONN GND LPC_LAD<2> HSBP Header Table 39. HSBP_ I2C Header Pin-out Pin 1 2 3 8.7.4 Signal Name SMB_HSBP_3V3STBY_DATA GND SMB_HSBP_3V3STBY_CLK SGPIO Header Table 40. SGPIO Header Pin-out Pin 1 2 3 4 8.
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On-board Connector/Header Overview Intel® Server Board S1400SP TPS Table 42. RJ-45 10/100/1000 NIC Connector Pin-out Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 8.8.3 Signal Name GND P1V8_NIC NIC_A_MDI3P NIC_A_MDI3N NIC_A_MDI2P NIC_A_MDI2N NIC_A_MDI1P NIC_A_MDI1N NIC_A_MDI0P NIC_A_MDI0N NIC_LINKA_1000_N (LED NIC_LINKA_100_N (LED) NIC_ACT_LED_N NIC_LINK_LED_N GND GND USB Connector The following table details the pin-out of the external USB connectors found on the back edge of the server boards.
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Intel® Server Board S1400SP TPS On-board Connector/Header Overview Table 45. Internal Type-A USB Connector Pin-out Signal Description P5V_USB_INT USB2_P2_F_DN USB2_P2_F_DP GROUND 8.9 Pin# 1 2 3 4 Other Connectors and Headers The server board includes a 2-pin chassis intrusion header which can be used when the chassis is configured with a chassis intrusion switch. On the server board, this header is labeled “CHAS INTR” and is located on the front edge of the server board.
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Jumper Blocks 9. Intel® Server Board S1400SP TPS Jumper Blocks The server board has several 3-pin jumper blocks that can be used to configure, protect, or recover specific features of the server boards. The following symbol identifies Pin 1 on each jumper block on the silkscreen: ▼ Figure 28. Jumper Blocks Note: 1. For safety purposes, the power cord should be disconnected from a system before removing any system components or moving any of the on-board jumper blocks. 2.
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Intel® Server Board S1400SP TPS Jumper Blocks Jumper Name Default Pins 2-3 System Results If pins 2-3 are jumpered with AC power plugged in, the CMOS settings clear in 5 seconds. Pins 2-3 should not be jumpered for normal system operation. J1H4: ME Force Update 1-2 ME Firmware Force Update Mode – Disabled (Default) 2-3 J1H6: Password Clear 1-2 ME Firmware Force Update Mode – Enabled These pins should have a jumper in place for normal system operation. 9.
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Jumper Blocks Intel® Server Board S1400SP TPS Note: System Update and Recovery files are included in the System Update Packages (SUP) posted to Intel®’s website. 1. Turn off the system and remove power cords. 2. Move the ME FRC UPD Jumper from the default (pins 1 and 2) operating position to the Force Update position (pins 2 and 3). 3. Re-attach system power cords. 4. Power on the system. Note: System Fans will boost and the BIOS Error Manager should report an 83A0 error code (ME in recovery mode). 5.
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Intel® Server Board S1400SP TPS Jumper Blocks Note: BIOS Error Manager should report a 5220 error code (BIOS Settings reset to default settings) 9.5 BMC Force Update Jumper Block The BMC Force Update jumper is used to put the BMC in Boot Recovery mode for a low-level update. It is used when the BMC has become corrupted and is non-functional, requiring a new BMC image to be loaded on to the server board. 1. Turn off the system and remove power cords. 2.
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Intel® Light Guided Diagnostics Intel® Server Board S1400SP TPS 10. Intel® Light Guided Diagnostics The server board includes several on-board LED indicators to aid troubleshooting various board level faults. The following diagram shows the location for each. Figure 29. On-Board Diagnostic LED Placement 96 Intel order number G64248-003 Revision 2.
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Intel® Server Board S1400SP TPS Intel® Light Guided Diagnostics Figure 30. Memory Slot Fault LED Locations 10.1 System ID LED The server board includes a blue system ID LED which is used to visually identify a specific server installed among many other similar servers. There are two options available for illuminating the System ID LED: 1. The front panel ID LED Button is pushed, which causes the LED to illuminate to a solid on state until the button is pushed again. 2.
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Intel® Light Guided Diagnostics Intel® Server Board S1400SP TPS Table 49. System Status LED State Definitions Color Green State Solid on Ok Criticality Description Indicates that the System Status is ‗Healthy‘. The system is not exhibiting any errors. AC power is present and BMC has booted and manageability functionality is up and running. Green ~1 Hz blink Degraded System degraded: 1. Redundancy loss such as power-supply or fan.
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Intel® Server Board S1400SP TPS Amber Solid on Intel® Light Guided Diagnostics Critical, nonrecoverable Fatal alarm – system has failed or shutdown: 1. CPU CATERR signal asserted 2. MSID mismatch detected (CATERR also asserts for this case). 3. CPU 1 is missing 4. CPU ThermalTrip 5. No power good – power fault 6. DIMM failure when there is only 1 DIMM present and hence no good memory present1. 7. Runtime memory uncorrectable error in non-redundant mode1. 8. DIMM Thermal Trip or equivalent 9.
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Intel® Light Guided Diagnostics Intel® Server Board S1400SP TPS condition during the POST process. The diagnostic LEDs can be used to identify the last POST process to be executed. See Appendix D for a complete description of how these LEDs are read, and for a list of all supported POST codes. 10.5 5 Volt Stand-By Present LED This LED is illuminated when a power cord (AC or DC) is connected to the server and the power supply is supplying 5 Volt Stand-by power to the server board.
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Intel® Server Board S1400SP TPS Environmental Limits Specification 11. Environmental Limits Specification The following table defines the Intel® Server Board S1400SP operating and non-operating environmental limits. Operation of the Intel® Server Board S1400SP at conditions beyond those shown in the following table may cause permanent damage to the system. Exposure to absolute maximum rating conditions for extended periods may affect system reliability. Table 51.
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Environmental Limits Specification Intel® Server Board S1400SP TPS building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions. Intel Corporation cannot be held responsible, if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits. 11.2 MTBF The following is the calculated Mean Time Between Failures (MTBF).
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Intel® Server Board S1400SP TPS Server Board Power Distribution 12. Server Board Power Distribution This section provides power supply design guidelines for a system using the Intel® Server Board S1400SP. The following diagram shows the power distribution implemented on this server board. Figure 31. Power Distribution Block Diagram 12.1 Processor Power Support The server boards support the Thermal Design Power (TDP) guideline for Intel® Xeon® processors.
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Server Board Power Distribution Intel® Server Board S1400SP TPS Table 53. Intel® Xeon® Processor TDP Guidelines TDP Power Max Tcase Icc Max 95 W 80W 80W (1 socket) 70W 60W 50W 78°C 75°C 71°C 130 A 85A 80A 70°C 67°C 65°C 110A 90A 65A 12.2 Power Supply Output Requirements This section is for reference purposes only. The intent is to provide guidance to system designers to determine a power supply to use with these server boards.
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Intel® Server Board S1400SP TPS Server Board Power Distribution 50Hz and 5kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only a test specification. The  step load may occur anywhere within the MIN load to the MAX load conditions. Table 56. Transient Load Requirements Output  Step Load Size (See note 2) 18A 0.5A 12V +5VSB 12.2.5 Load Slew Rate Test capacitive Load 0.5 A/sec 0.
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Server Board Power Distribution Intel® Server Board S1400SP TPS The measurement shall be made across a 100Ω resistor between each of DC outputs, including ground at the DC power connector and chassis ground (power subsystem enclosure). The test set-up shall use a FET probe such as Tektronix* model P6046 or equivalent. 12.2.
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Intel® Server Board S1400SP TPS Server Board Power Distribution Vout V1 10% Vout V2 V3 V4 Tvout rise Tvout_off Tvout_on Figure 32. Output Voltage Timing Table 60. Turn On/Off Timing Item Tsb_on_delay T ac_on_delay Tvout_holdup Tpwok_holdup Tpson_on_delay T pson_pwok Tpwok_on T pwok_off Tpwok_low Tsb_vout T5VSB_holdup Revision 2.1 Description Delay from AC being applied to 5VSB being within regulation. Delay from AC being applied to all output voltages being within regulation.
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Server Board Power Distribution Intel® Server Board S1400SP TPS AC Input Tvout_holdup Vout Tpwok_low TAC_on_delay Tsb_on_delay PWOK 5VSB Tpwok_off Tpwok_on Tsb_on_delay Tpwok_on Tpwok_off Tpson_pwok Tpwok_holdup T5VSB_holdup Tsb_vout Tpson_on_delay PSON AC turn on/off cycle PSON turn on/off cycle Figure 33. Turn On/Off Timing (Power Supply Signals) 12.2.
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Intel® Server Board S1400SP TPS Appendix A: Integration and Usage Tips Appendix A: Integration and Usage Tips  When adding or removing components or peripherals from the server board, you must remove AC power cord. With AC power plugged into the server board, 5-V standby is still present even though the server board is powered off.
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Appendix B: Integrated BMC Sensor Tables Intel® Server Board S1400SP TPS Appendix B: Integrated BMC Sensor Tables This appendix lists the sensor identification numbers and information about the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 2.0 for sensor and event/reading-type table information.
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Intel® Server Board S1400SP TPS  Appendix B: Integrated BMC Sensor Tables Rearm Sensors The rearm is a request for the event status of a sensor to be rechecked and updated upon a transition between good and bad states. You can rearm the sensors manually or automatically. This column indicates the type supported by the sensor.
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Appendix B: Integrated BMC Sensor Tables Intel® Server Board S1400SP TPS Table 61. Integrated BMC Core Sensors Full Sensor Name (Sensor name in SDR) Power Unit Status Sensor # 01h Platform Applicability All (Pwr Unit Status) Sensor Type Power Unit 09h Event/Reading Event Offset Triggers Type Sensor Specific 6Fh Contrib.
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Intel® Server Board S1400SP TPS Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Appendix B: Integrated BMC Sensor Tables Sensor Type Event/Reading Event Offset Triggers Type Contrib. To System Status 06 – Redundant: degraded from fully redundant state. Degraded 07 – Redundant: Transition from non-redundant state.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Button Sensor (Button) BMC Watchdog Voltage Regulator Watchdog Sensor # 09h 0Ah 0Bh Platform Applicability All All All Intel® Server Board S1400SP TPS Sensor Type Button/Switch 14h (Fan Redundancy) 114 0Ch Chassisspecific Sensor Specific 6Fh Mgmt System Health Digital Discrete 28h 03h Voltage 02h (VR Watchdog) Fan Redundancy1 Event/Reading Event Offset Triggers Type Digital Discrete 03h Fan Generic 04h
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Intel® Server Board S1400SP TPS Full Sensor Name (Sensor name in SDR) SSB Thermal Trip (SSB Therm Trip) IO Module Presence (IO Mod Presence) SAS Module Presence (SAS Mod Presence) BMC Firmware Health (BMC FW Health) System Airflow (System Airflow) FW Update Status Sensor # 0Dh 0Eh 0Fh 10h Platform Applicability All Appendix B: Integrated BMC Sensor Tables Sensor Type Temperature 01h Platformspecific Module/Board Platformspecific Module/Board All 11h All 12h All 15h 15h Mgmt Health 28h
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) IO Module2 Presence (IO Mod2 Presence) Baseboard Temperature 5 (Platform Specific) Baseboard Temperature 6 (Platform Specific) IO Module2 Temperature Sensor # (PCI Riser 5 Temp) PCI Riser 4 Temperature (PCI Riser 4 Temp) Baseboard +1.05V Processor3 Vccp (BB +1.
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Intel® Server Board S1400SP TPS Full Sensor Name (Sensor name in SDR) Baseboard +1.05V Processor4 Vccp Sensor # (Platform Specific) Front Panel Temperature (Front Panel Temp) SSB Temperature (SSB Temp) Baseboard Temperature 2 (Platform Specific) Baseboard Temperature 3 (Platform Specific) Baseboard Temperature 4 (Platform Specific) IO Module Temperature (I/O Mod Temp) Revision 2.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) PCI Riser 1 Temperature (PCI Riser 1 Temp) IO Riser Temperature Sensor # Temperature Sensor Type Event/Reading Event Offset Triggers Type 27h Platformspecific Temperature Threshold 01h 01h 28h Platformspecific Temperature Threshold 01h 01h 29h Chassisspecific Temperature Threshold 01h 01h 2Ah Chassisspecific Temperature Threshold 01h 01h 2Bh Chassisspecific Temperature Threshold 01h 01h 2Ch Pla
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Intel® Server Board S1400SP TPS Full Sensor Name (Sensor name in SDR) Network Interface Controller Temperature Sensor # Platform Applicability 2Fh All 30h–3Fh Chassis and Platform Specific 40h–4Fh Chassis and Platform Specific Appendix B: Integrated BMC Sensor Tables Sensor Type Event/Reading Event Offset Triggers Type Temperature Threshold 01h 01h Fan Threshold 04h 01h Fan Generic 08h [u,l] [c,nc] (LAN NIC Temp) Fan Tachometer Sensors (Chassis specific sensor names) Fan Present Sensor
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Power Supply 2 AC Power Input Sensor # Sensor Type Event/Reading Event Offset Triggers Type 55h Chassisspecific Other Units Threshold 0Bh 01h 58h Chassisspecific Current Threshold 03h 01h 59h Chassisspecific Current Threshold 03h 01h 5Ch Chassisspecific Temperature Threshold 01h 01h 5Dh Chassisspecific (PS2 Power In) Power Supply 1 +12V % of Maximum Current Output Platform Applicability Intel® Serv
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Intel® Server Board S1400SP TPS Full Sensor Name (Sensor name in SDR) Sensor # 69h 6Bh Processor 1 Status 70h Platform Applicability Chassisspecific All (P1 Status) Processor 2 Status 71h All (P2 Status) Processor 3 Status 72h (P3 Status) Processor 4 Status 73h (P4 Status) Processor 1 Thermal Margin (P1 Therm Margin) Processor 2 Thermal Margin (P2 Therm Margin) Processor 3 Thermal Margin (P3 Therm Margin) Processor 4 Thermal Margin (P4 Therm Margin) Revision 2.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Processor 1 Thermal Control % Sensor # 78h Platform Applicability All (P1 Therm Ctrl %) Processor 2 Thermal Control % 79h All (P2 Therm Ctrl %) Processor 3 Thermal Control % 7Ah (P3 Therm Ctrl %) Processor 4 Thermal Control % 7Bh Platformspecific 7Ch All (P4 Therm Ctrl %) Processor 1 ERR2 Timeout Platformspecific (P1 ERR2) Processor 2 ERR2 Timeout 7Dh All (P2 ERR2) Processor 3 ERR2 Timeout 7Eh (P3 ERR2) Proc
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Intel® Server Board S1400SP TPS Full Sensor Name (Sensor name in SDR) Catastrophic Error Sensor # 80h Platform Applicability All (CATERR) Processor1 MSID Mismatch (P1 MSID Mismatch) Processor Population Fault 81h 82h All All (CPU Missing) Processor 1 DTS Thermal Margin (P1 DTS Therm Mgn) Processor 2 DTS Thermal Margin (P2 DTS Therm Mgn) Processor 3 DTS Thermal Margin (P3 DTS Therm Mgn) Processor 4 DTS Thermal Margin (P4 DTS Therm Mgn) Processor2 MSID Mismatch (P2 MSID Mismatch) Revision 2.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Processor 1 VRD Temperature Sensor # 90h Platform Applicability All Intel® Server Board S1400SP TPS Sensor Type Temperature 01h (P1 VRD Hot) Processor 2 VRD Temperature 91h All Temperature 01h (P2 VRD Hot) Processor 3 VRD Temperature 92h All Temperature 01h (P3 VRD Hot) Processor 4 VRD Temperature 93h All Temperature 01h (P4 VRD Hot) Processor 1 Memory VRD Hot 0-1 94h All (P1 Mem01 VRD Hot) Processor 1 Memor
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Intel® Server Board S1400SP TPS Full Sensor Name (Sensor name in SDR) Processor 2 Memory VRD Hot 2-3 Sensor # 97h Platform Applicability All (P2 Mem23 VRD Hot) Processor 3 Memory VRD Hot 0-1 98h All (P3 Mem01 VRD Hot) Processor 3 Memory VRD Hot 2-3 99h All (P4 Mem23 VRD Hot) Processor 4 Memory VRD Hot 0-1 9Ah All (P4 Mem01 VRD Hot) Processor 4 Memory VRD Hot 2-3 9Bh All (P4 Mem23 VRD Hot) Power Supply 1 Fan Tachometer 1 (PS1 Fan Tach 1) Revision 2.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Intel® Server Board S1400SP TPS Sensor Type Power Supply 1 Fan Tachometer 2 (PS1 Fan Tach 2) A1h Chassisspecific Fan Power Supply 2 Fan Tachometer 1 (PS2 Fan Tach 1) A4h Chassisspecific Fan Power Supply 2 Fan Tachometer 2 (PS2 Fan Tach 2) A5h Chassisspecific Fan Processor 1 DIMM Aggregate Thermal Margin 1 04h 04h 04h Event/Reading Event Offset Triggers Type Contrib.
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Intel® Server Board S1400SP TPS Full Sensor Name (Sensor name in SDR) Processor 2 DIMM Aggregate Thermal Margin 2 Sensor # Platform Applicability Appendix B: Integrated BMC Sensor Tables Sensor Type Event/Reading Event Offset Triggers Type Contrib.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Processor 1 DIMM Thermal Trip C0h All (P1 Mem Thrm Trip) Processor 2 DIMM Thermal Trip C1h All (P2 Mem Thrm Trip) Processor 3 DIMM Thermal Trip C2h All (P3 Mem Thrm Trip) Processor 4 DIMM Thermal Trip C3h All (P4 Mem Thrm Trip) Global Aggregate Temperature Margin 1 Intel® Server Board S1400SP TPS Sensor Type Memory 0Ch Memory 0Ch Memory 0Ch Memory 0Ch Event/Reading Event Offset
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Intel® Server Board S1400SP TPS Full Sensor Name (Sensor name in SDR) Global Aggregate Temperature Margin 3 Sensor # Platform Applicability Appendix B: Integrated BMC Sensor Tables Sensor Type Event/Reading Event Offset Triggers Type CAh Platform Specific Temperature Threshold 01h 01h CBh Platform Specific Temperature Threshold 01h 01h CCh Platform Specific Temperature Threshold 01h 01h CDh Platform Specific Temperature Threshold 01h 01h CEh Platform Specific Temperature Thre
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Global Aggregate Temperature Margin 8 Sensor # CFh Platform Applicability Platform Specific Intel® Server Board S1400SP TPS Sensor Type Event/Reading Event Offset Triggers Type Temperature Threshold 01h 01h - Contrib.
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Intel® Server Board S1400SP TPS Full Sensor Name (Sensor name in SDR) Baseboard +1.05V Processor2 Vccp Sensor # D7h Platform Applicability All (BB +1.05Vccp P2) Baseboard +1.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Baseboard +1.1V Stand-by (BB +1.1V STBY) Baseboard CMOS Battery Sensor # DDh DEh Platform Applicability E4h Sensor Type Event/Reading Event Offset Triggers Type All Voltage 02h Threshold 01h All Voltage 02h Threshold 01h All Voltage 02h Threshold 01h (BB +3.3V Vbat) Baseboard +1.35V P1 Low Voltage Memory AB VDDQ Intel® Server Board S1400SP TPS [u,l] [c,nc] [u,l] [c,nc] [u,l] [c,nc] (BB +1.
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Intel® Server Board S1400SP TPS Full Sensor Name (Sensor name in SDR) Baseboard +3.3V Riser 1 Power Good Sensor # (HDD 1 - 15 Status) Event/Reading Event Offset Triggers Type EAh Voltage 02h Threshold 01h EBh Platform Specific Voltage 02h Threshold 01h (BB +3.3 RSR2 PGD) Hard Disk Drive 1 -15 Status Sensor Type Platform Specific (BB +3.3 RSR1 PGD) Baseboard +3.
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Appendix C: POST Code Diagnostic LED Decoder Intel® Server Board S1400SP TPS Appendix C: POST Code Diagnostic LED Decoder As an aid to assist in trouble shooting a system hang that occurs during a system’s Power-On Self Test (POST) process, the server board includes a bank of eight POST Code Diagnostic LEDs on the back edge of the server board.
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Intel® Server Board S1400SP TPS Appendix C: POST Code Diagnostic LED Decoder Table 62. POST Progress Code LED Example Upper Nibble AMBER LEDs LEDs Status Results MSB LED #7 8h ON 1 LED #6 4h OFF 0 LED #5 2h ON 1 Lower Nibble GREEN LEDs LED #4 1h OFF 0 LED #3 8h ON 1 Ah LED #2 4h ON 1 LED #1 2h OFF 0 LSB LED #0 1h OFF 0 Ch Upper nibble bits = 1010b = Ah; Lower nibble bits = 1100b = Ch; the two are concatenated as Ach. The following table provides a list of all POST progress codes. Table 63.
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Appendix C: POST Code Diagnostic LED Decoder Diagnostic LED Decoder 1 = LED On, 0 = LED Off Checkpoint Upper Nibble Lower Nibble MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h LED # #7 #6 #5 #4 #3 #2 #1 #0 78h 0 1 1 1 1 0 0 0 79h 0 1 1 1 1 0 0 1 90h 1 0 0 1 0 0 0 0 91h 1 0 0 1 0 0 0 1 92h 1 0 0 1 0 0 1 0 93h 1 0 0 1 0 0 1 1 94h 1 0 0 1 0 1 0 0 95h 1 0 0 1 0 1 0 1 96h 1 0 0 1 0 1 1 0 97h 1 0 0 1 0 1 1 1 98h 1 0 0 1 1 0 0 0 99h 1 0 0 1 1 0 0 1 9Ah 1 0 0 1 1 0 1 0 9Bh 1 0 0 1 1 0 1 1 9Ch 1 0 0 1 1 1 0 0 9Dh 1 0 0 1 1 1 0 1 A
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Intel® Server Board S1400SP TPS Appendix C: POST Code Diagnostic LED Decoder POST Memory Initialization MRC Diagnostic Codes There are two types of POST Diagnostic Codes displayed by the MRC during memory initialization; Progress Codes and Fatal Error Codes. The MRC Progress Codes are displayed to the Diagnostic LEDs that show the execution point in the MRC operational path at each step. Table 64.
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Appendix C: POST Code Diagnostic LED Decoder Intel® Server Board S1400SP TPS Table 65.
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Intel® Server Board S1400SP TPS Appendix D: POST Code Errors Appendix D: POST Code Errors Most error conditions encountered during POST are reported using POST Error Codes. These codes represent specific failures, warnings, or are informational. POST Error Codes may be displayed in the Error Manager display screen, and are always logged to the System Event Log (SEL). Logged events are available to System Management applications, including Remote and Out of Band (OOB) management.
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Appendix D: POST Code Errors Intel® Server Board S1400SP TPS Table 66.
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Intel® Server Board S1400SP TPS Error Code 852D 852E 852F 8530 8531 8532 8533 8534 8535 8536 8537 8538 8539 853A 853B 853C 853D 853E 853F (Go to 85C0) 8540 8541 8542 8543 8544 8545 8546 8547 8548 8549 854A 854B 854C 854D 854E 854F 8550 8551 8552 8553 8554 8555 8556 8557 8558 8559 855A 855B 855C 855D 855E 855F (Go to 85D0) 8560 8561 8562 Revision 2.
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Appendix D: POST Code Errors Error Code 8563 8564 8565 8566 8567 8568 8569 856A 856B 856C 856D 856E 856F 8570 8571 8572 8573 8574 8575 8576 8577 8578 8579 857A 857B 857C 857D 857E 857F (Go to 85E0) 85C0 85C1 85C2 85C3 85C4 85C5 85C6 85C7 85C8 85C9 85CA 85CB 85CC 85CD 85CE 85CF 85D0 85D1 85D2 85D3 85D4 85D5 85D6 85D7 85D8 85D9 85DA 142 Intel® Server Board S1400SP TPS Error Message DIMM_B1 encountered a Serial Presence Detection (SPD) failure DIMM_B2 encountered a Serial Presence Detection (SPD) failure DI
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Intel® Server Board S1400SP TPS Error Code 85DB 85DC 85DD 85DE 85DF 85E0 85E1 85E2 85E3 85E4 85E5 85E6 85E7 85E8 85E9 85EA 85EB 85EC 85ED 85EE 85EF 8604 8605 8606 92A3 92A9 A000 A001 A002 A003 A100 A421 A5A0 A5A1 A6A0 Appendix D: POST Code Errors Error Message DIMM_O2 disabled DIMM_O3 disabled DIMM_P1 disabled DIMM_P2 disabled DIMM_P3 disabled DIMM_K3 encountered a Serial Presence Detection (SPD) failure DIMM_L1 encountered a Serial Presence Detection (SPD) failure DIMM_L2 encountered a Serial Presence De
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Appendix D: POST Code Errors Beeps 4 Error Message BIOS Recovery failure Intel® Server Board S1400SP TPS POST Progress Code NA Description BIOS recovery has failed. This typically happens so quickly after recovery is initiated that it sounds like a 2-4 beep code. The Integrated BMC may generate beep codes upon detection of failure conditions. Beep codes are sounded each time the problem is discovered, such as on each power-up attempt, but are not sounded continuously.
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Intel® Server Board S1400SP TPS Appendix E: Supported Intel® Server Chassis Appendix E: Supported Intel® Server Chassis The Intel® Server System R1000SP product family is comprised of several available 1U rack mount server systems that are all integrated with an Intel® Server Board S1400SP. Server System Intel® Server System R1000SP product family Feature Processor Support Memory Chipset External I/O connections Revision 2.
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Appendix E: Supported Intel® Server Chassis Description Feature Internal I/O connectors/headers I/O Module Accessory Options Intel® Server Board S1400SP TPS  One Type-A USB 2.0 connector  One internal 2x5 pin serial port B header The following I/O modules utilize a single proprietary on-board connector. An installed I/O module can be supported in addition to standard on-board features and any add-in expansion cards.
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Intel® Server Board S1400SP TPS Glossary Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (for example, “82460GX”) with alpha entries following (for example, “AGP 4x”). Acronyms are then entered in their respective place, with non-acronyms following.
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Glossary I2 C Intel® Server Board S1400SP TPS Term Definition Inter-integrated circuit bus IA Intel® architecture IBF Input buffer ICH I/O controller hub IERR Internal error INIT Initialization signal IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface ITP In-target probe KCS Keyboard controller style KT Keyboard text KVM Keyboard, video, mouse LAN Local area network LCD Liquid crystal display LPC Low pin count LUN Logical unit number MA
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Intel® Server Board S1400SP TPS Term ROM Glossary Definition Read-only memory RTC Real-time clock SCI System Control Interrupt. A system interrupt used by hardware to notify the operating system of ACPI events. SDR Sensor data record SDRAM Synchronous dynamic random access memory SEL System event log SHA1 Secure Hash Algorithm 1 SIO Server Input/Output SMBus* A two-wire interface based on the I2C protocol.
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Reference Documents Intel® Server Board S1400SP TPS Reference Documents See the following documents for additional information: 150  Advanced Configuration and Power Interface Specification, Revision 3.0, http://www.acpi.info/.  Intelligent Platform Management Bus Communications Protocol Specification, Version 1.0. 1998. Intel Corporation, Hewlett-Packard* Company, NEC* Corporation, Dell* Computer Corporation.  Intelligent Platform Management Interface Specification, Version 2.0. 2004.