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Server Board S1200BT

Technical Product Specification

Intel order number G13326-003

Revision 1.0

March, 2011

Enterprise Platforms and Services Division

Summary of content (153 pages)

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® Intel Server Board S1200BT Technical Product Specification Intel order number G13326-003 Revision 1.
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Revision History Intel®Server Board S1200BT TPS Revision History Date July 2010 November 2010 January 2011 January 2011 March 2011 Revision Number 0.3 0.5 0.7 0.9 1.0 Modifications Initial release. Updated the hardware info and SE SKU. Updated S1200BTS info and BIOS setup page. Updated S1200BT video mode. Corrected typos. ii Revision 1.
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Intel®Server Board S1200BT TPS Disclaimers Disclaimers ® Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
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Table of Contents Intel®Server Board S1200BT TPS Table of Contents 1. Introduction ........................................................................................................................ 1 1.1 Chapter Outline ...................................................................................................... 1 1.2 Server Board Use Disclaimer ................................................................................. 1 2. Overview ...............................................
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Intel®Server Board S1200BT TPS Table of Contents 3.6.4 Floppy Disk Controller .......................................................................................... 27 3.6.5 Keyboard and Mouse Support .............................................................................. 28 3.6.6 Wake-up Control .................................................................................................. 28 3.7 Video Support ..........................................................................
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Table of Contents Intel®Server Board S1200BT TPS 5. Server Management Capability for Intel® Server Board S1200BTS............................... 46 5.1 5.1.1 Supper I/O............................................................................................................ 46 Key Features of supper I/O .................................................................................. 46 6. BIOS User Interface ............................................................................................
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Intel®Server Board S1200BT TPS 8.1 Table of Contents CMOS Clear and Password Reset Usage Procedure......................................... 105 8.1.1 Clearing the CMOS ............................................................................................ 106 8.1.2 Clearing the Password ....................................................................................... 106 8.2 Integrated BMC Force Update Procedure (Only for The Intel® Server Board S1200BTL) .................................
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List of Figures Intel®Server Board S1200BT TPS List of Figures Figure 1. Intel® Server Board S1200BTL Picture......................................................................... 4 Figure 2. Intel® Server Board S1200BTS Picture ........................................................................ 5 Figure 3. Intel® Server Board S1200BTL Layout ......................................................................... 6 ® Figure 4. Intel Server Board S1200BTS Layout .................................
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Intel®Server Board S1200BT TPS List of Figures Figure 33. Realtime Teperature and Voltage Status Screen (S1200BTS) ................................. 82 Figure 34. Boot Options Screen ................................................................................................ 83 Figure 35. Hard Disk Order Screen ........................................................................................... 84 Figure 36. CDROM Order Screen ....................................................................
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List of Tables Intel®Server Board S1200BT TPS List of Tables Table 1. Intel® Server Board S1200BT Feature Set .................................................................... 2 Table 2. Major Board Components ............................................................................................. 6 Table 3. Major Board Components ............................................................................................. 7 Table 4. Memory Configuration Table .....................................
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Intel®Server Board S1200BT TPS List of Tables Table 33. SAS Connector Pin-out (J2H1).................................................................................. 98 Table 34. External Serial A Port Pin-out (J8A1) ........................................................................ 98 Table 35. Internal 9-pin Serial B Header Pin-out (J1B2) ........................................................... 98 Table 36. Internal USB Connector Pin-out ( J1E1, J1D1) ..........................................
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List of Tables Intel®Server Board S1200BT TPS xii Revision 1.
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Intel®Server Board S1200BT TPS 1. Introduction Introduction This Technical Product Specification (TPS) provides board specific information detailing the features, functionality, and high-level architecture of the Intel® Server Board S1200BT. In addition, you can obtain design-level information for specific subsystems by ordering the External Product Specifications (EPS) or External Design Specifications (EDS) for a given subsystem.
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Overview Intel®Server Board S1200BT TPS 2. Overview The Intel® Server Board S1200BT is a monolithic printed circuit board (PCB) with features designed to support entry-level severs. It has two board SKUs, namely S1200BTL and S1200BTS. Intel® Server Board S1200BT Feature Set 2.1 ® Table 1.
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Intel®Server Board S1200BT TPS Overview Feature Add-in PCI Card, PCI Express* Card Description of S1200BTL Description of S1200BTS  Slot1: One 5V PCI 32 bit/33 MHz connector  Slot4: One 5V PCI 32 bit/33 MHz connector  Slot3: One PCI Express* Gen2 x8 (x4 throughput) connector  Slot5: One PCI Express* Gen2 x8 (x4 throughput) connector  Slot4: One PCI Express* Gen2 x8 (x4 throughput) connector  Slot6: One PCI Express* Gen2 x8 (x8 throughput) connector  Slot5: One PCI Express* Gen2 x8 (
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Overview 2.2 Intel®Server Board S1200BT TPS Server Board Layout ® Figure 1. Intel Server Board S1200BTL Picture 4 Revision 1.
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Intel®Server Board S1200BT TPS Overview ® Figure 2. Intel Server Board S1200BTS Picture 2.2.1 Server Board Connector and Component Layout The following figure shows the board layout of the server board. Each connector and major component is identified by a number or letter, and Table 2 provides the description. 5 Revision 1.
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Overview Intel®Server Board S1200BT TPS ® Figure 3. Intel Server Board S1200BTL Layout Table 2.
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Intel®Server Board S1200BT TPS Overview Description Description L CPU Power Connector CC HDD LED M SYS_FAN_4 DD Internal USB Connector N RMM4 Dedicated NIC connector EE CMOS battery O Four DIMM Slots FF Four 3Gb/s SATA ports P P/S AUX GG Two 6Gb/s SATA ports Q MAIN POWER HH Smart module ® Figure 4. Intel Server Board S1200BTS Layout Table 3. Major Board Components Description Description A Slot 4, 32 Mbit/33 MHz PCI N SYS FAN 1 B Slot 5.
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Overview Intel®Server Board S1200BT TPS Description Description C SATA_KEY P CPU Fan connector D Slot 7, PCI Express* Gen2 x8 (x16 connector) Q Chassis Intrusion E Ethernet and Dual USB COMBO R SATA_SGPIO F Ethernet and Dual USB COMBO S SYS_FAN_3 G Video port T Six 3Gb/s SATA ports H External Serial port U Low profile USB connector I CPU Power connector V Internal USB J SYS_FAN_2 W CMOS battery K DIMM slots X Front Panel L MAIN power connector Y HDD LED M TPM con
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Intel®Server Board S1200BT TPS Overview ® Figure 5. Intel Server Board S1200BTL – Hole and Component Positions 9 Revision 1.
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Overview Intel®Server Board S1200BT TPS ® Figure 6. Intel Server Board S1200BTL – Major Connector Pin Location (1 of 2) 10 Revision 1.
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Intel®Server Board S1200BT TPS Overview ® Figure 7. Intel Server Board S1200BTL – Major Connector Pin Location (2 of 2) 11 Revision 1.
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Overview Intel®Server Board S1200BT TPS ® Figure 8. Intel Server Board S1200BTL – Primary Side Keepout Zone 12 Revision 1.
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Intel®Server Board S1200BT TPS Overview ® Figure 9. Intel Server Board S1200BTL – Secondary Side Keepout Zone 13 Revision 1.
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Overview 2.2.3 Intel®Server Board S1200BT TPS Server Board Rear I/O Layout The following figure shows the layout of the rear I/O components for the server board. A Serial Port A C NIC Port 1 (1 Gb) and Dual USB Port Connector B Video D NIC port 2 (1 Gb) and Dual USB Port Connector ® Figure 10. Intel Server Board S1200BT Rear I/O Layout 14 Revision 1.
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Intel®Server Board S1200BT TPS 3. Functional Architecture Functional Architecture The architecture and design of the Intel® Server Board S1200BT is based on the Intel® C202 Chipset. The chipset is designed for systems based on the Intel® Xeon® processor in the FCLGA 1155 socket package. The Intel® Server Board S1200BTL uses Intel® C204 Chipset and the Intel® Server Board S1200BTS uses Intel® C202 Chipset.
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Functional Architecture Intel®Server Board S1200BT TPS Intel® Server Board S1200BTS Block Diagram VRD 12.0 VCORE VTT VSA ATX – 9.6" x 9.6" VPLL MEM VTT MEM VRD 12.
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Intel®Server Board S1200BT TPS Functional Architecture The server board does not support previous generations of the Intel® Xeon® processors. The list of supported processors may be found at http://serverconfigurator.intel.com. Note: The workstation processor is not supported in this platform. Intel® Core™ Processor i3-2100 Series 3.1.2 ® The Intel Core™ Processor i3-2100 Series highly integrated solution variant is composed of Duo cores.  FC-LGA 1155 socket package with 2.5 GT/s.
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Functional Architecture Intel®Server Board S1200BT TPS  The memory channels are named as ―Channel A‖ and ―Channel B‖.  The memory slots are named as ―Slot1‖ and ―Slot2‖ on each channel. Slot1will be the farthest from the processor socket.  DIMMs are named to reflect the channel and slot in which they are installed: 3.2.1 o Channel A, Slot1 is ―DIMM_A1‖. o Channel A, Slot2 is ―DIMM_A2‖. o Channel B, Slot1 is ―DIMM_B1‖. o Channel B, Slot2 is ―DIMM_B2‖.
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Intel®Server Board S1200BT TPS Functional Architecture This can also occur if all memory in the system fails and/or has become disabled during memory initialization. For example, if a DDR3 DIMM has no SPD information, the BIOS treats the DIMM slot as if no DDR3 DIMM is present on it. Therefore, if this is the only DDR3 DIMM installed in the system, there is no usable memory, and the BIOS goes to a memory error code 0xE8 as described above.
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Functional Architecture  Intel®Server Board S1200BT TPS The maximum memory bandwidth is 10.6 GB/s in Single-Channel mode or 21 GB/s in Dual-Channel Symmetric mode, assuming DDR3 running at 1333 MT/s. 3.2.3.1 Memory Configuration Table Table 4.
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Intel®Server Board S1200BT TPS Max Memory Possible 3.2.4 Functional Architecture 1Gb DRAM Technology (4x 2GB DIMMs) 2Gb DRAM Technology (4x 4GB DIMMs) 4Gb DRAM Technology (4x 8GB DIMMs) Publishing System Memory For S1200 Server Boards with an SNB-DT processor, the memory configurations and population rules are relatively simple. The overall configuration is a single processor/IMC, with two channels, and two DIMM slots on each channel.
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Functional Architecture Intel®Server Board S1200BT TPS  USB host interface  SMBus Host interface  Serial Peripheral interface  LAN interface  ACPI interface 3.4 I/O Sub-system Intel® C200 Series PCH provides extensive I/O support. 3.4.1 Digital Media Interface (DMI) Direct Media Interface (DMI) is the chip-to-chip connection between the processor and C202 chipset.
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Intel®Server Board S1200BT TPS Functional Architecture and an AHCI mode using memory space. Software that uses legacy mode will not have AHCI capabilities. Software that uses legacy mode does not have Advanced Host Configuration Interface (AHCI) capabilities. The Intel® C202 PCH Chipset supports the Serial ATA Specification, Revision 1.0a. The PCH also supports several optional sections of the Serial ATA II: Extensions to Serial ATA 1.0 Specification, Revision 1.
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Functional Architecture Intel®Server Board S1200BT TPS  USB Specification-compliant keyboards.  USB Specification-compliant mouse.  USB Specification-compliant storage devices that utilize bulk-only transport mechanism. USB devices are scanned to determine if they are required for booting. The BIOS supports USB 2.0 mode of operation, and as such supports USB 1.1 and USB 2.0 compliant devices and host controllers.
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Intel®Server Board S1200BT TPS                  Functional Architecture JTAG Master Eight I2C interfaces with master-slave and SMBus timeout support. All interfaces are SMBus 2.0 compliant.
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Functional Architecture Intel®Server Board S1200BT TPS Figure 13. Integrated BMC Hardware 3.6.1 Integrated BMC Embedded LAN Channel The Integrated BMC hardware includes two dedicated 1000M network interfaces. Interface 1: This interface is available from either of the available NIC ports in system that can be shared with the host. Only one NIC may be enabled for management traffic at any time. To change the NIC enabled for management traffic, please use the ―Write LAN Channel Port‖ OEM IPMI command.
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Intel®Server Board S1200BT TPS  Functional Architecture All users disabled 3.6.2 Optional RMM4 Advanced Management Board On the Intel® Server Board S1200BTL provides RMM4 module.   Give the customer the option to add a dedicated management 100 Mbit LAN interface to the product. Provide additional flash space, enabling the Advanced Management functions to support WS-MAN and CIMON. Table 7.
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Functional Architecture 3.6.5 Intel®Server Board S1200BT TPS Keyboard and Mouse Support The server board does not support PS/2 interface keyboards and mouse. However, the system BIOS recognizes USB specification-compliant keyboard and mouse. 3.6.6 Wake-up Control The super I/O contains functionality that allows various events to power on and power off the system. 3.7 Video Support Intel® Server Board S1200BTL 3.7.
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Intel®Server Board S1200BT TPS   Functional Architecture In dual mode, the onboard video controller is enabled and is the primary video device. The external video card is allocated resources and is considered the secondary video device. When KVM is enabled in iBMC FW, dual video is enabled. Table 10. Dual Video Modes Onboard Video Enabled Disabled Dual Monitor Video Enabled Disabled Onboard video controller.
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Functional Architecture Intel®Server Board S1200BT TPS provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). Lewisville also supports the Energy Efficient Ethernet (EEE) 802.az specification. The 82579 operates with the Platform Controller Hub (PCH) chipset that incorporates the MAC and interfaces with its integrated LAN controller through two interfaces: PCIebased and SMBus.
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Intel®Server Board S1200BT TPS Functional Architecture 3.11 TPM (Trusted Platform Module) There is one TPM module connector. The detail information is listed below:     Embedded TPM 1.2 firmware 33-MHz Low Pin Count (LPC) interface V1.1 Compliant with TCG PC client specific TPM Implementation Specification (TIS) V1.2 For the detail Intel® TPM module, please refer to TPM module user guide. Revision 1.
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Platform Management 4. Intel®Server Board S1200BT TPS Platform Management This chapter is only for The Intel® Server Board S1200BTL. The platform management subsystem is based on the Integrated BMC features of the ServerEngines* Pilot III. The onboard platform management subsystem consists of communication buses, sensors, system BIOS, and server management firmware. The following diagram provides an overview of the Server Management Bus (SMBUS) architecture used on this server board.
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Intel®Server Board S1200BT TPS Platform Management 4.1 Feature Support 4.1.1 IPMI 2.0 Features  Baseboard management controller (BMC).  IPMI Watchdog timer  Messaging support, including command bridging and user/session support  Chassis device functionality, including power/reset control and BIOS boot flags support  Event receiver device: The BMC receives and processes events from other platform subsystems.
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Platform Management Intel®Server Board S1200BT TPS  Signal testing support: The BMC provides test commands for setting and getting platform signal states.  The BMC generates diagnostic beep codes for fault conditions.  System GUID storage and retrieval  Front panel management: The BMC controls the system status LED and chassis ID LED. It supports secure lockout of certain front panel functionality and monitors button presses.
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Intel®Server Board S1200BT TPS  Platform Management o Human-readable SEL o Additional system configurability o Additional system monitoring capability o Enhanced on-line help Enhancements to KVM redirection o Support for higher resolution  Management support for PMBus rev1.2 compliant power supplies  Integrated BMC firmware reliability enhancements: o 4.
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Platform Management 4.2.1 Intel®Server Board S1200BT TPS Enabling Advanced Management Features The Advanced management features are to be delivered as part of the Integrated BMC firmware image. The Integrated BMC‘s baseboard SPI flash contains code/data for both the Basic and Advanced features. An optional add-in card Intel® RMM4-lite is used as the activation mechanism. When the Integrated BMC firmware initializes, it attempts to access the Intel® ® RMM4-lite.
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Intel®Server Board S1200BT TPS Platform Management The Remote Console window is a Java Applet that establishes TCP connections to the Integrated BMC. The protocol that is run over these connections is a unique KVM protocol and not HTTP or HTTPS. This protocol uses ports #7578 for KVM, #5120 for CDROM media redirection, and #5123 for Floppy/USB media redirection (both supporting encryption). 4.2.2.2 Performance The remote display accurately represents the local display.
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Platform Management 4.2.3 Intel®Server Board S1200BT TPS Media Redirection The embedded web server provides a Java applet to enable remote media redirection. This may be used in conjunction with the remote KVM feature, or as a standalone applet. The media redirection feature is intended to allow system administrators or users to mount a remote IDE or USB CD-ROM, floppy drive, or a USB flash disk as a remote device to the server.
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Intel®Server Board S1200BT TPS 4.2.3.1 Platform Management Availability The default inactivity timeout is 30 minutes and is not user-configurable. Media redirection sessions persist across system reset but not across an AC power loss or BMC reset. 4.2.3.
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Platform Management Intel®Server Board S1200BT TPS user does not have privilege to execute. (e.g. if a user does not have privilege to power control, then the item shall be displayed in grey-out font in that user‘s UI display). The web GUI also provides a launch point for some of the advanced features, such as KVM and media redirection. These features are grayed out in the GUI unless the system has been updated to support these advanced features.
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Intel®Server Board S1200BT TPS Platform Management A list of data that may be captured using this feature includes but is not limited to: 1. Platform sensor readings – This includes all ―readable‖ sensors that can be accessed by the Integrated BMC firmware and have associated SDRs populated in the SDR repository. This does not include any ―event-only‖ sensors.
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Platform Management Intel®Server Board S1200BT TPS sensors on the installed memory DIMMs. The Integrated Memory Controller (IMC) dynamically changes throttling levels to cap throttling based on memory and system thermal conditions as determined by the system and DIMM power and thermal parameters. Support for CLTT on mixed-mode DIMM populations (i.e. some installed DIMMs have valid temp sensors and some do not) is not supported.
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Intel®Server Board S1200BT TPS Platform Management The NM feature is implemented by a complementary architecture utilizing the ME, Integrated BMC, BIOS, and an ACPI-compliant OS. The ME provides the NM policy engine and power control/limiting functions (referred to as Node Manager or NM) while the Integrated BMC provides the external LAN link by which external management software can interact with the feature.
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Platform Management Intel®Server Board S1200BT TPS Task Capabilities & Features and Thermal Policy Limit power upon power excursion (OS operational) 2.
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Intel®Server Board S1200BT TPS Platform Management Alerts that signify fault conditions that should be recorded in the system SEL will be sent to the Integrated BMC by the ME using the IPMI Platform Event Message command. The Integrated BMC deposits such events into the SEL. The external software must configure the Integrated BMC‘s PEF and alerting features to then send that event out as an IPMI LAN alert, directed to the software application over the LAN link.
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Server Management Capability for Intel®Server Board S1200BTS 5. 5.1 Intel®Server Board S1200BT TPS Server Management Capability for Intel® Server Board S1200BTS Supper I/O 5.1.1 Key Features of supper I/O The W83627DHG-P is from the Nuvoton‘s Super I/O product line. This family features the LPC (Low Pin Count) interface. This interface is more economical than its ISA counterpart. It has approximately forty pins less, yet it provides as great performance.
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Intel®Server Board S1200BT TPS 6. BIOS User Interface BIOS User Interface 6.1 BIOS POST Initialization 6.1.1 BIOS Revision Identification 6.1.1.1 BIOS ID String The BIOS Identification string is used to uniquely identify the revision of the BIOS being used on the server. The BIOS ID string is displayed on the Power On Self Test (POST) diagnostic screen and in Setup and System Management BIOS (SMBIOS) structures. The BIOS ID string is formatted as follows: 6.1.1.2 BoardFamilyID.OEMID.MajorVer.
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BIOS User Interface  Intel®Server Board S1200BT TPS RelNum = Release Number, four decimal digits which are changed to identify distinct BIOS Releases. BIOS Releases are major collections of fixes and changes in functionality. - ―0001‖ is the starting Release Number for all platform BIOS releases, for each distinct BoardFamilyID and OEMID. This number increases by 1 for each BIOS release. It does not increment for a Release Revision.
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Intel®Server Board S1200BT TPS BIOS User Interface Table 13. POST HotKeys Recognized HotKey Combination 6.3 Function Enter Setup Pop up BIOS Boot Menu Network boot POST Logo Screen/Diagnostic Screen The Logo Screen/Diagnostic Screen appears in one of two forms:  If Quiet Boot is enabled in the BIOS setup, a ―splash screen‖ is displayed with a logo image, which is the standard Intel® Logo Screen or a customized OEM Logo Screen.
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BIOS User Interface 6.4 Intel®Server Board S1200BT TPS BIOS Boot Pop-up Menu The BIOS Boot Specification (BBS) provides a Boot Pop-up menu that can be invoked by pressing the key during POST. The BBS Pop-up menu displays all available boot devices. The boot order in the pop-up menu is not the same as the boot order in the BIOS setup. The pop-up menu simply lists all of the available devices from which the system can be booted, and allows a manual selection of the desired boot device.
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Intel®Server Board S1200BT TPS BIOS User Interface Note: If an Administrative Password has not been set, anyone who boots the system to Setup has access to all selection and data entry fields in Setup and can change any of them. 6.5.1.1 Setup Page Layout The Setup page layout is sectioned into functional areas. Each occupies a specific area of the screen and has dedicated functionality. The following table lists and describes each functional area.
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BIOS User Interface Intel®Server Board S1200BT TPS Each Setup menu page contains a number of features. Each feature is associated with a value field, except those used for informative purposes. Each value field contains configurable parameters. Depending on the security option chosen and in effect by the password, a menu feature‘s value may or may not be changed. If a value cannot be changed, its field is made inaccessible and appears grayed out. Table 15.
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Intel®Server Board S1200BT TPS Key BIOS User Interface Option Save and Exit Description Pressing the key causes the following message to display: Save configuration and reset? Yes No If ―Yes‖ is highlighted and is pressed, all changes are saved and the Setup is exited. If ―No‖ is highlighted and is pressed, or the key is pressed, the user is returned to where they were before was pressed without affecting any existing values. 6.5.1.
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BIOS User Interface Intel®Server Board S1200BT TPS  Information enclosed in square brackets ([ ]) in the tables identifies areas where the user must type in text instead of selecting from a provided option.  Whenever information is changed (except Date and Time), the systems requires a save and reboot to take place in order for the changes to take effect.
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Intel®Server Board S1200BT TPS BIOS User Interface Categories (Top Tabs) 2nd Level Screens 3rd Level Screens Security Screen (Tab) — — Server Management Screen (Tab) — —  Console Redirection —  System Information — [With BMC Only] BMC LAN Configuration — [Non-BMC Only] Hardware Monitor — [Non-BMC Only] Realtime Temperature and Voltage Status — — Boot Options Screen (Tab)  Hard Disk Order —  CDROM Order —  Floppy Order —  Network Device Order —  BEV Device Or
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BIOS User Interface 6.5.2.2 Intel®Server Board S1200BT TPS Main Screen (Tab) The Main Screen is the first screen that appears when the BIOS Setup configuration utility is entered, unless an error has occurred. If an error has occurred, the Error Manager Screen appears instead. Main Advanced Logged in as: Platform ID Security Server Management Boot Options Boot Manager Administrator/User System BIOS BIOS Version Build Date
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Intel®Server Board S1200BT TPS BIOS User Interface Screen Field Descriptions: 1. Logged in as: Option Values: Help Text: Comments: Information only. Displays password level that setup is running in: Administrator or User. With no passwords set, Administrator is the default mode. 2. Platform ID Option Values: < Platform ID> Help Text: Comments: Information only. Displays the Platform ID for the board on which the BIOS is executing POST. 3.
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BIOS User Interface Intel®Server Board S1200BT TPS [Enabled] – Display the logo screen during POST. [Disabled] – Display the diagnostic screen during POST. 7. POST Error Pause Option Values: Enabled Disabled Help Text: [Enabled] – Go to the Error Manager for critical POST errors. [Disabled] – Attempt to boot and do not go to the Error Manager for critical POST errors. Comments: If enabled, the POST Error Pause option takes the system to the error manager to review the errors when major errors occur.
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Intel®Server Board S1200BT TPS Main Advanced BIOS User Interface Security Server Management Boot Options Boot Manager ► Processor Configuration ► Memory Configuration ► Mass Storage Controller Configuration ► Serial Port Configuration ► USB Configuration ► PCI Configuration ► System Acoustic and Performance Configuration Figure 16. Advanced Screen Revision 1.
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BIOS User Interface Intel®Server Board S1200BT TPS Screen Field Descriptions: 1. Processor Configuration Option Values: Help Text: View/Configure processor information and settings. Comments: Selection only. Position to this line and press the key to go to the Processor Configuration group of configuration settings. 2. Memory Configuration Option Values: Help Text: View/Configure memory information and settings. Comments: Selection only.
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Intel®Server Board S1200BT TPS BIOS User Interface Comments: Selection only. Position to this line and press the key to go to the PCI Configuration group of configuration settings. 7. System Acoustic and Performance Configuration Option Values: Help Text: View/Configure system acoustic and performance information and settings. Comments: Selection only.
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BIOS User Interface Intel®Server Board S1200BT TPS Advanced Processor Configuration Processor ID stepping Processor Frequency Microcode Revision L1 Cache RAM L2 Cache RAM L3 Cache RAM Processor Version Intel® Turbo Boost Technology Enabled/Disabled Tech Enhanced Intel® SpeedStep® Turbo Boost Performance/Watt Mode Enabled/Disabled Power Optimized/Traditional Processor C3 Processor C6 Intel® Hype
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Intel®Server Board S1200BT TPS BIOS User Interface Screen Field Descriptions: 1. Processor ID Option Values: Help Text: Comments: Information only. Displays the Processor Signature value (from the CPUID instruction) identifying the type of processor and the stepping Processor Frequency Option Values: Help Text: Comments: 2. Information only. Displays current operating frequency of the processor.
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BIOS User Interface Intel®Server Board S1200BT TPS Option Values: Help Text: Comments: Information only. Displays Brand ID string read from processor with CPUID instruction. 7. Intel® Turbo Boost Technology Option Values: Enabled Disabled Help Text: ® Intel Turbo Boost Technology allows the processor to automatically increase its frequency if it is running below power, temperature, and current specifications.
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Intel®Server Board S1200BT TPS BIOS User Interface Help Text: Enable/Disable Processor C3 (ACPI C2/C3) report to OS Comments: This is normally Disabled, but can be Enabled for improved performance on certain benchmarks and in certain situations. 11. Processor C6 Option Values: Enabled Disabled Help Text: Enable/Disable Processor C6 (ACPI C3) report to OS Comments: This is normally Enabled but can be Disabled for improved performance on certain benchmarks and in certain situations. ® 12.
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BIOS User Interface 15. Intel®Server Board S1200BT TPS Intel® Virtualization Technology Option Values: Enabled Disabled Help Text: Intel® Virtualization Technology allows a platform to run multiple operating systems and applications in independent partitions. Note: A change to this option requires the system to be powered off and then back on before the setting takes effect. 66 Revision 1.
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Intel®Server Board S1200BT TPS BIOS User Interface Comments: This option is only visible if all processors installed in the system support Intel® VT. The software configuration installed on the system must support this feature in order for it to be enabled. Intel® VT for Directed I/O 16. Option Values: Enabled Disabled Help Text: Enable/Disable Intel® Virtualization Technology for Directed I/O (Intel® VT-d). Report the I/O device assignment to VMM through DMAR ACPI Tables.
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BIOS User Interface Intel®Server Board S1200BT TPS Note: Modifying this setting may affect system performance. Comments: System performance is usually best with Hardware Prefetcher Enabled. In certain unusual cases, disabling this may give improved results. 21. Adjacent Cache Line Prefetch Option Values: Enabled Disabled Help Text: [Enabled] - Cache lines are fetched in pairs (even line + odd line). [Disabled] - Only the current cache line required is fetched.
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Intel®Server Board S1200BT TPS BIOS User Interface Screen Field Descriptions: 1. Total Memory Option Values: Help Text: Comments: Information only. Displays the amount of memory available in the system in the form of installed DDR3 DIMMs, in units of GB. 2. Effective Memory Option Values: Help Text: Comments: OS in MB or GB. Information only.
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BIOS User Interface Intel®Server Board S1200BT TPS 3. Current Configuration Option Values: Single Channel Dual Channel Symmetric Intel® Flex Help Text: Comments: Displays one of the following:  Single Channel – DIMMs are operating in Single Channel mode. This is the configuration when only one channel is populated with DIMMs.  Dual Channel Symmetric – DIMMs are operating in Dual Channel Symmetric mode. This is the configuration when both channels are identically populated with DIMMs.
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Intel®Server Board S1200BT TPS BIOS User Interface Comments: Information only, for S1200 boards: Displays the state of each DIMM socket present on the board. Each DIMM socket field reflects one of the following possible states: 6.5.2.6  Installed – There is a DDR3 DIMM installed in this slot.  Not Installed – There is no DDR3 DIMM installed in this slot.  Failed – The DDR3 DIMM installed in this slot has been disabled by the BIOS in order to optimize the memory configuration.
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BIOS User Interface Intel®Server Board S1200BT TPS Advanced Serial Port Configuration Serial A Enable Enabled/Disabled Address 3F8h/2F8h/3E8h/2E8h IRQ 3 or 4 Serial B Enable Enabled/Disabled Address 3F8h/2F8h/3E8h/2E8h IRQ 3 or 4 Figure 20. Serial Port Configuration Screen 6.5.2.8 USB Configuration The USB Configuration screen allows the user to configure the USB controller options. To access this screen from the Main screen, select Advanced > USB Configuration.
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Intel®Server Board S1200BT TPS BIOS User Interface Advanced USB Configuration Detected USB Devices USB Controller Enabled/Disabled Legacy USB Support Enabled/Disabled/Auto Port 60/64 Emulation Enabled/Disabled Make USB Devices Non-Bootable Enabled/Disabled USB Mass Storage Device Configuration 10 seconds/20 seconds/30 seconds/40 seconds Device Reset timeout Mass Storage Devices: Auto/Floppy/Forced FDD/Hard Disk/CD-ROM Figure
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BIOS User Interface Intel®Server Board S1200BT TPS Advanced PCI Configuration Maximize Memory below 4GB Enabled / Disabled Memory Mapped I/O above 4GB Enabled / Disabled Onboard Video Enabled / Disabled Dual Monitor Video Enabled / Disabled Wake on LAN (PME) Enabled / Disabled Onboard NIC1 ROM Enabled / Disabled Onboard NIC2 ROM Enabled / Disabled Onboard NIC3 ROM Enabled / Disabled Onboard NIC4 ROM Enabled / Disabled Onboard NIC5 ROM Enabled / Disabled Onboard NIC iSCSI ROM Enabled /
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Intel®Server Board S1200BT TPS BIOS User Interface To access this screen from the Main screen, select Advanced > System Acoustic and Performance Configuration. To move to another screen, press the key to return to the Advanced screen, then select the desired screen. Advanced System Acoustic and Performance Configuration Set Throttling Mode Auto/CLTT/OLTT Altitude 300m or less/301m-900m/901m – 1500m/Higher than 1500m Set Fan Profile Performance, Acoustic Figure 23.
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BIOS User Interface 6.5.2.12 Intel®Server Board S1200BT TPS Server Management Screen (Tab) The Server Management screen allows the user to configure several server management features. This screen also provides an access point to the screens for configuring console redirection, displaying system information, and controlling the BMC LAN configuration.
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Intel®Server Board S1200BT TPS Main BIOS User Interface Advanced Security Server Management Boot Options Boot Manager Assert NMI on SERR Enabled / Disabled Assert NMI on PERR Enabled / Disabled Resume on AC Power Loss Stay Off / Last state / Power On Clear System Event Log Enabled / Disabled FRB-2 Enable Enabled / Disabled O/S Boot Watchdog Timer Enabled / Disabled O/S Boot Watchdog Timer Policy Power off / Reset O/S Boot Watchdog Timer Timeout 5 minutes / 10 minutes / 15 minutes / 20
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BIOS User Interface 6.5.2.14 Intel®Server Board S1200BT TPS System Information The System Information screen allows the user to view part numbers, serial numbers, and firmware revisions. To access this screen from the Main screen, select Server Management > System Information. To move to another screen, press the key to return to the Server Management screen, then select the desired screen.
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Intel®Server Board S1200BT TPS BIOS User Interface Server Management System Information Board Part Number Board Serial Number System Part Number System Serial Number Chassis Part Number Chassis Serial Number Asset Tag HSC Firmware Revision ME Firmware Revision UUID Figure 29.
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BIOS User Interface Intel®Server Board S1200BT TPS Server Management BMC LAN Configuration Baseboard LAN configuration IP Source IP Address Subnet Mask Gateway IP Static/Dynamic [0.0.0.0 IP display/edit] [0.0.0.0 IP display/edit] [0.0.0.0 IP display/edit] [0.0.0.0 IP display/edit] ® Intel RMM4 LAN configuration ® Intel RMM4 IP Source IP Address Subnet Mask Gateway IP[ Static/Dynamic [0.0.0.0 IP display/edit] [0.0.0.0 IP display/edit] [0.0.0.
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Intel®Server Board S1200BT TPS BIOS User Interface Server Management Hardware Monitor ► Real-time Temperature and Voltage Status Fan Controller Auto / Manual CPU Fan Altitude System Fan Altitude 300m/900m/1500m/3000m 300m/900m/1500m/3000m Figure 31.
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BIOS User Interface Intel®Server Board S1200BT TPS To access this screen from the Main screen, select Server Management > Hardware Monitor > Realtime Temperature and Voltage Status. To move to another screen, press the key to return to the Hardware Monitor screen, if necessary press the key again to return to the Server Management screen, then select the desired screen. Server Management Real time Temperature : CPU Fan PWM System Fan PWM System temperature Voltage status: +Vccp +12V +3.3V +5.
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Intel®Server Board S1200BT TPS Main Advanced BIOS User Interface Security Server Management Boot Options System Boot Timeout <0 - 65535> Boot Option #1 Boot Option #2 Boot Option #n Boot Manager ► Hard Disk Order ► CDROM Order ► Floppy Order ► Network Device Order ► BEV Device Order ► Add EFI Boot Option ► Delete EFI Boot Option EFI Optimized Boot Enabled/Disabled Use Legacy Video for EFI OS Enabled/Disabled Boot
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BIOS User Interface Intel®Server Board S1200BT TPS Boot Options Hard Disk Order Hard Disk #1 Hard Disk #2 Figure 35. Hard Disk Order Screen 6.5.2.20 CDROM Order The CDROM Order screen allows the user to control the order in which BIOS attempts to boot from the CDROM drives installed in the system. This screen is only available when there is at least one CDROM device available in the system configuration.
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Intel®Server Board S1200BT TPS BIOS User Interface Boot Options Floppy Order Floppy Disk #1 Floppy Disk #2 Figure 37. Floppy Order Screen 6.5.2.22 Network Device Order The Network Device Order screen allows the user to control the order in which BIOS attempts to boot from the network bootable devices installed in the system.
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BIOS User Interface Intel®Server Board S1200BT TPS Boot Options BEV Device Order BEV Device #1 BEV Device #2 Figure 39. BEV Device Order Screen 6.5.2.24 Add EFI Boot Option The Add EFI Boot Option screen allows the user to add an EFI boot option to the boot order. This screen is only available when there is at least one EFI bootable device present in the system configuration.
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Intel®Server Board S1200BT TPS BIOS User Interface Boot Options Delete EFI Boot Option Delete Boot Option Select one to Delete/Internal EFI Shell Figure 41. Delete EFI Boot Option Screen 6.5.2.26 Boot Manager Screen (Tab) The Boot Manager screen allows the user to view a list of devices available for booting, and to select a boot device for immediately booting the system. Note: This list is not in order according to the system Boot Option order.
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BIOS User Interface Intel®Server Board S1200BT TPS Error Manager ERROR CODE Exit SEVERITY INSTANCE Figure 43. Error Manager Screen 6.5.2.28 System Event Log Screen (Tab) The System Event Log screen appears only for server boards (other than Compute Module boards) which do not have an onboard Baseboard Management Controller. These boards maintain the System Event Log internally by using the SMBIOS Type 15 mechanism.
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Intel®Server Board S1200BT TPS 6.5.2.29 BIOS User Interface Exit Screen (Tab) The Exit screen allows the user to choose whether to save or discard the configuration changes made on other Setup screens. It also allows the user to restore the BIOS settings to the factory defaults or to save or restore them to a set of user-defined default values. If Load Default Values is selected, the factory default settings (noted in bold in the tables in this chapter) are applied.
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Connector/Header Locations and Pin-outs 7. 7.1 Intel®Server Board S1200BT TPS Connector/Header Locations and Pin-outs Board Connector Information The following section provides detailed information regarding all connectors, headers, and jumpers on the server board. It lists all connector types available on the board and the corresponding reference designators printed on the silkscreen. Table 17.
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Intel®Server Board S1200BT TPS Connector/Header Locations and Pin-outs Table 18. Board Connector Matrix on S1200BTS Connector Quantity Reference Designators Power supply 2 J9G1, J9A1 CPU Main memory 1 4 CPU Fan System Fans Battery NIC/Stack 2x USB Video Serial port A Front panel USB Internal Header PCI-E x16 PCI-E x8 PCI 32 Chassis Intrusion 3Gb/s Serial ATA SATA RAID key SATA_SGPIO 7.
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Connector/Header Locations and Pin-outs Intel®Server Board S1200BT TPS Pin Signal Pin Signal 11 +12 Vdc 23 +5 Vdc 12 +3.3 Vdc 24 GND Table 20. SSI Processor 8-PIN Power Connector Pin-out (J9A1) Pin 7.3 Signal Pin Signal 1 GND 5 P12V1 2 GND 6 P12V1 3 GND 7 P12V1 4 GND 8 P12V1 System Management Headers 7.3.
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Intel®Server Board S1200BT TPS Connector/Header Locations and Pin-outs Pin 17 19 21 23 25 27 29 7.3.2 Name Pin 18 20 22 24 GND GND GND GND 26 GND GND GND 28 30 Name RXD_0 RXD_1 RXD_2 RXD_3 TX_CLK RX_CLK PRESENT# LPC/IPMB Header Table 23. LPC/IPMB Header Pin-out (J1H5) 7.3.3 Pin 1 Signal Name SMB_IPMB_5VSB_DAT 2 3 GND SMB_IPMB_5VSB_CLK 4 P5V_STBY Description Integrated BMC IMB 5V standby data line Ground Integrated BMC IMB 5V standby clock line +5 V standby power HSBP Header Table 24.
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Connector/Header Locations and Pin-outs Pin 1 3 5 7 9 11 13 15 17 19 21 23 Intel®Server Board S1200BT TPS Signal Name P3V3_AUX NC PWR_LED_N P3V3 LED_HDD_ACT_N FP_PWR_BTN_N GND FP_RST_BTN_N GND FP_ID_BTN_N PU_FM_SIO_TEMP_SENSOR FP_NMI_BTN_N Pin 2 4 6 8 10 12 14 16 18 20 22 24 Signal Name P3V3_AUX P5V_STBY TP_LED_ID_N LED_STS_GREEN_N LED_STS_AMBER_N LED_ NIC1_ACT LED_NIC1_LINK_N SMB_SEN_3V3SB_DAT SMB_SEN_3V3SB_CLK INTRUDER_HDR LED_ NIC2_ACT LED_ NIC2_LINK_N Combined system BIOS and the Integrated BMC su
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Intel®Server Board S1200BT TPS 7.4.2 Connector/Header Locations and Pin-outs Reset Button The platform supports a front control panel reset button. Pressing the reset button initiates a request forwarded by the Integrated BMC to the chipset. The BIOS does not affect the behavior of the reset button. 7.4.3 System Status Indicator LED ® The Intel Server Board S1200BTL has a system status indicator LED on the front panel.
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Connector/Header Locations and Pin-outs 7.5 Intel®Server Board S1200BT TPS I/O Connectors 7.5.1 VGA Connector The following table details the pin-out definition of the VGA connector (J7A1 on S1200BTL and J6A1 on S1200BTS): Table 28. VGA Connector Pin-out Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7.5.
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Intel®Server Board S1200BT TPS Connector/Header Locations and Pin-outs Table 30. RJ-45 10/100/1000 NIC Connector Pin-out (J6A1) Pin 1 3 5 7 9 11 13 15 17 19 21 7.5.
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Connector/Header Locations and Pin-outs Intel®Server Board S1200BT TPS Table 33. SAS Connector Pin-out (J2H1) Pin 1 2 3 4 5 6 7 7.5.
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Intel®Server Board S1200BT TPS 7.5.6 Connector/Header Locations and Pin-outs USB Connector There are four external USB ports on two NIC/USB combinations. Section 5.5.2 details the pinout of the connector. Two 2x5 connector on the server board (J1D1, J1E1) provides an option to support an additional USB port, each connector supporting two USB ports. The following table defines the pin-out of the connector. Table 36.
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Connector/Header Locations and Pin-outs 7.6 Intel®Server Board S1200BT TPS PCI Express* Slot/PCI Slot/Riser Card Slot A PCI-E Riser card will enable a PCI-E add-on card to be accommodated in the 1U chassis. The following table shows the pin-out for this riser slot. Table 38. Pin-out of adaptive riser slot/PCI Express slot 6 Pin B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 Signal +12V +12V RSVD GND SMCLK SMDATA GND +3.3V JTAG1 +3.
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Intel®Server Board S1200BT TPS Pin Connector/Header Locations and Pin-outs Signal B39 GND B40 GND B41 PETP6 B42 PETN6 B43 GND B44 GND B45 PETP7 B46 PETN7 B47 GND B48 PRSNT2_N B49 GND End of x8 B50 PETP8 B51 PETN8 B52 GND B53 GND B54 PETP9 B55 PETN9 B56 GND B57 GND B58 PETP10 B59 PETN10 B60 GND B61 GND B62 PExP11 B63 PETN11 B64 GND B65 GND B66 PETP12 B67 PETN12 B68 GND B69 GND B70 PETP13 B71 PETN13 B72 GND B73 GND B74 PETP14 B75 PETN14 B76 GND B77 GND B78 PETP15 B79 PETN15 B80 GND B81 PRSNT2_N B82 RSVD
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Connector/Header Locations and Pin-outs Intel®Server Board S1200BT TPS Table 39. Three PCI Express* x8 connectors (J2B2, J3B1 and J4B2) Pin Signal Pin Signal Pin Signal Pin Signal A1 PRSNT1# B1 +12V A26 HSIP[2] B26 GND A2 A3 A4 A5 +12V +12V GND JTAG2/TCk B2 B3 B4 B5 +12V RESERVED GND SMCLK A27 A28 A29 A30 GND GND HSIP[3] HSIN[3] B27 B28 B29 B30 HSOP[3] HSON[3] GND RESERVED A6 JTAG3/TDI B6 SMDAT A31 GND B31 PRSNT2# A7 A8 A9 A10 JTAG4/TDO JTAG5/TMS +3.3V +3.
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Intel®Server Board S1200BT TPS Pin # Signal B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 7.7 REQ# V_IO AD[31] AD[29] Ground AD[27] AD[25] +3.3V C/BE[3]# AD[23] Ground AD[21] AD[19] +3.3V Connector/Header Locations and Pin-outs Pin # A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Signal Ground PME# AD[30] +3.3V AD[28] AD[26] Ground AD[24] IDSEL +3.3V AD[22] AD[20] Ground AD[18] Pin # B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 Signal M66EN KEY KEY AD[08] AD[07] +3.
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Jumper Blocks 8. Intel®Server Board S1200BT TPS Jumper Blocks The server board has several 3-pin jumper blocks that can be used to configure, protect or recover specific features of the server board. Figure 46. Jumper Blocks (J4A2, J1F1, J1F3, J1F2, and J1E2) on S1200BTL Table 42.
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Intel®Server Board S1200BT TPS Jumper Blocks Figure 47. Jumper Blocks (J2G1, J1G1, J1H3, and J2J1) on S1200BTS Table 43. Server Board Jumpers (J2G1, J1G1, J1H3, and J2J1) on S1200BTS Jumper Name J1H3: CMOS Clear Pins 1-2 2-3 J1J2: ME Force Update J1G1: Password Clear 1-2 2-3 1-2 2-3 J2G1: BIOS Recovery 1-2 2-3 8.1 System Results These pins should have a jumper in place for normal system operation.
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Jumper Blocks Intel®Server Board S1200BT TPS features has changed from previous generation Intel® server boards. The following procedure outlines the new usage model. 8.1.1 Clearing the CMOS To clear the CMOS, perform the following steps: 1. Power down the server. Do not unplug the power cord. 2. Open the server chassis. For instructions, see your server chassis documentation. 3. Move jumper from the default operating position (covering pins 1 and 2) to the reset/clear position (covering pins 2 and 3).
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Intel®Server Board S1200BT TPS 8.2 Jumper Blocks Integrated BMC Force Update Procedure (Only for The Intel® Server Board S1200BTL) When performing the standard Integrated BMC firmware update procedure, the update utility places the Integrated BMC into an update mode, allowing the firmware to load safely onto the flash device.
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Jumper Blocks Intel®Server Board S1200BT TPS 1. Power down and remove the AC power cord. 2. Open the server chassis. For instructions, see your server chassis documentation. 3. Move jumper from the default operating position (covering pins 1 and 2) to the enabled position (covering pins 2 and 3). 4. Close the server chassis. 5. Reconnect the AC cord and power up the server. 6. Perform the ME firmware update procedure as documented in the README.
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Intel®Server Board S1200BT TPS Intel®Light Guided Diagnostics Intel® Light Guided Diagnostics 9. The server board has several on-board diagnostic LEDs to assist in troubleshooting board-level issues. This section shows where each LED is located on the server board and describes the function of each LED. 9.1 System Status LED (Only for S1200BTL) The server board provides a system status indicator LED on the front panel.
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Intel®Light Guided Diagnostics Intel®Server Board S1200BT TPS Figure 48. POST Code Diagnostic LED Location A B C D E Status LED ID LED Diagnostic LED #7 (MSB LED) Diagnostic LED #6 Diagnostic LED #5 F G H I J Diagnostic LED #4 Diagnostic LED #3 Diagnostic LED #2 Diagnostic LED #1 Diagnostic LED #0 (LSB LED) 110 Revision 1.
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Intel®Server Board S1200BT TPS Design and Environmental Specifications 10. Design and Environmental Specifications 10.1 Intel® Server Board S1200BT Design Specifications The operation of the server board at conditions beyond those shown in the following table may cause permanent damage to the system. Exposure to absolute maximum rating conditions for extended periods may affect system reliability. Table 45.
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Design and Environmental Specifications Intel®Server Board S1200BT TPS suggested thermal and current design values for anticipating future processor needs. The following table provides maximum values for Icc, TDP power and TCASE for the Intel® Xeon® SandyBridge Series processor. ® ® Table 46. Intel Xeon Processor TDP Guidelines TDP Power 95 W Maximum TCASE Icc Maximum 67.0ºC 150 A 10.3 Power Supply Output Requirements This section is for reference purposes only.
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Intel®Server Board S1200BT TPS 10.3.1 Design and Environmental Specifications Grounding The grounds of the power supply output connector pins provide the power return path. The output connector ground pins are connected to the safety ground (power supply enclosure). This grounding is designed to ensure passing the maximum allowed common mode noise levels. The power supply is provided with a reliable protective earth ground. All secondary circuits are connected to protective earth ground.
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Design and Environmental Specifications Intel®Server Board S1200BT TPS ∆ Step Load Size (See note 2) Output +5 VSB Load Slew Rate 0.5 A Test capacitive Load 0.25 A/µsec 20 µF Note: Step loads on each 12 V output may happen simultaneously and should be tested that way. 10.3.6 Capacitive Loading The power supply is stable and meets all requirements with the following capacitive loading ranges. Table 50. Capacitve Loading Conditions Output 10.3.7 Minimum Maximum Units +3.
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Intel®Server Board S1200BT TPS Design and Environmental Specifications  The output voltages must rise from 10% to within regulation limits (Tvout_rise) within 5 ms to 70 ms, except for 5 VSB, in which case it is allowed to rise from 1.0 ms to 25 ms.  The +3.3 V, +5 V, and +12 V output voltages should start to rise approximately at the same time.  All outputs must rise monotonically.  The +5 V output must be greater than the +3.3 V output during any point of the voltage rise.
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Design and Environmental Specifications Intel®Server Board S1200BT TPS Table 53. Turn On/Off Timing Item Tsb_on_delay Tac_on_delay Tvout_holdup Tpwok_holdup Tpson_on_delay Tpson_pwok Tpwok_on Tpwok_off Tpwok_low Tsb_vout T5VSB_holdup Description Minimum Delay from AC being applied to 5 VSB being within regulation. Delay from AC being applied to all output voltages being within regulation. Duration for which all output voltages stay within regulation after loss of AC. Measured at 80% of maximum load.
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Intel®Server Board S1200BT TPS 10.3.11 Design and Environmental Specifications Residual Voltage Immunity in Standby Mode The power supply is immune to any residual voltage placed on its outputs (typically, a leakage voltage through the system from standby output) up to 500 mV. There is no additional heat generated nor stressing of any internal components with this voltage applied to any individual output and all outputs simultaneously.
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Design and Environmental Specifications Intel®Server Board S1200BT TPS Output Voltage -12 V +5 VSB Minimum (V) -13.3 5.7 118 Maximum (V) -14.5 6.5 Revision 1.
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Intel®Server Board S1200BT TPS Appendix A: Integration and Usage Tips Appendix A: Integration and Usage Tips  When adding or removing components or peripherals from the server board, AC power must be removed. With AC power plugged into the server board, 5-Volt standby is still present even though the server board is powered off.  When updating BIOS and BMC, AC power must be on.
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Appendix B: Integrated BMC Sensor Tables Intel®Server Board S1200BT TPS Appendix B: Integrated BMC Sensor Tables Intel® Server Board S1200BTL implements the below sensors: Sensor Type Codes Sensor table given below lists the sensor identification numbers and information regarding the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. Refer to the Intelligent Platform Management Interface Specification, Version 2.
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Intel®Server Board S1200BT TPS   Appendix B: Integrated BMC Sensor Tables T: Threshold value Rearm Sensors The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states. Rearming the sensors can be done manually or automatically. This column indicates the type supported by the sensor.
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Appendix B: Integrated BMC Sensor Tables Intel®Server Board S1200BT TPS Table 56. BMC Core Sensors Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Sensor Type Event/Reading Type Event Offset Triggers Contrib.
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Intel®Server Board S1200BT TPS Full Sensor Name (Sensor name in SDR) Sensor # Appendix B: Integrated BMC Sensor Tables Platform Applicability Sensor Type Event/Reading Type Event Offset Triggers Contrib.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Intel®Server Board S1200BT TPS Sensor Type Event/Reading Type Event Offset Triggers Contrib.
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Intel®Server Board S1200BT TPS Full Sensor Name (Sensor name in SDR) Sensor # Appendix B: Integrated BMC Sensor Tables Platform Applicability Sensor Type Event/Reading Type Event Offset Triggers Contrib.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Intel®Server Board S1200BT TPS Sensor Type Event/Reading Type Event Offset Triggers Contrib.
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Intel®Server Board S1200BT TPS Full Sensor Name (Sensor name in SDR) Sensor # Appendix B: Integrated BMC Sensor Tables Platform Applicability Sensor Type Event/Reading Type Event Offset Triggers Contrib. To System Status Assert/Deassert Readable Event Data Rearm Stand-by Value/Offsets Baseboard Processor Vcc (BB P1 Vcc) Baseboard Processor VccUSA (BB P1 VccUSA) Baseboard +1.05V PCH (BB +1.05V PCH) Baseboard +1.05V Auxiliary (BB +1.05V AUX) Baseboard +1.35V VDDQ (BB +1.
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Appendix B: Integrated BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Intel®Server Board S1200BT TPS Sensor Type Event/Reading Type Event Offset Triggers Contrib.
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Intel®Server Board S1200BT TPS Appendix C: POST Code Diagnostic LED Decoder Appendix C: POST Code Diagnostic LED Decoder During the system boot process, the BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the POST code to the POST Code Diagnostic LEDs on the back edge of the server board.
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Appendix C: POST Code Diagnostic LED Decoder Progress Code Intel®Server Board S1200BT TPS Diagnostic LED Decoder O = On, X=Off Upper Nibble Lower Nibble MSB 8h 4h 2h 1h 8h 4h 2h 1h LSB #7 #6 #5 #4 #3 #2 #1 #0 Description X X X X X O O X Early CPU initialization during Sec Phase X X X X X O O O Early South Bridge initialization X X X X O X X X 0x09 X X X X O X X O End Of Sec Phase 0x0E X X X X O O O X CPU Microcode Not Found. 0x0F X X X X O O O O CPU Microcode Not Loaded.
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Intel®Server Board S1200BT TPS Progress Code Appendix C: POST Code Diagnostic LED Decoder Diagnostic LED Decoder O = On, X=Off Upper Nibble Lower Nibble MSB 8h 4h 2h 1h 8h 4h 2h 1h LSB #7 #6 #5 #4 #3 #2 #1 #0 Description 0x71 X O O O X X X O DXE SB SMM initialization 0x72 X O O O X X O X DXE SB devices initialization 0x78 X O O O O X X X DXE ACPI initialization 0x79 X O O O O X X O DXE CSM initialization 0x90 O X X O X X X X DXE BDS Started 0x91 O X X O X X X O DXE BDS connect dr
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Appendix C: POST Code Diagnostic LED Decoder Progress Code Intel®Server Board S1200BT TPS Diagnostic LED Decoder O = On, X=Off Upper Nibble Lower Nibble MSB 8h 4h 2h 1h 8h 4h 2h 1h LSB #7 #6 #5 #4 #3 #2 #1 #0 Description 0xB1 O X O O X X X O RT Set Virtual Address Map End 0xB2 O X O O X X O X DXE Legacy Option ROM init 0xB3 O X O O X X O O DXE Reset system 0xB4 O X O O X O X X DXE USB Hot plug 0xB5 O X O O X O X O DXE PCI BUS Hot plug 0xB6 O X O O X O O X DXE NVRAM cleanup 0xB7
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Intel®Server Board S1200BT TPS Appendix D: POST Code Errors Appendix D: POST Code Errors The BIOS outputs the current boot progress codes on the video screen. Progress codes are 32bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. The class and subclass fields point to the type of hardware that is being initialized. The operation field represents the specific initialization activity.
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Appendix D: POST Code Errors Intel®Server Board S1200BT TPS Error Code Error Message Response 8180 Processor 01 microcode update not found Minor 8190 Watchdog timer failed on last boot Major 8198 OS boot watchdog timer failure Major 8300 Baseboard management controller failed self-test Major 8305 Hot Swap Controller failure Major 83A0 Management Engine (ME) failed Selftest Major 83A1 Management Engine (ME) Failed to respond.
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Intel®Server Board S1200BT TPS Appendix D: POST Code Errors POST Error Beep Codes The following table lists POST error beep codes. Prior to system video initialization, the BIOS uses these beep codes to inform users on error conditions. The beep code is followed by a user-visible code on POST Progress LEDs. Table 60. POST Error Beep Codes Beeps 3 Error Message Memory error POST Progress Code Multiple Description System halted because a fatal error related to the memory was detected.
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Appendix E: Supported Intel®Server Chassis Intel®Server Board S1200BT TPS Appendix E: Supported Intel® Server Chassis The Intel® Server Board S1200BT is supported in the following Intel® server chassis: 1. Intel® Server Chassis P4304XXSFCN 2. Intel® Server Chassis P4304XXSHCN 136 Revision 1.
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Intel®Server Board S1200BT TPS Glossary Glossary This appendix contains important terms used in this document. For ease of use, numeric entries are listed first (for example, ―82460GX‖) followed by alpha entries (for example, ―AGP 4x‖). Acronyms are followed by non-acronyms.
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Glossary Intel®Server Board S1200BT TPS Term Definition Hz Hertz (1 cycle/second) I2C Inter-Integrated Circuit Bus IA Intel Architecture IBF Input Buffer ICH I/O Controller Hub ICMB Intelligent Chassis Management Bus IERR Internal Error IFB I/O and Firmware Bridge ILM Independent Loading Mechanism IMC Integrated Memory Controller INTR Interrupt I/OAT I/O Acceleration Technology IOH I/O Hub IP Internet Protocol IPMB Intelligent Platform Management Bus IPMI Intelligent Platf
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Intel®Server Board S1200BT TPS Glossary Term Definition PECI Platform Environment Control Interface PEF Platform Event Filtering PEP Platform Event Paging PIA Platform Information Area (This feature configures the firmware for the platform hardware) PLD Programmable Logic Device PMI Platform Management Interrupt POST Power-On Self Test PSMI Power Supply Management Interface PWM Pulse-Width Modulation QPI QuickPath Interconnect RAM Random Access Memory RASUM Reliability, Availabili
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Glossary Intel®Server Board S1200BT TPS Term ZIF Definition Zero Insertion Force 140 Revision 1.
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Intel®Server Board S1200BT TPS Reference Documents Reference Documents Refer to the following documents for additional information:  Intel® Server Board S1200BT BIOS External Product Specification  Intel® Server Board S1200BT Common Core Integrated BMC External Product Specification Revision 1.