Technical Product Specification

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Intel

Server Board S2400EP

Intel order number G50763-002

Revision 2.0

December, 2013

Platform Collaboration and Systems Division - Marketing

Summary of content (168 pages)

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Intel®Server Board S2400EP Technical Product Specification Intel order number G50763-002 Revision 2.
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Revision History Intel®Server Board S2400EP TPS Revision History Date May 2012 Revision Number 1.0 Initial release. May 2012 1.01 Updated contents. July 2012 1.1 Updated contents. December 2013 2.0 Added support for Intel Xeon processor E5-2400 v2 product family ii Modifications ® ® Intel order number G50763-002 Revision 2.
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Intel®Server Board S2400EP TPS Disclaimers Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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Table of Contents Intel®Server Board S2400EP TPS Table of Contents 1. Introduction ........................................................................................................................ 1 1.1 Chapter Outline ...................................................................................................... 1 1.2 Server Board Use Disclaimer ................................................................................. 2 2. Product Overview .......................................
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Intel®Server Board S2400EP TPS Table of Contents 4.2.1 TPM security BIOS ............................................................................................... 47 4.2.2 Physical Presence ................................................................................................ 48 4.2.3 TPM Security Setup Options ................................................................................ 48 4.3 Intel® Trusted Execution Technology (Intel® TXT) .....................................
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Table of Contents Intel®Server Board S2400EP TPS 6.9.10 LAN Alerting ......................................................................................................... 75 6.9.11 Alert Policy Table ................................................................................................. 75 6.9.12 SM-CLP (SM-CLP Lite) ........................................................................................ 75 6.9.13 Embedded Web Server ...................................................
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Intel®Server Board S2400EP TPS Table of Contents 8.6.3 HSBP Header....................................................................................................... 98 8.6.4 SGPIO Header ..................................................................................................... 98 8.7 I/O Connectors ..................................................................................................... 98 8.7.1 VGA Connector ..............................................................
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Table of Contents 12.2.8 12.3 Intel®Server Board S2400EP TPS Timing Requirements ......................................................................................... 116 Residual Voltage Immunity in Stand-by Mode .................................................... 118 Appendix A: Integration and Usage Tips ............................................................................ 119 Appendix B: BMC Sensor Tables....................................................................................
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Intel®Server Board S2400EP TPS List of Figures List of Figures Figure 1. Intel® Server Board S2400EP Layout ........................................................................... 4 Figure 2. Intel® Light Guided Diagnostic LED Identification ......................................................... 5 Figure 3. Jumper Block Identification .......................................................................................... 6 Figure 4. Intel® Server Boards S2400EP2/S2400EP4 Rear I/O Layout ........
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List of Figures Intel®Server Board S2400EP TPS Figure 33. Output Voltage Timing ........................................................................................... 117 Figure 34. Turn On/Off Timing (Power Supply Signals) .......................................................... 118 Figure 35.POST Diagnostic LED Location .............................................................................. 138 Figure 36. Intel® Server System R1000EP ........................................................
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Intel®Server Board S2400EP TPS List of Tables List of Tables Table 1. Intel® Server Boards S2400EP Feature Set .................................................................. 3 Table 2. Mixed Processor Configurations Error Summary (Preliminary. Subject to Change) .... 20 Table 3. UDIMM Support Guidelines (Preliminary. Subject to Change) ..................................... 24 Table 4. RDIMM Support Guidelines (Preliminary. Subject to Change) ..................................... 25 Table 5.
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List of Tables Intel®Server Board S2400EP TPS Table 33. Multiport SAS/SATA Connector Pin-out (SCU_0 (0-3)) ............................................. 94 Table 34. Multiport SAS/SATA Connector Pin-out (SCU_1 (4-7)) ............................................. 94 Table 35. Internal Type-A USB Connector Pin-out (USB_6) ..................................................... 95 Table 36. SSI 4-pin Fan Header Pin-out ...................................................................................
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Intel®Server Board S2400EP TPS List of Tables Table 67. POST Progress Codes ............................................................................................ 139 Table 68. MRC Progress Codes ............................................................................................. 141 Table 69. MRC Fatal Error Codes ........................................................................................... 142 Table 70. POST Error Beep Codes ..................................................
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List of Tables Intel®Server Board S2400EP TPS xiv Intel order number G50763-002 Revision 2.
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Intel®Server Board S2400EP TPS 1. Introduction Introduction This Technical Product Specification (TPS) provides board specific information detailing the ® features, functionality, and high-level architecture of the Intel Server Board S2400EP. Design-level information related to specific server board components and subsystems can be obtained by ordering External Product Specifications (EPS) or External Design Specifications (EDS) related to this server generation.
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Introduction 1.2 Intel®Server Board S2400EP TPS Server Board Use Disclaimer ® Intel Server Boards contain a number of high-density VLSI (Very-large-scale integration) and power delivery components that require adequate airflow for cooling. Intel® ensures through its own chassis development and testing that when Intel® server building blocks are used together, the fully integrated system meets the intended thermal requirements of these components.
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Intel®Server Board S2400EP TPS 2. Product Overview Product Overview The Intel® Server Board S2400EP is monolithic printed circuit boards (PCBs) with features designed to support the 1U rack server markets. This server board is designed to support the Intel® Xeon® processor E5-2400 product family. Previous generation Intel® Xeon® processors are not supported. 2.1 Intel®Server Boards S2400EP Feature Set ® Table 1.
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Product Overview Intel®Server Board S2400EP TPS Feature Description Video  Integrated 2D Video Controller  16 MB DDR3 Memory Storage  Two 7-pin single port AHCI SATA connectors capable of supporting up to 6 Gb/sec  Two SCU 4-port mini-SAS connectors capable of supporting up to eight 3 Gb/sec SAS/SATA HDD ®  Intel RAID C600 Upgrade Key support providing expanded SATA/SAS RAID capabilities Security Intel TPM module – AXXTPME5 (Accessory Option) Server Management     Form Factor SSI CEB 1
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Intel®Server Board S2400EP TPS Product Overview ® Figure 2. Intel Light Guided Diagnostic LED Identification Revision 2.
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Product Overview Intel®Server Board S2400EP TPS Figure 3. Jumper Block Identification 6 Intel order number G50763-002 Revision 2.
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Intel®Server Board S2400EP TPS Product Overview ® Figure 4. Intel Server Boards S2400EP2/S2400EP4 Rear I/O Layout Revision 2.
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Product Overview 2.3 Intel®Server Board S2400EP TPS Server Board Mechanical Drawings Figure 5. Major Board Components 8 Intel order number G50763-002 Revision 2.
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Intel®Server Board S2400EP TPS Product Overview ® Figure 6. Intel Server Board S2400EP – Mounting Hole Locations (1 of 2) Revision 2.
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Product Overview Intel®Server Board S2400EP TPS ® Figure 7. Intel Server Board S2400EP – Mounting Hole Locations (2 of 2) 10 Intel order number G50763-002 Revision 2.
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Intel®Server Board S2400EP TPS Product Overview ® Figure 8. Intel Server Boards S2400EP – Major Connector Pin-1 Locations (1 of 2) Revision 2.
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Product Overview Intel®Server Board S2400EP TPS ® Figure 9. Intel Server Boards S2400EP – Major Connector Pin-1 Locations (2 of 2) 12 Intel order number G50763-002 Revision 2.
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Intel®Server Board S2400EP TPS Product Overview ® Figure 10. Intel Server Boards S2400EP – Primary Side Keep-out Zone Revision 2.
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Product Overview Intel®Server Board S2400EP TPS ® Figure 11. Intel Server Boards S2400EP – Primary Side Card Side Keep-out Zone 14 Intel order number G50763-002 Revision 2.
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Intel®Server Board S2400EP TPS Product Overview ® Figure 12. Intel Server Boards S2400EP – Primary Side Air Duct Keep-out Zone Revision 2.
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Product Overview Intel®Server Board S2400EP TPS ® Figure 13. Intel Server Boards S2400EP – Second Side Keep-out Zone . 16 Intel order number G50763-002 Revision 2.
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Intel®Server Board S2400EP TPS 3. Product Architecture Overview Product Architecture Overview The architecture and design of the Intel® Server Board S2400EP is developed around the ® ® integrated features and functions of the Intel Xeon processor E5-2400 product family, the ® ® Intel C602 (-A) chipset, the Intel Ethernet Controller I350 GbE controller chip, and the Server Engines* Pilot-III Server Management Controller.
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Product Architecture Overview Intel®Server Board S2400EP TPS ® ® ® Note: Previous generation Intel Xeon processors are not supported on the Intel server boards described in this document. Visit the Intel® web site for a complete list of supported processors. 3.1.1 Processor Socket Assembly Each processor socket of the server board is pre-assembled with an Independent Latching Mechanism (ILM) and Back Plate which allow for secure placement of the processor and processor heat to the server board.
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Intel®Server Board S2400EP TPS Product Architecture Overview When using a single processor configuration, the processor must be installed into the processor socket labeled “CPU_1”. When two processors are installed, the following population rules apply:  Both processors must be of the same processor family.  Both processors must have the same number of cores.  Both processors must have the same cache size for all levels of processor cache memory.
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Product Architecture Overview Intel®Server Board S2400EP TPS Minor: The message is displayed on the screen or on the Error Manager screen, and the POST Error Code is logged to the SEL. The system continues booting in a degraded state. The user may want to replace the erroneous unit. The POST Error Pause option setting in the BIOS setup does not have any effect on this error. Table 2. Mixed Processor Configurations Error Summary (Preliminary.
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Intel®Server Board S2400EP TPS Error Processor frequency (speed) not identical Product Architecture Overview Severity Fatal System Action The BIOS detects the processor frequency difference, and responds as follows:  Adjusts all processor frequencies to the highest common frequency.  No error is generated – this is not an error condition.  Continues to boot the system successfully.
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Product Architecture Overview 3.2 Intel®Server Board S2400EP TPS Processor Function Overview With the release of the Intel® Xeon® processor E5-2400 product family, several key system components, including the CPU, Integrated Memory Controller (IMC), and Integrated IO Module (IIO), have been combined into a single processor package and feature per socket; One Intel® QuickPath Interconnect point-to-point links capable of up to 8.0 GT/s, up to 24 lanes of Gen 3 PCI Express* links capable of 8.
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Intel®Server Board S2400EP TPS 3.2.1 Product Architecture Overview Intel®QuickPath Interconnect ® The Intel QuickPath Interconnect is a high speed, packetized, point-to-point interconnect used in the processor. The narrow high-speed links stitch together processors in distributed shared memory and integrated I/O platform architecture. It offers much higher bandwidth with low latency.
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Product Architecture Overview Intel®Server Board S2400EP TPS  LRDIMM DDR3 – QR – x4 and x8 data widths with direct map or with rank multiplication Up to 8 ranks supported per memory channel, 1, 2 or 4 ranks per DIMM  Open with adaptive idle page close timer or closed page policy  Per channel memory test and initialization engine can initialize DRAM to all logical zeros with valid ECC (with or without data scrambler) or a predefined test pattern  Isochronous access support for Quality of Service
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Intel®Server Board S2400EP TPS Product Architecture Overview SRx8 ECC 1GB 2GB 4GB 1066, 1333 1066, 1333 1066, 1333 1066, 1333 1066 1066 DRx8 ECC 2GB 4GB 8GB 1066, 1333 1066, 1333 1066, 1333 1066, 1333 1066 1066 Notes: ® 1. Supported DRAM Densities are 1Gb, 2Gb, and 4Gb. Only 2Gb and 4Gb are validated by Intel . 2. Command Address Timing is 1N for 1DPC and 2N for 2DPC. 3. For Memory Population Rules, please refer to the Romley Platform Design Guide.
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Product Architecture Overview 3.2.2.2 Intel®Server Board S2400EP TPS Memory Slot Identification and Population Rules Note: Although mixed DIMM configurations may be functional, Intel® only performs platform validation on systems that are configured with identical DIMMs installed. Each processor provides four banks of memory, each capable of supporting up to 2 DIMMs.  DIMMs are organized into physical slots on DDR3 memory channels that belong to processor sockets.
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Intel®Server Board S2400EP TPS Product Architecture Overview ® Figure 17. Intel Server Board S2400EP DIMM Slot Layout The following are generic DIMM population requirements that generally apply to the Intel Server Board S2400EP. ®  All DIMMs must be DDR3 DIMMs  Registered DIMMs must be ECC only, Unbuffered DIMMs can be ECC or non-ECC. . However, Intel® only validates and supports ECC memory for its server products.  Mixing of Registered and Unbuffered DIMMs is not allowed per platform.
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Product Architecture Overview Intel®Server Board S2400EP TPS  When one DIMM is used, it must be populated in the BLUE DIMM slot (farthest away from the CPU) of a given channel.  When single, dual and quad rank DIMMs are populated for 2DPC, always populate the higher number rank DIMM first (starting from the farthest slot), for example, first quad rank, then dual rank, and last single rank DIMM. 3.2.2.
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Intel®Server Board S2400EP TPS Product Architecture Overview population between channels (Mirrored and Lockstep) require that ECC DIMMs be populated. Independent Channel Mode is the only mode that supports non-ECC DIMMs in addition to ECC DIMMs. For RAS modes that require matching populations, the same slot positions across channels must hold the same DIMM type with regards to size and organization.
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Product Architecture Overview 3.2.2.4.3 Intel®Server Board S2400EP TPS Mirrored Channel Mode Channel Mirroring Mode gives the best memory RAS capability by maintaining two copies of the data in main memory. If there is an Uncorrectable ECC Error, the channel with the error is disabled and the system continues with the “good” channel, but in a non-redundant configuration.
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Intel®Server Board S2400EP TPS Product Architecture Overview on independent channels are configured to deliver a burst length of eight. The maximum read bandwidth for a given Rank is half of peak. There is another draw back in using lockstep mode, that is, higher power consumption since the total activation power is about twice of the independent channel operation if comparing to same type of DIMMs. 3.2.2.
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Product Architecture Overview Intel®Server Board S2400EP TPS However, before returning control to the OS drivers via Machine Check Exception (MCE) or Non-Maskable Interrupt (NMI), the Uncorrectable Memory ECC Error is logged to the SEL, the appropriate memory slot fault LED is lit, and the System Status LED state is changed to solid Amber. 3.2.2.
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Intel®Server Board S2400EP TPS Product Architecture Overview Figure 18. Functional Block Diagram of Processor IIO Sub-system The following sub-sections will describe the server board features that are directly supported by the processor IIO module. These include the Riser Card Slots, Network Interface, and connectors for the optional I/O modules and SAS Module. Features and functions of the Intel® C600 Series chipset will be described in its own dedicated section. 3.2.3.
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Product Architecture Overview Intel®Server Board S2400EP TPS Figure 19. Server Board Layout - I/O Module Connector Supported I/O modules include: ® Table 6. Supported Intel I/O Module Options (TBD) Description 4-port 1Gb Ethernet Networking IO Module (“Powerville) 2-port 10Gb Ethernet Networking IO Module (“Twinville”) 2-port 10Gb Ethernet SFP IO Module (“Niantic”) FDR InfiniBand* I/O Module 3.2.
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Intel®Server Board S2400EP TPS Product Architecture Overview Figure 20. Functional Block Diagram – Chipset Supported Features and Functions ® On the Intel Server Boards S2400EP, the chipset provides support for the following on-board functions:       PCI Express* root ports Low Pin Count (LPC) interface Universal Serial Bus (USB) Controller Serial Attached SCSI (SAS)/Serial ATA (SATA) Support Intel® Rapid Storage Technology Manageability Features 3.3.
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Product Architecture Overview    Intel®Server Board S2400EP TPS Two USB ports are routed to an internal 10-pin connector that can be cabled for front panel support One internal Type ‘A’ USB port Two USB ports are routed to the INTEGRATED BMC 3.3.3 On-board serial Attached SCSI (SAS)/Serial ATA(SATA) Support and Options ® The Intel C600-A chipset provides storage support via two integrated controllers: AHCI and SCU.
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Intel®Server Board S2400EP TPS 3.3.4 Product Architecture Overview Network Interface ® On-board network connectivity is provided by means of two onboard Intel Ethernet Controller I350 providing up to two 10/100/1000 Mb Ethernet ports. The NIC chip is supported by implementing x4 PCIe Gen2 signals from the Intel® C600 PCH. On the Intel® Server Board S2400EP2, two external 10/100/1000 Mb RJ45 Ethernet ports are provided.
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Product Architecture Overview Intel®Server Board S2400EP TPS  BMC LAN channel 1 MAC address = NIC1 MAC address + 2  BMC LAN channel 2 MAC address = NIC1 MAC address + 3  BMC LAN channel 3 (RMM4) MAC address = NIC1 MAC address + 4 The printed MAC address on the server board and/or server system is assigned to NIC1 on the server board. 3.3.
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Intel®Server Board S2400EP TPS Product Architecture Overview ® Table 9.
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Product Architecture Overview Intel®Server Board S2400EP TPS  OS Support = Windows 7*, Windows 2008*, Windows 2003*, RHEL*, SLES*, other Linux* variants using partial source builds.  Utilities = Windows* GUI and CLI, Linux* GUI and CLI, DOS CLI, and EFI CLI 3.3.5.
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Intel®Server Board S2400EP TPS 3.4 Product Architecture Overview Integrated Baseboard Management Controller Overview The server board utilizes the I/O controller, Graphics Controller, and Baseboard Management features of the ServerEngines* Pilot-III Server Management Controller. The following is an overview of the features as implemented on the server board from each embedded controller. Figure 22. Functional Block Diagram – integrated BMC Supported Features and Functions Revision 2.
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Product Architecture Overview Intel®Server Board S2400EP TPS Figure 23. Integrated BMC Hardware 3.4.
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Intel®Server Board S2400EP TPS 3.4.1.1 Product Architecture Overview Keyboard and Mouse Support The server board does not support PS/2 interface keyboards and mice. However, the system BIOS recognizes USB specification-compliant keyboard and mice. 3.4.2 Wake-up Control The super I/O contains functionality that allows various events to power on and power off the system. 3.4.
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Product Architecture Overview Intel®Server Board S2400EP TPS Table 11. Video mode On-board Video Enabled Disabled Dual Monitor Video Enabled Shaded if on-board video is set to "Disabled" Disabled 3.4.4 Baseboard Management Controller The server board utilizes the following features of the embedded baseboard management controller.                          3.4.4.1    44 IPMI 2.
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Intel®Server Board S2400EP TPS     Product Architecture Overview Supports both text and Graphics redirection Hardware assisted Video redirection using the Frame Processing Engine Direct interface to the Integrated Graphics Controller registers and Frame buffer Hardware-based encryption engine Revision 2.
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Additional Embedded Server Feature Options Intel®Server Board S2400EP TPS 4. Additional Embedded Server Feature Options 4.1 BIOS Password Protection The BIOS uses passwords to prevent unauthorized tampering with the server setup. Passwords can restrict entry to the BIOS Setup, restrict use of the Boot Popup menu, and suppress automatic USB device reordering. There is also an option to require a Power On password entry in order to boot the system.
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Intel®Server Board S2400EP TPS Additional Embedded Server Feature Options In addition to restricting access to most Setup fields to viewing only when a User password is entered, defining a User password imposes restrictions on booting the system. In order to simply boot in the defined boot order, no password is required. However, the F6 Boot popup prompts for a password, and can only be used with the Administrator password.
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Additional Embedded Server Feature Options Intel®Server Board S2400EP TPS  Produces ACPI TPM device and methods to allow a TPM-enabled operating system to send TPM administrative command requests to the BIOS.  Verifies operator physical presence. Confirms and executes operating system TPM administrative command requests.  Provides BIOS Setup options to change TPM security states and to clear TPM ownership.
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Intel®Server Board S2400EP TPS 4.2.3.1 Additional Embedded Server Feature Options Security Screen ® To enter the BIOS Setup, press the F2 function key during boot time when the OEM or Intel logo displays. The following message displays on the diagnostics screen and under the Quiet Boot logo screen: Press to enter setup When the Setup is entered, the Main screen displays.
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Additional Embedded Server Feature Options Intel®Server Board S2400EP TPS Table 12. TPM Setup Utility – Security Configuration Screen Fields Setup Item TPM State* Options Enabled and Activated Help Text – Comments Information only. Enabled and Deactivated Shows the current TPM device state. Disabled and Activated A disabled TPM device will not execute commands that use TPM functions and TPM security operations will not be available.
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Intel®Server Board S2400EP TPS Additional Embedded Server Feature Options Technology requires the system to include a TPM v1.2, as defined by the Trusted Computing Group TPM PC Client specifications, Revision 1.2. When available, Intel® Trusted Execution Technology can be enabled or disabled in the processor via a BIOS Setup option. For general information about Intel® TXT, visit the Intel® Trusted Execution Technology website, http://www.intel.com/technology/security/. Revision 2.
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Technology Support Intel®Server Board S2400EP TPS 5. Technology Support 5.1 Intel®Trusted Execution Technology The Intel® Xeon® Processor E5 4600/2600/2400/1600 Product Families support Intel® Trusted Execution Technology (Intel® TXT), which is a robust security environment designed to help protect against software-based attacks. Intel® Trusted Execution Technology integrates new security features and capabilities into the processor, chipset and other platform components.
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Intel®Server Board S2400EP TPS Technology Support DMAR. Each RMRR has a Device Scope listing the devices in the system that can cause a DMA request to the region. For more information on the DMAR table and the DRHD entry format, refer to the Intel® Virtualization Technology for Directed I/O Architecture Specification. For more general information about VT-x, VT-d, and VT-c, a good reference is Enabling Intel® Virtualization Technology Features and Benefits White Paper. 5.
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Technology Support Intel®Server Board S2400EP TPS The NM feature is implemented by a complementary architecture utilizing the ME, BMC, BIOS, and an ACPI-compliant OS. The ME provides the NM policy engine and power control/limiting functions (referred to as Node Manager or NM) while the BMC provides the external LAN link by which external management software can interact with the feature.
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Intel®Server Board S2400EP TPS Technology Support monitoring device is possible (there is potential loss in accuracy and responsiveness using nonPMBus* devices). The NM SmaRT/CLST feature does specifically require PMBus*-compliant power supplies as well as additional hardware on the baseboard. Revision 2.
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Platform Management Functional Overview 6. Intel®Server Board S2400EP TPS Platform Management Functional Overview Platform management functionality is supported by several hardware and software components integrated on the server board that work together to control system functions, monitor and report system health, and control various thermal and performance features in order to maintain (when possible) server functionality in the event of component failure and/or environmentally stressed conditions.
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Intel®Server Board S2400EP TPS Platform Management Functional Overview o  BMC self-test: The BMC performs initialization and run-time self-tests and makes results available to external entities. See also the Intelligent Platform Management Interface Specification Second Generation v2.0. 6.1.2 Non IPMI Features The BMC supports the following non-IPMI features.
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Platform Management Functional Overview Intel®Server Board S2400EP TPS  Power state retention  Power fault analysis  Intel® Light-Guided Diagnostics  Address Resolution Protocol (ARP): The BMC sends and responds to ARPs (supported on embedded NICs).  Dynamic Host Configuration Protocol (DHCP): The BMC performs DHCP (supported on embedded NICs).  E-mail alerting  Embedded web server o Support for embedded web server UI in Basic Manageability feature set.
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Intel®Server Board S2400EP TPS Platform Management Functional Overview Table 14. ACPI Power States State S0 Supported Yes S1 Yes Description Working.  The front panel power LED is on (not controlled by the BMC).  The fans spin at the normal speed, as determined by sensor inputs.  Front panel buttons work normally. Sleeping. Hardware context is maintained; equates to processor and chipset clocks being stopped.
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Platform Management Functional Overview Intel®Server Board S2400EP TPS FW defect triggered by a rare sequence of events or a BMC hang due to some type of HW glitch (for example, power). This feature is comprised of a set of capabilities whose purpose is to detect misbehaving subsections of BMC firmware, the BMC CPU itself, or HW subsystems of the BMC component, and to take appropriate action to restore proper operation.
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Intel®Server Board S2400EP TPS Platform Management Functional Overview The BIOS gets the watchdog expiration status from the BMC. If the status shows an expired FRB2 timer, the BIOS enters the failure in the system event log (SEL). In the OEM bytes entry in the SEL, the last POST code generated during the previous boot attempt is written. FRB2 failure is not reflected in the processor status sensor value. The FRB2 failure does not affect the front panel LEDs. 6.
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Platform Management Functional Overview Intel®Server Board S2400EP TPS Events logged to the SEL can be viewed using Intel’s SELVIEW utility, Embedded Web Server, and Active System Console. 6.8 System Fan Management The BMC controls and monitors the system fans. Each fan is associated with a fan speed sensor that detects fan failure and may also be associated with a fan presence sensor for hotswap support.
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Intel®Server Board S2400EP TPS Type OLTT OLTT OLTT OLTT OLTT OLTT CLTT CLTT CLTT CLTT Platform Management Functional Overview Profile 2 3 4 5 6 7 1 3 5 7 Details Acoustic, 900M altitude Performance, 900M altitude Acoustic, 1500M altitude Performance, 1500M altitude Acoustic, 3000M altitude Performance, 3000M altitude 300M altitude 900M altitude 1500M altitude 3000M altitude Each group of profiles allows for varying fan control policies based on the altitude.
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Platform Management Functional Overview Intel®Server Board S2400EP TPS Figure 25. Fan Speed Control Process 6.8.4 Memory Thermal Throttling The server board provides support for system thermal management through open loop throttling (OLTT) and closed loop throttling (CLTT) of system memory. Normal system operation uses closed-loop thermal throttling (CLTT) and DIMM temperature monitoring as major factors in overall thermal and acoustics management.
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Intel®Server Board S2400EP TPS  Platform Management Functional Overview Dynamic Closed Loop Thermal Throttling (Dynamic-CLTT): CLTT control registers are configured by BIOS MRC during POST. The memory throttling is run as a closed-loop system with the DIMM temperature sensors as the control input. Adjustments are made to the throttling during runtime based on changes in system cooling (fan speed).
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Platform Management Functional Overview Intel®Server Board S2400EP TPS 2. User 2 (“root”) always has the administrator privilege level. 3. All user passwords (including passwords for 1 and 2) may be modified. User IDs 3-15 may be used freely, with the condition that user names are unique. Therefore, no other users can be named “” (Null), “root,” or any other existing user name. 6.9.
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Intel®Server Board S2400EP TPS Platform Management Functional Overview The NC-SI is a DMTF industry standard protocol for the side band management LAN interface. This protocol provides a fast multi-drop interface for management traffic. The baseboard NIC(s) are connected to a single BMC RMII/RGMII port that is configured for RMII operation. The NC-SI protocol is used for this connection and provides a 100 Mb/s fullduplex multi-drop interface which allows multiple NICs to be connected to the BMC.
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Platform Management Functional Overview Intel®Server Board S2400EP TPS  NIC 3 MAC address = NIC 1 MAC address + 2 (for OS usage)  NIC 4 MAC address = NIC 1 MAC address + 3 (for OS usage)  BMC LAN channel 1 MAC address = NIC1 MAC address + 4  BMC LAN channel 2 MAC address = NIC1 MAC address + 5  BMC LAN channel 3 (RMM4) MAC address = NIC1 MAC address + 6 The printed MAC address on the server board and/or server system is assigned to NIC1 on the server board.
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Intel®Server Board S2400EP TPS Platform Management Functional Overview The BMC supports IPv4 and IPv6 simultaneously so they are both configured separately and completely independently. For example, IPv4 can be DHCP configured while IPv6 is statically configured or vice versa. The parameters for IPv6 are similar to the parameters for IPv4 with the following differences:  An IPv6 address is 16 bytes vs. 4 bytes for IPv4.  An IPv6 prefix is 0 to 128 bits whereas IPv4 has a 4-byte subnet mask.
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Platform Management Functional Overview Intel®Server Board S2400EP TPS The LAN Failover feature applies only to BMC LAN traffic. It bonds all available Ethernet devices but only one is active at a time. When enabled, If the active connection’s leash is lost, one of the secondary connections is automatically configured so that it has the same IP address (the next active LAN link will be chosen randomly from the pool of backup LAN links with link status as “UP”).
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Intel®Server Board S2400EP TPS  Platform Management Functional Overview LAN configuration parameter 12 (Default Gateway Address) When changing from DHCP to Static configuration, the initial values of these three parameters will be equivalent to the existing DHCP-set parameters. Additionally, the BMC observes the following network safety precautions: 1. The user may only set a subnet mask that is valid, per IPv4 and RFC 950 (Internet Standard Subnetting Procedure).
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Platform Management Functional Overview  Intel®Server Board S2400EP TPS LAN configuration parameter 12 (Default Gateway Address) To prevent users from disrupting the BMC’s LAN configuration, the BMC treats these parameters as read-only while DHCP is enabled for the associated LAN channel. Using the Set LAN Configuration Parameter command to attempt to change one of these parameters under such circumstances has no effect, and the BMC returns error code 0xD5, “Cannot Execute Command.
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Intel®Server Board S2400EP TPS Platform Management Functional Overview  Echo request (ping): The BMC sends an Echo Reply.  Destination unreachable: If message is associated with an active socket connection within the BMC, the BMC closes the socket. 6.9.6 Virtual Local Area Network (VLAN) The BMC supports VLAN as defined by IPMI 2.0 specifications. VLAN is supported internally by the BMC, not through switches.
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Platform Management Functional Overview 6.9.7 Intel®Server Board S2400EP TPS Secure Shell (SSH) Secure Shell (SSH) connections are supported for SMASH-CLP sessions to the BMC. 6.9.8 Serial-over-LAN (SOL 2.0) The BMC supports IPMI 2.0 SOL. IPMI 2.0 introduced a standard serial-over-LAN feature. This is implemented as a standard payload type (01h) over RMCP+. Three commands are implemented for SOL 2.0 configuration.  “Get SOL 2.0 Configuration Parameters” and “Set SOL 2.
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Intel®Server Board S2400EP TPS  Power off  Power cycle  Reset  OEM action  Alerts Platform Management Functional Overview The “Diagnostic interrupt” action is not supported. 6.9.10 LAN Alerting The BMC supports sending embedded LAN alerts, called SNMP PET (Platform Event traps), and SMTP email alerts. The BMC supports a minimum of four LAN alert destinations. 6.9.10.
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Platform Management Functional Overview Intel®Server Board S2400EP TPS The SM-CLP utilized by a remote user by connecting a remote system via one of the system NICs. It is possible for third party management applications to create scripts using this CLP and execute them on server to retrieve information or perform management tasks such as reboot the server, configure events, and so on. The BMC embedded SM-CLP feature includes the following capabilities:  Power on/off/reset the server.
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Intel®Server Board S2400EP TPS Platform Management Functional Overview interface shall authenticate the user before allowing a web session to be initiated. Encryption using 128-bit SSL is supported. User authentication is based on user id and password. The GUI presented by the embedded web server authenticates the user before allowing a web session to be initiated. It presents all functions to all users but grays-out those functions that the user does not have privilege to execute.
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Platform Management Functional Overview Intel®Server Board S2400EP TPS  Display of processor and memory information as is available over IPMI over LAN.  Ability to get and set Node Manager (NM) power policies.  Display of power consumed by the server.  Ability to view and configure VLAN settings.  Warn user the reconfiguration of IP address will cause disconnect.  Capability to block logins for a period of time after several consecutive failed login attempts.
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Intel®Server Board S2400EP TPS Platform Management Functional Overview  Note that the chassis ID will turn on because of the original chassis ID button press and will reflect in the Virtual Front Panel after VFP sync with BMC. Virtual Front Panel won’t reflect the chassis LED software blinking via software command as there is no mechanism to get the chassis ID Led status.  Only Infinite chassis ID ON/OFF via software command will reflect in EWS during automatic/manual EWS sync up with BMC.
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Platform Management Functional Overview Intel®Server Board S2400EP TPS  System memory map. The system memory map is provided by BIOS on the current boot. This includes the EFI memory map and the Legacy (E820) memory map depending on the current boot.  Power supplies debug capability. o Capture of power supply “black box” data and power supply asset information. Power supply vendors are adding the capability to store debug data within the power supply itself.
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Intel®Server Board S2400EP TPS Platform Management Functional Overview Category Internal BMC Data External BMC Data External BIOS Data System Data Data BMC uptime/load Process list Free Memory Detailed Memory List Filesystem List/Info BMC Network Info BMC Syslog BMC Configuration Data Hex SEL listing Human-readable SEL listing Human-readable sensor listing BIOS configuration settings POST codes for the two most recent boots SMBIOS table for the current boot 256 bytes of PCI config data for each PCI dev
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Advanced Management Feature Support (RMM4) 7. Intel®Server Board S2400EP TPS Advanced Management Feature Support (RMM4) The integrated baseboard management controller has support for advanced management ® features which are enabled when an optional Intel Remote Management Module 4 (RMM4) is installed. RMM4 is comprised of two boards – RMM4 lite and the optional Dedicated Server Management NIC (DMN). Table 21.
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Intel®Server Board S2400EP TPS Advanced Management Feature Support (RMM4) ® Figure 27. Intel RMM4 Dedicated Management NIC Installation Table 22. Enabling Advanced Management Features Manageability Hardware Benefits ® Comprehensive IPMI based base manageability features ® No dedicated NIC for management Enables KVM and media redirection via onboard NIC ® Dedicated NIC for management traffic. Higher bandwidth connectivity for KVM and media Redirection with 1Gbe NIC.
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Advanced Management Feature Support (RMM4) Intel®Server Board S2400EP TPS physically at the managed server. KVM redirection console support the following keyboard layouts: English, Dutch, French, German, Italian, Russian, and Spanish. KVM redirection includes a “soft keyboard” function. The “soft keyboard” is used to simulate an entire keyboard that is connected to the remote system.
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Intel®Server Board S2400EP TPS 7.1.2 Advanced Management Feature Support (RMM4) Performance The remote display accurately represents the local display. The feature adapts to changes to the video resolution of the local display and continues to work smoothly when the system transitions from graphics to text or vice-versa. The responsiveness may be slightly delayed depending on the bandwidth and latency of the network. Enabling KVM and/or media encryption will degrade performance.
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Advanced Management Feature Support (RMM4) Intel®Server Board S2400EP TPS Once mounted, the remote device appears just like a local device to the server, allowing system administrators or users to install software (including operating systems), copy files, update BIOS, and so on, or boot the server from this device. The following capabilities are supported:  The operation of remotely mounted devices is independent of the local devices on the server. Both remote and local devices are useable in parallel.
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Intel®Server Board S2400EP TPS Advanced Management Feature Support (RMM4)  5120 – CD Redirection  5123 – FD Redirection  5124 – CD Redirection (Secure)  5127 – FD Redirection (Secure)  7578 – Video Redirection  7582 – Video Redirection (Secure) Revision 2.
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On-board Connector/Header Overview 8. Intel®Server Board S2400EP TPS On-board Connector/Header Overview This section identifies the location and pin-out for on-board connectors and headers of the server board that provide an interface to system options/features, on-board platform management, or other user accessible options/features. 8.1 Power Connectors The main power supply connection uses an SSI-compliant 2x12 pin connector.
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Intel®Server Board S2400EP TPS Pin 2 3 4 5 8.2 On-board Connector/Header Overview Signal SMB_DAT_FP_PWR_R SMB_ALRT_3_ESB_R 3.3 V SENSE3.3 V SENSE+ Color Black Red Yellow Green Front Panel Headers and Connectors The server board includes several connectors that provide various possible front panel options. This section provides a functional description and pin-out for each connector. 8.2.
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On-board Connector/Header Overview 8.2.1.1 Intel®Server Board S2400EP TPS Power/Sleep Button and LED Support Pressing the Power button will toggle the system power on and off. This button also functions as a sleep button if enabled by an ACPI compliant operating system. Pressing this button will send a signal to the integrated BMC, which will power on or power off the system. The power LED is a single color and is capable of supporting different indicator states as defined in the following table.
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Intel®Server Board S2400EP TPS On-board Connector/Header Overview Table 28. NMI Signal Generation and Event Logging Causal Event Signal Generation NMI Front Panel Diag Interrupt Sensor Event Logging Support Chassis Control command (pulse diagnostic interrupt) X – Front panel diagnostic interrupt button pressed X X Watchdog Timer pre-timeout expiration with NMI/diagnostic interrupt action X X 8.2.1.
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On-board Connector/Header Overview Color State Intel®Server Board S2400EP TPS Criticality Description Correctable Errors over a threshold and migrating to a spare DIMM (memory sparing). This indicates that the user no longer has spared DIMMs indicating a redundancy lost condition. Corresponding DIMM LED lit.  Uncorrectable memory error has occurred in memory Mirroring Mode, causing Loss of Redundancy.
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Intel®Server Board S2400EP TPS 8.2.2 On-board Connector/Header Overview Front Panel USB Connector The server board includes a 10-pin connector, that when cabled, can provide up to two USB ports to a front panel. On the server board the connector is labeled “FP USB” and is located on the front edge of the board. The following table provides the connector pin-out. Table 30. Front Panel USB Connector Pin-out (FP USB) Signal Description P5V_USB_FP USB2_P11_F_D N USB2_P11_F_DP GROUND 8.2.
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On-board Connector/Header Overview Intel®Server Board S2400EP TPS SATA_TXN GROUND SATA_RXN SATA_RXP GROUND 8.3.2 3 4 5 6 7 Multiport Mini-SAS/SATA Connectors The server board includes two 40-pin high density multiport mini-SAS/SATA connectors. On the server board, these connectors are labeled as “SCU_0” supporting the chipset embedded SCU 0 controller, and “SCU_1”, supporting the embedded SCU 1 controller. Both connectors can support up to four SATA or SAS ports each.
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Intel®Server Board S2400EP TPS On-board Connector/Header Overview Signal Description GROUND SAS6_RX_C_DP SAS6_RX_C_DN GROUND SAS7_RX_C_DP SAS7_RX_C_DN GROUND GROUND GROUND GROUND GROUND 8.3.
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On-board Connector/Header Overview 1 2 3 4 Ground 12V Fan Tach Fan PWM GND Power In Out Intel®Server Board S2400EP TPS Ground is the power supply ground Power supply 12 V FAN_TACH signal is connected to the BMC to monitor the fan speed FAN_PWM signal to control fan speed Table 37.
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Intel®Server Board S2400EP TPS On-board Connector/Header Overview Table 38. Serial A Connector Pin-out Signal Description RTS DTR SOUT GROUND RI SIN DSR CTS 8.6 Pin # 1 2 3 4 5 6 7 8 System Management Headers 8.6.1 Intel®Remote Management Module 4 Connector ® ® A 40-pin Intel RMM4 connector and a 7-pin Intel RMM4 Lite connector are included on the ® ® server board to support the optional Intel Remote Management Module 4 or Intel Remote Management Module 4 Lite.
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On-board Connector/Header Overview Pin 7 8.6.2 Intel®Server Board S2400EP TPS Signal Name Pin 8 SPI_RMM4_LITE_CS_N Signal Name GND TPM connector Table 41. TPM connector Pin-out Pin 1 3 5 7 9 11 13 8.6.3 Signal Name No pin LPC_LAD<0> IRQ_SERIAL P3V3 RST_IBMC_NIC_N LPC_LAD<3> GND Pin 2 4 6 8 10 12 14 Signal Name LPC_LAD<1> GND LPC_FRAME_N GND CLK_33M_TPM_CONN GND LPC_LAD<2> HSBP Header Table 42. HSBP_I2C Header Pin-out Pin 1 2 3 8.6.
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Intel®Server Board S2400EP TPS Pin 7 8 9 10 11 12 13 14 15 8.7.2 On-board Connector/Header Overview Signal Name GND GND P5V GND TP_VID_CONN_B11 V_IO_DDCDAT V_IO_HSYNC_CONN V_IO_VSYNC_CONN V_IO_DDCCLK Description Ground Ground +5V DC Ground No connection DDCDAT HSYNC (horizontal sync) VSYNC (vertical sync) DDCCLK NIC Connectors The server board provides two stacked RJ-45/2xUSB connectors side-by-side on the back edge of the board.
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On-board Connector/Header Overview Pin 1 2 3 4 5 6 7 8 9 10 Intel®Server Board S2400EP TPS Signal Name USB_PWR_5V USB_PWR_5V USB _PN_CONN USB _PN_CONN USB _PP_CONN USB _PP_CONN Ground Ground Key TP_USB _NC Description USB power USB power USB port negative signal USB port negative signal USB port positive signal USB port positive signal No pin Test point The server board provides one additional Type A USB port to support the installation of a USB device inside the server chassis. Table 48.
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Intel®Server Board S2400EP TPS 9. Jumper Blocks Jumper Blocks The server boards have several 3-pin jumper blocks that can be used to configure, protect, or recover specific features of the server boards. The following symbol identifies Pin 1 on each jumper block on the silkscreen: ▼ Figure 29. Jumper Blocks Note: 1. For safety purposes, the power cord should be disconnected from a system before removing any system components or moving any of the on-board jumper blocks. 2.
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Jumper Blocks Intel®Server Board S2400EP TPS Table 51. Server Board Jumpers Jumper Name Pin s 1-2 BMC Firmware Force Update Mode – Disabled (Default) 2-3 BMC Firmware Force Update Mode – Enabled J1L6: BIOS Recovery 1-2 Pins 1-2 should be jumpered for normal system operation. (Default) 2-3 The main system BIOS does not boot with pins 2-3 jumpered. The system only boots from EFI-bootable recovery media with a recovery BIOS image present.
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Intel®Server Board S2400EP TPS Jumper Blocks 7. The STARTUP.NSH file automatically executes and initiates the flash update. When complete, the IFlash utility will display a message. 8. Power OFF the system and return the BIOS Recovery jumper to its default position. 9. Power ON the system. 10. Do NOT interrupt the BIOS POST during the first boot. 11. Configure desired BIOS settings. 9.
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Jumper Blocks 9.3 Intel®Server Board S2400EP TPS Password Clear Jumper Block This jumper causes both the User password and the Administrator password to be cleared if they were set. The operator should be aware that this creates a security gap until passwords have been installed again through the BIOS Setup utility. This is the only method by which the Administrator and User passwords can be cleared unconditionally.
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Intel®Server Board S2400EP TPS 9.5 Jumper Blocks BMC Force Update Jumper Block The BMC Force Update jumper is used to put the BMC in Boot Recovery mode for a low-level update. It is used when the BMC has become corrupted and is non-functional, requiring a new BMC image to be loaded on to the server board. 1. Turn off the system and remove power cords 2. Move the BMC FRC UPDT Jumper from the default (pins 1 and 2) operating position to the Force Update position (pins 2 and 3) 3.
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Intel®Light Guided Diagnostics Intel®Server Board S2400EP TPS 10. Intel®Light Guided Diagnostics The server board includes several on-board LED indicators to aid troubleshooting various board level faults. The following diagram shows the location for each. Figure 30. On-Board Diagnostic LED Placement 106 Intel order number G50763-002 Revision 2.
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Intel®Server Board S2400EP TPS Intel®Light Guided Diagnostics Figure 31. Memory Slot Fault LED Locations 10.1 System ID LED The server board includes a blue system ID LED which is used to visually identify a specific server installed among many other similar servers. There are two options available for illuminating the System ID LED. 1. The front panel ID LED Button is pushed, which causes the LED to illuminate to a solid on state until the button is pushed again. 2.
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Intel®Light Guided Diagnostics Intel®Server Board S2400EP TPS 10.2 System Status LED The server board includes a bi-color System Status LED. The System Status LED on the server board is tied directly to the System Status LED on the front panel (if present). This LED indicates the current health of the server. Possible LED states include solid green, blinking green, blinking amber, and solid amber.
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Intel®Server Board S2400EP TPS Color State Intel®Light Guided Diagnostics Criticality Description  BMC booting Linux*. (Indicated by Chassis ID solid ON). System in degraded state (no manageability). Control has been passed from BMC uBoot to BMC Linux* itself. It will be in this state for ~10-~20 seconds.  BMC Watchdog has reset the BMC.  Power Unit sensor offset for configuration error is asserted.  HDD HSC is off-line or degraded.
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Intel®Light Guided Diagnostics Intel®Server Board S2400EP TPS  A BMC FW update, upon receiving a BMC cold reset command  Upon a BMC watchdog initiated reset. The following table defines the LED states during the BMC Boot/Reset process: Table 53.
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Intel®Server Board S2400EP TPS Intel®Light Guided Diagnostics 10.6 Fan Fault LEDs The server board includes a Fan Fault LED next to each of the six system fans and both CPU fans. The LED has two states: On and Off. The BMC lights a fan fault LED if the associated fan-tach sensor has a lower critical threshold event status asserted. Fan-tach sensors are manual re-arm sensors. Once the lower critical threshold is crossed, the LED remains lit until the sensor is rearmed.
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Environmental Limits Specification Intel®Server Board S2400EP TPS 11. Environmental Limits Specification Operation of the server board at conditions beyond those shown in the following table may cause permanent damage to the system. Exposure to absolute maximum rating conditions for extended periods may affect long term system reliability. Table 54.
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Intel®Server Board S2400EP TPS Power Supply Specification Guidelines 12. Power Supply Specification Guidelines This section provides power supply design guidelines for a system using the Intel® Server Boards S2400EP including voltage and current specifications, and power supply on/off sequencing characteristics. The following diagram shows the power distribution implemented on these server boards. Figure 32. Power Distribution Block Diagram 12.
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Power Supply Specification Guidelines Intel®Server Board S2400EP TPS ® ® Table 55. Intel Xeon Processor Dual Processor TDP Guidelines TDP Power Max Tcase Icc Max 95 W 78 °C 130 A 80W 75 °C 85A 80W 1 socket 71 °C 80A 70W 70 °C 110A 60W 67 °C 90A 50W 65 °C 65A 12.2 Power Supply Output Requirements This section is for reference purposes only. The intent is to provide guidance to system designers to determine a power supply to use with these server boards.
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Intel®Server Board S2400EP TPS Power Supply Specification Guidelines The +12 V1, +12 V2, +12 V3, +12 V4, –12 V, and 5V SB outputs only use remote sense referenced to the ReturnS signal. The remote sense input impedance to the power supply must be greater than 200  on 3.3 VS and 5 VS. This is the value of the resistor connecting the remote sense to the output voltage internal to the power supply. Remote sense must be able to regulate out a minimum of 200 mV drop.
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Power Supply Specification Guidelines 12.2.6 Intel®Server Board S2400EP TPS Capacitive Loading The power supply should be stable and meet all requirements within the following capacitive loading range. Table 59. Capacitive Loading Conditions Output 12.2.7 +3.3V 250 Min Max 5000 Units F +5V 400 5000 F +12V 500 8000 F -12V 1 350 F +5VSB 20 350 F Ripple/Noise The maximum allowed ripple/noise output of the power supply is defined in below table.
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Intel®Server Board S2400EP TPS Power Supply Specification Guidelines Vout 10% Vout V1 V2 V3 V4 Tvout_rise Tvout_off Tvout_on Figure 33. Output Voltage Timing Table 62. Turn On/Off Timing Item Tsb_on_delay Description Delay from AC being applied to 5VSB being within regulation. Tac_on_delay Delay from AC being applied to all output voltages being within regulation. Tvout_holdup Time all output voltages stay within regulation after loss of AC. Tested at 75% of maximum load.
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Power Supply Specification Guidelines Intel®Server Board S2400EP TPS AC Input Tvout_holdup Vout Tpwok_low TAC_on_delay Tsb_on_delay PWOK 5VSB Tpwok_off Tpwok_on Tsb_on_delay Tpwok_on Tpwok_holdup Tsb_vout Tpwok_off Tpson_pwok T5VSB_holdup Tpson_on_delay PSON AC turn on/off cycle PSON turn on/off cycle Figure 34. Turn On/Off Timing (Power Supply Signals) 12.
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Intel®Server Board S2400EP TPS Appendix A: Integration and Usage Tips Appendix A: Integration and Usage Tips  When adding or removing components or peripherals from the server board, you must remove AC power cord. With AC power plugged into the server board, 5-V standby is still present even though the server board is powered off.
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Appendix B: BMC Sensor Tables Intel®Server Board S2400EP TPS Appendix B: BMC Sensor Tables This appendix lists the sensor identification numbers and information about the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 2.0 for sensor and event/reading-type table information.
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Intel®Server Board S2400EP TPS  Appendix B: BMC Sensor Tables Rearm Sensors The rearm is a request for the event status of a sensor to be rechecked and updated upon a transition between good and bad states. You can rearm the sensors manually or automatically. This column indicates the type supported by the sensor.
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Appendix B: BMC Sensor Tables Intel®Server Board S2400EP TPS Note: All sensors listed below may not be present on all platforms. Please check platform EPS section for platform applicability and platform chassis section for chassis specific sensors. Redundancy sensors will be only present on systems with appropriate hardware to support redundancy (for instance, fan or power supply) Table 63.
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Intel®Server Board S2400EP TPS Full Sensor Name (Sensor name in SDR) Sensor # Appendix B: BMC Sensor Tables Platform Applicability Sensor Type Event/Reading Type Event Offset Triggers (IPMI Watchdog) 03h All Watchdog 2 23h Sensor Specific 6Fh Readable Value/Offs ets OK As – OK As and De – 04 – Nonredundant: sufficient resources. Transition from insufficient state. Degraded 05 - Nonredundant: insufficient resources Fatal 06 – Redundant: degraded from fully redundant state.
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Appendix B: BMC Sensor Tables Full Sensor Name (Sensor name in SDR) FP Interrupt (FP NMI Diag Int) SMI Timeout (SMI Timeout) System Event Log (System Event Log) Sensor # 05h 06h 07h Intel®Server Board S2400EP TPS Platform Applicability Chassis specific All All Sensor Type Critical Interrupt Sensor Specific 13h 6Fh SMI Timeout Digital Discrete F3h Event Logging Disabled 10h System Event (System Event) Button Sensor (Button) BMC Watchdog 08h All (Fan Redundancy) Sensor Specific 6Fh Sen
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Intel®Server Board S2400EP TPS Full Sensor Name (Sensor name in SDR) SSB Thermal Trip (SSB Therm Trip) IO Module Presence (IO Mod Presence) SAS Module Presence (SAS Mod Presence) BMC Firmware Health (BMC FW Health) Revision 2.
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Appendix B: BMC Sensor Tables Full Sensor Name (Sensor name in SDR) System Airflow (System Airflow) Baseboard Temperature 1 Sensor # Platform Applicability Threshold 01h Temperature Threshold 01h 01h Temperature Threshold 01h 01h Temperature Threshold 01h 01h Platformspecific Temperature Threshold 01h 01h Platformspecific Temperature Threshold 01h 01h Platformspecific Temperature Threshold 01h 01h Platformspecific Temperature Threshold 01h 01h Platformspecific Temperatur
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Intel®Server Board S2400EP TPS Full Sensor Name (Sensor name in SDR) Sensor # Appendix B: BMC Sensor Tables Platform Applicability Hot-swap Backplane 2 Temperature Network Interface Controller Temperature (Chassis specific sensor names) Fan Present Sensors (Fan x Present) Power Supply 1 Status (PS1 Status) Revision 2.
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Appendix B: BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Power Supply 2 Status (PS2 Status) Power Supply 1 AC Power Input Sensor # 51h 54h (PS1 Power In) Power Supply 2 AC Power Input 55h (PS2 Power In) Power Supply 1 +12V % of Maximum Current Output 58h Intel®Server Board S2400EP TPS Platform Applicability Chassisspecific Sensor Type Event/Reading Type Power Supply Sensor Specific 08h 6Fh Chassisspecific Other Units Threshold 0Bh 01h Chassisspecific Other Units Threshol
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Intel®Server Board S2400EP TPS Full Sensor Name (Sensor name in SDR) Hard Disk Drive 16 - 24 Status (HDD 16 - 24 Status) Processor 1 Status (P1 Status) Processor 2 Status (P2 Status) Processor 1 Thermal Margin Sensor # Appendix B: BMC Sensor Tables Platform Applicability 60h – Chassisspecific 68h 70h 71h All All 74h All 75h All 78h All (P1 Therm Margin) Processor 2 Thermal Margin (P2 Therm Margin) Processor 1 Thermal Control % (P1 Therm Ctrl %) Processor 2 Thermal Control % 79h All (P
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Appendix B: BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Processor 2 ERR2 Timeout Sensor # 7Dh Intel®Server Board S2400EP TPS Platform Applicability All (P2 ERR2) Catastrophic Error (CATERR) Processor0 MSID Mismatch 80h 81h All All (P0 MSID Mismatch) Processor Population Fault 82h All (CPU Missing) Processor1 MSID Mismatch 87h All (P1 MSID Mismatch) Processor 1 VRD Temperature 90h All (P1 VRD Hot) Processor 2 VRD Temperature 91h All (P2 VRD Hot) Processor 1 Memory VRD Hot 0-
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Intel®Server Board S2400EP TPS Full Sensor Name (Sensor name in SDR) Processor 2 Memory VRD Hot 2-3 Sensor # 97h Appendix B: BMC Sensor Tables Platform Applicability All (P2 Mem23 VRD Hot) Contrib.
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Appendix B: BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Global Aggregate Temperature Margin 2 Sensor # (BB +12.0V) Baseboard +5V (BB +5.0V) Baseboard +3.3V (BB +3.
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Intel®Server Board S2400EP TPS Full Sensor Name (Sensor name in SDR) Baseboard +5V Standby Sensor # D3h Appendix B: BMC Sensor Tables Platform Applicability All (BB +5.0V STBY) Baseboard +3.3V Auxiliary D4h All (BB +3.3V AUX) Baseboard +1.05V Processor 1 Vccp D6h All (BB +1.05Vccp P1) Baseboard +1.05V Processor 1 Vccp D7h All (BB +1.05Vccp P2) Baseboard +1.5V P1 Memory AB VDDQ D8h All (BB +1.5 P1MEM AB) Baseboard +1.5V P1 Memory CD VDDQ D9h All (BB +1.5 P1MEM CD) Baseboard +1.
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Appendix B: BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Baseboard CMOS Battery Sensor # DEh Intel®Server Board S2400EP TPS Platform Applicability E4h Event/Reading Type Event Offset Triggers Voltage 02h Threshold 01h [u,l] [c,nc] Voltage 02h Threshold 01h [u,l] [c,nc] Voltage 02h Threshold 01h [u,l] [c,nc] Voltage 02h Threshold 01h [u,l] [c,nc] Voltage 02h Threshold 01h [u,l] [c,nc] Platform Specific Voltage 02h Threshold 01h [u,l] [c,nc] Platform Specific Voltage 02h
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Intel®Server Board S2400EP TPS Appendix C: Management Engine Generated SEL Event Messages Appendix C: Management Engine Generated SEL Event Messages This appendix lists the OEM System Event Log message format of events generated by the Management Engine (ME). This includes the definition of event data bytes 10-16 of the Management Engine generated SEL records. For System Event Log format information, see the Intelligent Platform Management Interface Specification, Version 2.0. Revision 2.
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Appendix C: Management Engine Generated SEL Event Messages Intel®Server Board S2400EP TPS Table 64. Server Platform Services Firmware Health Event Server Platform Services Firmware Health Event Request Byte 1 - EvMRev =04h (IPMI2.
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Intel®Server Board S2400EP TPS Appendix C: Management Engine Generated SEL Event Messages Table 65. Node Manager Health Event Node Manager Health Event Request Byte 1 - EvMRev =04h (IPMI2.
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Appendix D: POST Code Diagnostic LED Decoder Intel®Server Board S2400EP TPS Appendix D: POST Code Diagnostic LED Decoder As an aid to assist in trouble shooting a system hang that occurs during a system’s Power-On Self Test (POST) process, the server board includes a bank of eight POST Code Diagnostic LEDs on the back edge of the server board.
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Intel®Server Board S2400EP TPS Appendix D: POST Code Diagnostic LED Decoder Table 66. POST Progress Code LED Example Upper Nibble AMBER LEDs LEDs Status Results MSB LED #7 8h ON 1 LED #6 4h OFF 0 LED #5 2h ON 1 Lower Nibble GREEN LEDs LED #4 1h OFF 0 LED #3 8h ON 1 LED #2 4h ON 1 Ah LED #1 2h OFF 0 LSB LED #0 1h OFF 0 Ch Upper nibble bits = 1010b = Ah; Lower nibble bits = 1100b = Ch; the two are concatenated as ACh The following table provides a list of all POST progress codes. Table 67.
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Appendix D: POST Code Diagnostic LED Decoder Checkpoint Diagnostic LED Decoder 1 = LED On, 0 = LED Off Upper Nibble Lower Nibble MSB LSB 8h 4h 2h 1h 8h 4h 2h 1h #7 #6 #5 #4 #3 #2 #1 #0 0 1 1 1 1 0 0 1 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 1 0 1 0 0 1 0 0 1 0 1 0 1 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 1 1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 0 0 1 0 0 1 1 1 0 1 1 0 1 0 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 0 0 0 1 1 1 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 1 0 1
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Intel®Server Board S2400EP TPS Appendix D: POST Code Diagnostic LED Decoder POST Memory Initialization MRC Diagnostic Codes There are two types of POST Diagnostic Codes displayed by the MRC during memory initialization; Progress Codes and Fatal Error Codes. The MRC Progress Codes are displays to the Diagnostic LEDs that show the execution point in the MRC operational path at each step. Table 68.
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Appendix D: POST Code Diagnostic LED Decoder Intel®Server Board S2400EP TPS Table 69.
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Intel®Server Board S2400EP TPS Appendix E: POST Code Errors Appendix E: POST Code Errors Error Code 0012 0048 0140 0141 0146 0191 0192 0194 0195 0196 0197 5220 5221 5224 8130 8131 8132 8133 8160 8161 8162 8163 8170 8171 8172 8173 8180 8181 8182 8183 8190 8198 8300 8305 83A0 83A1 84F2 84F3 84F4 84FF 8500 8501 8520 8521 8522 8523 8524 8525 8526 8527 8528 8529 852A 852B 852C 852D 852E 852F 8530 Revision 2.
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Appendix E: POST Code Errors Error Code 8531 8532 8533 8534 8535 8536 8537 8538 8539 853A 853B 853C 853D 853E 853F (Go to 85C0) 8540 8541 8542 8543 8544 8545 8546 8547 8548 8549 854A 854B 854C 854D 854E 854F 8550 8551 8552 8553 8554 8555 8556 8557 8558 8559 855A 855B 855C 855D 855E 855F (Go to 85D0) 8560 8561 8562 8563 8564 8565 8566 8567 8568 8569 856A 144 Intel®Server Board S2400EP TPS DIMM_F3 failed test/initialization DIMM_G1 failed test/initialization DIMM_G2 failed test/initialization DIMM_G3 faile
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Intel®Server Board S2400EP TPS Error Code 856B 856C 856D 856E 856F 8570 8571 8572 8573 8574 8575 8576 8577 8578 8579 857A 857B 857C 857D 857E 857F (Go to 85E0) 85C0 85C1 85C2 85C3 85C4 85C5 85C6 85C7 85C8 85C9 85CA 85CB 85CC 85CD 85CE 85CF 85D0 85D1 85D2 85D3 85D4 85D5 85D6 85D7 85D8 85D9 85DA 85DB 85DC 85DD 85DE 85DF 85E0 85E1 85E2 85E3 85E4 85E5 85E6 Revision 2.
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Appendix E: POST Code Errors Error Code 85E7 85E8 85E9 85EA 85EB 85EC 85ED 85EE 85EF 8604 8605 8606 92A3 92A9 A000 A001 A002 A003 A100 A421 A5A0 A5A1 A6A0 Intel®Server Board S2400EP TPS Error Message DIMM_N1 encountered a Serial Presence Detection (SPD) failure DIMM_N2 encountered a Serial Presence Detection (SPD) failure DIMM_N3 encountered a Serial Presence Detection (SPD) failure DIMM_O1 encountered a Serial Presence Detection (SPD) failure DIMM_O2 encountered a Serial Presence Detection (SPD) failure
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Intel®Server Board S2400EP TPS Appendix E: POST Code Errors Table 71. Integrated BMC Beep Codes Code 1-5-2-1 Reason for Beep No CPUs installed or first CPU socket is empty. Associated Sensors CPU1 socket is empty, or sockets are populated incorrectly CPU1 must be populated before CPU2. 1-5-2-4 MSID Mismatch 1-5-4-2 Power fault 1-5-4-4 1-5-1-2 Power control fault (power good assertion timeout).
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Appendix F: Supported Intel®Server System Intel®Server Board S2400EP TPS Appendix F: Supported Intel®Server System Intel® Server System product integrates the Intel® Server board S2400EP is the 1U rack mount ® Intel Server System R1000EP product family. ® Figure 36. Intel Server System R1000EP ® Table 72.
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Intel®Server Board S2400EP TPS Feature Appendix F: Supported Intel®Server System Server System – Intel®Server System R1000EP product family Integrated Server Board – Intel®Server Board S2400EP Description Internal I/O connectors / headers  One Type-A USB 2.0 connector  One DH-10 Serial-B port connector  One SAS ROC module connector I/O Module Accessory Options The following I/O modules utilize a single proprietary on-board connector.
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Glossary Intel®Server Board S2400EP TPS Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (for example, “82460GX”) with alpha entries following (for example, “AGP 4x”). Acronyms are then entered in their respective place, with non-acronyms following.
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Intel®Server Board S2400EP TPS Glossary Term GPIO General Purpose I/O GTL Gunning Transceiver Logic GPA Guest Physical Address HSC Hot-Swap Controller HPA Host Physical Address Hz Hertz (1 cycle/second) I2C Inter-Integrated Circuit Bus IA Intel Architecture IBF Input Buffer ICH I/O Controller Hub IC MB Intelligent Chassis Management Bus IERR Internal Error IFB I/O and Firmware Bridge ILM Independent Loading Mechanism IMC Integrated Memory Controller INTR Interrupt IOAT I/O
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Glossary Intel®Server Board S2400EP TPS Term Definition NIC Network Interface Controller Nm Nanometer NMI Non-maskable Interrupt NUMA Non-Uniform Memory Architecture NVSRAM Non-volatile Static Random Access Memory OBF Output Buffer OEM Original Equipment Manufacturer Ohm Unit of electrical resistance PAE Physical Address Extension PECI Platform Environment Control Interface PEF Platform Event Filtering PEP Platform Event Paging PIA Platform Information Area (This feature configu
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Intel®Server Board S2400EP TPS Glossary Term TDP Thermal Design Power TIM Thermal Interface Material UART Universal Asynchronous Receiver/Transmitter UDIMM Unbuffered Dual In-Line Memory Module UDP User Datagram Protocol UHCI Universal Host Controller Interface URS Unified Retention System UTC Universal time coordinate VID Voltage Identification VLSI Very-large-scale integration VRD Voltage Regulator Down VT Virtualization Technology Word 16-bit quantity ZIF Zero Insertion Force
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Reference Documents Intel®Server Board S2400EP TPS Reference Documents  Advanced Configuration and Power Interface Specification, Revision 3.0, http://www.acpi.info/.  Intelligent Platform Management Bus Communications Protocol Specification, Version 1.0. 1998. Intel Corporation, Hewlett-Packard* Company, NEC* Corporation, Dell* Computer Corporation.  Intelligent Platform Management Interface Specification, Version 2.0. 2004.