Technical Product Specification

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Intel

Server Boards S5000PSL and

S5000XSL

Intel order number: D41763-008

Revision 1.7

August, 2010

Enterprise Platforms and Services Division – Marketing

Summary of content (112 pages)

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Intel® Server Boards S5000PSL and S5000XSL Technical Product Specification Intel order number: D41763-008 Revision 1.
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Revision History Intel® Server Boards S5000PSL and S5000XSL TPS Revision History Date May 2006 Revision Number 1.0 September 2006 1.1 September 2006 1.2 Updated Reference Documents section. August 2007 1.3 Updated to reflect new processor support and new product codes where applicable. Updated sections 3.1, 3.1.3.4.2.3, 3.2.1.4, 3.2.1.5, 3.2.2.1, 3.5.2, and 6.1. Added 3.1.3.4.2.3. Updated Tables 1, 2, and 46. Updated Figure 2. Updated Appendix A and Appendix E.
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Intel® Server Boards S5000PSL and S5000XSL Disclaimers Disclaimers Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
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Table of Contents Intel® Server Boards S5000PSL and S5000XSL TPS Table of Contents 1. 2. 3. Introduction .......................................................................................................................... 1 1.1 Chapter Outline........................................................................................................ 1 1.2 Server Board Use Disclaimer .................................................................................. 1 Server Board Overview ........
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Intel® Server Boards S5000PSL and S5000XSL TPS Table of Contents 3.6.2 Floppy Disk Controller ........................................................................................... 32 3.6.3 Keyboard and Mouse Support ............................................................................... 32 3.6.4 Wake-up Control.................................................................................................... 32 3.6.5 System Health Support..............................................
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Table of Contents 7.2 Fan Fault LEDs...................................................................................................... 53 7.3 System ID LED and System Status LED ............................................................... 54 7.3.1 8. DIMM Fault LEDs .................................................................................................. 56 7.5 Processor Fault LEDs............................................................................................ 57 7.
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Intel® Server Boards S5000PSL and S5000XSL TPS Table of Contents Appendix A: Integration and Usage Tips................................................................................ 72 Appendix B: BMC Sensor Tables ............................................................................................ 73 Appendix C: POST Code Diagnostic LED Decoder ............................................................... 89 Appendix D: POST Code Errors ........................................................
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List of Figures Intel® Server Boards S5000PSL and S5000XSL TPS List of Figures Figure 1. Server Board Photograph .............................................................................................. 4 Figure 2. Board Layout ................................................................................................................. 5 Figure 3. Mounting Hole Positions ................................................................................................ 7 Figure 4.
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Intel® Server Boards S5000PSL and S5000XSL TPS List of Tables List of Tables Table 1. Server Board Features.................................................................................................... 2 Table 2. Major Board Components ............................................................................................... 6 Table 3. I2C Addresses for Memory Module SMB ...................................................................... 18 Table 4.
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List of Tables Intel® Server Boards S5000PSL and S5000XSL TPS Table 33. Internal 9-pin Serial B Header Pin-out (J1B1)............................................................. 45 Table 34. Stacked PS/2 Keyboard and Mouse Port Pin-out (J9A1) ........................................... 45 Table 35. External USB Connector Pin-out (JA6A1, JA6A2) ...................................................... 46 Table 36. Internal USB Connector Pin-out (J3J1)..........................................................
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Intel® Server Boards S5000PSL and S5000XSL TPS List of Tables Revision 1.
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Intel® Server Boards S5000PSL and S5000XSL TPS 1. Introduction Introduction This Technical Product Specification (TPS) provides board-specific information about the features, functionality, and high-level architecture of the Intel® Server Boards S5000PSL and S5000XSL. For details about board subsystems, including the chipset, BIOS, and server management, see the Intel® S5000 Server Board Family Datasheet.
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Server Board Overview 2. Intel® Server Boards S5000PSL and S5000XSL TPS Server Board Overview The Intel® Server Boards S5000PSL and S5000XSL are monolithic printed circuit boards with features that support the pedestal server markets. 2.1 Server Board Feature Set Table 1. Server Board Features Feature Description Server Board Dimension 13.0 inches x 12.0 inches (330.2 mm x 304.8 mm).
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Intel® Server Boards S5000PSL and S5000XSL TPS Feature Server Board Overview Description Server Board Dimension 13.0 inches x 12.0 inches (330.2 mm x 304.8 mm). Hard Drive Support for six SATA-2 hard drives. [4] Support for four SAS/SATA-2 hard drives with non-expanded backplane . LAN Two 10/100/1000 Intel 82563EB PHYs supporting Intel I/O Acceleration Technology. Fans Support for Two processor fans. Four front hot-swap fans. Two rear system fans.
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Server Board Overview 2.2 Intel® Server Boards S5000PSL and S5000XSL TPS Server Board Layout Figure 1. Server Board Photograph 2.2.1 Server Board Connector and Component Layout The following figure shows the board layout of the server board. Each connector and major component is identified by a letter. A table of component descriptions follows the figure. 4 Revision 1.
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Intel® Server Boards S5000PSL and S5000XSL TPS Server Board Overview Figure 2. Board Layout Revision 1.
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Server Board Overview Intel® Server Boards S5000PSL and S5000XSL TPS Table 2.
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Intel® Server Boards S5000PSL and S5000XSL TPS 2.2.2 Server Board Overview Server Board Mechanical Drawings Figure 3. Mounting Hole Positions Revision 1.
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Server Board Overview Intel® Server Boards S5000PSL and S5000XSL TPS Figure 4. Component Positions 8 Revision 1.
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Intel® Server Boards S5000PSL and S5000XSL TPS 11.20 [ 0.441 304.80 [ 12.000 ] ] 116.000 [ 4.5669 18.72 [ 0.737 ] TYP Server Board Overview 60.100 [ 2.3661 ] 20.32 [ 0.800 TYP HEATSINK DISSASEMBLY AREA, .275" [8.26mm] MAX COMPONENT HEIGHT RESTRICTION, 4 PLACES ] ] IMM3 COMPONENT HEIGHT 3.6 MM Ø 10.160 [ 0.4000 ] GROUND PAD BOTH SIDES NO COMPONENT 8 PLCS 72.800 [ 2.8661 ] .433" [14mm] MAX COMPONENT HEIGHT RESTRICTION 301.50 [ 11.870 TYP 311.66 [ 12.270 TYP 322.40 [ 12.693 TYP 326.57 [ 12.
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Server Board Overview Intel® Server Boards S5000PSL and S5000XSL TPS LIMITED COMPONENT HEIGHT .058" MAXIMUM 13 PLACES 2X 3.120 [ 0.1228 78.74 [ 3.100 7.620 [ 0.3000 TYP 20.320 [ 0.8000 ] ] ] ] SEE DETAIL B 20.320 [ 0.8000 ] 11 PLCS 3 R 25.40 [ 1.000 TYP ] 2X 8.000 [ 0.3150 2X 0.350 [ 0.0138 ] ] NO COMPONENTS ALLOWED TRACES OKAY IN THIS REGION 5.08 [ 0.200 ] TYP R 14.730 [ 0.5799 66.554 [ 2.6202 ] TYP ] 177.80 [ 7.000 ] Ø 10.160 GROUND PAD [ 0.4000 ] NO COMPONENT 1 PLACE .100 [2.
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Intel® Server Boards S5000PSL and S5000XSL TPS 5.00 [ 0.197 3X 4.00 [ 0.157 ] Server Board Overview 5.00 [ 0.197 ] ] 3X 3.00 [ 0.118 3X 10.13 [ 0.399 ] ] CHASSIS ID PADS Figure 7. Restricted Areas on Side 2, “Detail B” Revision 1.
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288.290 [11.3500] 273.091 [10.7516] 188.152 [7.4076] 193.152 [7.6044] Intel® Server Boards S5000PSL and S5000XSL TPS 0.000 [0.0000] 16.510 [0.6500] Server Board Overview 10.160 [0.4000] 0.000 [0.0000] 14.0mm COMPONENT HEIGHT LIMIT DEFINED BY DUCT DETAIL 26.635 [1.0486] 26.578 [1.0464] SUPPORT AREA, NO COMPONENT ALLOWED 111.351 [4.3839] 118.351 [4.6595] 14.0mm COMPONENT HEIGHT LIMIT DEFINED BY DUCT DETAIL SUPPORT AREA, NO COMPONENT ALLOWED 145.600 [5.7323] 43.302 [1.7048] 16.
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Intel® Server Boards S5000PSL and S5000XSL TPS 2.2.3 Server Board Overview Server Board ATX I/O Layout The following figure shows the layout of the rear I/O components for the server board. A C B D E G F H AF000222 A. PS/2 mouse E. NIC port 1 (1 Gb) B. PS/2 keyboard F. USB port 2 (top), 3 (bottom) C. Serial port G. NIC port 2 (1 Gb) D. Video H. USB port 0 (top), 1 (bottom) Figure 9. ATX I/O Layout Revision 1.
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Functional Architecture 3. Intel® Server Boards S5000PSL and S5000XSL TPS Functional Architecture The architecture and design of the Intel® Server Boards S5000PSL and S5000XSL are based on the Intel® S5000P and S5000X chipsets respectively. These chipsets are designed for systems that use the Intel® Xeon® processor with system bus speeds of 667 MHz, 1066 MHz, and 1333 MHz.
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Intel® Server Boards S5000PSL and S5000XSL TPS Functional Architecture Figure 10. Functional Block Diagram Revision 1.
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Functional Architecture 3.
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Intel® Server Boards S5000PSL and S5000XSL TPS 3.1.2.1 Functional Architecture Processor Population Rules When two processors are installed, both must be of identical revision, core voltage, and bus/core speed. When only one processor is installed, it must be in the socket labeled CPU1. The other socket must be empty. The board is designed to provide up to 130A of current per processor. Processors with higher current requirements are not supported.
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Functional Architecture 3.1.3 Intel® Server Boards S5000PSL and S5000XSL TPS Memory Subsystem The MCH masters four fully buffered DIMM (FBD) memory channels. FBD memory utilizes a narrow high-speed frame-oriented interface referred to as a channel. The four FBD channels are organized into two branches of two channels per branch. Each branch is supported by a separate memory controller. The two channels on each branch operate in lock-step to increase FBD bandwidth.
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Intel® Server Boards S5000PSL and S5000XSL TPS Device 3.1.3.1 Functional Architecture Address DIMM C2 0xA2 DIMM D1 0xA0 DIMM D2 0xA2 Memory RASUM Features The MCH supports several memory RASUM (Reliability, Availability, Serviceability, Usability, and Manageability) features.
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Functional Architecture Intel® Server Boards S5000PSL and S5000XSL TPS Table 6. Maximum Eight-DIMM System Memory Configuration – x2 Quad Rank DRAM Technology x2 Quad Rank Maximum Capacity Mirrored Mode Maximum Capacity Non-mirrored Mode 1024 Mb 16 GB 32 GB 2048 Mb 16 GB 32 GB Note: Only fully buffered DDR2 DIMMs (FBDIMMs) are supported on this server board. For a list of supported memory for this server board, see http://www.intel.com/support/motherboards/server/s5000psl/sb/CS-022924.htm. 3.1.3.
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Intel® Server Boards S5000PSL and S5000XSL TPS Functional Architecture Table 7. Supported DIMM Configurations Branch 0 Branch 1 Channel A DIMM_A 1 Channel B DIMM_A 2 DIMM_B 1 DIMM B2 Channel C DIMM C1 DIMM C2 Channel D DIMM D1 Mirroring Possible Sparing Possible DIMM D2 Y (0) Y Y (0) Y Notes: Y (0, 1) Single channel mode is only tested and supported with a 512MB x8 FBDIMM installed in DIMM Slot A1. The supported memory configurations must meet population rules defined above.
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Functional Architecture Intel® Server Boards S5000PSL and S5000XSL TPS Note: The server board supports single DIMM mode operation. Intel will only validate and support this configuration with a single 512 MB x8 FBDIMM installed in DIMM socket A1. 3.1.3.4 Non-mirrored Mode Memory Upgrades The minimum memory upgrade increment is two DIMMs per branch. The DIMMs must cover the same slot position on both channels. DIMMs pairs must be identical with respect to size, speed, and organization.
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Intel® Server Boards S5000PSL and S5000XSL TPS 3.1.3.4.2 Functional Architecture Sparing Mode Memory Configuration The MCH provides memory sparing capabilities. Sparing is a RAS feature that involves configuring a DIMM to be placed in reserve so it can be used to replace a DIMM that fails. DIMM sparing occurs within a given bank of memory and is not supported across branches.
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Functional Architecture Intel® Server Boards S5000PSL and S5000XSL TPS DIMM_C1 and DIMM_C2 need not be identical in organization, size, and speed. DIMM_D1 and DIMM_D2 need not be identical in organization, size, and speed. Sparing should be enabled in the BIOS setup. The BIOS will configure Rank Sparing Mode. The larger of the pairs {DIMM_A1, DIMM_B1}, {DIMM_A2, DIMM_B2}, {DIMM_C1, DIMM_D1}, and {DIMM_C2, DIMM_D2} are selected as the spare pair units. 3.1.3.4.2.
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Intel® Server Boards S5000PSL and S5000XSL TPS 3.2.1 Functional Architecture PCI Subsystem The primary I/O buses for the server board are PCI, PCI Express*, and PCI-X, with six independent PCI bus segments. The PCI buses comply with the PCI Local Bus Specification, Revision 2.3. The following table lists the characteristics of the PCI bus segments. Details about each bus segment follow the table. Table 8.
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Functional Architecture 3.2.1.3 Intel® Server Boards S5000PSL and S5000XSL TPS PE0: One x4 PCI Express* Bus Segment One x4 PCI Express* bus segment is directed through the ESB2-E. This PCI Express* segment, PE0, is routed to PCI Express* Slot 4 that is special keyed to support ROMB card. 3.2.1.4 PE1: One x4 PCI Express* Bus Segment One x4 PCI Express* bus segment is directed through the ESB2-E. This PCI Express* segment, PE1, is routed to PCI Express* Slot 3.
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Intel® Server Boards S5000PSL and S5000XSL TPS Functional Architecture Table 9. PCI Express* Slot 6 Riser Setup Slot 6 Setup 1 LP Riser Type 1 GPI: ESB2 GPI 28 PCI-E Pin: B48 [RSVD] 0 1 2 2U Riser, 2 x4 PCI Express* Slots 1U Riser, 1 x8 PCI Express* Slot3 LP Riser Type 0 GPI: ESB2 GPI 27 PCI-E Pin: B49 [GND] 1 0 Notes: 1. The server board contains a weak pull-up resistor on the two Riser Type nets. 2.
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Functional Architecture Intel® Server Boards S5000PSL and S5000XSL TPS Intel® Embedded Server RAID Technology Option ROM Intel® Embedded Server RAID Technology II drivers, most recent revision At least two SATA hard disk drives Intel® Embedded Server RAID Technology is not available in the following configurations: 3.2.2.
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Intel® Server Boards S5000PSL and S5000XSL TPS 3.3.1 Functional Architecture Video Modes The ATI* ES1000 chip supports all standard IBM* VGA modes. The following table shows the 2D modes supported for both CRT and LCD: Table 11.
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Functional Architecture Intel® Server Boards S5000PSL and S5000XSL TPS The LSI SAS1064e controller supports a 32-bit external memory bus that provides an interface for Flash ROM and NVSRAM devices. 3.4.1 SAS RAID Support RAID modes 0, 1, and 10 are supported. An optional SAS RAID Key can be used to support Software RAID 5. The server board can support up to four hard drives with a non-expander backplane or support up to eight hard drives with an expander backplane. 3.4.
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Intel® Server Boards S5000PSL and S5000XSL TPS Functional Architecture through more efficient network data movement and reduced system overhead. Intel multi-port network adapters with Intel® I/OAT provide high-performance I/O for server consolidation and virtualization via stateless network acceleration that seamlessly scales across multiple ports and virtual machines.
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Functional Architecture Intel® Server Boards S5000PSL and S5000XSL TPS Table 13. Serial B Header Pin-out Pin 1 3.6.2 Signal Name Serial Port B Header Pin-out DCD 2 DSR 3 RX 4 RTS 5 TX 6 CTS 7 DTR 8 RI 9 GND Floppy Disk Controller The server board does not support a floppy disk controller interface. However, the system BIOS recognizes USB floppy devices. 3.6.
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Intel® Server Boards S5000PSL and S5000XSL TPS 4. Platform Management Platform Management The platform management subsystem is based on the integrated Baseboard Management Controller features of the ESB2-E. The on-board platform management subsystem consists of communication buses, sensors, system BIOS, and server management firmware. The following diagram provides an overview of the Server Management Bus (SMBus) architecture used on this server board. See Appendix B for on-board sensor data.
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Platform Management Intel® Server Boards S5000PSL and S5000XSL TPS Figure 16. SMBus Block Diagram 34 Revision 1.
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Intel® Server Boards S5000PSL and S5000XSL TPS Connector/Header Locations and Pin-outs 5. Connector/Header Locations and Pin-outs 5.1 Board Connector Information The following section provides detailed information regarding all connectors, headers and jumpers on the server board. The following table lists all connector types available on the board and the corresponding reference designators printed on the silkscreen: Table 14.
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Connector/Header Locations and Pin-outs Connector Intel® Server Boards S5000PSL and S5000XSL TPS Quantity Reference Designators Connector Type Pin Count LCP/AUX IPMB 1 J2J1 Header 4 IPMB 1 J4J1 Header 3 HDD Activity 1 J2J3 Header 2 Configuration jumpers 4 J1D2 (Password Clear), J1D1 (CMOS Clear), J1C3 (BIOS Bank Select), J1E3 (BMC Force Update) Jumper 3 5.2 Power Connectors The main power supply connection uses an SSI-compliant 2x12 pin connector (J9B5).
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Intel® Server Boards S5000PSL and S5000XSL TPS Connector/Header Locations and Pin-outs Table 16. 12 V Power Connector Pin-out (J3J2) Pin Signal Color 1 GND Black 2 GND Black 3 GND Black 4 GND Black 5 +12 Vdc Yellow/black 6 +12 Vdc Yellow/black 7 +12 Vdc Yellow/black 8 +12 Vdc Yellow/black Table 17. Power Supply Signal Connector Pin-out (J9D1) Pin 1 Signal SMB_CLK_ESB_FP_PWR_R Color Orange 2 SMB_DAT_ESB_FP_PWR_R Black 3 SMB_ALRT_3_ESB_R Red 4 3.3 V SENSE- Yellow 5 3.
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Connector/Header Locations and Pin-outs Intel® Server Boards S5000PSL and S5000XSL TPS Table 19.
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Intel® Server Boards S5000PSL and S5000XSL TPS Pin 5.3.
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Connector/Header Locations and Pin-outs 5.3.4 Intel® Server Boards S5000PSL and S5000XSL TPS HSBP Header Table 22. HSBP Header Pin-out (J1J7, J1J2) Pin 5.3.5 Signal Name Description 1 SMB_IPMB_5V_DAT BMC IMB 5V Data Line 2 GND Ground 3 SMB_IPMB_5V_CLK BMC IMB 5V Clock Line 4 GND – HSBP_A P5V – HSBP_B Ground for HSBP A +5V for HSBP B SGPIO Header Table 23. SGPIO Header Pin-out (J2H1, J1J5) Pin 5.3.
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Intel® Server Boards S5000PSL and S5000XSL TPS 5.4 Connector/Header Locations and Pin-outs Front Panel Connector The server board provides a 24-pin SSI front panel connector (J1E4) for use with Intel® and third-party chassis. The following table provides the pin-out for this connector. Table 26. Front Panel SSI Standard 24-pin Connector Pin-out (J1E4) Pin 5.
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Connector/Header Locations and Pin-outs Pin 5.5.2 Intel® Server Boards S5000PSL and S5000XSL TPS Signal Name Description 8 GND Ground 9 TP_VID_CONN_B9 No connection 10 GND Ground 11 TP_VID_CONN_B11 No connection 12 V_IO_DDCDAT DDCDAT 13 V_IO_HSYNC_CONN HSYNC (horizontal sync) 14 V_IO_VSYNC_CONN VSYNC (vertical sync) 15 V_IO_DDCCLK DDCCLK NIC Connectors The server board provides two stacked RJ-45/2xUSB connectors side-by-side on the back edge of the board (JA6A1, JA6A2).
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Intel® Server Boards S5000PSL and S5000XSL TPS Pin 5.5.
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Connector/Header Locations and Pin-outs Pin 5.5.
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Intel® Server Boards S5000PSL and S5000XSL TPS Connector/Header Locations and Pin-outs Table 33. Internal 9-pin Serial B Header Pin-out (J1B1) Pin 5.5.
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Connector/Header Locations and Pin-outs Intel® Server Boards S5000PSL and S5000XSL TPS Table 35. External USB Connector Pin-out (JA6A1, JA6A2) Pin Signal Name Description 1 USB_OC USB_PWR 2 USB_PN DATAL0 (Differential data line paired with DATAH0) 3 USB_PP DATAH0 (Differential data line paired with DATAL0) 4 GND Ground One 2x5 connector on the server board (J3J1) provides an option to support additional two USB ports.
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Intel® Server Boards S5000PSL and S5000XSL TPS Connector/Header Locations and Pin-outs Table 37. SSI 4-pin Fan Header Pin-out (J9J1, J5J1, J9B3, J9B4) Pin Signal Name Type Description 1 Ground GND Ground is the power supply ground 2 12V Power Power supply 12 V 3 Fan Tach In FAN_TACH signal is connected to the BMC to monitor the fan speed 4 Fan PWM Out FAN_PWM signal to control fan speed Table 38.
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Jumper Blocks 6. Intel® Server Boards S5000PSL and S5000XSL TPS Jumper Blocks The server board has several 3-pin jumper blocks that can be used to configure, protect, or recover specific features of the server board.
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Intel® Server Boards S5000PSL and S5000XSL TPS 6.1 Jumper Blocks CMOS Clear and Password Reset Usage Procedure The CMOS Clear (J1D1) and Password Reset (J1D2) recovery features are designed such that the desired operation can be achieved with minimal system downtime. The usage procedure for these two features has changed from previous generation Intel server boards. The following procedure outlines the new usage model. 6.1.1 Clearing the CMOS To clear the CMOS, perform the following steps: 1.
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Jumper Blocks 6.2 Intel® Server Boards S5000PSL and S5000XSL TPS BMC Force Update Procedure When performing a standard BMC firmware update procedure, the update utility places the BMC into an update mode, allowing the firmware to load safely onto the flash device. In the unlikely event that the BMC firmware update process fails due to the BMC not being in the proper update state, the server board provides a BMC Force Update jumper (J1E3), which will force the BMC into the proper update state.
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Intel® Server Boards S5000PSL and S5000XSL TPS Jumper Blocks To perform a normal BIOS update, perform the following steps: 1. Boot the system with the jumper covering pins 2 and 3. 2. Update the BIOS using iFlash or the Intel® One Flash Update (OFU) utility. 3. Reset the system. The current BIOS will validate and then boot from the new BIOS. If the system cannot boot, perform the following steps to recover: 1. Boot the system with the jumper covering pins 1 and 2. 2.
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Intel® Light-Guided Diagnostics 7. Intel® Server Boards S5000PSL and S5000XSL TPS Intel® Light-Guided Diagnostics The server boards have several on-board diagnostic LEDs to assist in troubleshooting boardlevel issues. This section provides a description, location and function of each LED on the server board. For a more detailed description of what drives the diagnostic LED operation, see the Intel® S5000 Server Board Family Datasheet. 7.
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Intel® Server Boards S5000PSL and S5000XSL TPS 7.2 Intel® Light Guided Diagnostics Fan Fault LEDs Fan fault LEDs are present for the two CPU fans and the two rear system fans. The two CPU fan fault LEDs are located next to each CPU fan header. The two rear system fan fault LEDs are located next to each rear system fan header as shown in the following figure. AF000203 Figure 19. Fan Fault LED Locations Revision 1.
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Intel® Light-Guided Diagnostics 7.3 Intel® Server Boards S5000PSL and S5000XSL TPS System ID LED and System Status LED The server board provides LEDs for both system ID and system status. These LEDs are located in the rear I/O area of the server board between the PS/2 mouse/keyboard stacked connectors and the video/serial stacked connectors. The location of these LEDs is shown in the following figure. A B AF000204 A. B. System ID LED System Status LED Figure 20.
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Intel® Server Boards S5000PSL and S5000XSL TPS Intel® Light Guided Diagnostics The bi-color System Status LED operates as follows: Table 40. System Status LED Color State Criticality Description Off Green/ Amber N/A Alternating Blink Not ready Not ready AC power off Pre DC Power On – 20-30 second BMC Initialization when AC is applied to the server. Control Panel buttons are disabled until BMC initialization is completed. System booted and ready.
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Intel® Light-Guided Diagnostics 7.3.1 Intel® Server Boards S5000PSL and S5000XSL TPS System Status LED – BMC Initialization When the AC power is first applied to the system and 5V-STBY is present, the BMC controller on the server board requires 5-10 seconds to initialize. During this time, the system status LED blinks, alternating between amber and green, and the power button functionality of the control panel is disabled preventing the server from powering up.
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Intel® Server Boards S5000PSL and S5000XSL TPS 7.5 Intel® Light Guided Diagnostics Processor Fault LEDs The server board provides a fault LED for each processor socket. These LEDs are located near the processor sockets. AF000206 Figure 22. Processor Fault LED Locations 7.
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Intel® Light-Guided Diagnostics Intel® Server Boards S5000PSL and S5000XSL TPS A. Status LED D. Bit 2 LED (POST LED) B. ID LED E. Bit 1 LED (POST LED) C. MSB LED (POST LED) F. LSB LED (POST LED) Figure 23. POST Code Diagnostic LED Location 58 Revision 1.
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Intel® Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications 8. Design and Environmental Specifications 8.1 Intel® Server Boards S5000PSL and S5000XSL Design Specifications The operation of the server boards at conditions beyond those shown in the following table may cause permanent damage to the system. Exposure to absolute maximum rating conditions for extended periods may affect system reliability. Table 41.
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Design and Environmental Specifications 8.3 Intel® Server Boards S5000PSL and S5000XSL TPS Server Board Power Requirements This section provides power supply design guidelines for a system using the Intel® Server Boards S5000PSL and S5000XSL, including voltage and current specifications, and power supply on/off sequencing characteristics. The following diagram shows the power distribution implemented on these server boards. Figure 24. Power Distribution Block Diagram 60 Revision 1.
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Intel® Server Boards S5000PSL and S5000XSL TPS 8.3.1 Design and Environmental Specifications Processor Power Support The server board supports the Thermal Design Point (TDP) guideline for Intel® Xeon® processors. The Flexible Motherboard Guidelines (FMB) has also been followed to help determine the suggested thermal and current design values for anticipating future processor needs.
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Design and Environmental Specifications 8.4.1 Intel® Server Boards S5000PSL and S5000XSL TPS Grounding The grounds of the pins of the power supply output connector provide the power return path. The output connector ground pins is connected to safety ground (power supply enclosure). This grounding is designed to ensure passing the maximum allowed common mode noise levels. 8.4.
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Intel® Server Boards S5000PSL and S5000XSL TPS 8.4.5 Design and Environmental Specifications Dynamic Loading The output voltages should remain within limits for the step loading and capacitive loading specified in the following table. The load transient repetition rate should be tested between 50 Hz and 5 kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only a test specification. The step load may occur anywhere within the minimum load to the maximum load conditions.
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Design and Environmental Specifications 8.4.7 Intel® Server Boards S5000PSL and S5000XSL TPS Ripple/Noise The maximum allowed ripple/noise output of the power supply is defined in the following table. This is measured over a bandwidth of 0 Hz to 20 MHz at the power supply output connectors. A 10 F tantalum capacitor in parallel with a 0.1 F ceramic capacitor are placed at the point of measurement. Table 47. Ripple and Noise +3.3 V 50mVp-p Notes: 1. 2. 3. 4. 8.4.
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Intel® Server Boards S5000PSL and S5000XSL TPS Design and Environmental Specifications V out 10% V out V1 V2 V3 V4 Tvout_rise Tvout_off Tvout_on TP02313 Figure 25. Output Voltage Timing Table 49. Turn On/Off Timing Item Description Minimum Tsb_on_delay Delay from AC being applied to 5 VSB being within regulation. Tac_on_delay Delay from AC being applied to all output voltages being within regulation. Tvout_holdup Time all output voltages stay within regulation after loss of AC.
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Design and Environmental Specifications Intel® Server Boards S5000PSL and S5000XSL TPS AC Input Tvout_holdup Vout Tpwok_low TAC_on_delay Tsb_on_delay PWOK 5VSB Tpwok_off Tpwok_on Tsb_on_delay Tpwok_on Tpwok_off Tpson_pwok Tpwok_holdup T5VSB_holdup Tsb_vout Tpson_on_delay PSON AC turn on/off cycle PSON turn on/off cycle Figure 26. Turn On/Off Timing (Power Supply Signals) 8.4.
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Intel® Server Boards S5000PSL and S5000XSL TPS 9. Regulatory and Certification Information Regulatory and Certification Information To help ensure EMC compliance with your local regional rules and regulations, before computer integration, make sure that the chassis, power supply, and other modules have passed EMC testing using a server board with a microprocessor from the same family (or higher) and operating at the same (or higher) speed as the microprocessor used on this server board.
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Regulatory and Certification Information 9.1.
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Intel® Server Boards S5000PSL and S5000XSL TPS Regulatory and Certification Information 9.3 Electromagnetic Compatibility Notices 9.3.1 FCC Verification Statement (USA) This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Intel Corporation 5200 N.E.
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Regulatory and Certification Information 9.3.3 Intel® Server Boards S5000PSL and S5000XSL TPS Europe (CE Declaration of Conformity) This product has been tested in accordance too, and complies with the Low Voltage Directive (73/23/EEC) and EMC Directive (89/336/EEC). The product has been marked with the CE Mark to illustrate its compliance. 9.3.
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Intel® Server Boards S5000PSL and S5000XSL TPS Regulatory and Certification Information 9.4 Restriction of Hazardous Substances (RoHS) Compliance Intel has a system in place to restrict the use of banned substances in accordance with the European Directive 2002/95/EC. Compliance is based on declaration that materials banned in the RoHS Directive are either (1) below all applicable substance threshold limits or (2) an approved/pending RoHS exemption applies.
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Appendix A: Integration and Usage Tips Intel® Server Boards S5000PSL and S5000XSL TPS Appendix A: Integration and Usage Tips When adding or removing components or peripherals from the server board, AC power must be removed. With AC power plugged into the server board, 5-volt standby is still present even though the server board is powered off. Processors must be installed in order. CPU 1 is located near the edge of the server board and must be populated to operate the board.
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Intel® Server Boards S5000PSL and S5000XSL TPS Appendix B: BMC Sensor Tables Appendix B: BMC Sensor Tables This appendix lists the sensor identification numbers and information about the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 2.0, for sensor and event/reading-type table information.
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Appendix B: BMC Sensor Tables Intel® Server Boards S5000PSL and S5000XSL TPS Rearm Sensors The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states. Rearming the sensors can be done manually or automatically. This column indicates the type supported by the sensor.
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Intel® Server Boards S5000PSL and S5000XSL TPS Appendix B: BMC Sensor Tables Table 50.
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Appendix B: BMC Sensor Tables Sensor Name[1] Sensor Number System Applicability Intel® Server Boards S5000PSL and S5000XSL TPS Sensor Type Event/Rea ding Type Event Offset Triggers Criticality Assert/De-a ssert Readable Value/Offse ts Event Data Rearm Standby Platform Security Violation 04h All Platform Security Violation Attempt 06h Sensor Specific 6Fh Secure mode violation attempt Out-of-band access password violation OK As and De – Trig Offset A, I X Physical Security 05h Physic
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Intel® Server Boards S5000PSL and S5000XSL TPS Sensor Name[1] Sensor Number System Applicability Sensor Type Appendix B: BMC Sensor Tables Event/Rea ding Type Event Offset Triggers Criticality Assert/De-a ssert Readable Value/Offse ts Event Data Rearm Standby BB +1.8V 14h All Voltage 02h Threshold 01h [u,l] [c,nc] Threshold defined As and De Analog R, T A, I – BB +3.3V 15h All Voltage 02h Threshold 01h [u,l] [c,nc] Threshold defined As and De Analog R, T A, I – BB +3.
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Appendix B: BMC Sensor Tables Sensor Name[1] Sensor Number System Applicability Intel® Server Boards S5000PSL and S5000XSL TPS Sensor Type Event/Rea ding Type Event Offset Triggers Criticality Assert/De-a ssert Readable Value/Offse ts Event Data Rearm Standby SYS FAN 2 TACH 53h Chassisspecific Fan 04h Threshold 01h [l] [c,nc] [4] Threshold defined As and De Analog R, T M, I – SYS FAN 3 TACH' 54h Chassisspecific Fan 04h Threshold 01h [l] [c,nc] [4] Threshold defined As and De
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Intel® Server Boards S5000PSL and S5000XSL TPS Sensor Name[1] Sensor Number System Applicability Sensor Type Appendix B: BMC Sensor Tables Event/Rea ding Type Event Offset Triggers Criticality Assert/De-a ssert Readable Value/Offse ts Event Data Rearm Standby Fan 7 Present 66h Chassisspecific Fan 04h Generic 08h Device present OK As and De – T A – Fan 8 Present 67h Chassisspecific Fan 04h Generic 08h Device present OK As and De – T A – Fan 9 Present 68h Chassisspecific
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Appendix B: BMC Sensor Tables Sensor Name[1] Power Supply Status[5] 2 Sensor Number 71h System Applicability Chassisspecific Intel® Server Boards S5000PSL and S5000XSL TPS Sensor Type Event/Rea ding Type Power Supply Sensor Specific 08h 6Fh Event Offset Triggers Criticality Presence OK Failure Degraded Predictive fail Degraded A/C lost Degraded Assert/De-a ssert Readable Value/Offse ts As and De – Event Data Rearm Standby Trig Offset A X Configuration error OK Power Nozzle Power
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Intel® Server Boards S5000PSL and S5000XSL TPS Sensor Name[1] Sensor Number System Applicability Sensor Type Appendix B: BMC Sensor Tables Event/Rea ding Type Event Offset Triggers Criticality Assert/De-a ssert Readable Value/Offse ts Analog Power Gauge (aggregate power) Power Supply 2 7Dh Chassisspecific Other Units 0Bh Threshold 01h [u] [c,nc] Threshold defined As and De System ACPI Power State 82h All System ACPI Power State 22h Sensor Specific 6Fh S0/G0 S1 S3 S4 S5/G2 G3 mechanical
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Appendix B: BMC Sensor Tables Sensor Name[1] Proc 2 Status Sensor Number 91h System Applicability All Intel® Server Boards S5000PSL and S5000XSL TPS Sensor Type Processor 07h Event/Rea ding Type Sensor Specific 6Fh Event Offset Triggers Criticality Disabled Degraded IERR Critical Thermal trip Critical Config error Critical Assert/De-a ssert Readable Value/Offse ts As and De – Analog Presence OK Disabled Degraded Threshold defined As and De – – Threshold defined As and De Ev
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Intel® Server Boards S5000PSL and S5000XSL TPS Sensor Name[1] Sensor Number System Applicability Sensor Type Appendix B: BMC Sensor Tables Event/Rea ding Type Event Offset Triggers Criticality OK PCIe Link3 PCIe Link4 PCIe Link5 PCIe Link6 PCIe Link7 PCIe Link8 PCIe Link9 PCIe Link10 A3h A4h A5h A6h A7h A8h A9h AAh All All All All All All All All Sensor Specific 6Fh Sensor Specific 6Fh Bus correctable error Bus uncorrectable error Degraded Sensor Specific 6Fh Sensor Speci
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Appendix B: BMC Sensor Tables Sensor Name[1] PCIe Link11 PCIe Link12 PCIe Link13 Sensor Number ABh ACh ADh System Applicability All All All Intel® Server Boards S5000PSL and S5000XSL TPS Sensor Type Event/Rea ding Type Event Offset Triggers Criticality Sensor Specific 6Fh Sensor Specific 6Fh Bus correctable error OK Bus uncorrectable error Degraded Sensor Specific 6Fh Sensor Specific 6Fh Bus correctable error OK Bus uncorrectable error Degraded Sensor Specific 6Fh Sensor Specific 6
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Intel® Server Boards S5000PSL and S5000XSL TPS Sensor Name[1] Sensor Number System Applicability Sensor Type Appendix B: BMC Sensor Tables Event/Rea ding Type Event Offset Triggers Criticality Assert/De-a ssert Readable Value/Offse ts Event Data Rearm Standby CPU Population Error D8h All Processor 07h Generic 03h 01h –- State asserted Critical As and De – R, T A – DIMM A1 E0h All Slot Connector 21h Sensor Specific 6Fh Fault status asserted Degraded As – Trig Offset A – As
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Appendix B: BMC Sensor Tables Sensor Name[1] DIMM D1 DIMM D2 Sensor Number E6h E7h System Applicability All All Intel® Server Boards S5000PSL and S5000XSL TPS Sensor Type Slot Connector 21h Slot Connector 21h Event/Rea ding Type Sensor Specific 6Fh Sensor Specific 6Fh Event Offset Triggers Criticality Disabled Degraded Sparing OK Fault status asserted Degraded Device installed OK Disabled Degraded Sparing OK Fault status asserted Degraded Device installed OK Disabled Degrad
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Intel® Server Boards S5000PSL and S5000XSL TPS Sensor Name[1] Sensor Number System Applicability 0Ch Sparing Redundancy B1 DIMM Sparing Enabled B1 DIMM Sparing Redundancy Sensor Type F2h F3h All All Entity Presence 25h Memory 0Ch Appendix B: BMC Sensor Tables Event/Rea ding Type 0Bh Sensor Specific 6Fh Discrete 0Bh Event Offset Triggers Criticality Assert/De-a ssert Readable Value/Offse ts Event Data Rearm Standby Non-redundant: sufficient resources from redundant Non-redundant: suffici
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Appendix B: BMC Sensor Tables Sensor Name[1] Mirroring Redundancy Notes: 1. 2. 3. 4. 5. 6. 7. 8.
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Intel® Server Boards S5000PSL and S5000XSL TPS Appendix C: POST Code Diagnostic LED Decoder Appendix C: POST Code Diagnostic LED Decoder During the system boot process, the BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the POST code to the POST Code Diagnostic LEDs on the back edge of the server board.
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Appendix C: POST Code Diagnostic LED Decoder Intel® Server Boards S5000PSL and S5000XSL TPS In the following example, the BIOS sends a value of ACh to the diagnostic LED decoder. The LEDs are decoded as follows: Red bits = 1010b = Ah Green bits = 1100b = Ch Since the red bits correspond to the upper nibble and the green bits correspond to the lower nibble, the two are concatenated as ACh. Table 51.
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Intel® Server Boards S5000PSL and S5000XSL TPS 0x58h Diagnostic LED Decoder G=Green, R=Red, A=Amber MSB Bit 2 Bit 1 LSB G R Off R Resetting USB bus 0x59h G Checkpoint Appendix C: POST Code Diagnostic LED Decoder Description R Off A Reserved for USB devices ATA/ATAPI/SATA 0x5Ah G R G R Resetting PATA/SATA bus and all devices 0x5Bh G R G A Reserved for ATA 0x5Ch G A Off R Resetting SMBUS 0x5Dh G A Off A Reserved for SMBUS 0x70h Off R R R Resetting the video controller
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Appendix C: POST Code Diagnostic LED Decoder Intel® Server Boards S5000PSL and S5000XSL TPS 0xD1 Diagnostic LED Decoder G=Green, R=Red, A=Amber MSB Bit 2 Bit 1 LSB R R Off A Trying boot device selection 0xD2 R R G R Trying boot device selection 0xD3 R R G A Trying boot device selection 0xD4 R A Off R Trying boot device selection 0xD5 R A Off A Trying boot device selection 0xD6 R A G R Trying boot device selection 0xD7 R A G A Trying boot device selection 0xD8 A R
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Intel® Server Boards S5000PSL and S5000XSL TPS Appendix C: POST Code Diagnostic LED Decoder 0x35h Diagnostic LED Decoder G=Green, R=Red, A=Amber MSB Bit 2 Bit 1 LSB Off G R A Handing off control to the crisis recovery capsule 0x3Fh G Unable to complete crisis recovery. Checkpoint G A A Description Revision 1.
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Appendix D: POST Code Errors Intel® Server Boards S5000PSL and S5000XSL TPS Appendix D: POST Code Errors Whenever possible, the BIOS will output the current boot progress codes on the video screen. Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. The class and subclass fields point to the type of hardware that is being initialized. The operation field represents the specific initialization activity.
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Intel® Server Boards S5000PSL and S5000XSL TPS Error Code 8305 Appendix D: POST Code Errors Error Message Response Hot-swap controller failed Pause 84F2 Baseboard management controller failed to respond Pause 84F3 Baseboard management controller in update mode Pause 84F4 Sensor data record empty Pause 84FF System event log full Pause 8500 Memory Component could not be configured in the selected RAS mode. Pause 8520 DIMM_A1 failed Self Test (BIST).
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Appendix D: POST Code Errors Intel® Server Boards S5000PSL and S5000XSL TPS POST Error Beep Codes The following table lists POST error beep codes. Prior to system Video initialization, the BIOS uses these beep codes to inform users on error conditions. The beep code is followed by a user visible code on POST Progress LEDs. Table 54. POST Error Beep Codes Beeps Error Message Description 3 Memory error System halted because a fatal error related to the memory was detected.
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Intel® Server Boards S5000PSL and S5000XSL TPS Appendix E: Supported Intel® Server Chassis Appendix E: Supported Intel® Server Chassis The Intel® Server Boards S5000PSL and S5000XSL are supported in the following Intel® pedestal server chassis: Intel® Server Chassis SC5400 BASE Intel® Server Chassis SC5400 BRP Intel® Server Chassis SC5400 LX Intel® Server Chassis SC5400 LXi Intel® Entry Server Chassis SC5299-E DP Intel® Entry Server Chassis SC5299-E BRP Revision 1.
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Glossary Intel® Server Boards S5000PSL and S5000XSL TPS Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (e.g., “82460GX”) followed by alpha entries (e.g., “AGP 4x”). Acronyms are followed by non-acronyms.
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Intel® Server Boards S5000PSL and S5000XSL TPS Term Glossary Definition IC MB Intelligent Chassis Management Bus IERR Internal Error IFB I/O and Firmware Bridge INTR Interrupt IP Internet Protocol IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface IR Infrared ITP In-Target Probe KB 1024 bytes KCS Keyboard Controller Style LAN Local Area Network LCD Liquid Crystal Display LED Light Emitting Diode LPC Low Pin Count LUN Logical Unit Number
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Glossary Intel® Server Boards S5000PSL and S5000XSL TPS Term Definition SECC Single Edge Connector Cartridge SEEPROM Serial Electrically Erasable Programmable Read-Only Memory SEL System Event Log SIO Server Input/Output SMI Server Management Interrupt (SMI is the highest priority nonmaskable interrupt) SMM Server Management Mode SMS Server Management Software SNMP Simple Network Management Protocol TBD To Be Determined TIM Thermal Interface Material UART Universal Asynchronous Rece
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Intel® Server Boards S5000PSL and S5000XSL TPS Reference Documents Reference Documents See the following documents for additional information: Intel® S5000 Server Board Family Datasheet Intel® Server Boards S5000PSL and S5000XSL Specification Update Intel® 5000 Series Chipset Memory Controller Hub Datasheet Intel® 631xESB/632xESB I/O Controller Hub Datasheet Revision 1.