Technical Product Specification

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Intel® Server Boards S5520HC,

S5500HCV, and S5520HCT

Intel order number E39529-013

Revision 1.9

June 2011

Enterprise Platforms and Services Division

Summary of content (190 pages)

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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT Technical Product Specification Intel order number E39529-013 Revision 1.
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Revision History Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Revision History Date February 2008 Revision Number 0.1 Modifications Preliminary Draft March 2008 0.3 Content Update March 2008 0.5 Updated sections 2.1 and 3.2 April 2008 0.55 Updated product code and processor support related information. August 2008 0.6 Updated product code and memory support related information; S5500HCV DIMM slot population change; and Chassis Intrusion header location change September 2008 0.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Disclaimers Disclaimers Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
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Table of Contents Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Table of Contents 1. Introduction .......................................................................................................................... 1 1.1 Chapter Outline ........................................................................................................ 1 1.2 Server Board Use Disclaimer .................................................................................. 1 2. Overview ....................
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Table of Contents 3.3.10 Supported Memory Configuration .......................................................................... 36 3.3.11 Memory Error Handling .......................................................................................... 38 3.4 ICH10R .................................................................................................................. 39 3.4.1 Serial ATA Support ...........................................
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Table of Contents Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 4.4.1 Manageability Engine (ME) .................................................................................... 70 5. BIOS Setup Utility ............................................................................................................... 72 5.1 Logo/Diagnostic Screen ......................................................................................... 72 5.2 BIOS Boot Popup Menu ..................................
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Table of Contents 9.4 Power Supply Output Requirements ................................................................... 131 9.4.1 Grounding ............................................................................................................ 131 9.4.2 Stand-by Outputs ................................................................................................. 131 9.4.3 Remote Sense ......................................................
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List of Figures Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS List of Figures Figure 1. Intel® Server Board S5520HC........................................................................................ 5 Figure 2. Intel® Server Board S5500HCV ..................................................................................... 5 Figure 3. Major Board Components .............................................................................................. 7 Figure 4. Mounting Hole Locations ...
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS List of Figures Figure 40. Setup Utility — Console Redirection Screen Display ................................................ 96 Figure 41. Setup Utility — Server Management System Information Screen Display ................ 98 Figure 42. Setup Utility — Boot Options Screen Display ............................................................ 99 Figure 43. Setup Utility — Add New Boot Option Screen Display ............................................
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List of Tables Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS List of Tables Table 1. IOH High-Level Summary ............................................................................................. 20 Table 2. Mixed Processor Configurations ................................................................................... 23 Table 3. Memory Running Frequency vs. Processor SKU ......................................................... 31 Table 4. Memory Running Frequency vs.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS List of Tables Table 39. Setup Utility — CDROM Order Fields ....................................................................... 103 Table 40. Setup Utility — Floppy Order Fields .......................................................................... 103 Table 41. Setup Utility — Network Device Order Fields ........................................................... 104 Table 42. Setup Utility — BEV Device Order Fields .........................
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List of Tables Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Table 80. Turn On/Off Timing ................................................................................................... 135 Table 81. Compatible Chassis/Heatsink Matrix ........................................................................ 147 Table 82. Integrated BMC Core Sensors .................................................................................. 152 Table 83. Platform Specific BMC Features ..................
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS List of Tables Revision 1.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 1. Introduction Introduction This Technical Product Specification (TPS) provides board-specific information detailing the features, functionality, and high-level architecture of the Intel® Server Boards S5520HC, S5500HCV and S5520HCT. In addition, you can obtain design-level information for a given subsystem by ordering the External Product Specifications (EPS) for the specific subsystem.
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Overview 2. Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Overview The Intel® Server Boards S5520HC, S5500HCV and S5520HCT are monolithic printed circuit boards (PCBs) with features designed to support the pedestal server markets. 2.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Feature Add-in Card Slots Overview Description  Intel® Server Board S5520HC/S5520HCT: Six expansion slots  One full-length/full-height PCI Express* Gen2 slot (x16 Mechanically, x8 Electrically)  Three full-length/full-height PCI Express* Gen2 x8 slots  One full-length/full-height PCI Express* Gen1 slot (x8 Mechanically, x4 Electrically) shared with SAS Module slot*.
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Overview Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Feature Server Management Description  Onboard ServerEngines* LLC Pilot II* Controller  Integrated Baseboard Management Controller (Integrated BMC), IPMI 2.0 compliant  Integrated Super I/O on LPC interface  Support for Intel® Remote Management Module 3  Intel® Light-Guided Diagnostics on field replaceable units  Support for Intel® System Management Software 3.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Overview Server Board Layout Figure 1. Intel® Server Board S5520HC Figure 2. Intel® Server Board S5500HCV 2.1.1 Server Board Connector and Component Layout The following figure shows the layout of the server board. Each connector and major component is identified by a number or letter, and a description is given below the figure. Revision 1.
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Overview Callout A B C D E F G H Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Description Slot 1, 32-bit/33 MHz PCI, Keying for 5V and Universal Intel® RMM3 Slot Slot 2, PCI Express* x4 (x8 Mechanically) Low-profile USB Solid State Drive Header Slot 3, PCI Express* Gen2 x8 Slot 4, PCI Express* Gen2 x8 Slot 5, PCI Express* Gen2 x8 (Empty on Intel® Server Board S5500HCV) Callout S5520HC: Slot 6, PCI Express* Gen2 x8 (x16 Description W System Fan 2 Header (6-pin) X Y Z AA BB System Fan 1 H
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Callout I J K L M N O P Description Mechanically) S5500HCV: Slot 6, PCI Express* Gen2 x4 (x16 Mechanically) Battery Back Panel I/O Ports Diagnostic and Identify LED‘s System Fan 5 Header (4-pin) Power Connector for Processor 1 and Memory attached to Processor 1 Processor 1 Fan Header (4-pin) DIMM Sockets of Memory Channel A, B, and C Power Connector for Processor 2 and Memory attached to Processor 2 Overview Callout EE FF GG HH II Description HSB
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Overview 2.1.2 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Server Board Mechanical Drawings Figure 4. Mounting Hole Locations Revision 1.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Overview Figure 5. Major Connector Pin-1 Locations (1 of 2) Revision 1.
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Overview Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Figure 6. Major Connector Pin-1 Locations (2 of 2) Revision 1.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Overview Figure 7. Primary Side Keep-out Zone (1 of 2) Revision 1.
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Overview Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Figure 8. Primary Side Keep-out Zone (2 of 2) Revision 1.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Overview Figure 9. Primary Side Air Duct Keep-out Zone Revision 1.
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Overview Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Figure 10. Primary Side Card-Side Keep-out Zone Revision 1.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Overview Figure 11. Second Side Keep-out Zone Revision 1.
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Overview 2.1.3 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Server Board Rear I/O Layout The following drawing shows the layout of the rear I/O components for the server boards. Callout A Description System Status LED Callout E B ID LED F C Diagnostics LED‘s G D Serial Port A Description Video NIC Port 1 (1 Gb, Default Management Port) USB Port 2 (top), 3 (bottom) NIC Port 2 (1 Gb) USB Port 0 (top), 1 (bottom) Figure 12. Rear I/O Layout Revision 1.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 3. Functional Architecture Functional Architecture The architecture and design of the Intel® Server Boards S5520HC, S5500HCV and S5520HCTis based on the Intel® 5520/5500 and ICH10R chipset. The chipset is designed for systems based on the Intel® Xeon® Processor 5500 Series in an FC-LGA 1366 Socket B package with Intel® QuickPath Interconnect (Intel® QPI) speed at 6.40 GT/s, 5.86 GT/s, and 4.80 GT/s.
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Functional Architecture Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Figure 13. Intel® Server Board S5520HC Functional Block Diagram Revision 1.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Functional Architecture Figure 14. Intel® Server Board S5500HCV Functional Block Diagram Revision 1.
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Functional Architecture 3.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 3.1.3 Functional Architecture Enterprise South Bridge Interface (ESI) One x4 ESI link interface supporting PCI Express Gen1 (2.5 Gbps) transfer rate for connecting Intel® ICH10R in the Intel® Server Boards S5520HC, S5500HCV and S5520HCT. 3.1.4 Manageability Engine (ME) An embedded ARC controller is within the IOH providing the Intel® Server Platform Services (SPS). The controller is also commonly referred to as the Manageability Engine (ME). 3.
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Functional Architecture 3.2 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Processor Support The Intel® Server Boards S5520HC, S5500HCV and S5520HCT support the following processors:  One or two Intel® Xeon® Processor 5500 Series with a 4.8 GT/s, 5.86 GT/s, or 6.4 GT/s Intel® QPI link interface and Thermal Design Power (TDP) up to 95 W.  One or two Intel® Xeon® Processor 5600 Series with a 6.4 GT/s Intel® QPI link interface and Thermal Design Power (TDP) up to 130 W.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Functional Architecture Table 2. Mixed Processor Configurations Error Processor family not identical Severity Halt System Action The BIOS detects the error condition and responds as follows: – Logs the error into the system event log (SEL). – Alerts the Integrated BMC about the configuration error. – Does not disable the processor. – Displays ―0194: Processor 0x family mismatch detected‖ message in the Error Manager.
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Functional Architecture Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Error Processor Intel® QuickPath Interconnect speeds not identical Severity Halt System Action The BIOS detects the error condition and responds as follows: – Adjusts all processor QPI frequencies to highest common frequency. – No error is generated – this is not an error condition – Continues to boot the system successfully.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS  Functional Architecture Intel® 64 mode when 64-bit extension technology is enabled (Entering Intel® 64 mode requires enabling PAE). You can enable and disable the XD bit in the BIOS Setup. The default behavior is enabled. 3.2.7 Core Multi-Processing The BIOS setup provides the ability to selectively enable one or more cores. The default behavior is to enable all cores. You can do this through the BIOS setup option for active core count.
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Functional Architecture Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Figure 15. Unified Retention System and Unified Back Plate Assembly Revision 1.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 3.3 Functional Architecture Memory Subsystem The Intel® Xeon® Processor 5500 Series on the Intel® Server Boards S5520HC, S5500HCV and S5520HCT are populated on CPU sockets. Each processor installed on the CPU socket has an integrated memory controller (IMC), which supports up to three DDR3 channels and groups DIMMs on the server boards into autonomous memory. 3.3.
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Functional Architecture Server Board Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS CPU Socket CPU 1 Intel® Server Board S5520HC CPU 2 DIMM Identifier A1 (Blue) A2 (Black) B1 (Blue) B2 (Black) C1 (Blue) C2 (Black) D1 (Blue) D2 (Black) E1 (Blue) E2 (Black) F1 (Blue) F2 (Black) Channel/Slot Channel A, Slot 0 Channel A, Slot 1 Channel B, Slot 0 Channel B, Slot 1 Channel C, Slot 0 Channel C, Slot 1 Channel D, Slot 0 Channel D, Slot 1 Channel E, Slot 0 Channel E, Slot 1 Channel F, Slot 0 Channel
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Server Board CPU Socket CPU 1 Intel® Server S5500HCV Board CPU 2 Functional Architecture DIMM Identifier A1 (Blue) A2 (Black) B1 (Blue) B2 (Black) C1 (Blue) C2 (Black) D1 (Blue) E1 (Blue) F1 (Blue) Channel/Slot Channel A, Slot 0 Channel A, Slot 1 Channel B, Slot 0 Channel B, Slot 1 Channel C, Slot 0 Channel C, Slot 1 Channel D, Slot 0 Channel E, Slot 0 Channel F, Slot 0 Figure 17. Intel® Server Board S5500HCV DIMM Slots Arrangement 3.3.
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Functional Architecture Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Mixing of RDIMMs and UDIMMs is not supported.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Functional Architecture Table 3. Memory Running Frequency vs. Processor SKU DIMM Type DDR3 1066 DDR3 800 800 Processor Integrated Memory Controller (IMC) Max. Frequency (Hz) 800 800 DDR3 1333 800 1066 800 1066 1066 1333 800 1066 1333 Memory Running Frequency (Hz) = Fastest Common Frequency of Processor IMC and Memory Table 4. Memory Running Frequency vs.
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Functional Architecture 3.3.4 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Publishing System Memory The BIOS displays the ―Total Memory‖ of the system during POST if the ―Quiet Boot‖ is disabled in the BIOS Setup. This is the total size of memory discovered by the BIOS during POST, and is the sum of the individual sizes of installed DDR3 DIMMs in the system. The BIOS also provides the total memory of the system in the BIOS setup (Main page and Advanced | Memory Configuration Page).
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Functional Architecture  Bank Interleaving – Interleave cache-line data between participant ranks.  Channel Interleaving – Interleave between channel when not in Mirrored Channel Mode.  Socket Interleaving – Interleaved memory can spread between both CPU sockets when NUMA mode is disabled, given both CPU sockets are populated and DDR3 DIMMs are installed in slots for both sockets. 3.3.6 Memory Test 3.3.6.
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Functional Architecture 3.3.8.2 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Independent Channel Mode In the Independent Channel mode, you can populate multiple channels on any channel in any order. The Independent Channel mode provides less RAS capability but better DIMM isolation in case of errors. Moreover, it allows the best interleave mode possible and thereby increases performance and thermal characteristics.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS  Functional Architecture Optimization techniques used by the Intel® Xeon® Processor 5500 Series to maximize memory bandwidth In the Independent Channel mode, all the DDR3 channels operate independently. Also, you can use the Independent Channel mode to support single DIMM configuration in Channel A and in the Single Channel mode.
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Functional Architecture Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 14. The minimal population upgrade recommended for enabling CPU 2 socket are DIMM_A1 and DIMM_D1. This configuration supports only the Independent Channel mode. 15. In the Mirrored Channel mode, memory population on Channels A and B should be identical, including across adjacent slots on the channels, memory population on Channels D and E should be identical, including across adjacent slots on the channels.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Functional Architecture Table 5.
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Functional Architecture 3.3.11 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Memory Error Handling The BIOS classifies memory errors into the following categories:  Correctable ECC errors: This correction could be the result of an ECC correction, a successfully retried memory cycle, or both.  Unrecoverable/Fatal ECC Errors: The ECC engine detects these errors but cannot correct them.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 3.4 Functional Architecture ICH10R The ICH10R provides extensive I/O support. Functions and capabilities include:  PCI Express* Base Specification, Revision 1.1, support  PCI Local Bus Specification, Revision 2.3, support for 33-MHz PCI operations (supports up to four REQ#/GNT# pairs)  ACPI Power Management Logic Support, Revision 3.
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Functional Architecture    Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Intel® Embedded Server RAID Technology II Option ROM Intel® Embedded Server RAID Technology II drivers, most recent revision At least two SATA hard disk drives 3.4.1.1.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 3.4.2 Functional Architecture USB 2.0 Support The USB controller functionality integrated into the ICH10R provides the server boards with an interface for up to ten USB 2.0 ports. All ports are high-speed, full-speed, and low-speed capable.      Four external connectors are located on the back edge of the server boards. One internal 2x5 header (J1D1) is provided, capable of supporting two optional USB 2.0 ports.
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Functional Architecture 3.5 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS PCI Subsystem The primary I/O buses for the Intel® Server Board S5520HC are PCI, PCI Express* Gen1, and PCI Express* Gen2 with six independent PCI bus segments. The primary I/O buses for the Intel® Server Board S5500HCV are PCI, PCI Express* Gen1, and PCI Express* Gen2 with five independent PCI bus segments. PCI Express* Gen1 and Gen2 are dual-simplex point-to-point serial differential low-voltage interconnects.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Functional Architecture Table 9. Intel® Server Board S5500HCV PCI Bus Segment Characteristics PCI Bus Segment PCI32 ICH10R PE1, PE2, PE3, PE4 ICH10R PCI Express* Ports Voltage 5V Width 32 bit Speed 33 MHz Type PCI 3.3 V x4 10 Gb/s PCI Express* Gen1 PE5 ICH10R PCI Express* Port PE1, PE2 5500 IOH PCI Express* Ports PE3 5500 IOH PCI Express* Port PE7, PE8 5500 IOH PCI Express* Ports PE9, PE10 5500 IOH PCI Express* Ports 3.3 V x1 2.5 Gb/s 3.
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Functional Architecture 3.6 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Intel®SAS Entry RAID Module AXX4SASMOD (Optional Accessory) The Intel® Server Boards S5520HC, S5500HCV and S5520HCT provide a Serial Attached SCSI (SAS) module slot (J2J1) for the installation of an optional Intel® SAS Entry RAID Module AXX4SASMOD.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Functional Architecture Figure 19. Intel® SAS Entry RAID Module AXX4SASMOD Functional Block Diagram 3.6.1 SAS RAID Support The BIOS Setup Utility provides drive configuration options on the Advanced | Mass Storage Controller Configuration setup page for the Intel® SAS Entry RAID Module AXX4SASMOD, some of which affect the ability to configure RAID.
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Functional Architecture Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Table 12. Intel® SAS Entry RAID Module AXX4SASMOD Storage Mode SW RAID = Intel® Embedded Server RAID Technology II (ESRTII) IT/IR RAID = IT/IR RAID, Entry Hardware RAID Storage Mode* IT/IR RAID Description 4 SAS Ports Up to 10 SAS or SATA drives via expander backplanes RAID Types and Levels Supported Native SAS pass through mode without RAID function. Entry Hardware RAID.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 3.7 Functional Architecture Baseboard Management Controller The Intel® Server Boards S5520HC, S5500HCV and S5520HCT have an integrated BMC controller based on ServerEngines* Pilot II. The BMC controller is provided by an embedded ARM9 controller and associated peripheral functionality that is required for IPMI-based server management.
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Functional Architecture Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Figure 20. Integrated BMC Hardware 3.7.1 BMC Embedded LAN Channel The BMC hardware includes two dedicated 10/100 network interfaces, which are given below: Interface 1: This interface is available from either of the available NIC ports in system that can be shared with the host. Only one NIC may be enabled for management traffic at any time. The default active interface is onboard NIC1.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 3.8 Functional Architecture Serial Ports The Intel® Server Boards S5520HC, S5500HCV and S5520HCT provide two serial ports: an external DB9 serial port and an internal DH-10 serial header. The rear DB9 serial A port is a fully-functional serial port that can support any standard serial device. Serial B is an optional port accessible through a 9-pin internal DH-10 header.
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Functional Architecture Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Table 14. Video Modes 2D Mode 640 x 480 800 x 600 1024 x 768 1152 x 864 1280 x 1024 1440 x 900 1600 x 1200 3.11.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Functional Architecture 3.12 Network Interface Controller (NIC) The Intel® Server Boards S5520HC, S5500HCV and S5520HCT provide dual onboard LAN ports with support for 10/100/1000 Mbps operation. The two LAN ports are based on the onboard Intel® 82575EB controller, which is a single, compact component with two, fullyintegrated GbE Media Access Control (MAC) and Physical Layer (PHY) ports. The Intel® 82575EB controller provides a standard IEEE 802.
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Functional Architecture Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 3.13 *Trusted Platform Module (TPM) – Supported only on S5520HCT 3.13.1 Overview Trusted Platform Module (TPM) is a hardware-based security device that addresses the growing concern on boot process integrity and offers better data protection. TPM protects the system start-up process by ensuring it is tamper-free before releasing system control to the operating system.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 3.13.2.1 Functional Architecture Physical Presence Administrative operations to the TPM require TPM ownership or physical presence indication by the operator to confirm the execution of administrative operations. The BIOS implements the operator presence indication by verifying the setup Administrator password. A TPM administrative sequence invoked from the operating system proceeds as follows: 1.
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Functional Architecture Main Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Advanced Security Server Management Administrator Password Status User Password Status Set Administrator Password [1234aBcD] Set User Password [1234aBcD] Front Panel Lockout Enabled/Disabled TPM State TPM Administrative Control Boot Options Boot Manager No Operation/T
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 3.13.3 Intel®Trusted Execution Technology (Intel®TXT) 3.13.3.1 Overview Functional Architecture Intel® Trusted Execution Technology (Intel® TXT) for safer computing, formerly code named LaGrande Technology, is a versatile set of hardware extensions to Intel® processors and chipsets that enhance the platform with security capabilities such as measured launch and protected execution.
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Functional Architecture Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS System pre-requirements: Processor: B1 or later stepping Intel® Xeon Processor 5600 Series Server Board: Intel® Server Board S5520HCT; PBA version E80888-553 or later Memory: At least 1 GB memory installed Intel® TXT Setup: 1 – Enable TPM module: Go to BIOS setup Menu page, Security Tab, set administrator password. Figure 22. Setting Administrator password in BIOS 2.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Functional Architecture Figure 23. Activating TPM 4. Go to BIOS setup Menu, Security Tab, TPM State should be ―Enabled & Activated‖. Revision 1.
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Functional Architecture Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Figure 24. TPM activated 5. Go to BIOS Setup Menu, Advanced -> Processor Configuration, set Intel® VT for directed I/O and Intel® TXT option as ―Enabled‖ Revision 1.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Functional Architecture Figure 25. BIOS setting for TXT 6. Press ―F10‖ to save and exit, now Intel® TXT is successfully enabled. 3.14 ACPI Support The Intel® Server Boards S5520HC, S5500HCV and S5520HCT support S0, S1, and S5 states. S1 is considered a sleep state. The Intel® Server Boards S5520HC, S5500HCV and S5520HCT can wake up from S1 state using the USB devices in addition to the sources described in the following paragraph.
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Functional Architecture Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 3.15 Intel®Virtualization Technology Intel® Virtualization Technology is designed to support multiple software environments sharing the same hardware resources. Each software environment may consist of an operating system and applications. You can enable or disable the Intel® Virtualization Technology in the BIOS Setup. The default behavior is disabled.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 4. Platform Management Platform Management The platform management subsystem is based on the Integrated BMC features of the ServerEngines* Pilot II. The onboard platform management subsystem consists of communication buses, sensors, and the system BIOS, and server management firmware. Figure 27 provides an illustration of the Server Management Bus (SMBUS) architecture as used on these server boards. 4.1 Feature Support 4.1.1 IPMI 2.
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Platform Management Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS  Fault resilient booting (FRB): FRB2 is supported by the watchdog timer functionality.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 4.2 Platform Management Optional Advanced Management Feature Support This section explains the advanced management features supported by the BMC firmware. Table 17 lists basic and advanced feature support. Individual features may vary by platform. For more information, refer to Appendix C. Table 17. Basic and Advanced Management Features Feature IPMI 2.
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Platform Management Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS as a Java* applet. The client system must have a Java Runtime Environment (JRE) Version 1.6 (JRE6) or later to run the KVM or media redirection applets. You can download the latest Java Runtime Environment (JRE) update: http://java.com/en/download/index.jsp. This feature is only enabled when the Intel® RMM3 is present.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Platform Management  The operation of remotely mounted devices is independent of the local devices on the server. Both remote and local devices are usable in parallel.  You can mount either IDE (CD-ROM, floppy) or USB devices as a remote device to the server.  It is possible to boot all supported operating systems from the remotely mounted device and to boot from disk IMAGE (*.IMG) and CD-ROM or DVD-ROM ISO files.
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Platform Management 4.2.5 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Embedded Web server The BMC provides an embedded web server for out-of-band management. User authentication is handled by IPMI user names and passwords. Base functionality for the embedded web server includes:  Power Control  Sensor Reading  SEL Reading  KVM/Media Redirection: Only available when the Intel® RMM3 is present.  IPMI User Management The web server is available on all enabled LAN channels.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 4.3 Platform Management Platform Control This server platform has embedded platform control which is capable of automatically adjusting system performance and acoustic levels. Performance Management Performance Throttling Integrated Control Acoustic Management Thermal Monitoring Fan Speed Control Figure 26.
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Platform Management 4.3.1 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Memory Open and Closed Loop Thermal Throttling Open-Loop Thermal Throttling (OLTT) Throttling is a solution to cool the DIMMs by reducing memory traffic allowed on the memory bus, which reduces power consumption and thermal output. With OLTT, the system throttles in response to memory bandwidth demands instead of actual memory temperature.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Platform Management BIOS fails to get the Thermal SDRs, then it uses the Memory Reference Code (MRC) default settings for the memory throttling settings. The BIOS Setup Utility provides options to set the fan profile or operating mode the platform will operate under. Each operating mode has a predefined profile for which specific platform targets are configured, which in turn determines how the system fans operate to meet those targets.
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Platform Management Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS platform, but the increased airflow of this operating mode greatly reduces both possible memory throttling from occurring and dynamic fan speed changes based on processor utilization. 4.3.2.3.2 Acoustics Mode With the platform running in Acoustics mode, several platform control algorithm variables are set to ensure acoustic targets are not exceeded for specified Intel platforms.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Platform Management Figure 27. SMBUS Block Diagram Revision 1.
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BIOS Setup Utility Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 5. BIOS Setup Utility 5.1 Logo/Diagnostic Screen The Logo/Diagnostic Screen displays in one of two forms:   If Quiet Boot is enabled in the BIOS setup, a logo splash screen is displayed. By default, Quiet Boot is enabled in the BIOS setup. If the logo displays during POST, press to hide the logo and display the diagnostic screen.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS BIOS Setup Utility  Localization - The BIOS Setup uses the Unicode standard and is capable of displaying setup forms in all languages currently included in the Unicode standard. The Intel® server board BIOS is only available in English.  Console Redirection - The BIOS Setup is functional via console redirection over various terminal emulation standards.
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BIOS Setup Utility Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Table 20.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 5.3.1.4 BIOS Setup Utility Menu Selection Bar The Menu Selection Bar is located at the top of the BIOS Setup Utility screen. It displays the major menu selections available to the user. By using the left and right arrow keys, the user can select the menus listed here. Some menus are hidden and become available by scrolling off the left or right of the current selections. 5.3.
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BIOS Setup Utility 5.3.2.1 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Main Screen Unless an error occurred, the Main screen is the first screen displayed when the BIOS Setup is entered. If an error occurred, the Error Manager screen displays instead. Main Advanced Security Server Management Boot Options Boot Manager Logged in as Platform ID System BIOS Version S5500.86B.xx.yy.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Setup Item Options Help Text Size Enabled Disabled [Enabled] – Display the logo screen during POST. POST Error Pause Enabled Disabled [Disabled] – Display the diagnostic screen during POST. [Enabled] – Go to the Error Manager for critical POST errors. [Disabled] – Attempt to boot and do not go to the Error Manager for critical POST errors.
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BIOS Setup Utility 5.3.2.2 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Advanced Screen The Advanced screen provides an access point to configure several options. On this screen, the user selects the option they must configure. Configurations are performed on the selected screen and not directly on the Advanced screen. To access this screen from the Main screen, press the right arrow until the Advanced screen is selected.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 5.3.2.2.1 BIOS Setup Utility Processor Configuration Screen The Processor screen allows the user to view the processor core frequency, system bus frequency, and to enable or disable several processor options. This screen also allows the user to view information about a specific processor. To access this screen from the Main screen, select Advanced > Processor.
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BIOS Setup Utility Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Table 23. Setup Utility — Processor Configuration Screen Fields Setup Item Processor ID Options Help Text Comments Information only. Processor CPUID Information only. Current frequency of the processor. Information only. Revision of the loaded microcode. Information only. Size of the Processor L1 Cache. Information only. Size of the Processor L2 Cache Information only. Size of the Processor L3 Cache. Information only.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Setup Item Intel® Virtualization Technology for Directed I/O Options Enabled Disabled Disabled Help Text Enable/Disable Intel® Virtualization Technology for Directed I/O. Report the I/O device assignment to VMM through DMAR ACPI Tables Enable/Disable Intel® VT-d Interrupt Remapping support. Interrupt Remapping Enabled Coherency Support Enabled Disabled Enable/Disable Intel® VT-d Coherency support.
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BIOS Setup Utility 5.3.2.2.2 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Memory Screen The Memory screen allows the user to view details about the system memory DDR3 DIMMs installed. This screen also allows the user to open the Configure Memory RAS and Performance screen. To access this screen from the Main screen, select Advanced > Memory.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS BIOS Setup Utility Table 24. Setup Utility — Memory Configuration Screen Fields Setup Item Total Memory Options Help Text Effective Memory Current Configuration Comments Information only. The amount of memory available in the system in the form of installed DDR3 DIMMs in units of MB or GB. Information only. The amount of memory available to the operating system in MB or GB.
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BIOS Setup Utility Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 5.3.2.2.2.1 Configure Memory RAS and Performance Screen The Configure Memory RAS and Performance screen allows the user to customize several memory configuration options, such as whether to use Memory Mirroring. To access this screen from the Main screen, select Advanced > Memory > Configure Memory RAS and Performance.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 5.3.2.2.3 BIOS Setup Utility Mass Storage Controller Screen The Mass Storage screen allows the user to configure the SATA/SAS controller when it is present on the baseboard module card of an Intel system. To access this screen from the Main menu, select Advanced > Mass Storage.
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BIOS Setup Utility Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Table 26. Setup Utility — Mass Storage Controller Configuration Screen Fields Setup Item Intel® Entry SAS RAID Module ® Configure Intel Entry SAS RAID Module Onboard SATA Controller SATA Mode Options Enabled Disabled IT/IR RAID Intel® ESRTII Enabled Disabled Enhanced Compatibility AHCI SW RAID Help Text Enabled or Disable the Intel® SAS Entry RAID Module Comments Unavailable if the SAS Module (AXX4SASMOD) is not present.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 5.3.2.2.4 BIOS Setup Utility Serial Ports Screen The Serial Ports screen allows the user to configure the Serial A [COM 1] and Serial B [COM2] ports. To access this screen from the Main screen, select Advanced > Serial Port. Advanced Serial Port Configuration Serial A Enable Enabled/Disabled Address 3F8h/2F8h/3E8h/2E8h IRQ 3 or 4 Serial B Enable Enabled/Disabled Address 3F8h/2F8h/3E8h/2E8h IRQ 3 or 4 Figure 34.
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BIOS Setup Utility 5.3.2.2.5 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS USB Configuration Screen The USB Configuration screen allows the user to configure the USB controller options. To access this screen from the Main screen, select Advanced > USB Configuration.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS BIOS Setup Utility Table 28. Setup Utility — USB Controller Configuration Screen Fields Setup Item Detected USB Devices Options USB Controller Enabled Disabled Legacy USB Support Enabled Disabled Auto Port 60/64 Emulation Enabled Disabled Make USB Devices NonBootable Enabled Disabled Device Reset timeout 10 sec 20 sec 30 sec 40 sec Auto Floppy Forced FDD Hard Disk CD-ROM One line for each mass storage device in system USB 2.
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BIOS Setup Utility 5.3.2.2.6 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS PCI Screen The PCI Screen allows the user to configure the PCI add-in cards, onboard NIC controllers, and video options. To access this screen from the Main screen, select Advanced > PCI.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Setup Item Onboard NIC iSCSI ROM Options Enabled Disabled Help Text If enabled. loads the embedded option ROM for the onboard network controllers. Warning: If [Disabled] is selected, NIC1 and NIC2 cannot be used to boot or wake the system. NIC 1 MAC Address NIC 2 MAC Address 5.3.2.2.7 BIOS Setup Utility Comments This option is grayed out and not accessible if either the NIC1 or NIC2 ROMs are enabled. Information only.
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BIOS Setup Utility Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Table 30. Setup Utility — System Acoustic and Performance Configuration Screen Fields Setup Item Set Throttling Mode Altitude Options Auto CLTT OLTT 300m or less 301m-900m 901m-1500m Higher than 1500m Help Text [Auto] – Auto Throttling mode. [CLTT] – Closed Loop Thermal Throttling Mode. [OLTT] – Open Loop Thermal Throttling Mode. [300m or less] (980ft or less) Comments Optimal performance setting near sea level.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS BIOS Setup Utility Table 31.
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BIOS Setup Utility Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Setup Item TPM Administrative Control** Options No Operation Turn On Turn Off Clear Ownership Help Text [No Operation] - No changes to current state. [Turn On] - Enables and activates TPM. [Turn Off] - Disables and deactivates TPM. [Clear Ownership] - Removes the TPM ownership authentication and returns the TPM to a factory default state. Note: The BIOS setting returns to [No Operation] on every boot cycle by default.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Main Advanced Security Server Management BIOS Setup Utility Boot Options Assert NMI on SERR Enabled/Disabled Assert NMI on PERR Enabled/Disabled Resume on AC Power Loss Stay Off/Last state/Reset Clear System Event Log Enabled/Disabled FRB-2 Enable Enabled/Disabled O/S Boot Watchdog Timer Enabled/Disabled O/S Boot Watchdog Timer Policy Power off/Reset O/S Boot Watchdog Timer Timeout 5 minutes/10 minutes/15 minutes/20 minutes ACPI
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BIOS Setup Utility Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Setup Item O/S Boot Watchdog Timer Options Enabled Disabled Help Text If enabled, the BIOS programs the watchdog timer with the timeout value selected. If the OS does not complete booting before the timer expires, the BMC resets the system and an error is logged. Requires OS support or Intel Management Software. Comments O/S Boot Watchdog Timer Policy Power Off Reset Grayed out when O/S Boot Watchdog Timer is disabled.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS BIOS Setup Utility Table 33. Setup Utility — Console Redirection Configuration Fields Setup Item Console Redirection Options Disabled Serial Port A Serial Port B Flow Control None RTS/CTS Baud Rate 9600 19.2K 38.4K 57.6K 115.2K Terminal Type PC-ANSI VT100 VT100+ VT-UTF8 Disabled Enabled Legacy OS Redirection 5.3.2.5 Help Text Console redirection allows a serial port to be used for server management tasks.
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BIOS Setup Utility Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS  Server Management  System Information Board Part Number Board Serial Number System Part Number System Serial Number Chassis Part Number Chassis Serial Number Asset Tag BMC Firmware Revision HSC Firmware Revision ME Firmware Revision SDR Revision UUID Figure 41. Setup Utility — Server Management System Information Screen Display Table 34.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Main Advanced Security Server Management BIOS Setup Utility Boot Options System Boot Timeout <0 - 65535> Boot Option #1 Boot Option #2 Boot Option #x Boot Manager Hard Disk Order CDROM Order Floppy Order Network Device Order BEV Device Order Add New Boot Option ►Delete Boot Option EFI Optimized Boot Enabled/Disabled Use Legacy Video for EFI OS Enabled/Disabled
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BIOS Setup Utility Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Table 35. Setup Utility — Boot Options Screen Fields Setup Item Boot Timeout Options 0 - 65535 Help Text The number of seconds the BIOS should pause at the end of POST to allow the user to press the [F2] key for entering the BIOS Setup utility. Valid values are 0-65535. Zero is the default. A value of 65535 causes the system to go to the Boot Manager menu and wait for user input for every system boot.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS BIOS Setup Utility If all types of bootable devices are installed in the system, then the default boot order is: 1. 2. 3. 4. 5. 6. CD/DVD-ROM Floppy Disk Drive Hard Disk Drive PXE Network Device BEV (Boot Entry Vector) Device EFI Shell and EFI Boot paths 5.3.2.6.1 Add New Boot Option Screen The Add Boot Option screen allows the user to remove an EFI boot option from the boot order.
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BIOS Setup Utility 5.3.2.6.2 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Delete Boot Option Screen The Delete Boot Option screen allows the user to remove an EFI boot option from the boot order. Note that while you can delete the Internal EFI Shell in this screen, it is restored to the Boot Order on the next reboot. You cannot permanently delete the Internal EFI Shell. To access this screen from the Main screen, select Boot Options > Delete Boot Options.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 5.3.2.6.4 BIOS Setup Utility CDROM Order Screen The CDROM Order screen allows the user to control the CDROM devices. To access this screen from the Main screen, select Boot Options > CDROM Order. Boot Options CDROM #1 CDROM #2 Figure 46. Setup Utility — CDROM Order Screen Display Table 39. Setup Utility — CDROM Order Fields Setup Item CDROM #1 CDROM #2 5.3.2.6.
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BIOS Setup Utility Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Setup Item Floppy Disk #2 5.3.2.6.6 Options Available Legacy devices for this Device group. Help Text Set system boot order by selecting the boot option for this position. Network Device Order Screen The Network Device Order screen allows the user to control the network bootable devices. To access this screen from the Main screen, select Boot Options > Network Device Order.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS BIOS Setup Utility Table 42. Setup Utility — BEV Device Order Fields Setup Item BEV Device #1 Options Available Legacy devices for this Device group. Available Legacy devices for this Device group. BEV Device #2 5.3.2.7 Help Text Set system boot order by selecting the boot option for this position. Set system boot order by selecting the boot option for this position.
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BIOS Setup Utility 5.3.2.8 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Error Manager Screen The Error Manager screen displays any errors encountered during POST. Error Manager ERROR CODE Exit SEVERITY INSTANCE Figure 51. Setup Utility — Error Manager Screen Display Table 44. Setup Utility — Error Manager Screen Fields Setup Item Displays System Errors 5.3.2.9 Comments Information only. Displays errors that occurred during POST.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS BIOS Setup Utility Table 45. Setup Utility — Exit Screen Fields Setup Item Save Changes and Exit Help Text Exit the BIOS Setup utility after saving changes. The system reboots if required. The [F10] key can also be used. Comments User prompted for confirmation only if any of the setup fields were modified. Discard Changes and Exit Exit the BIOS Setup utility without saving changes. The [Esc] key can also be used.
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Connector/Header Locations and Pin-outs Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 6. Connector/Header Locations and Pin-outs 6.1 Board Connector Information The following section provides detailed information regarding all connectors, headers, and jumpers on the server boards. The following table lists all connector types available on the board and the corresponding preference designators printed on the silkscreen. Table 46.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Connector Quantity Connector/Header Locations and Pin-outs Reference Designators Connector Type Pin Count Configuration jumpers 4 J1E6 (CMOS Clear), J1E2 (ME Force Update), J1E4 (Password Clear), J1E5 Jumper (BIOS Recovery), J1H1 (BMC Force Update), 3 HDD Led J1E1 2 1 Header * Empty on Intel® Server Board S5500HCV. 6.2 Power Connectors The main power supply connection uses an SSI-compliant 2x12 pin connector (J1K3).
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Connector/Header Locations and Pin-outs Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Table 49. CPU 2 Power Connector Pin-out (J9K1) Pin 1 2 3 4 5 6 7 8 Signal GND of Pin 5 GND of Pin 6 GND of Pin 7 GND of Pin 8 +12 Vdc CPU2 +12 Vdc CPU2 +12 Vdc DDR3_CPU2 +12 Vdc DDR3_CPU2 Color Black Black Black Black Yellow/black Yellow/black Yellow/black Yellow/black Table 50. Power Supply Auxiliary Signal Connector Pin-out (J9K2) Pin 1 2 3 4 5 6.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Pin 27 29 31 33 6.3.2 Signal Name 3V3_AUX GND GND Pin 28 30 32 GND 34 Connector/Header Locations and Pin-outs Signal Name SPI_DO SPI_CLK SPI_DI RMM3_Present_N (pulled high on baseboard and shorted to ground on the plug-in module) LCP/IPMB Header Table 52. LCP/IPMB Header Pin-out (J1G6) Pin 1 2 3 4 6.3.
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Connector/Header Locations and Pin-outs Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Table 55.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 6.5.2 Connector/Header Locations and Pin-outs NIC Connectors The server boards provide two stacked RJ-45/2xUSB connectors side-by-side on the back edge of the board (J5A1, J6A1). The pin-out for NIC connectors is identical and defined in the following table. Table 57. RJ-45 10/100/1000 NIC Connector Pin-out (J5A1, J6A1) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 6.5.
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Connector/Header Locations and Pin-outs Pin 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 6.5.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 6.5.6 Connector/Header Locations and Pin-outs USB Connector The following table details the pin-out of the external USB connectors (J5A1, J6A1) found on the back edge of the server boards. Table 62.
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Connector/Header Locations and Pin-outs Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Table 65.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Connector/Header Locations and Pin-outs Table 67. SSI 4-pin Fan Header Pin-out (J7K1, J9A2, J9A3) Pin 1 2 3 4 Signal Name Ground 12V Fan Tach Fan PWM Type GND Power In Out Description Ground is the power supply ground Power supply 12 V FAN_TACH signal is connected to the BMC to monitor the fan speed FAN_PWM signal to control fan speed Table 68.
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Jumper Blocks 7. Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Jumper Blocks The server boards have several 3-pin jumper blocks that you can use to configure, protect, or recover specific features of the server boards. The following symbol identifies Pin 1 on each jumper block on the silkscreen: ▼ Figure 53. Jumper Blocks (J1E2, J1E4, J1E5, J1E6, J1H1) Table 69.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 7.1 Jumper Blocks CMOS Clear and Password Reset Usage Procedure The CMOS Clear (J1E6) and Password Reset (J1E4) recovery features are designed to achieve the desired operation with minimum system down time. The usage procedure for these two features has changed from previous generation Intel® server boards. The following procedure outlines the new usage model. 7.1.1 Clearing the CMOS 1. Power down the server and unplug the AC power cord. 2.
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Jumper Blocks 7.2 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Force BMC Update Procedure When performing a standard BMC firmware update procedure, the update utility places the BMC into an update mode, allowing the firmware to load safely onto the flash device. In the unlikely event the BMC firmware update process fails due to the BMC not being in the proper update state, the server boards provide a Force BMC Update jumper (J1H1) that forces the BMC into the proper update state.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Jumper Blocks 8. Power down the system and remove the AC power cord. 9. Open the server chassis. 10. Move the BIOS recovery jumper (J1E5) from the ―enabled‖ position (covering pins 2 and 3) to the ―disabled‖ position (covering pins 1 and 2). 11. Close the server chassis. 12. Reconnect the AC power cord and power up the server. Warning: DO NOT interrupt the BIOS POST during the first boot after the BIOS recovery. Revision 1.
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Intel®Light Guided Diagnostics 8. Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Intel®Light Guided Diagnostics Both server boards have several onboard diagnostic LEDs to assist in troubleshooting boardlevel issues. This section provides a description of the location and function of each LED on the server boards. 8.1 5-volt Stand-by LED Several server management features of these server boards require a 5-V stand-by voltage supplied from the power supply.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 8.2 Intel®Light Guided Diagnostics Fan Fault LED’s Fan fault LEDs are present for the two CPU fans and the one rear system fan. The fan fault LEDs illuminate when the corresponding fan has fault. Figure 55. Fan Fault LED’s Location Revision 1.
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Intel®Light Guided Diagnostics 8.3 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS System ID LED and System Status LED The server boards provide LEDs for both system ID and system status. These LEDs are located in the rear I/O area of the server board as shown in the following figure. A. B. System ID LED System Status LED Figure 56.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS  Intel®Light Guided Diagnostics By issuing the appropriate hex IPMI ―Chassis Identify‖ value, the ID LED will either blink blue for 15 seconds and turn off or will blink indefinitely until the appropriate hex IPMI Chassis Identify value is issue to turn it off. The bi-color (green/amber) System Status LED operates as follows: Table 70.
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Intel®Light Guided Diagnostics 8.4 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS DIMM Fault LEDs The server boards provide memory fault LED for each DIMM socket. These LEDs are located as shown in the following figure. The DIMM fault LED illuminates when the corresponding DIMM slot has memory installed and a memory error occurs. * D2, E2, and F2 DIMM slot and Fault LED’s are empty in Intel®Server Board S5500HCV Figure 57. DIMM Fault LED’s Location Revision 1.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 8.5 Intel®Light Guided Diagnostics Post Code Diagnostic LEDs Eight amber POST code diagnostic LEDs are located on the back edge of the server boards in the rear I/O area of the server boards by the serial A connector. During the system boot process, the BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number.
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Design and Environmental Specifications Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 9. Design and Environmental Specifications 9.1 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT Design Specifications Operation of the Intel® Server Boards S5520HC and/or S5500HCV at conditions beyond those shown in the following table may cause permanent damage to the system. Exposure to absolute maximum rating conditions for extended periods may affect system reliability. Table 71.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS   Design and Environmental Specifications Duty Cycle: 100% Quality Level: II Table 72. MTBF Estimate S5520HC MTBF (hours) 79,000 99,000 124,000 158,000 201,000 S5500HCV MTBF (hours) 89,000 111,000 140,000 178,000 227,000 Ambient Air Temperature (º C) Air Temp. at Board for 10(º C) rise (º C) 45 40 35 30 25 55 50 45 40 35 Revision 1.
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Design and Environmental Specifications 9.3 Intel®Server Board S5520HC and S5520HCS5500HCV TPS Server Board Power Requirements This section provides power supply design guidelines for a system using the Intel ® Server Boards S5520HC, S5500HCV and S5520HCT including voltage and current specifications, and power supply on/off sequencing characteristics. The following diagram shows the power distribution implemented on these server boards. Figure 59. Power Distribution Block Diagram Revision 1.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 9.3.1 Design and Environmental Specifications Processor Power Support The server boards support the Thermal Design Power (TDP) guideline for Intel® Xeon® processors. The Flexible Motherboard Guidelines (FMB) were also followed to determine the suggested thermal and current design values for anticipating future processor needs.
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Design and Environmental Specifications 9.4.3 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Remote Sense The power supply should have remote sense return (ReturnS) to regulate out ground drops for all output voltages: +3.3 V, +5 V, +12 V1, +12 V2, +12 V3, +12 V4, -12 V, and 5 VSB. The power supply should use remote sense to regulate out drops in the system for the +3.3 V, +5 V, and +12 V1 outputs.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Design and Environmental Specifications Table 76. Transient Load Requirements Output  Step Load Size 1 Load Slew Rate Test Capacitive Load +3.3 V 7.0 A 0.25A/sec 4700F +5 V 7.0 A 0.25A/sec 1000F +12 V 25 A 0.25A/sec 4700F +5 VSB 0.5 A 0.25A/sec 20F 1. Step loads on each 12 V output may happen simultaneously. 9.4.6 Capacitive Loading The power supply should be stable and meet all requirements within the following capacitive loading range.
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Design and Environmental Specifications Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Table 79. Output Voltage Timing Item Tvout_rise Tvout_rise Description Output voltage rise time from each main output. All main outputs must be within regulation of each other within this time. Tvout_rise All main outputs must leave regulation within this time. 1. The 5 VSB output voltage rise time is from 1.0 ms to 25 ms Minimum 5.0 1 N/A Maximum 70 1 50 Units ms ms N/A 400 ms Figure 60.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Design and Environmental Specifications Table 80. Turn On/Off Timing Item Tsb_on_delay Description Delay from AC being applied to 5 VSB being within regulation. Tac_on_delay Delay from AC being applied to all output voltages being within regulation. Tvout_holdup Time all output voltages stay within regulation after loss of AC.
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Design and Environmental Specifications 9.4.9 Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Residual Voltage Immunity in Stand-by Mode The power supply should be immune to any residual voltage placed on its outputs (typically, a leakage voltage through the system from stand-by output) up to 500 mV. There should be no additional heat generated or stressing of any internal components with this voltage applied to any individual output and all outputs simultaneously.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Regulatory and Certification Information 10. Regulatory and Certification Information To help ensure EMC compliance with your local regional rules and regulations, before computer integration, make sure that the chassis, power supply, and other modules have passed EMC testing using a server board with a microprocessor from the same family (or higher) and operating at the same (or higher) speed as the microprocessor used on this server board.
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Regulatory and Certification Information      BSMI CNS13438 Emissions (Taiwan) RRL Notice No. 1997-41 (EMC) & 1997-42 (EMI) (Korea) GOST R 29216-91 Emissions (Russia) – Listed on System License GOST R 50628-95 Immunity (Russia) – Listed on System License Belarus License (Belarus) – Listed on System License 10.1.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Identification Regulatory and Certification Information PB number for non-boxed boards (typically high-end boards) 10.3 Electromagnetic Compatibility Notices FCC (USA) This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
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Regulatory and Certification Information Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS ICES-003 (Canada) Cet appareil numérique respecte les limites bruits radioélectriques applicables aux appareils numériques de Classe A prescrites dans lanorme sur le matériel brouilleur: ―Apparelis Numériques‖, NMB-003 édictee par le Ministre Canadian des Communications.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Regulatory and Certification Information RRL KCC (Korea) 10.4 Product Ecology Change (EU RoHS) Intel has a system in place to restrict the use of banned substances in accordance with the European Directive 2002/95/EC. Compliance is based on declaration that materials banned in the RoHS Directive are either (1) below all applicable threshold limits or (2) an approved/pending RoHS exemption applies.
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Regulatory and Certification Information Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS CRoHS Substance Tables: China CRoHS requires products to be provided with controlled substance information. Intel understands the end-seller (entity placing product into market place) is responsible for providing the controlled substance information. Controlled substance information is required to be in Simplified Chinese. Substance table for this board product is as follows: Revision 1.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Revision 1.
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Regulatory and Certification Information Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS 10.6 China Packaging Recycle Marks (or GB18455-2001) Intel EPSD has the following ecological compliances: Cardboard and fiberboard packaging will be marked as recyclable in China. China Packaging Recycling Marks is required on retail packaging to be marked as recyclable using China‘s recycling logo.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Appendix A: Integration and Usage Tips Appendix A: Integration and Usage Tips  Prior to adding or removing components or peripherals from the server board, you must remove the AC power cord. With AC power plugged into the server board, 5-V standby is still present even though the server board is powered off.  This server board supports Intel® Xeon® Processor 5500 Series only.
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Appendix A: Integration and Usage Tips - - Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Step 2: Decide the PCI device with location number (Bus number, Device number, and Function number) using PCI map dump from the system generating the PCI device SEL event, There are multiple means to dump the PCI map.
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Intel®Server Boards S5520HC, S5500HCV and S5520HCT TPS Appendix B: Compatible Intel®Server Chassis Appendix B: Compatible Intel® Server Chassis Refer to the following table for the compatible Intel® Server Chassis of Intel® Server Boards S5520HC, S5500HCV and S5520HCT: Passive tower processor heatsink(s) (product code: FXXRGTHSINK) is required when installing the Intel® Server Board S5520HC or S5500HCV in the Intel® Server Chassis SC5600LX.
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Appendix B: Compatible Intel®Server Chassis S5520HC S5500HCV Chassis SKU Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Heatsink Includes Intel®Thermal Solution STS100C (w/ fan, Active mode) Intel®Thermal Solution STS100A (Active) (Passive Tower Heatsink) BXSTS100C BXSTS100A FXXRGTHSINK FXXRGTHSINK Chassis Boxed Product Code Note: Must install active processor heatsink with the airflow direction as shown in the following figure when installing in a compatible Intel® Server Chassis.
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Intel®Server Boards S5520HC, S5500HCV and S5520HCT TPS Appendix B: Compatible Intel®Server Chassis Figure 62. Active Processor Heatsink Installation Requirement Revision 1.
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Appendix C: BMC Sensor Tables Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Appendix C: BMC Sensor Tables This appendix lists the sensor identification numbers and information about the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 2.0 for sensor and event/reading-type table information.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS  Appendix C: BMC Sensor Tables Rearm Sensors The rearm is a request for the event status of a sensor to be rechecked and updated upon a transition between good and bad states. You can rearm the sensors manually or automatically. This column indicates the type supported by the sensor.
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Appendix C: BMC Sensor Tables Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Table 82.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Appendix C: BMC Sensor Tables Readable Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Sensor Type Event/Reading Type Event Offset Triggers 06 – Redundant: degraded from fully redundant state. Degraded 07 – Redundant: Transition from non-redundant state.
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Appendix C: BMC Sensor Tables Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Readable Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Sensor Type Event/Reading Type Event Offset Triggers Contrib. To System Status Assert/De -assert Event Value/Offs ets Data Rearm Standby BB +1.1V IOH (BB +1.1V IOH) 10h All Voltage 02h Threshold 01h [u,l] [c,nc] nc = Degraded c = Non-fatal As and De Analog R, T A – BB +1.1V P1 Vccp (BB +1.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Appendix C: BMC Sensor Tables Readable Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Sensor Type Event/Reading Type Event Offset Triggers Contrib. To System Status Assert/De -assert Event Value/Offs ets Rearm Data Standby BB +5.0V STBY (BB +5.0V STBY) 1Ah All Voltage 02h Threshold 01h [u,l] [c,nc] nc = Degraded c = Non-fatal As and De Analog R, T A X BB +12.0V (BB +12.
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Appendix C: BMC Sensor Tables Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Readable Full Sensor Name (Sensor name in SDR) Fan Present Sensors (Fan x Present) Fan Redundancy 1 (Fan Redundancy) Sensor # 40h–45h 46h Platform Applicability Chassisspecific Chassisspecific Sensor Type Fan 04h Fan 04h Event/Reading Type Generic 08h Generic 0Bh Event Offset Triggers Event Contrib.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Appendix C: BMC Sensor Tables Readable Full Sensor Name (Sensor name in SDR) Power Supply 1 Status (PS1 Status) Power Supply 2 Status (PS2 Status) Sensor # 50h 51h Platform Applicability Chassisspecific Chassisspecific Sensor Type Power Supply 08h Power Supply 08h Event/Reading Type Sensor Specific 6Fh Sensor Specific 6Fh Event Offset Triggers Contrib.
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Appendix C: BMC Sensor Tables Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Readable Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Sensor Type Event/Reading Type Event Offset Triggers Contrib.
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Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Appendix C: BMC Sensor Tables Readable Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Sensor Type Event/Reading Type Event Offset Triggers Contrib.
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Appendix D: Platform Specific BMC Appendix Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Appendix D: Platform Specific BMC Appendix Table 83.
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Intel®Server Boards S5520HC, S5500HCV and S5520HCT TPS Appendix E: POST Code Diagnostic LED Decoder Appendix E: POST Code Diagnostic LED Decoder During the system boot process, the BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the POST code to the POST Code Diagnostic LEDs on the back edge of the server board.
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Appendix E: POST Code Diagnostic LED Decoder  Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Upper nibble bits = 1110b = Eh; Lower nibble bits = 1101b = Dh; the two are concatenated as EDh. Find the meaning of POST Code EDh in below table – Memory Population Error: RDIMMs and UDIMMs cannot be mixed in the system. Table 85.
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Intel®Server Boards S5520HC, S5500HCV and S5520HCT TPS Progress Code Appendix E: POST Code Diagnostic LED Decoder Progress Code Definition USB 0x58 Resetting USB bus 0x59 Reserved for USB devices ATA/ATAPI/SATA 0x5A Resetting SATA bus and all devices 0x5B Reserved for ATA SMBUS 0x5C Resetting SMBUS 0x5D Reserved for SMBUS Local Console 0x70 Resetting the video controller (VGA) 0x71 Disabling the video controller (VGA) 0x72 Enabling the video controller (VGA) Remote Console 0x78 Resett
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Appendix E: POST Code Diagnostic LED Decoder Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Progress Code 0xB8 Progress Code Definition Resetting the removable media device 0xB9 Disabling the removable media device 0xBA Detecting the presence of a removable media device (CDROM detection, etc.
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Intel®Server Boards S5520HC, S5500HCV and S5520HCT TPS Appendix F: POST Error Messages and Handling Appendix F: POST Error Messages and Handling Whenever possible, the BIOS outputs the current boot progress codes on the video screen. Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. The class and subclass fields point to the type of hardware being initialized. The operation field represents the specific initialization activity.
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Appendix F: POST Error Messages and Handling Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Table 86. POST Error Messages and Handling Error Code 0012 0048 Error Message CMOS date/time not set Password check failed Response Pause Pause 0108 0109 No Pause No Pause 0140 0141 0146 0192 0193 0194 0195 0196 0197 0198 019F 5220 5221 5224 8160 8161 8180 Keyboard component encountered a locked error. Keyboard component encountered a stuck key error.
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Intel®Server Boards S5520HC, S5500HCV and S5520HCT TPS Appendix F: POST Error Messages and Handling Error Code 8542 8543 8544 8545 Error Message DIMM_B1 Disabled. DIMM_B2 Disabled. DIMM_C1 Disabled. DIMM_C2 Disabled. Response Pause Pause Pause Pause 8546 8547 8548 8549 854A 854B 8560 8561 8562 8563 8564 8565 8566 8567 8568 8569 856A 856B 85A0 85A1 85A2 DIMM_D1 Disabled. DIMM_D2 Disabled. DIMM_E1 Disabled. DIMM_E2 Disabled. DIMM_F1 Disabled. DIMM_F2 Disabled.
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Appendix F: POST Error Messages and Handling Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Error Code 92A3 92A9 92C6 92C7 Error Message Serial port component was not detected Serial port component encountered a resource conflict error Serial Port controller error Serial Port component encountered an input error.
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Intel®Server Boards S5520HC, S5500HCV and S5520HCT TPS Appendix F: POST Error Messages and Handling POST Error Beep Codes The following table lists the POST error beep codes. Prior to system video initialization, the BIOS uses these beep codes to inform users of error conditions. The beep code is followed by a user-visible code on the POST Progress LED‘s. Table 87.
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Appendix G: Installation Guidelines Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Appendix G: Installation Guidelines 1.
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Intel®Server Boards S5520HC, S5500HCV and S5520HCT TPS Appendix G: Installation Guidelines 5. When EFI Shell is selected as the first device on the BIOS boot option list, some RAID adapters may not enter their configuration screen before the server board boots into EFI Shell.
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Glossary Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Glossary ACPI Term Definition Advanced Configuration and Power Interface AHCI AMT AP APIC ARP ASIC ATS BBS BEV BIOS BIST Advanced Host Controller Interface Active Management Technology Application Processor Advanced Programmable Interrupt Control Address Resolution Protocol Application Specific Integrated Circuit Address Translation Technology BIOS Boot Specification Boot Entry Vector Basic Input/Output System Built-in Self Test BMC bpp
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Intel®Server Boards S5520HC, S5500HCV and S5520HCT TPS Term Glossary Definition GPA GPIO HPA HSC Guest Physical Address General Purpose I/O Host Physical Address Hot-Swap Controller HT Hz I2C IA ICH ILM IMC INTR IOH IPMB IPMI IRQ ITE JBOD JRE KB KVM LAN LCD LDAP LED Hyper-Threading Hertz (1 cycle/second) Inter-Integrated Circuit Bus Intel® Architecture I/O Controller Hub Independent Loading Mechanism Integrated Memory Controller Interrupt I/O HUB Intelligent Platform Management Bus Intelligent Platfo
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Glossary Intel®Server Boards S5520HC, S5500HCV, and S5520HCT TPS Term Definition PCB PCI PECI PEF Print Circuit Board Peripheral Component Interconnect Platform Environment Control Interface Platform Event Filtering PEP PMBus PMI POST PWM QPI RAID RAS RASUM RDIMM RISC RMII ROM RTC SAS SATA SDR SEEPROM SEL SES SGPIO Platform Event Paging Power Management Bus Platform Management Interrupt Power-on Self Test Pulse-Width Modulation QuickPath Interconnect Redundant Array of Independent Disks Reliability,
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Intel®Server Boards S5520HC, S5500HCV and S5520HCT TPS Term Glossary Definition VID VLSI VRD VT Voltage Identification Very-large-scale integration Voltage Regulator Down Virtualization Technology VT-d Word WS-MAN XD bit Virtualization Technology for Directed I/O 16-bit quantity Web Service for Management Execute Disable Bit Revision 1.
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Reference Documents Intel®Server Board S5520HC / S5500HCV TPS Reference Documents See the following documents for additional information: Intel® Server Boards S5520HC and S5500HCV Specification Update Revision 1.