Technical Product Specification

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Server System SC5650HCBRP

Intel order number E81443-002

Revision 1.2

April, 2010

Enterprise Platforms and Services Division

Summary of content (232 pages)

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Intel® Server System SC5650HCBRP Technical Product Specification Intel order number E81443-002 Revision 1.
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Revision History Intel® Server System SC5650HCBRP TPS Revision History Date September 2009 Revision Number 1.0 Modifications Initial Release March 2010 1.1 - Updated Section 3.3 April 2010 1.2 - Removed CCC related notice - Updated Section 2.1 and 3.2 to add Intel® Xeon® Processor 5600 series support ii Revision 1.
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Intel® Server System SC5650HCBRP TPS Disclaimers Disclaimers Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
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Table of Contents Intel® Server System SC5650HCBRP TPS Table of Contents 1. 2. Introduction .......................................................................................................................... 1 1.1 Chapter Outline ........................................................................................................ 1 1.2 Server System Use Disclaimer ................................................................................ 1 Overview ...................................
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Intel® Server System SC5650HCBRP TPS 3.3.3 Processor Cores, QPI Links and DDR3 Channels Frequency Configuration ........ 32 3.3.4 Publishing System Memory ................................................................................... 35 3.3.5 Memory Interleaving .............................................................................................. 36 3.3.6 Memory Test .......................................................................................................... 36 3.3.
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Table of Contents 4.1.5 Control and Indicator Functions ............................................................................. 71 4.1.6 PMBus Monitoring Interface .................................................................................. 74 4.2 5. Mechanical Overview ............................................................................................. 77 4.2.2 DC Output Specification ........................................................................................
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Intel® Server System SC5650HCBRP TPS 6.4 6.4.1 7. 8. Intel® Intelligent Power Node Manager ................................................................ 110 Manageability Engine (ME) .................................................................................. 110 BIOS Setup Utility ............................................................................................................. 112 7.1 Logo / Diagnostic Screen.........................................................................
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Table of Contents Intel® Server System SC5650HCBRP TPS 10.4 DIMM Fault LEDs ................................................................................................ 171 10.5 Post Code Diagnostic LEDs ................................................................................ 172 11. Design and Environmental Specifications ..................................................................... 173 11.1 Intel® Server System SC5650HCBRP Design Specifications ..............................
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Intel® Server System SC5650HCBRP TPS List of Figures List of Figures Figure 1. Front View Components (with Front Bezel Assembly) .................................................. 5 Figure 2. Front View Components (with Drive Access Door Open) .............................................. 6 Figure 3. Internal Components ..................................................................................................... 7 Figure 4. Back Panel Components ...................................................
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List of Figures Intel® Server System SC5650HCBRP TPS Figure 32. 6-HDD Expander SAS HSBP Board Layout ............................................................ 100 Figure 33. SMBUS Block Diagram ............................................................................................ 111 Figure 34. Setup Utility — Main Screen Display ....................................................................... 116 Figure 35. Setup Utility — Advanced Screen Display ..........................................
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Intel® Server System SC5650HCBRP TPS Revision 1.
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List of Tables Intel® Server System SC5650HCBRP TPS List of Tables Table 1. IOH High-Level Summary ............................................................................................. 23 Table 2. Mixed Processor Configurations ................................................................................... 26 Table 3. Memory Running Frequency vs. Processor SKU.......................................................... 33 Table 4. Memory Running Frequency vs. Memory Population ..................
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Intel® Server System SC5650HCBRP TPS List of Tables Table 33. PWOK Signal Characteristics ..................................................................................... 73 Table 34. LED Indicators ............................................................................................................ 74 Table 35. Environmental Requirements ...................................................................................... 79 Table 36. Cable Lengths ...........................................
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List of Tables Intel® Server System SC5650HCBRP TPS Table 68. BIOS Setup: Keyboard Command Bar...................................................................... 114 Table 69. Setup Utility — Main Screen Fields .......................................................................... 116 Table 70. Setup Utility — Advanced Screen Display Fields ..................................................... 118 Table 71. Setup Utility — Processor Configuration Screen Fields ......................................
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Intel® Server System SC5650HCBRP TPS List of Tables Table 103. Front Panel SSI Standard 24-pin Connector Pin-out (J1B3) .................................. 155 Table 104. VGA Connector Pin-out (J7A1) ............................................................................... 156 Table 105. RJ-45 10/100/1000 NIC Connector Pin-out (J5A1, J6A1) ...................................... 156 Table 106. SATA / SAS Connector Pin-out (J1E3, J1G1, J1G4, J1G5, J1F1, J1F4) ............... 157 Table 107.
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List of Tables Intel® Server System SC5650HCBRP TPS xvi Revision 1.
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Intel® Server System SC5650HCBRP TPS 1. Introduction Introduction This Technical Product Specification (TPS) provides board-specific information detailing the features, functionality, and high-level architecture of the Intel® Server System SC5650HCBRP. In addition, you can obtain design-level information for a given subsystem by ordering the External Product Specifications (EPS) for the specific subsystem.
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Introduction Intel® Server System SC5650HCBRP TPS cannot be held responsible if components fail or the server board does not operate correctly when used outside any of the published operating or non-operating limits. 2 Intel order number E81443-002 Revision 1.
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Intel® Server System SC5650HCBRP TPS 2. Overview Overview The Intel® Server System SC5650HCBRP has monolithic printed circuit board (PCB) with features designed to support the pedestal server markets. 2.1 Intel® Server System SC5650HCBRP Feature Set Feature Processors Description • Support for one or two Intel® Xeon® Processor(s) 5500 series up to 95W Thermal Design Power • Support for one or two Intel® Xeon® Processor(s) 5600 series up to 130W Thermal Design Power • 4.8 GT/s, 5.86 GT/s, and 6.
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Overview Feature I/O control support Intel® Server System SC5650HCBRP TPS Description • External connections: DB9 serial port A connection One DH 10 serial port connector (optional) Two RJ-45 NIC connectors for 10/100/1000 Mb connections: Dual GbE through the ® Intel 82575EB Network Connection. Four USB 2.0 ports at the back of the board • Internal connections: Two 9-pin USB headers, each supports two USB 2.0 ports One DH10 serial port B header Six SATA connectors at 1.
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Intel® Server System SC5650HCBRP TPS 2.1.1 2.1.1.1 Overview Intel® Server System SC5650HCBRP Layout Front View Components A B C D E F 5.25-inch Device Drive Bays Front Control Panel 3.5-inch Drive Bay Access Door Drive Bay Access Door Door Lock Front Panel USB Ports Figure 1. Front View Components (with Front Bezel Assembly) Revision 1.
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Overview Intel® Server System SC5650HCBRP TPS Hot-swap Disk Drive Bay A Figure 2. Front View Components (with Drive Access Door Open) 2.1.1.2 6 Internal Components Intel order number E81443-002 Revision 1.
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Intel® Server System SC5650HCBRP TPS A B C D E F G H I J Overview Tool-less Device Bay Locks 5.25-inch Device Bays 3.5-inch Device Bay Drive Cage Retention Mechanism PCI Add-in Card Guide / System Fan Assembly Server Board Front Panel USB Ports Rear Tool-less PCI Retention Mechanisms Fan Duct / System Fan Assembly Power Supply Figure 3. Internal Components 2.1.1.
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Overview 2.1.1.
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Intel® Server System SC5650HCBRP TPS 2.1.2 Overview Mechanical Locks ® The Intel Server System SC5650HCBRP chassis support the installation of a padlock loop (see letter “A” in the following figure) at the rear of the chassis. Additionally, the system ships with a two-position mechanical lock (see letter “B”) on the front bezel assembly to prevent access to the hard drives and the interior of the system. Figure 6. Mechanical Locks 2.1.
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Overview Callout A B C D E F G H I 10 Intel® Server System SC5650HCBRP TPS Description Slot 1, 32-bit/33 MHz PCI, Keying for 5V and Universal ® Intel RMM3 Slot Slot 2, PCI Express* x4 (x8 Mechanically) Low-profile USB Solid State Drive Header Slot 3, PCI Express* Gen2 x8 Slot 4, PCI Express* Gen2 x8 Slot 5, PCI Express* Gen2 x8 Slot 6, PCI Express* Gen2 x8 (x16 Mechanically) Battery Callout Description W System Fan 2 Header (6-pin) X Y Z AA BB CC DD EE System Fan 1 Header (6-pin) Main Power Connec
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Intel® Server System SC5650HCBRP TPS Callout J K L M N O P Description Back Panel I/O Ports Diagnostic and Identify LED’s System Fan 5 Header (4-pin) Power Connector for Processor 1 and Memory attached to Processor 1 Processor 1 Fan Header (4-pin) DIMM Sockets of Memory Channel A, B, and C Power Connector for Processor 2 and Memory attached to Processor 2 Overview Callout FF GG HH II Description SATA Port 2 HSBP_A SATA Port 3 SATA Software RAID 5 Key Header JJ KK Chassis Intrusion Header SATA Port 4 L
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Overview Intel® Server System SC5650HCBRP TPS Figure 8. Mounting Hole Locations 12 Intel order number E81443-002 Revision 1.
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Intel® Server System SC5650HCBRP TPS Overview Figure 9. Major Connector Pin-1 Locations (1 of 2) Revision 1.
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Overview Intel® Server System SC5650HCBRP TPS Figure 10. Major Connector Pin-1 Locations (2 of 2) 14 Intel order number E81443-002 Revision 1.
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Intel® Server System SC5650HCBRP TPS Overview Figure 11. Primary Side Keep-out Zone (1 of 2) Revision 1.
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Overview Intel® Server System SC5650HCBRP TPS Figure 12. Primary Side Keep-out Zone (2 of 2) 16 Intel order number E81443-002 Revision 1.
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Intel® Server System SC5650HCBRP TPS Overview Figure 13. Primary Side Air Duct Keep-out Zone Revision 1.
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Overview Intel® Server System SC5650HCBRP TPS Figure 14. Primary Side Card-Side Keep-out Zone 18 Intel order number E81443-002 Revision 1.
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Intel® Server System SC5650HCBRP TPS Overview Figure 15. Second Side Keep-out Zone Revision 1.
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Overview 2.1.7 Intel® Server System SC5650HCBRP TPS Rear I/O Layout The following drawing shows the layout of the rear I/O components for the Intel® Server System SC5650HCBRP. Callout A Description System Status LED Callout E B ID LED F C Diagnostics LED’s G D Serial Port A Description Video NIC Port 1 (1 Gb, Default Management Port) USB Port 2 (top), 3 (bottom) NIC Port 2 (1 Gb) USB Port 0 (top), 1 (bottom) Figure 16. Rear I/O Layout 20 Intel order number E81443-002 Revision 1.
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Intel® Server System SC5650HCBRP TPS 3. Functional Architecture Functional Architecture The architecture and design of the Intel® Server System SC5650HCBRP is based on the Intel® 5520 and ICH10R chipset. The chipset is designed for systems based on the Intel® Xeon® Processor 5500 Series and Intel® Xeon® Processor 5600 Series in an FC-LGA 1366 Socket B package with Intel® QuickPath Interconnect (Intel® QPI) speed at 6.40 GT/s, 5.86 GT/s, and 4.80 GT/s.
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Functional Architecture Intel® Server System SC5650HCBRP TPS Figure 17. Intel® Server System SC5650HCBRP Functional Block Diagram 22 Intel order number E81443-002 Revision 1.
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Intel® Server System SC5650HCBRP TPS 3.
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Functional Architecture 3.1.3 Intel® Server System SC5650HCBRP TPS Enterprise South Bridge Interface (ESI) One x4 ESI link interface supporting PCI Express Gen1 (2.5 Gbps) transfer rate for connecting Intel® ICH10R in the server board of Intel® Server System SC5650HCBRP. 3.1.4 Manageability Engine (ME) An embedded ARC controller is within the IOH providing the Intel® Server Platform Services (SPS). The controller is also commonly referred to as the Manageability Engine (ME). 3.1.
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Intel® Server System SC5650HCBRP TPS 3.2 Functional Architecture Processor Support The Intel® Server Boards S5520HC, S5500HCV and S5520HCT support the following processors: z One or two Intel® Xeon® Processor 5500 Series with a 4.8 GT/s, 5.86 GT/s, or 6.4 GT/s Intel® QPI link interface and Thermal Design Power (TDP) up to 95 W. z One or two Intel® Xeon® Processor 5600 Series with a 6.4 GT/s Intel® QPI link interface and Thermal Design Power (TDP) up to 130 W.
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Functional Architecture Intel® Server System SC5650HCBRP TPS Table 2. Mixed Processor Configurations Error Processor family not identical Processor stepping mismatch Severity Halt Pause System Action The BIOS detects the error condition and responds as follows: – Logs the error into the system event log (SEL). – Alerts the Integrated BMC about the configuration error. – Does not disable the processor. – Displays “0194: Processor 0x family mismatch detected” message in the Error Manager.
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Intel® Server System SC5650HCBRP TPS Error Severity Processor microcode missing 3.2.3 Functional Architecture Minor System Action The BIOS detects the error condition and responds as follows: – Logs the error into the SEL. – Does not disable the processor. – Displays “8180: Processor 0x microcode update not found” message in the Error Manager or on the screen. – The system continues to boot in a degraded state, regardless of the setting of POST Error Pause in Setup.
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Functional Architecture 3.2.7 Intel® Server System SC5650HCBRP TPS Core Multi-Processing The BIOS setup provides the ability to selectively enable one or more cores. The default behavior is to enable all cores. You can do this through the BIOS setup option for active core count. The BIOS creates entries in the Multi-Processor Specification, Version 1.4 tables to describe multi-core processors. 3.2.
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Intel® Server System SC5650HCBRP TPS Functional Architecture Figure 18. Unified Retention System and Unified Back Plate Assembly Revision 1.
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Functional Architecture 3.3 Intel® Server System SC5650HCBRP TPS Memory Subsystem The Intel® Xeon® Processor 5500 Series and Intel® Xeon® Processor 5600 Series on the Intel® Server System SC5650HCBRP are populated on CPU sockets. Each processor installed on the CPU socket has an integrated memory controller (IMC), which supports up to three DDR3 channels and groups DIMMs on the server boards into autonomous memory. 3.3.
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Intel® Server System SC5650HCBRP TPS Server Board Functional Architecture CPU Socket CPU 1 Intel® Server System SC5650HCBRP CPU 2 DIMM Identifier A1 (Blue) A2 (Black) B1 (Blue) B2 (Black) C1 (Blue) C2 (Black) D1 (Blue) D2 (Black) E1 (Blue) E2 (Black) F1 (Blue) F2 (Black) Channel / Slot Channel A, Slot 0 Channel A, Slot 1 Channel B, Slot 0 Channel B, Slot 1 Channel C, Slot 0 Channel C, Slot 1 Channel D, Slot 0 Channel D, Slot 1 Channel E, Slot 0 Channel E, Slot 1 Channel F, Slot 0 Channel F, Slot 1
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Functional Architecture Intel® Server System SC5650HCBRP TPS Support Registered DDR3 DIMMs (RDIMMs), and ECC Unbuffered DDR3 DIMMs (UDIMMs). Mixing of RDIMMs and UDIMMs is not supported.
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Intel® Server System SC5650HCBRP TPS Functional Architecture Table 3. Memory Running Frequency vs. Processor SKU DIMM Type 800 Processor Integrated Memory Controller (IMC) Max. Frequency (Hz) DDR3 800 DDR3 1066 DDR3 1333 800 800 800 1066 800 1066 1066 1333 800 1066 1333 Memory Running Frequency (Hz) = Fastest Common Frequency of Processor IMC and Memory Table 4. Memory Running Frequency vs.
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Functional Architecture Intel® Server System SC5650HCBRP TPS 1N: One clock cycle for the DRAM commands arrive at the DIMMs to execute. 2N: Two clock cycles for the DRAM commands arrive at the DIMMs to execute. 34 Intel order number E81443-002 Revision 1.
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Intel® Server System SC5650HCBRP TPS 3.3.4 Functional Architecture Publishing System Memory z z z z 3.3.4.1 The BIOS displays the “Total Memory” of the system during POST if the “Quiet Boot” is disabled in the BIOS Setup. This is the total size of memory discovered by the BIOS during POST, and is the sum of the individual sizes of installed DDR3 DIMMs in the system. The BIOS also provides the total memory of the system in the BIOS setup (Main page and Advanced | Memory Configuration Page).
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Functional Architecture 3.3.5 Intel® Server System SC5650HCBRP TPS Memory Interleaving ® The Intel Xeon® Processor 5500 Series and Intel® Xeon® Processor 5600 Series support the following memory interleaving mode: Bank Interleaving – Interleave cache-line data between participant ranks. Channel Interleaving – Interleave between channel when not in Mirrored Channel Mode.
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Intel® Server System SC5650HCBRP TPS Functional Architecture Channel RAS feature are supported only if both CPU sockets are populated and support the right population. For more information, refer to section 3.3.9, Memory Population and Upgrade Rules. 3.3.8.2 Independent Channel Mode In the Independent Channel mode, you can populate multiple channels on any channel in any order. The Independent Channel mode provides less RAS capability but better DIMM isolation in case of errors.
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Functional Architecture Intel® Server System SC5650HCBRP TPS Current RAS mode of operation Existing DDR3 DIMM population DDR3 DIMM characteristics Optimization techniques used by the Intel® Xeon® Processor 5500 Series to maximize memory bandwidth In the Independent Channel mode, all the DDR3 channels operate independently. Also, you can use the Independent Channel mode to support single DIMM configuration in Channel A and in the Single Channel mode.
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Intel® Server System SC5650HCBRP TPS Functional Architecture timing, technology and size, CPU 2 memory channels D, E, and F can have a different match of the parameters, channel RAS still functions. 13. The Minimal memory population possible is DIMM_A1. In this configuration, the system operates in the Independent Channel Mode. Mirrored Channel Mode is not possible. 14. The minimal population upgrade recommended for enabling CPU 2 socket are DIMM_A1 and DIMM_D1.
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Functional Architecture Intel® Server System SC5650HCBRP TPS M – Indicates whether the configuration supports the Mirrored Channel mode of operation. It is one of the following: Y indicating Yes; N indicating No. N – Identifies the total number of DIMMs that constitute the given configuration. Table 5.
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Intel® Server System SC5650HCBRP TPS 3.3.11 Functional Architecture Memory Error Handling The BIOS classifies memory errors into the following categories: Correctable ECC errors: This correction could be the result of an ECC correction, a successfully retried memory cycle, or both. Unrecoverable/Fatal ECC Errors: The ECC engine detects these errors but cannot correct them.
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Functional Architecture 3.4 Intel® Server System SC5650HCBRP TPS ICH10R The ICH10R provides extensive I/O support. Functions and capabilities include: PCI Express* Base Specification, Revision 1.1, support PCI Local Bus Specification, Revision 2.3, support for 33-MHz PCI operations (supports up to four REQ#/GNT# pairs) ACPI Power Management Logic Support, Revision 3.
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Intel® Server System SC5650HCBRP TPS Functional Architecture • • Intel® Embedded Server RAID Technology II Option ROM Intel® Embedded Server RAID Technology II drivers, most recent revision • At least two SATA hard disk drives 3.4.1.1.
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Functional Architecture 3.4.2 Intel® Server System SC5650HCBRP TPS USB 2.0 Support The USB controller functionality integrated into the ICH10R provides the server boards with an interface for up to ten USB 2.0 ports. All ports are high-speed, full-speed, and low-speed capable. • • Four external connectors are located on the back edge of the server boards. One internal 2x5 header (J1D1) is provided, capable of supporting two optional USB 2.0 ports.
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Intel® Server System SC5650HCBRP TPS 3.5 Functional Architecture PCI Subsystem The primary I/O buses for the server board of Intel® Server System SC5650HCBRP are PCI, PCI Express* Gen1, and PCI Express* Gen2 with six independent PCI bus segments. PCI Express* Gen1 and Gen2 are dual-simplex point-to-point serial differential low-voltage interconnects. A PCI Express* topology can contain a Host Bridge and several endpoints (I/O devices). The signaling bit rate is 2.
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Functional Architecture 3.6 Intel® Server System SC5650HCBRP TPS Intel® SAS Entry RAID Module AXX4SASMOD (Optional Accessory) The Intel® Server System SC5650HCBRP provides a Serial Attached SCSI (SAS) module slot (J2J1) for the installation of an optional Intel® SAS Entry RAID Module AXX4SASMOD. Once the optional Intel® SAS Entry RAID Module AXX4SASMOD is detected, the x4 PCI Express* links from the ICH10R to Slot 2 (x8 mechanically, x4 electrically) switches to the SAS module slot.
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Intel® Server System SC5650HCBRP TPS Functional Architecture Figure 21. Intel® SAS Entry RAID Module AXX4SASMOD Functional Block Diagram 3.6.1 SAS RAID Support The BIOS Setup Utility provides drive configuration options on the Advanced | Mass Storage Controller Configuration setup page for the Intel® SAS Entry RAID Module AXX4SASMOD, some of which affect the ability to configure RAID.
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Functional Architecture Intel® Server System SC5650HCBRP TPS Table 9. Intel® SAS Entry RAID Module AXX4SASMOD Storage Mode SW RAID = Intel® Embedded Server RAID Technology II (ESRTII) IT/IR RAID = IT/IR RAID, Entry Hardware RAID Storage Mode* RAID Types and Levels Supported Description Driver RAID Management Software RAID Software User’s Guide Compatible Backplane Native SAS pass through mode without RAID function.
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Intel® Server System SC5650HCBRP TPS 3.7 Functional Architecture Baseboard Management Controller The Intel® Server System SC5650HCBRP has an integrated BMC controller based on ServerEngines* Pilot II. The BMC controller is provided by an embedded ARM9 controller and associated peripheral functionality that is required for IPMI-based server management.
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Functional Architecture Intel® Server System SC5650HCBRP TPS Figure 22. Integrated BMC Hardware 3.7.1 BMC Embedded LAN Channel The BMC hardware includes two dedicated 10/100 network interfaces. Interface 1: This interface is available from either of the available NIC ports in system that can be shared with the host. Only one NIC may be enabled for management traffic at any time. The default active interface is onboard NIC1.
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Intel® Server System SC5650HCBRP TPS 3.8 Functional Architecture Serial Ports The Intel® Server System SC5650HCBRP provides two serial ports: an external DB9 serial port and an internal DH-10 serial header. The rear DB9 serial A port is a fully-functional serial port that can support any standard serial device. Serial B is an optional port accessible through a 9-pin internal DH-10 header. You can use a standard DH-10 to DB9 cable to direct serial B to the rear of a chassis.
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Functional Architecture 3.11.1 Intel® Server System SC5650HCBRP TPS Video Modes The integrated video controller supports all standard IBM* VGA modes. The following table shows the 2D modes supported for both CRT and LCD. Table 11. Video Modes 2D Video Mode Support 2D Mode 8 bpp Supported 640 x 480 800 x 600 1024 x 768 1152 x 864 1280 x 1024 1440 x 900 1600 x 1200 3.11.
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Intel® Server System SC5650HCBRP TPS Functional Architecture 3.12 Network Interface Controller (NIC) The Intel® Server System SC5650HCBRP provides dual onboard LAN ports with support for 10/100/1000 Mbps operation. The two LAN ports are based on the onboard Intel® 82575EB controller, which is a single, compact component with two, fully-integrated GbE Media Access Control (MAC) and Physical Layer (PHY) ports. The Intel® 82575EB controller provides a standard IEEE 802.
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Functional Architecture Intel® Server System SC5650HCBRP TPS 3.13 ACPI Support The Intel® Server System SC5650HCBRP supports S0, S1, and S5 states. S1 is considered a sleep state. The Intel® Server System SC5650HCBRP can wake up from S1 state using the USB devices in addition to the sources described in the following paragraph.
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Intel® Server System SC5650HCBRP TPS 4. Power Sub-system 4.1 600-W 1+1 Power Supply Module Power Sub-system The 600-W power supply module specification defines a 1+1 power supply module that supports pedestal server systems. It defines a 600-W power supply with 2 outputs: +12Vdc and +5Vsb. A separate cage (including power distribution board) is designed to plug directly to the output connector of the PS module and provide additional power converters to produce other required voltages.
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Power Sub-system 4.1.1.1 Intel® Server System SC5650HCBRP TPS Handle and Retention Mechanism The power supply has a handle to provide a place to grip the power supply for removal and insertion. The power supply has a simple retention mechanism to retain the power supply once it is inserted. This mechanism withstands the specified mechanical shock and vibration requirements. The tab on the retention mechanism is green to indicate it is a hot-swap touch point.
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Intel® Server System SC5650HCBRP TPS Power Sub-system Table 13. Acoustic Requirements Operating Conditions Maximum (1+0 & 1+1) Inlet Temperature Condition 45ºC % of Single module Maximum Loading Condition 100% < 6.5 Operating (1+0 & 1+1) 40°C 60% < 5.2 Idle (1+0 & 1+1) 35°C 40% < 4.0 4.1.1.3 LwAd (BA) Temperature Requirements The power supply operates within all specified limits over the Top temperature range described in the following table.
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Power Sub-system 4.1.2.2 Intel® Server System SC5650HCBRP TPS Efficiency The following table provides the required minimum efficiency level at four loading conditions: 100%, 50%, 20% and 10%. Efficiency is tested at the AC input voltage 230VAC. Table 15. Efficiency Loading 100% of Maximum 50% of Maximum 20% of Maximum 10% of Maximum Efficiency 85% 89% 85% 75% Power Factor > 0.9 > 0.9 > 0.85 > 0.75 4.1.2.
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Intel® Server System SC5650HCBRP TPS Power Sub-system Table 17. AC Line Sag Transient Performance Duration Sag Continuous 10% 0 to 1 AC cycle 100% > 1 AC cycle >10% Operating AC Voltage Nominal AC Voltage ranges Line Frequency Loading 50/60 Hz 100% Nominal AC Voltage ranges 50/60 Hz 75% Nominal AC Voltage ranges 50/60 Hz 100% Performance Criteria No loss of function or performance. No loss of function or performance. Loss of function acceptable, self recoverable. Table 18.
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Power Sub-system Intel® Server System SC5650HCBRP TPS Table 19. Performance Criteria Level A Description The apparatus should continue to operate as intended. No degradation of performance. B The apparatus should continue to operate as intended. No degradation of performance beyond spec limits. C Temporary loss of function is allowed provided the function is self-recoverable or restorable by the operation of the controls. 4.1.2.7.
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Intel® Server System SC5650HCBRP TPS Power Sub-system Table 20. Holdup Requirements Loading 100% Holdup Time 12 msec 60% 20 msec An AC line dropout is defined to be when the AC input drops to 0VAC at any phase of the AC line for any length of time. During an AC dropout condition, the power supply meets dynamic voltage regulation requirements. An AC line dropout of any duration will not cause tripping of control signals or protection circuits.
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Power Sub-system o 4.1.2.11.2 Intel® Server System SC5650HCBRP TPS A continuous input voltage below the nominal input range should not damage the power supply or cause overstress to any power supply component. The power supply must be able to return to normal power up state after a brownout condition. Maximum input current under a continuous brownout should not blow the fuse.
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Intel® Server System SC5650HCBRP TPS Power Sub-system Table 21. Edge Finger Power Supply Connector Pin-out Connector Gold finger edge connector: 2X25 Revision 1.2 Upper Side +12 V Pin No Top. 1 Pin No.
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Power Sub-system Intel® Server System SC5650HCBRP TPS Signals that are defined as low true or high true use the following convention: signal# = low true Reserved pins are reserved for future use. 4.1.3.2 Grounding The ground of the pins of the power supply output connector provides the power return path. The output connector ground pins are connected to safety ground (power supply enclosure). This grounding is well-designed to ensure passing the maximum allowed Common Mode Noise levels.
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Intel® Server System SC5650HCBRP TPS 4.1.3.6 Power Sub-system Voltage Regulation The power supply output voltages stay within the following voltage limits when operating at steady state and dynamic loading conditions. These limits include the peak-peak ripple/noise specified in the Voltage Regulation Limits table. All outputs are measured with reference to the GND. The +12V and +5VSB outputs are measured at the power distribution board output harness connector. Table 23.
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Power Sub-system 4.1.3.9 Intel® Server System SC5650HCBRP TPS Closed Loop Stability The power supply is unconditionally stable under all line/load/transient load conditions, including capacitive load ranges. A minimum 45-degree phase margin and -10dB-gain margin is met. Closed-loop stability is ensured at the maximum and minimum loads, as applicable. 4.1.3.10 Common Mode Noise The Common Mode Noise on any output does not exceed 350mV pk-pk over the frequency band of 10 Hz to 20 MHz. 4.1.3.
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Intel® Server System SC5650HCBRP TPS Power Sub-system Item Tvout_on Description All main outputs must be within regulation of each other within this time. T vout_off All main outputs must leave regulation within this time. Minimum Maximum 50 Units msec 400 msec * The 5VSB output voltage rise time should be from 1.0 ms to 25.0 ms. Vout V1 10% Vout V2 V3 V4 Tvout rise Tvout_off Tvout_on Figure 24. Output Voltage Timing Revision 1.
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Power Sub-system Intel® Server System SC5650HCBRP TPS Table 28. Turn On / Off Timing Item Tsb_on_delay Description Delay from AC being applied to 5 VSB being within regulation. Minimum Tac_on_delay Delay from AC being applied to all output voltages being within regulation. Tvout_holdup Time all output voltages stay within regulation after loss of AC.
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Intel® Server System SC5650HCBRP TPS Power Sub-system Figure 25. Turn On/Off Timing (Power Supply Signals) A C Input T vout_h oldup V ou t T pw ok_low T A C _on _delay T sb_ on _delay T pw ok_on PW O K 5V SB T pw ok_off T sb_ on _delay T pw ok_on Tp T pson T pw ok_h oldup T 5V S B _ ho ldup T sb_ vout T pson _on _delay PSO N A C turn on/off cycle 4.1.3.
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Power Sub-system Intel® Server System SC5650HCBRP TPS While in standby mode, at no load condition, the residual voltage on the 12-V output does not exceed 100 mV. 4.1.3.16 Soft Starting The power supply contains control circuits that provide monotonic soft start of its outputs without overstressing the AC line or any power supply components at any specified AC line or load conditions. There is no requirement for rise time on the 5VSB but the turn on/off is monotonic. 4.1.3.
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Intel® Server System SC5650HCBRP TPS Power Sub-system connector during any single point of fail. The voltage will never trip any lower than the minimum levels when measured at the power pins of the power supply connector. Table 30. Over-voltage Protection Limits 4.1.4.3 Output Voltage +12 V MIN (V) 13.3 MAX (V) 14.5 +5 VSB 5.7 6.
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Power Sub-system Intel® Server System SC5650HCBRP TPS Table 31. PSON# Signal Characteristic Signal Type Accepts an open collector/drain input from the system. Pull-up to VSB located in power supply. PSON# = Low ON PSON# = High or Open OFF MIN MAX Logic level low (power supply ON) 0V 1.0V Logic level high (power supply OFF) 2.0V 5.25V Source current, Vpson = low 4mA Power up delay: Tpson_on_delay PWOK delay: 4.1.5.
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Intel® Server System SC5650HCBRP TPS 4.1.5.3 Power Sub-system PWOK (Power OK) Output Signal PWOK is a power OK signal and is pulled HIGH by the power supply to indicate that all the outputs are within the regulation limits of the power supply. When any output voltage falls below regulation limits or when AC power has been removed for a time sufficiently long so the power supply operation is no longer guaranteed, PWOK will be de-asserted to a LOW state.
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Power Sub-system Intel® Server System SC5650HCBRP TPS Table 34.
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Intel® Server System SC5650HCBRP TPS Power Sub-system System addressing Address2/Address1/ Address0 0/0/0 0/0/1 0/1/0 0/1/1 1/0/0 1/0/1 1/1/0 1/1/1 PMBus device read addresses 2 B0h/B1h1 B2h/B3h B4h/B5h B6h/B7h B8h/B9h BAh/BBh BCh/BDh BEh/BFh 1 Non-redundant power supplies use the 0/0/0 address location The addressing method uses the 7 MSB bits to set the address and the LSB to define whether a device is reading or writing.
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Power Sub-system 4.2 Intel® Server System SC5650HCBRP TPS 600-W Power Distribution Board (PDB) This specification defines the power distribution board (PDB) for the ERP12V 600-W 1+1 redundant power supply and for the ERP 12V 600-W 2+0 non-redundant power supply. The PDB is designed to plug directly to the output connector of the power supply and contains three DC/DC power converters to produce other required voltages: +3.
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Intel® Server System SC5650HCBRP TPS 4.2.1 Revision 1.
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Power Sub-system Intel® Server System SC5650HCBRP TPS Figure 26. Mechanical Drawing for Dual (1+1 Configuration) Power Supply Enclosure 4.2.1.1 Airflow Requirements There is no fan in the cage; the cage is cooled by the fan in the power supply module(s) when combined together in the system. 78 Intel order number E81443-002 Revision 1.
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Intel® Server System SC5650HCBRP TPS 4.2.1.2 Power Sub-system Temperature Requirements The PDB operates within all specified limits over the Top temperature range. Table 35. Environmental Requirements Item Top 4.2.1.3 Description Operating temperature range. MIN 0 Tnon-op Non-operating temperature range.
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Power Sub-system Pin 3* 4* 5 6 7 8 9 10 11 12 Signal COM COM RS +5VDC 5V RS COM +5VDC COM PWR OK 5 VSB +12V3 +12V3 +12V3 RS +3.3VDC Intel® Server System SC5650HCBRP TPS 18 AWG Color Black Black (24AWG) Red Red (24AWG) Black Red Black Gray (24AWG) Purple Yellow Yellow Yellow (24AWG) Orange Pin 16 17 18 19 20 21 22 23 24 Signal PSON# COM COM COM Reserved +5VDC +5VDC +5VDC COM 18 AWG Color Green (24AWG) Black Black Black N.C. Red Red Red Black Note: Remote Sense wire double-crimped.
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Intel® Server System SC5650HCBRP TPS 4.2.1.6 Power Sub-system Processor 0 Power Connector (P2) Connector housing: 8-Pin Molex* 39-01-2080 or equivalent Contact: Molex* 44476-1111 or equivalent Table 38.
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Power Sub-system Intel® Server System SC5650HCBRP TPS Table 40. P5, P6, P7, and P8 Peripheral Power Connectors 4.2.1.9 Pin 1 Signal +12V4 18 AWG Color Green 2 COM Black 3 COM Black 4 +5 VDC Red Right-angle SATA Power Connectors (P9) Connector housing: JWT* F6002HS0-5P-18 or equivalent Table 41. P9 Right-angle SATA Power Connector Pin 4.2.1.10 Signal 18 AWG Color 1 +3.
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Intel® Server System SC5650HCBRP TPS Power Sub-system output voltage internal to the DC/DC converter. Remote sense must be able to regulate out of up to 300mV drop on the +3.3V and 5V outputs. Also, the power supply ground return remote sense (ReturnS) passes through the PDB and the output harness to regulate out ground drops for its +12V and 5Vsb output voltages. The power supply uses remote sense (12VRS) to regulate out drops up to the 240VA protection circuits on the PDB. 4.2.2.
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Power Sub-system Intel® Server System SC5650HCBRP TPS All outputs are measured with reference to the return remote sense signal (ReturnS). The 3.3V and 5V outputs are measured at the remote sense point; all other voltages are measured at the output harness connectors. Table 45. Voltage Regulation Limits Converter Output + 3.3VDC Tolerance - 5% / +5% MIN +3.14 + 5VDC - 5% / +5% +4.75 +5.00 +5.25 VDC + 12VDC (12V1/2/3/4) - 5% / +5% +11.40 +12.00 +12.60 VDC - 12VDC - 10% / +10% -10.80 -12.
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Intel® Server System SC5650HCBRP TPS 4.2.2.7 Power Sub-system DC/DC Converters Closed Loop Stability Each DC/DC converter is unconditionally stable under all line/load/transient load conditions, including capacitive load ranges. A minimum of 45 degrees phase margin and –10dB-gain margin is required. 4.2.2.8 Common Mode Noise The Common Mode Noise on any output does not exceed 350 mV peak-peak over the frequency band of 10 Hz to 30 MHz. 4.2.2.
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Power Sub-system Intel® Server System SC5650HCBRP TPS Table 49. Output Voltage Timing Item Tvout_rise Description Output voltage rise time from each main output. Tvout_on T vout_off Minimum 5.0* Maximum 70* Units msec All main outputs must be within regulation of each other within this time. 50 msec All main outputs must leave regulation within this time. 400 msec * The 5VSB output voltage rise time shall be from 1.0 ms to 25.0 ms.
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Intel® Server System SC5650HCBRP TPS Item Tpwok_off Power Sub-system Description Delay from PWOK de-asserted to output voltags (3.3V, 5V, 12V, -12V) dropping out of regulation limits. Loading Minimum Maximum Units ms 1 Tpwok_low Duration of PWOK being in the de-asserted state during an off/on cycle using AC or the PSON signal. 100 Tsb_vout Delay from 5VSB being in regulation to O/Ps being in regulation at AC turn on.
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Power Sub-system 4.2.2.13 Intel® Server System SC5650HCBRP TPS Soft Start Requirements The power supply contains a control circuit which provides monotonic soft start for its outputs without overstressing the AC line or any power supply components at any specified AC line or load conditions. There is no requirement for rise time on the 5VSB, but the turn on/off is monotonic. 4.2.
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Intel® Server System SC5650HCBRP TPS Power Sub-system Table 52. Over-voltage Protection (OVP) Limits Output Voltage +3.3V 4.2.3.3 OVP MIN (V) 3.9 OVP MAX (V) 4.5 +5V 5.7 6.5 -12V -13.3 -14.5 +12V1/2/3/4 See Power Supply specification. +5vsb See Power Supply specification. Over Temperature Protection (OTP) There is not a requirement of thermal sensor located on the cage and have OTP function itself.
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Power Sub-system 4.2.4.2 Intel® Server System SC5650HCBRP TPS PSKILL The purpose of the PSKill pin is to allow for hot swapping of the power supply. The mating pin of this signal on the cage input connector is tied to ground, and its resistance is less than 5 ohms. 4.2.4.3 PWOK (Power OK) Input and Output Signals PWOK is a power OK signal and will be pulled HIGH by the power supply to indicate that all the outputs are within the regulation limits of the power supply.
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Intel® Server System SC5650HCBRP TPS Power Sub-system Open collector / drain output from power supply. Pull-up to VSB located in system. 50 μA Signal Type (Active Low) Sink current, Alert# = high Alert# rise and fall time 4.2.5 100 μs PMBus The PMBus features included in this specification are requirements for ac/dc silver box power supply for use in mainstream server systems. This specification is based on the PMBus specifications parts I and II, revision 1.2. 4.2.5.
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6-HDD Expander SAS Hot Swap Backplane Intel® Server System SC5650HCBRP TPS 5. 6-HDD Expander SAS Hot Swap Backplane 5.1 6-HDD Expander SAS Hot Swap Backplane Overview The Intel® Server System SC5650HCBRP integrates one 6-HDD Expander SAS Hot-swap Backplane (HSBP). The architecture is based on the Vitesse VSC7161* SAS Expander with enclosure management controller and has support for up to six SAS or SATA drives. The 6HDD Expander SAS HSBP supports the following feature set: 1.
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Intel® Server System SC5650HCBRP TPS 6-HDD Expander SAS Hot Swap Backplane Figure 29. 6HDD Active SAS/SATA HSBP Block Diagram 5.1.1 SAS Expander Vitesse VSC7161* The Vitesse VSC7161* device is a 10-port, self-configuring SAS Expander that supports 1.5 Gbps and 3.0 Gbps. This device is used for server and enclosure applications for mid-range and enterprise storage systems requiring active SAS port expansion. The features include: 1.5 Gbps and 3.
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6-HDD Expander SAS Hot Swap Backplane Intel® Server System SC5650HCBRP TPS interface or vendor-specific SMP implementation. As the SMP management application client, the CPU (in Master mode) handles all SMP initiator requests and all SMP response functions. 5.1.1.
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Intel® Server System SC5650HCBRP TPS 6-HDD Expander SAS Hot Swap Backplane Table 56. 7-pin SAS Connector Pin-out Connector Contact Number 5.1.1.3 Signal Name 1 GND 2 SASn_EP_RX_P 3 SASn_EP_RX_N 4 GND 5 SASn_EP_TX_N 6 SASn_EP_TX_P 7 GND I2C Serial Bus Interface The Vitesse VSC7161* SAS Expander supports two independent I2C interface ports with bus speed of up to 400 Kbits. The I2C bus at port 0 supports a TI TMP75* or equivalent I2C-based temperature sensor.
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6-HDD Expander SAS Hot Swap Backplane Intel® Server System SC5650HCBRP TPS Table 58. 6HDD I2C Bus Loading Device VIH VIL TMP75* Power Well P3V3 0.7 VCC 0.3 VCC 0.4 V/3 mA 1 uA 3 PF I2C Address 90h VSC7161* P3V3 2.0 V 0.8 V 0.4 V/4 mA 10 uA N/A N/A SAS_I2C0_DAT, SAS_I2C0_CLK AT24C64* P3V3 0.7 VCC 0.3 VCC 0.4 V/2.1 mA 3 uA 8 PF A0h SAS_I2C0_DAT, SAS_I2C0_CLK VSC7161* P3V3 2.0 V 0.8 V 0.
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Intel® Server System SC5650HCBRP TPS VSC7161* PIN Name P0_6 I/O Type Power Well O 3.3 V 6-HDD Expander SAS Hot Swap Backplane Programming Description Test Point P0_6 System Function Connection TP_EP_P0_6 P0_7 O 3.3 V Test Point P0_7 TP_EP_P0_7 P0_8 O 3.3 V FLASH(U3B1) write protect control FM_ROM0_WP_N Pull up 4.7 K to 3.3 V P0_9 O 3.3 V U3B2(not stuffed) write protect control FM_ROM1_WP_N Pull up 4.7 K to 3.3 V P0_10 O 3.3 V FRU(U3E2) write protect control FM_FRU_WP Pull up 4.
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6-HDD Expander SAS Hot Swap Backplane 5.1.5 Intel® Server System SC5650HCBRP TPS SAS/SATA Drive Connectors The 6-HDD Expander SAS HSBP provides six 22-pin SAS/SATA connectors for hot-swap hard disk drives supporting a 1.5 GHz and 3.0 GHz transfer rate. The following table defines the pin-out of the 22-pin SAS/SATA Drive Connector: Table 61. 22-pin SAS/SATA Connector Pin-out Connector Contact Number 5.1.
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Intel® Server System SC5650HCBRP TPS 5.1.7 6-HDD Expander SAS Hot Swap Backplane Clock Generation and Distribution The 6-HDD Expander SAS HSBP HSBP provides one clock source. A 75-MHz oscillator provides the clock to the VSC7161* SAS Expander. 5.1.8 IPMB Header - IPMB The following table defines the pin-out of the 4-pin IPMB Header. Table 63.
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6-HDD Expander SAS Hot Swap Backplane 5.1.10 Intel® Server System SC5650HCBRP TPS Board Layouts The following figures show the board layout and connector placement of the 6-HDD Expander SAS hot-swap backplane. A: SATA/SAS hot-swap drive connectors B: SATA/SAS cable connectors C: IPMB header D: Power connectors Note: The secondary side is mirrored Figure 32. 6-HDD Expander SAS HSBP Board Layout 5.1.11 Connector Specifications Table 64.
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Intel® Server System SC5650HCBRP TPS 6. Platform Management Platform Management The platform management subsystem is based on the Integrated BMC features of the ServerEngines* Pilot II. The onboard platform management subsystem consists of communication buses, sensors, and the system BIOS, and server management firmware. Figure 33 provides an illustration of the Server Management Bus (SMBUS) architecture as used on these server boards. 6.1 Feature Support 6.1.1 IPMI 2.
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Platform Management 102 Intel® Server System SC5650HCBRP TPS Chassis intrusion detection (dependant on platform support) Basic fan control using TControl version 2 SDRs Fan redundancy monitoring and support Power supply redundancy monitoring and support Hot swap fan support Acoustic management: Supports multiple fan profiles Signal testing support: The BMC provides test commands for setting and getting platform signal states.
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Intel® Server System SC5650HCBRP TPS 6.2 Platform Management Optional Advanced Management Feature Support This section explains the advanced management features supported by the BMC firmware. Table 13 lists basic and advanced feature support. Individual features may vary by platform. For more information, refer to Appendix C. Table 65. Basic and Advanced Management Features Feature IPMI 2.
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Platform Management 6.2.2 Intel® Server System SC5650HCBRP TPS Keyboard, Video, and Mouse (KVM) Redirection The advanced management features include support for keyboard, video, and mouse redirection (KVM) over LAN. This feature is available remotely from the embedded web server as a Java* applet. The client system must have a Java Runtime Environment (JRE) Version 1.6 (JRE6) or later to run the KVM or media redirection applets.
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Intel® Server System SC5650HCBRP TPS Platform Management administrators or users to boot the server or install software (including operating systems), copy files, update the BIOS, and so forth, or boot the server from this device. The following capabilities are supported: The operation of remotely mounted devices is independent of the local devices on the server. Both remote and local devices are usable in parallel.
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Platform Management Intel® Server System SC5650HCBRP TPS Software Inventory Profile (FW Version) Note: WS-MAN features will be made available after production launch. 6.2.5 Embedded Web server The BMC provides an embedded web server for out-of-band management. User authentication is handled by IPMI user names and passwords.
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Intel® Server System SC5650HCBRP TPS 6.3 Platform Management Platform Control This server platform has embedded platform control which is capable of automatically adjusting system performance and acoustic levels.
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Platform Management 6.3.1 Intel® Server System SC5650HCBRP TPS Memory Open and Closed Loop Thermal Throttling Open-Loop Thermal Throttling (OLTT) Throttling is a solution to cool the DIMMs by reducing memory traffic allowed on the memory bus, which reduces power consumption and thermal output. With OLTT, the system throttles in response to memory bandwidth demands instead of actual memory temperature.
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Intel® Server System SC5650HCBRP TPS Platform Management BIOS fails to get the Thermal SDRs, then it uses the Memory Reference Code (MRC) default settings for the memory throttling settings. The BIOS Setup Utility provides options to set the fan profile or operating mode the platform will operate under. Each operating mode has a predefined profile for which specific platform targets are configured, which in turn determines how the system fans operate to meet those targets.
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Platform Management 6.3.2.3.1 Intel® Server System SC5650HCBRP TPS Performance Mode (Default) With the platform running in Performance mode (Default), several platform control algorithm variables are set to enhance the platform’s capability of operating at maximum performance targets for the given system. In doing so, the platform is programmed with higher fan speeds at lower ambient temperatures.
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Intel® Server System SC5650HCBRP TPS Platform Management Figure 33. SMBUS Block Diagram Revision 1.
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BIOS Setup Utility Intel® Server System SC5650HCBRP TPS 7. BIOS Setup Utility 7.1 Logo / Diagnostic Screen The Logo / Diagnostic Screen displays in one of two forms: If Quiet Boot is enabled in the BIOS setup, a logo splash screen is displayed. By default, Quiet Boot is enabled in the BIOS setup. If the logo displays during POST, press to hide the logo and display the diagnostic screen.
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Intel® Server System SC5650HCBRP TPS 7.3.1 BIOS Setup Utility Operation The BIOS Setup has the following features: Localization - The BIOS Setup uses the Unicode standard and is capable of displaying setup forms in all languages currently included in the Unicode standard. The Intel® server board BIOS is only available in English. Console Redirection - The BIOS Setup is functional via console redirection over various terminal emulation standards.
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BIOS Setup Utility Intel® Server System SC5650HCBRP TPS Each Setup menu page contains a number of features. Each feature is associated with a value field except those used for informative purposes. Each value field contains configurable parameters. Depending on the security option selected and in effect by the password, a menu feature’s value may or may not change. If a value cannot be changed, its field is made inaccessible and appears grayed out. Table 68.
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Intel® Server System SC5650HCBRP TPS Key Option Save and Exit BIOS Setup Utility Description Pressing causes the following message to display: Save configuration and reset? Yes No If “Yes” is highlighted and is pressed, all changes are saved and the Setup is exited. If “No” is highlighted and is pressed, or the key is pressed, the user is returned to where they were before was pressed without affecting any existing values. 7.3.1.
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BIOS Setup Utility 7.3.2.1 Intel® Server System SC5650HCBRP TPS Main Screen Unless an error occurred, the Main screen is the first screen displayed when the BIOS Setup is entered. If an error occurred, the Error Manager screen displays instead. Main Advanced Security Server Management Boot Options Boot Manager Logged in as Platform ID System BIOS Version S5500.86B.xx.yy.
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Intel® Server System SC5650HCBRP TPS Setup Item Build Date Options BIOS Setup Utility Help Text Comments Information only. Displays the current BIOS build date. Memory Size Quiet Boot Information only. Displays the total physical memory installed in the system, in MB or GB. The term physical memory indicates the total memory discovered in the form of installed DDR3 DIMMs. Enabled Disabled [Enabled] – Display the logo screen during POST. [Disabled] – Display the diagnostic screen during POST.
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BIOS Setup Utility 7.3.2.2 Intel® Server System SC5650HCBRP TPS Advanced Screen The Advanced screen provides an access point to configure several options. On this screen, the user selects the option they must configure. Configurations are performed on the selected screen and not directly on the Advanced screen. To access this screen from the Main screen, press the right arrow until the Advanced screen is selected.
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Intel® Server System SC5650HCBRP TPS 7.3.2.2.1 BIOS Setup Utility Processor Configuration Screen The Processor screen allows the user to view the processor core frequency, system bus frequency, and to enable or disable several processor options. This screen also allows the user to view information about a specific processor. To access this screen from the Main screen, select Advanced > Processor.
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BIOS Setup Utility Intel® Server System SC5650HCBRP TPS Table 71. Setup Utility — Processor Configuration Screen Fields Setup Item Processor ID Options Help Text Comments Information only. Processor CPUID Processor Frequency Information only. Current frequency of the processor. Microcode Revision Information only. Revision of the loaded microcode. L1 Cache RAM Information only. Size of the Processor L1 Cache. L2 Cache RAM Information only.
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Intel® Server System SC5650HCBRP TPS Setup Item Intel® Virtualization Technology Options Enabled Disabled BIOS Setup Utility Help Text Intel® Virtualization Technology allows a platform to run multiple operating systems and applications in independent partitions. Comments Note: A change to this option requires the system to be powered off and then back on before the setting takes effect.
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BIOS Setup Utility 7.3.2.2.2 Intel® Server System SC5650HCBRP TPS Memory Screen The Memory screen allows the user to view details about the system memory DDR3 DIMMs installed. This screen also allows the user to open the Configure Memory RAS and Performance screen. To access this screen from the Main screen, select Advanced > Memory.
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Intel® Server System SC5650HCBRP TPS BIOS Setup Utility Table 72. Setup Utility — Memory Configuration Screen Fields Setup Item Total Memory Options Help Text Effective Memory Comments Information only. The amount of memory available in the system in the form of installed DDR3 DIMMs in units of MB or GB. Information only. The amount of memory available to the operating system in MB or GB.
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BIOS Setup Utility Intel® Server System SC5650HCBRP TPS 7.3.2.2.2.1 Configure Memory RAS and Performance Screen The Configure Memory RAS and Performance screen allows the user to customize several memory configuration options, such as whether to use Memory Mirroring. To access this screen from the Main screen, select Advanced > Memory > Configure Memory RAS and Performance.
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Intel® Server System SC5650HCBRP TPS 7.3.2.2.3 BIOS Setup Utility Mass Storage Controller Screen The Mass Storage screen allows the user to configure the SATA/SAS controller when it is present on the baseboard module card of an Intel system. To access this screen from the Main menu, select Advanced > Mass Storage.
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BIOS Setup Utility Setup Item SATA Mode Intel® Server System SC5650HCBRP TPS Options Enhanced Compatibility AHCI SW RAID Help Text [ENHANCED] - Supports up to 6 SATA ports with IDE Native Mode. [COMPATIBILITY] - Supports up to 4 SATA ports[0/1/2/3] with IDE Legacy mode and 2 SATA ports[4/5] with IDE Native Mode. [AHCI] - Supports all SATA ports using the Advanced Host Controller Interface. [SW RAID] - Supports configuration of SATA ports for RAID via RAID configuration software.
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Intel® Server System SC5650HCBRP TPS 7.3.2.2.4 BIOS Setup Utility Serial Ports Screen The Serial Ports screen allows the user to configure the Serial A [COM 1] and Serial B [COM2] ports. To access this screen from the Main screen, select Advanced > Serial Port. Advanced Serial Port Configuration Serial A Enable Enabled/Disabled Address 3F8h / 2F8h / 3E8h / 2E8h IRQ 3 or 4 Serial B Enable Enabled/Disabled Address 3F8h / 2F8h / 3E8h / 2E8h IRQ 3 or 4 Figure 40.
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BIOS Setup Utility 7.3.2.2.5 Intel® Server System SC5650HCBRP TPS USB Configuration Screen The USB Configuration screen allows the user to configure the USB controller options. To access this screen from the Main screen, select Advanced > USB Configuration.
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Intel® Server System SC5650HCBRP TPS BIOS Setup Utility Table 76. Setup Utility — USB Controller Configuration Screen Fields Setup Item Detected USB Devices USB Controller Options Enabled Disabled Help Text Comments Information only. Shows the number of USB devices in the system. [Enabled] - All onboard USB controllers are turned on and accessible by the OS. [Disabled] - All onboard USB controllers are turned off and inaccessible by the OS.
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BIOS Setup Utility 7.3.2.2.6 Intel® Server System SC5650HCBRP TPS PCI Screen The PCI Screen allows the user to configure the PCI add-in cards, onboard NIC controllers, and video options. To access this screen from the Main screen, select Advanced > PCI.
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Intel® Server System SC5650HCBRP TPS BIOS Setup Utility Setup Item Onboard NIC2 ROM Comments Options Enabled Disabled Help Text If enabled. loads the embedded option ROM for the onboard network controllers. Warning: If [Disabled] is selected, NIC2 cannot be used to boot or wake the system. Onboard NIC iSCSI ROM Enabled Disabled If enabled. loads the embedded option ROM for the onboard network controllers. Warning: If [Disabled] is selected, NIC1 and NIC2 cannot be used to boot or wake the system.
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BIOS Setup Utility Intel® Server System SC5650HCBRP TPS Table 78. Setup Utility — System Acoustic and Performance Configuration Screen Fields Setup Item Set Throttling Mode Altitude Auto Options Help Text [Auto] – Auto Throttling mode. CLTT [CLTT] – Closed Loop Thermal Throttling Mode. OLTT 300m or less [OLTT] – Open Loop Thermal Throttling Mode. [300m or less] (980ft or less) 301m-900m Optimal performance setting near sea level.
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Intel® Server System SC5650HCBRP TPS Main Advanced Security BIOS Setup Utility Server Management Administrator Password Status User Password Status Set Administrator Password [1234aBcD] Set User Password [1234aBcD] Front Panel Lockout Enabled / Disabled Boot Options Boot Manager No Operation / Turn On / Turn Off / Clear Ownership TPM State TPM Adminis
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BIOS Setup Utility Setup Item Front Panel Lockout Intel® Server System SC5650HCBRP TPS Options Enabled Disabled TPM State* Help Text If enabled, locks the power button and reset button on the system's front panel. If [Enabled] is selected, power and reset must be controlled via a system management interface. Comments Enabled and Activated Information only. Enabled and Deactivated Shows the current TPM device state.
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Intel® Server System SC5650HCBRP TPS Main Advanced Security BIOS Setup Utility Server Management Boot Options Boot Manager Assert NMI on SERR Enabled / Disabled Assert NMI on PERR Enabled / Disabled Resume on AC Power Loss Stay Off / Last state / Reset Clear System Event Log Enabled / Disabled FRB-2 Enable Enabled / Disabled O/S Boot Watchdog Timer Enabled / Disabled O/S Boot Watchdog Timer Policy Power off / Reset O/S Boot Watchdog Timer Timeout 5 minutes / 10 minutes / 15 minutes /
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BIOS Setup Utility Intel® Server System SC5650HCBRP TPS Table 80. Setup Utility — Server Management Configuration Screen Fields Setup Item Assert NMI on SERR Assert NMI on PERR Resume on AC Power Loss Options Enabled Help Text On SERR, generate an NMI and log an error. Disabled Note: [Enabled] must be selected for the Assert NMI on PERR setup option to be visible. Enabled On PERR, generate an NMI and log an error.
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Intel® Server System SC5650HCBRP TPS 7.3.2.4.1 BIOS Setup Utility Console Redirection Screen The Console Redirection screen allows the user to enable or disable console redirection and configure the connection options for this feature. To access this screen from the Main screen, select Server Management > Console Redirection. Server Management Console Redirection Console Redirection Disabled / Serial Port A / Serial Port B Flow Control None / RTS/CTS Baud Rate 9.6k / 19.2k / 38.4k / 57.6k / 115.
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BIOS Setup Utility Intel® Server System SC5650HCBRP TPS Table 81. Setup Utility — Console Redirection Configuration Fields Setup Item Console Redirection Options Disabled Serial Port A Help Text Console redirection allows a serial port to be used for server management tasks. Serial Port B [Disabled] - No console redirection. [Serial Port A] - Configure serial port A for console redirection. [Serial Port B] - Configure serial port B for console redirection.
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Intel® Server System SC5650HCBRP TPS 7.3.2.5 BIOS Setup Utility Server Management System Information Screen The Server Management System Information screen allows the user to view part numbers, serial numbers, and firmware revisions. To access this screen from the Main screen, select Server Management > System Information.
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BIOS Setup Utility Intel® Server System SC5650HCBRP TPS Setup Item Comments UUID 7.3.2.6 Information only Boot Options Screen The Boot Options screen displays any bootable media encountered during POST and allows the user to configure the desired boot device. To access this screen from the Main screen, select Boot Options.
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Intel® Server System SC5650HCBRP TPS BIOS Setup Utility Table 83. Setup Utility — Boot Options Screen Fields Setup Item Boot Timeout Options 0 - 65535 Help Text The number of seconds the BIOS should pause at the end of POST to allow the user to press the [F2] key for entering the BIOS Setup utility. Comments After entering the necessary timeout, press the Enter key to register that timeout value to the system. These settings Valid values are 0-65535. Zero is the default.
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BIOS Setup Utility Intel® Server System SC5650HCBRP TPS If all types of bootable devices are installed in the system, then the default boot order is: 1. 2. 3. 4. 5. 6. CD/DVD-ROM Floppy Disk Drive Hard Disk Drive PXE Network Device BEV (Boot Entry Vector) Device EFI Shell and EFI Boot paths 7.3.2.6.1 Add New Boot Option Screen The Add Boot Option screen allows the user to remove an EFI boot option from the boot order.
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Intel® Server System SC5650HCBRP TPS 7.3.2.6.2 BIOS Setup Utility Delete Boot Option Screen The Delete Boot Option screen allows the user to remove an EFI boot option from the boot order. Note that while you can delete the Internal EFI Shell in this screen, it is restored to the Boot Order on the next reboot. You cannot permanently delete the Internal EFI Shell. To access this screen from the Main screen, select Boot Options > Delete Boot Options.
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BIOS Setup Utility 7.3.2.6.3 Intel® Server System SC5650HCBRP TPS Hard Disk Order Screen The Hard Disk Order screen allows the user to control the hard disks. To access this screen from the Main screen, select Boot Options > Hard Disk Order. Boot Options Hard Disk #1 < Available Hard Disks > Hard Disk #2 < Available Hard Disks > Figure 51. Setup Utility — Hard Disk Order Screen Display Table 86. Setup Utility — Hard Disk Order Fields 7.3.2.6.
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Intel® Server System SC5650HCBRP TPS BIOS Setup Utility Table 87. Setup Utility — CDROM Order Fields Setup Item CDROM #1 Options Available legacy devices for this Device group. Help Text Set system boot order by selecting the boot option for this position. CDROM #2 Available legacy devices for this Device group. Set system boot order by selecting the boot option for this position. 7.3.2.6.5 Floppy Order Screen The Floppy Order screen allows the user to control the floppy drives.
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BIOS Setup Utility 7.3.2.6.6 Intel® Server System SC5650HCBRP TPS Network Device Order Screen The Network Device Order screen allows the user to control the network bootable devices. To access this screen from the Main screen, select Boot Options > Network Device Order. Boot Options Network Device #1 Network Device #2 Figure 54. Setup Utility — Network Device Order Screen Display Table 89.
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Intel® Server System SC5650HCBRP TPS BIOS Setup Utility Table 90. Setup Utility — BEV Device Order Fields 7.3.2.7 Setup Item BEV Device #1 Options Available legacy devices for this Device group. Help Text Set system boot order by selecting the boot option for this position. BEV Device #2 Available legacy devices for this Device group. Set system boot order by selecting the boot option for this position.
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BIOS Setup Utility 7.3.2.8 Intel® Server System SC5650HCBRP TPS Error Manager Screen The Error Manager screen displays any errors encountered during POST. Error Manager ERROR CODE Exit SEVERITY INSTANCE Figure 57. Setup Utility — Error Manager Screen Display Table 92. Setup Utility — Error Manager Screen Fields Setup Item Displays System Errors 148 Comments Information only. Displays errors that occurred during POST. Revision 1.
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Intel® Server System SC5650HCBRP TPS 7.3.2.9 BIOS Setup Utility Exit Screen The Exit screen allows the user to choose whether to save or discard the configuration changes made on the other screens. It also allows the user to restore the server to the factory defaults or to save or restore them to the set of user-defined default values. If Load Default Values is selected, the factory default settings (noted in bold in the tables in this chapter) are applied.
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BIOS Setup Utility Setup Item Save as User Default Values Intel® Server System SC5650HCBRP TPS Help Text Save current BIOS Setup utility values as custom user default values. If needed, the user default values can be restored via the Load User Default Values option below. Comments User prompted for confirmation. Note: Clearing the CMOS or NVRAM does not cause the User Default values to be reset to the factory default values. Load User Default Values 150 Load user default values.
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Intel® Server System SC5650HCBRP TPS Connector/Header Locations and Pin-outs 8. Connector/Header Locations and Pin-outs 8.1 Server Board Connector Information The following section provides detailed information regarding all connectors, headers, and jumpers on the server boards. The following table lists all connector types available on the board and the corresponding preference designators printed on the silkscreen. Table 94.
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Connector/Header Locations and Pin-outs Connector Quantity Intel® Server System SC5650HCBRP TPS Reference Designators Connector Type Pin Count Chassis Intrusion 1 J1F6 Header 2 Serial ATA 6 J1G1, J1G4, J1G5, J1E3, J1F1, J1F4 Header 7 HSBP 2 J1F5, J1G3 Header 4 SATA SGPIO 1 J1G2 Header 4 LCP/IPMB 1 J1G6 Header 4 Configuration jumpers 4 J1E6 (CMOS Clear), J1E2 (ME Force Update), J1E4 (Password Clear), J1E5 (BIOS Recovery), J1H1 (BMC Force Update), Jumper 3 HDD Led 1 J1E1
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Intel® Server System SC5650HCBRP TPS Connector/Header Locations and Pin-outs Table 96. CPU 1 Power Connector Pin-out (J9A1) Pin Signal Color 1 GND of Pin 5 Black 2 GND of Pin 6 Black 3 GND of Pin 7 Black 4 GND of Pin 8 Black 5 +12 Vdc CPU1 Yellow / black 6 +12 Vdc CPU1 Yellow / black 7 +12 Vdc DDR3_CPU1 Yellow / black 8 +12 Vdc DDR3_CPU1 Yellow / black Table 97.
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Connector/Header Locations and Pin-outs Intel® Server System SC5650HCBRP TPS Note: This connector is not compatible with the Intel® Remote Management Module (Intel® RMM) or the Intel® Remote Management Module 2 (Intel® RMM2). Table 99.
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Intel® Server System SC5650HCBRP TPS 8.3.4 Connector/Header Locations and Pin-outs SGPIO Header Table 102. SGPIO Header Pin-out (J1G2) Pin 1 2 8.4 Signal Name SGPIO_CLOCK Description SGPIO Clock Signal SGPIO_LOAD SGPIO Load Signal 3 SGPIO_DATAOUT0 SGPIO Data Out 4 SGPIO_DATAOUT1 SGPIO Data In Front Panel Connector The server board provides a 24-pin SSI front panel connector (J1B3) for use with Intel® and third-party chassis. The following table provides the pin-out for this connector.
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Connector/Header Locations and Pin-outs Intel® Server System SC5650HCBRP TPS Table 104. VGA Connector Pin-out (J7A1) Pin 1 8.5.
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Intel® Server System SC5650HCBRP TPS 8.5.3 Connector/Header Locations and Pin-outs SATA Connectors The server board provides up to six SATA connectors: SATA-0 (J1G5), SATA-1 (J1G4), SATA2 (J1G1), SATA-3 (J1F4), SATA-4 (J1F1), and SATA-5 (J1E3). The pin configuration for each connector is identical and defined in the following table. Table 106. SATA / SAS Connector Pin-out (J1E3, J1G1, J1G4, J1G5, J1F1, J1F4) Pin 1 8.5.
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Connector/Header Locations and Pin-outs 8.5.5 Pin 35 37 Name Intel® Server System SC5650HCBRP TPS GND Pin 36 Name PE_ICH10_SAS_SW_RXP2 PE_ICH10_SAS_SW_RXN2 38 GND 39 GND 40 PE_ICH10_SAS_SW_RXP3 41 PE_ICH10_SAS_SW_RXN3 42 GND 43 GND 44 CLK_100M_SAS_DP 45 CLK_100M_SAS_DN 46 GND 47 GND 48 P3V3 49 P3V3 50 P3V3 Serial Port Connectors The server board provides one external DB9 Serial A port (J8A1) and one internal 9-pin Serial B header (J1B1).
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Intel® Server System SC5650HCBRP TPS 8.5.6 Connector/Header Locations and Pin-outs USB Connector The following table details the pin-out of the external USB connectors (J5A1, J6A1) found on the back edge of the server boards. Table 110.
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Connector/Header Locations and Pin-outs Intel® Server System SC5650HCBRP TPS One low-profile 2x5 connector (J2D2) on the server board provides an option to support a lowprofile USB Solid State Drive. Table 113.
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Intel® Server System SC5650HCBRP TPS Connector/Header Locations and Pin-outs Table 115. SSI 4-pin Fan Header Pin-out (J7K1, J9A2, J9A3) Pin 1 Signal Name Ground Type GND Description Ground is the power supply ground 2 12V Power Power supply 12 V 3 Fan Tach In FAN_TACH signal is connected to the BMC to monitor the fan speed 4 Fan PWM Out FAN_PWM signal to control fan speed Table 116.
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Jumper Blocks 9. Intel® Server System SC5650HCBRP TPS Jumper Blocks The server board has several 3-pin jumper blocks that you can use to configure, protect, or recover specific features of the server boards. The following symbol identifies Pin 1 on each jumper block on the silkscreen: ▼ Figure 59. Jumper Blocks (J1E2, J1E4, J1E5, J1E6, J1H1) Table 117.
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Intel® Server System SC5650HCBRP TPS 9.1 Jumper Blocks CMOS Clear and Password Reset Usage Procedure The CMOS Clear (J1E6) and Password Reset (J1E4) recovery features are designed to achieve the desired operation with minimum system down time. The usage procedure for these two features has changed from previous generation Intel® server boards. The following procedure outlines the new usage model. 9.1.1 Clearing the CMOS 1. Power down the server and unplug the AC power cord. 2.
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Jumper Blocks Intel® Server System SC5650HCBRP TPS BMC into the proper update state. In the event the standard BMC firmware update process fails, complete the following procedure: 1. Power down and remove the AC power cord. 2. Open the server chassis. See your server chassis documentation for instructions. 3. Move the jumper (J1H1) from the default operating position (covering pins 1 and 2) to the enabled position (covering pins 2 and 3). 4. Close the server chassis. 5.
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Intel® Server System SC5650HCBRP TPS Jumper Blocks 10. Move the BIOS recovery jumper (J1E5) from the “enabled” position (covering pins 2 and 3) to the “disabled” position (covering pins 1 and 2). 11. Close the server chassis. 12. Reconnect the AC power cord and power up the server. Warning: DO NOT interrupt the BIOS POST during the first boot after the BIOS recovery. Revision 1.
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Intel® Light Guided Diagnostics Intel® Server System SC5650HCBRP TPS 10. Intel® Light Guided Diagnostics The Server Board in the Intel® Server System SC5650HCBRP has several onboard diagnostic LEDs to assist in troubleshooting board-level issues. This section provides a description of the location and function of each LED on the server boards. 10.1 5-volt Stand-by LED Several server management features of these server boards require a 5-V stand-by voltage supplied from the power supply.
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Intel® Server System SC5650HCBRP TPS Intel® Light Guided Diagnostics Figure 60. 5-volt Stand-by Status LED Location 10.2 Fan Fault LED’s Fan fault LEDs are present for the two CPU fans and the one rear system fan. The fan fault LEDs illuminate when the corresponding fan has fault. Revision 1.
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Intel® Light Guided Diagnostics Intel® Server System SC5650HCBRP TPS Figure 61. Fan Fault LED’s Location 168 Revision 1.
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Intel® Server System SC5650HCBRP TPS Intel® Light Guided Diagnostics 10.3 System ID LED and System Status LED The server board provides LEDs for both system ID and system status. These LEDs are located in the rear I/O area of the server board as shown in the following figure. A. B. System ID LED System Status LED Figure 62.
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Intel® Light Guided Diagnostics Intel® Server System SC5650HCBRP TPS By issuing the appropriate hex IPMI “Chassis Identify” value, the ID LED will either blink blue for 15 seconds and turn off or will blink indefinitely until the appropriate hex IPMI Chassis Identify value is issue to turn it off. The bi-color (green / amber) System Status LED operates as follows: Table 118. System Status LED Color Green State Solid on Criticality System OK Description System booted and ready.
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Intel® Server System SC5650HCBRP TPS Intel® Light Guided Diagnostics 10.4 DIMM Fault LEDs The server board provides memory fault LED for each DIMM socket. These LEDs are located as shown in the following figure. The DIMM fault LED illuminates when the corresponding DIMM slot has memory installed and a memory error occurs. Figure 63. DIMM Fault LED’s Location Revision 1.
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Intel® Light Guided Diagnostics Intel® Server System SC5650HCBRP TPS 10.5 Post Code Diagnostic LEDs Eight amber POST code diagnostic LEDs are located on the back edge of the server boards in the rear I/O area of the server boards by the serial A connector. During the system boot process, the BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number.
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Intel® Server System SC5650HCBRP TPS Design and Environmental Specifications 11. Design and Environmental Specifications 11.1 Intel® Server System SC5650HCBRP Design Specifications Operation of the Intel® Server System SC5650HCBRP at conditions beyond those shown in the following table may cause permanent damage to the system. Exposure to absolute maximum rating conditions for extended periods may affect system reliability. Table 119.
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Design and Environmental Specifications • • Intel® Server System SC5650HCBRP TPS Duty Cycle: 100% Quality Level: II Table 120. MTBF Estimate MTBF (hours) Intel® Server System SC5650HCBRP 43600 Intel® Server Board S5520HC 174 124,000 600-W Power Supply Unit 356,000 Hot Swap Power Supply Power Distribution Board 919,000 System Fans 100,000 6-HDD Expander SAS Hot Swap Backplane 1,300,000 Front Panel 7,000,000 Intrusion switch 25,000,000 Revision 1.
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Intel® Server System SC5650HCBRP TPS Design and Environmental Specifications 11.3 Processor Power Support The server boards support the Thermal Design Power (TDP) guideline for Intel® Xeon® processors. The Flexible Motherboard Guidelines (FMB) were also followed to determine the suggested thermal and current design values for anticipating future processor needs. The following table provides maximum values for Icc, TDP power and TCASE for the compatible Intel® Xeon® Processor 5500 series. Table 121.
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Regulatory and Certification Information Intel® Server System SC5650HCBRP TPS 12. Regulatory and Certification Information To help ensure EMC compliance with your local regional rules and regulations, before computer integration, make sure that the chassis, power supply, and other modules have passed EMC testing using a server board with a microprocessor from the same family (or higher) and operating at the same (or higher) speed as the microprocessor used on this server board.
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Intel® Server System SC5650HCBRP TPS • • • • • BSMI CNS13438 Emissions (Taiwan) RRL Notice No. 1997-41 (EMC) & 1997-42 (EMI) (Korea) GOST R 29216-91 Emissions (Russia) – Listed on System License GOST R 50628-95 Immunity (Russia) – Listed on System License Belarus License (Belarus) – Listed on System License 12.1.
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Regulatory and Certification Information Intel® Server System SC5650HCBRP TPS 12.
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Intel® Server System SC5650HCBRP TPS Regulatory and Certification Information This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation.
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Regulatory and Certification Information Intel® Server System SC5650HCBRP TPS ICES-003 (Canada) Cet appareil numérique respecte les limites bruits radioélectriques applicables aux appareils numériques de Classe A prescrites dans lanorme sur le matériel brouilleur: “Apparelis Numériques”, NMB-003 édictee par le Ministre Canadian des Communications.
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Intel® Server System SC5650HCBRP TPS Regulatory and Certification Information RRL KCC (Korea) 12.4 Product Ecology Change (EU RoHS) Intel has a system in place to restrict the use of banned substances in accordance with the European Directive 2002/95/EC. Compliance is based on declaration that materials banned in the RoHS Directive are either (1) below all applicable threshold limits or (2) an approved / pending RoHS exemption applies. RoHS implementation details are not fully defined and may change.
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Regulatory and Certification Information Intel® Server System SC5650HCBRP TPS CRoHS Substance Tables: China CRoHS requires products to be provided with controlled substance information. Intel understands the end-seller (entity placing product into market place) is responsible for providing the controlled substance information. Controlled substance information is required to be in Simplified Chinese. Substance table for this board product is as follows: 182 Revision 1.
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Intel® Server System SC5650HCBRP TPS Regulatory and Certification Information Revision 1.
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Regulatory and Certification Information Intel® Server System SC5650HCBRP TPS 12.6 China Packaging Recycle Marks (or GB18455-2001) Intel EPSD has the following ecological compliances: Cardboard and fiberboard packaging will be marked as recyclable in China. China Packaging Recycling Marks is required on retail packaging to be marked as recyclable using China’s recycling logo.
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Intel® Server System SC5650HCBRP TPS Appendix A: Integration and Usage Tips Appendix A: Integration and Usage Tips Prior to adding or removing components or peripherals from the server board, you must remove the AC power cord. With AC power plugged into the server board, 5-V standby is still present even though the server board is powered off. This server board supports Intel® Xeon® Processor 5500 Series only. This server board does not support previous generation Intel® Xeon® processors.
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Appendix A: Integration and Usage Tips à 186 Intel® Server System SC5650HCBRP TPS device SEL event, There are multiple means to dump the PCI map.
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Intel® Server System SC5650HCBRP TPS Appendix B: Processor Active Heat Sink Installation Appendix B: Processor Active Heat Sink Installation Active processor heat sink(s) is required Table 122.
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Appendix C: BMC Sensor Tables Intel® Server System SC5650HCBRP TPS Appendix C: BMC Sensor Tables This appendix lists the sensor identification numbers and information about the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 2.0 for sensor and event/reading-type table information.
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Intel® Server System SC5650HCBRP TPS Appendix C: BMC Sensor Tables - T: Threshold value Rearm Sensors The rearm is a request for the event status of a sensor to be rechecked and updated upon a transition between good and bad states. You can rearm the sensors manually or automatically. This column indicates the type supported by the sensor.
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Appendix C: BMC Sensor Tables Intel® Server System SC5650HCBRP TPS Table 123.
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Intel® Server System SC5650HCBRP TPS Full Sensor Name (Sensor name in SDR) Sensor # Platform Applicability Appendix C: BMC Sensor Tables Sensor Type Event / Reading Type Event Offset Triggers Contrib. To System Status 06 – Redundant: degraded from fully redundant state. Degraded 07 – Redundant: Transition from non-redundant state.
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Appendix C: BMC Sensor Tables Full Sensor Name (Sensor name in SDR) System Event (System Event) BB +1.1V IOH (BB +1.1V IOH) BB +1.1V P1 Vccp (BB +1.1V P1 Vccp) BB +1.1V P2 Vccp (BB +1.1V P2 Vccp) BB +1.5V P1 DDR3 (BB +1.5V P1 DDR3) BB +1.5V P2 DDR3 (BB +1.5V P2 DDR3) BB +1.8V AUX (BB +1.8V AUX) BB +3.3V (BB +3.3V) BB +3.3V STBY (BB +3.
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Intel® Server System SC5650HCBRP TPS Full Sensor Name (Sensor name in SDR) BB +3.3V Vbat (BB +3.3V Vbat) BB +5.0V (BB +5.0V) BB +5.0V STBY (BB +5.0V STBY) BB +12.0V (BB +12.0V) BB -12.0V (BB -12.0V) Baseboard Temperature (Baseboard Temp) Front Panel Temperature (Front Panel Temp) IOH Thermal Margin (IOH Therm Margin) Processor 1 Memory Thermal Margin (Mem P1 Thrm Mrgn) Revision 1.
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Appendix C: BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Processor 2 Memory Thermal Margin Sensor # (Fan x Present) Fan Redundancy 1 (Fan Redundancy) 194 Sensor Type Event / Reading Type Dual processor only Temperature Threshold 01h 01h 30h–39h Chassisspecific Fan Threshold 04h 01h 40h–45h Chassisspecific Fan Generic 08h Fan Tachometer Sensors Fan Present Sensors Platform Applicability 24h (Mem P2 Thrm Mrgn) (Chassis specific sensor names) Intel® Server System SC5650H
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Intel® Server System SC5650HCBRP TPS Full Sensor Name (Sensor name in SDR) Power Supply 1 Status (PS1 Status) Power Supply 2 Status (PS2 Status) Revision 1.2 Sensor # 50h 51h Platform Applicability Chassisspecific Chassisspecific Appendix C: BMC Sensor Tables Sensor Type Power Supply 08h Power Supply 08h Event / Reading Type Event Offset Triggers Contrib. To System Status 04 - Nonredundant: Sufficient resources. Transition from insufficient.
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Appendix C: BMC Sensor Tables Full Sensor Name (Sensor name in SDR) Sensor # Intel® Server System SC5650HCBRP TPS Platform Applicability Sensor Type Event / Reading Type Event Offset Triggers 06 – Configuration error Power Supply 1 AC Power Input 52h (PS1 Power In) Power Supply 2 AC Power Input 53h (PS2 Power In) Power Supply 1 +12V % of Maximum Current Output 54h (PS1 Curr Out %) Power Supply 2 +12V % of Maximum Current Output 55h (PS2 Curr Out %) Power Supply 1 Temperature 56h (PS1 Tempe
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Intel® Server System SC5650HCBRP TPS Full Sensor Name (Sensor name in SDR) Processor 1 Thermal Margin (P1 Therm Margin) Processor 2 Thermal Margin (P2 Therm Margin) Processor 1 Thermal Control % Sensor # Platform Applicability 62h All 63h Dual processor only 64h All 65h Dual processor only (P1 Therm Ctrl %) Processor 2 Thermal Control % (P2 Therm Ctrl %) Processor 1 VRD Temp (P1 VRD Hot) Processor 2 VRD Temp (P2 VRD Hot) Catastrophic Error (CATERR) CPU Missing (CPU Missing) IOH Thermal Trip (IOH
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Appendix C: BMC Sensor Tables 198 Intel® Server System SC5650HCBRP TPS Intel order number E81443-002 Revision 1.
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Intel® Server System SC5650HCBRP TPS Appendix D: Platform Specific BMC Appendix Appendix D: Platform Specific BMC Appendix Table 124.
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Appendix E: POST Code Diagnostic LED Decoder Intel® Server System SC5650HCBRP TPS Appendix E: POST Code Diagnostic LED Decoder During the system boot process, the BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the POST code to the POST Code Diagnostic LEDs on the back edge of the server board.
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Intel® Server System SC5650HCBRP TPS Appendix E: POST Code Diagnostic LED Decoder Upper nibble bits = 1110b = Eh; Lower nibble bits = 1101b = Dh; the two are concatenated as EDh. Find the meaning of POST Code EDh in below table – Memory Population Error: RDIMMs and UDIMMs cannot be mixed in the system. Table 126.
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Appendix E: POST Code Diagnostic LED Decoder Progress Code 0x53-0x57 Intel® Server System SC5650HCBRP TPS Progress Code Definition Reserved for PCI Bus USB 0x58 Resetting USB bus 0x59 Reserved for USB devices ATA / ATAPI / SATA 0x5A Resetting SATA bus and all devices 0x5B Reserved for ATA SMBUS 0x5C Resetting SMBUS 0x5D Reserved for SMBUS Local Console 0x70 Resetting the video controller (VGA) 0x71 Disabling the video controller (VGA) 0x72 Enabling the video controller (VGA) Remote Con
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Intel® Server System SC5650HCBRP TPS Progress Code Appendix E: POST Code Diagnostic LED Decoder Progress Code Definition Removable Media 0xB8 Resetting the removable media device 0xB9 Disabling the removable media device 0xBA Detecting the presence of a removable media device (CDROM detection, etc.
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Appendix E: POST Code Diagnostic LED Decoder Progress Code 0x3F 204 Intel® Server System SC5650HCBRP TPS Progress Code Definition Unable to complete crisis recovery Revision 1.
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Intel® Server System SC5650HCBRP TPS Appendix F: POST Error Messages and Handling Appendix F: POST Error Messages and Handling Whenever possible, the BIOS outputs the current boot progress codes on the video screen. Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. The class and subclass fields point to the type of hardware being initialized. The operation field represents the specific initialization activity.
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Appendix F: POST Error Messages and Handling Intel® Server System SC5650HCBRP TPS Table 127. POST Error Messages and Handling Error Code Error Message Response 0012 CMOS date / time not set Pause 0048 Password check failed Pause 0108 Keyboard component encountered a locked error. No Pause 0109 Keyboard component encountered a stuck key error. No Pause 0113 Fixed Media The SAS RAID firmware can not run properly. The user should attempt to Pause reflash the firmware.
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Intel® Server System SC5650HCBRP TPS Appendix F: POST Error Messages and Handling Error Code Error Message Response 852A DIMM_F1 failed Self Test (BIST). Pause 852B DIMM_F2 failed Self Test (BIST). Pause 8540 DIMM_A1 Disabled. Pause 8541 DIMM_A2 Disabled. Pause 8542 DIMM_B1 Disabled. Pause 8543 DIMM_B2 Disabled. Pause 8544 DIMM_C1 Disabled. Pause 8545 DIMM_C2 Disabled. Pause 8546 DIMM_D1 Disabled. Pause 8547 DIMM_D2 Disabled. Pause 8548 DIMM_E1 Disabled.
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Appendix F: POST Error Messages and Handling Intel® Server System SC5650HCBRP TPS Error Code Error Message Response 9246 Mouse component encountered a controller error. No Pause 9266 Local Console component encountered a controller error. No Pause 9268 Local Console component encountered an output error. No Pause 9269 Local Console component encountered a resource conflict error. No Pause 9286 Remote Console component encountered a controller error.
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Intel® Server System SC5650HCBRP TPS Appendix F: POST Error Messages and Handling POST Error Beep Codes The following table lists the POST error beep codes. Prior to system video initialization, the BIOS uses these beep codes to inform users of error conditions. The beep code is followed by a user-visible code on the POST Progress LED’s. Table 128.
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Appendix G: Installation Guidelines Intel® Server System SC5650HCBRP TPS Appendix G: Installation Guidelines 1.
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Intel® Server System SC5650HCBRP TPS Appendix G: Installation Guidelines 5. When EFI Shell is selected as the first device on the BIOS boot option list, some RAID adapters may not enter their configuration screen before the server board boots into EFI Shell. Description In an Intel® Server System SC5650HCBRP based system with EFI shell as first boot device, after users press hot keys to enter RAID adapter configuration screen that hooks option ROM on INT 19h, the system may boot in to EFI shell instead.
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Glossary Intel® Server System SC5650HCBRP TPS Glossary Term Definition ACPI Advanced Configuration and Power Interface AHCI Advanced Host Controller Interface AMT Active Management Technology AP Application Processor APIC Advanced Programmable Interrupt Control ARP Address Resolution Protocol ASIC Application Specific Integrated Circuit ATS Address Translation Technology BBS BIOS Boot Specification BEV Boot Entry Vector BIOS Basic Input / Output System BIST Built-in Self Test BMC
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Intel® Server System SC5650HCBRP TPS Term Glossary Definition FW Firmware FWH Firmware Hub GB 1024 MB GPA Guest Physical Address GPIO General Purpose I/O HPA Host Physical Address HSC Hot-Swap Controller HT Hyper-Threading Hz Hertz (1 cycle / second) I2C Inter-Integrated Circuit Bus IA Intel® Architecture ICH I/O Controller Hub ILM Independent Loading Mechanism IMC Integrated Memory Controller INTR Interrupt IOH I/O HUB IPMB Intelligent Platform Management Bus IPMI Intel
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Glossary Intel® Server System SC5650HCBRP TPS Term Definition NUMA Non-Uniform Memory Access NVSRAM Non-volatile Static Random Access Memory OEM Original Equipment Manufacturer Ohm Unit of electrical resistance OLTT Open-Loop Thermal Throttling PAE Physical Address Extension PCB Print Circuit Board PCI Peripheral Component Interconnect PECI Platform Environment Control Interface PEF Platform Event Filtering PEP Platform Event Paging PMBus Power Management Bus PMI Platform Manage
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Intel® Server System SC5650HCBRP TPS Term Glossary Definition TPS Technical Product Specification UART Universal Asynchronous Receiver / Transmitter UDIMM Unbuffered Dual In-Line Memory Module UDP User Datagram Protocol UHCI Universal Host Controller Interface URS Unified Retention System USB Universal Serial Bus UTC Universal time coordinate VGA Video Graphic Array VID Voltage Identification VLSI Very-large-scale integration VRD Voltage Regulator Down VT Virtualization Technology
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Intel® Server System SC5650HCBRP TPS Reference Documents Reference Documents See the following documents for additional information: 216 Intel® Server Boards S5520HC and S5500HCV, Intel® Server System SC5650HCBRP Specification Update Intel® Server Chassis SC5650 Technical Product Specification Update Intel® Server Board S5520HC Technical Product Specification Update Revision 1.