Intel® 64 Architecture x2APIC Specification Reference Number: 318148-004 March 2010 i
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INTRODUCTION CHAPTER 1 INTRODUCTION 1.1 INTRODUCTION The xAPIC architecture provided a key mechanism for interrupt delivery in many generations of Intel processors and platforms across different market segments. This document describes the x2APIC architecture which is extended from the xAPIC architecture (the latter was first implemented on Intel® Pentium® 4 Processors, and extended the APIC architecture implemented on Pentium and P6 processors).
INTRODUCTION However no modifications are required to PCI or PCIe devices that support direct interrupt delivery to the processors via Message Signaled Interrupts. Similarly no modifications are required to the IOxAPIC. The routing of interrupts from these devices in x2APIC mode leverages the interrupt remapping architecture specified in the Intel Virtualization Technology for Directed I/O, Rev 1.1 specification. Modifications to ACPI interfaces to support x2APIC are described in the ACPI 4.
INTRODUCTION Table 1-1. Description of terminology Term Description APIC ID A unique ID that can identify individual agent in a platform (or clustered configuration). The maximum bit-width supported is 8 bit, versus 32 bits in x2APIC. local xAPIC ID The value configured in the local APIC ID register in xAPIC mode. This is an 8-bit value for xAPIC, and x2APIC in xAPIC mode. Because this is used to specify a target destination in physical delivery mode, it is also referred to as physical xAPIC ID.
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LOCAL X2APIC ARCHITECTURE CHAPTER 2 LOCAL X2APIC ARCHITECTURE 2.1 X2APIC ENHANCEMENTS The key enhancements provided by the x2APIC architecture over xAPIC are the following: • Support for two modes of operation to provide backward compatibility and extensibility for future platform innovations: — In xAPIC compatibility mode, APIC registers are accessed through memory mapped interface to a 4K-Byte page, identical to the xAPIC architecture.
LOCAL X2APIC ARCHITECTURE 2.2 DETECTING AND ENABLING X2APIC A processor’s support to operate its local APIC in the x2APIC mode can be detected by querying the extended feature flag information reported by CPUID. When CPUID is executed with EAX = 1, the returned value in ECX[Bit 21] indicates processor’s support for the x2APIC mode. If CPUID.(EAX=01H):ECX[Bit 21] is set, then the local APIC in the processor supports the x2APIC capability and can be placed into the x2APIC mode.
LOCAL X2APIC ARCHITECTURE bit 10 to zero. Section 2.7, “x2APIC STATE TRANSITIONS” provides a detailed state diagram for the state transitions allowed for the local APIC. 2.3 X2APIC MODE REGISTER INTERFACE In xAPIC mode, the software model for accessing the APIC registers is through a memory mapped interface.
LOCAL X2APIC ARCHITECTURE • The SELF IPI register is available only if x2APIC mode is enabled. The MSR address space is compressed to allow for future growth. Every 32 bit register on a 128- bit boundary in the legacy MMIO space is mapped to a single MSR in the local x2APIC MSR address space. The upper 32-bits of all x2APIC MSRs (except for the ICR) are reserved. Table 2-2.
LOCAL X2APIC ARCHITECTURE Table 2-2. Local APIC Register Address Map Supported by x2APIC (Contd.) MMIO Offset (xAPIC mode) MSR Offset (x2APIC mode) Register Name R/W Semantics 0120H 012H ISR bits 64:95 Read Only. 0130H 013H ISR bits 96:127 Read Only. 0140H 014H ISR bits 128:159 Read Only. 0150H 015H ISR bits 160:191 Read Only. 0160H 016H ISR bits 192:223 Read Only. 0170H 017H ISR bits 224:255 Read Only. 0180H 018H Trigger Mode Register (TMR); bits 0:31 Read Only.
LOCAL X2APIC ARCHITECTURE Table 2-2. Local APIC Register Address Map Supported by x2APIC (Contd.) MMIO Offset (xAPIC mode) MSR Offset (x2APIC mode) Register Name R/W Semantics 0320H 032H LVT Timer Register Read/Write. 0330H 033H LVT Thermal Sensor Register Read/Write. 0340H 034H LVT Performance Monitoring Register Read/Write. 0350H 035H LVT LINT0 Register Read/Write. 0360H 036H LVT LINT1 Register Read/Write. 0370H 037H LVT Error Register Read/Write.
LOCAL X2APIC ARCHITECTURE 2.3.4 Error Handling RDMSR and WRMSR operations to reserved addresses in the x2APIC mode will raise a GP fault. (Note: In xAPIC mode, an APIC error is indicated in the Error Status Register on an illegal register access.) Additionally reserved bit violations cause GP faults as detailed in Section 2.3.3. Beyond illegal register access and reserved bit violations, other APIC errors are logged in Error Status Register. The details on Error Status Register are in Section 2.3.5.4.
LOCAL X2APIC ARCHITECTURE Other semantics change related to reading/writing the ICR in x2APIC mode vs. xAPIC mode are: • Completion of the WRMSR instruction to the ICR does not guarantee that the interrupt to be dispatched has been received by the targeted processors. If the system software usage requires this guarantee, then the system software should explicitly confirm the delivery of the interrupt to the specified targets using an alternate software mechanisms.
LOCAL X2APIC ARCHITECTURE last write to the ESR. Errors are collected regardless of LVT Error mask bit, but the APIC will only issue an interrupt due to the error if the LVT Error mask bit is cleared. In the x2APIC mode, the write of a zero value is enforced. Software writes zero’s to the ESR to clear the error status. Writes of a non-zero value to the Error Status Register in x2APIC mode will raise a GP fault. The layout of ESR is shown in Figure 2-2.
LOCAL X2APIC ARCHITECTURE Table 2-3. MSR/MMIO Interface of a Local x2APIC in Different Modes of Operation MMIO Interface MSR Interface xAPIC mode Available GP Fault x2APIC mode Behavior identical to xAPIC in globally disabled state Available 2.3.
LOCAL X2APIC ARCHITECTURE than 32 bits in its hardware. System software should be agnostic to the actual number of bits that are implemented. All non-implemented bits will return zeros on reads by software. The APIC ID value of FFFF_FFFFH and the highest value corresponding to the implemented bit-width of the local APIC ID register in the system are reserved and cannot be assigned to any logical processor.
LOCAL X2APIC ARCHITECTURE MSR Address: 80DH 31 0 Logical x2APIC ID Figure 2-4. Logical Destination Register in x2APIC Mode In the xAPIC mode, the Destination Format Register (DFR) through MMIO interface determines the choice of a flat logical mode or a clustered logical mode. Flat logical mode is not supported in the x2APIC mode. Hence the Destination Format Register (DFR) is eliminated in x2APIC mode.
LOCAL X2APIC ARCHITECTURE 2.4.3 Interrupt Command Register In x2APIC mode, the layout of the Interrupt Command Register is shown in Figure 25. The lower 32 bits of ICR in x2APIC mode is identical to the lower half of the ICR in xAPIC mode, except bit 12 (Delivery Status) is not used since it is not needed in X2APIC mode.1 The destination ID field is expanded to 32 bits in x2APIC mode.
LOCAL X2APIC ARCHITECTURE debugging; however, software should not assume the value returned by reading the ICR is the last written value. A destination ID value of FFFF_FFFFH is used for broadcast of interrupts in both logical destination and physical destination modes. 2.4.4 Deriving Logical x2APIC ID from the Local x2APIC ID In x2APIC mode, the 32-bit logical x2APIC ID, which can be read from LDR, is derived from the 32-bit local x2APIC ID.
LOCAL X2APIC ARCHITECTURE MSR Address: 083FH 31 8 7 Reserved 0 Vector Figure 2-6. SELF IPI register The SELF IPI register is a write-only register. A RDMSR instruction with address of the SELF IPI register will raise a GP fault. The handling and prioritization of a self-IPI sent via the SELF IPI register is architecturally identical to that for an IPI sent via the ICR from a legacy xAPIC unit.
LOCAL X2APIC ARCHITECTURE Directed EOI capability is intended to enable system software to perform directed EOIs to specific IOxAPICs in the system. System software desiring to perform a directed EOI would do the following: • inhibit the broadcast of EOI message by setting bit 12 of the Spurious Interrupt Vector Register, and • following the EOI to the local x2APIC unit for a level triggered interrupt, perform a directed EOI to the IOxAPIC generating the interrupt by writing to its EOI register.
LOCAL X2APIC ARCHITECTURE x2APIC modes of a local x2APIC unit. Layout of the Local APIC Version register is as shown in Figure 2-8. The Directed EOI feature is supported if bit 24 is set to 1. 31 25 24 23 Reserved 16 15 Max LVT Entry 0 8 7 Reserved Vector Directed EOI Support MMIO Address: FEE0 0030H MSR Address: 0803H Figure 2-8. Local APIC Version Register of x2APIC 2.
LOCAL X2APIC ARCHITECTURE • The local APIC ID is initialized by hardware with a 32 bit ID (x2APIC ID). The lowest 8 bits of the x2APIC ID is the legacy local xAPIC ID, and is stored in the upper 8 bits of the APIC register for access in xAPIC mode. • The following APIC registers are reset to all zeros for those fields that are defined in the xAPIC mode: — IRR, ISR, TMR, ICR, LDR, TPR, Divide Configuration Register (See Chapter 8 of “Intel® 64 and IA-32 Architectures Software Developer’s Manual“, Vol.
LOCAL X2APIC ARCHITECTURE 2.7.1.1 x2APIC After RESET The valid transitions from the xAPIC mode state are: • to the x2APIC mode by setting EXT to 1 (resulting EN=1, EXTD= 1). The physical x2APIC ID (see Figure 2-3) is preserved across this transition and the logical x2APIC ID (see Figure 2-4) is initialized by hardware during this transition as documented in Section 2.4.4.
LOCAL X2APIC ARCHITECTURE A RESET in the disabled state places the x2APIC in the xAPIC mode. All APIC registers (including the local APIC ID register) are initialized as described in Section 2.7.1. An INIT in the disabled state keeps the x2APIC in the disabled state. 2.7.1.
LOCAL X2APIC ARCHITECTURE processor topology. The relevant information in CPUID leaves 01H and 04H do not directly map to individual levels of the topology, but merely relate to the sharing characteristics below different levels. The extended topology enumeration leaf of CPUID provides topology information and data that simplify the algorithm to sort out the processor topology within a physical package from a 32-bit x2APIC ID.
LOCAL X2APIC ARCHITECTURE Table 2-4. CPUID Leaf 0BH Information (Contd.) Initial EAX Value Information Provided about the Processor NOTES: * Software should use this field (EAX[4:0]) to enumerate processor topology of the system. ** Software must not use EBX[15:0] to enumerate processor topology of the system. This value in this field (EBX[15:0]) is only intended for display/diagnostic purposes.
LOCAL X2APIC ARCHITECTURE 2.8.1 Consistency of APIC IDs and CPUID The consistency of physical x2APIC ID in MSR 802H in x2APIC mode and the 32-bit value returned in CPUID.0BH:EDX is facilitated by processor hardware. CPUID.0BH:EDX will report the full 32 bit ID, in xAPIC and x2APIC mode. This allows BIOS to determine if a system has processors with IDs exceeding the 8-bit initial APIC ID limit (CPUID.01H:EBX[31:24]). Initial APIC ID (CPUID.01H:EBX[31:24]) is always equal to CPUID.0BH:EDX[7:0].
LOCAL X2APIC ARCHITECTURE • 2-24 Re-directible/Lowest Priority inter-processor interrupts are not supported in the x2APIC architecture.
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LOCAL X2APIC ARCHITECTURE 2-26
INDEX A APIC. . . . . . . . . . . . . . . . . . . . . . . 1, 2, 1, 6, 7, 9, 17 APIC ID. . . . . . . . . . . . . . . . . . . . . . . . . 3, 11, 14, 23 C CPUID instruction deterministic cache parameters leaf . . . . . . . . 21 D DFR Destination Format Register . . . . . . . . . 3, 12, 18 E EOI End Of Interrupt register. . . . . . . . . . . 1, 4, 7, 15 ESR Error Status Register . . . . . . . . . . . . . . . . . . 5, 7 I ICR Interrupt Command Register . . . 3, 13, 14, 15, 18 Initial APIC ID . . . . . . .
S SELF IPI register . . . . . . . . . . . . . . . . . . . . . . . . 4, 7 SVR Spurious Interrupt Vector Register . . . . . . . . . 16 T TMR Trigger Mode Register . . . . . . . . . . 5, 15, 16, 18 TPR Task Priority Register. . . . . . . . . . . . . . . 4, 7, 18 X x2APIC . . . . . . . . . . . . . . . . . . . . . . . 2, 1, 2, 15, 23 x2APIC ID . . . . . . . . . . 3, 10, 11, 12, 14, 18, 20, 23 x2APIC Mode2, 1, 2, 3, 6, 7, 9, 10, 11, 13, 14, 15, 17, 23 xAPIC . . . . . . . . . . . . . . .
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