Intel® IXF1104 4-Port Gigabit Ethernet Media Access Controller Datasheet The Intel® IXF1104 is a four-port Gigabit MAC that supports IEEE 802.3 10/100/1000 Mbps applications. The IXF1104 supports a System Packet Interface Phase 3 (SPI3) system interface to a network processor or ASIC, and concurrently supports copper and fiber physical layer devices (PHYs).
Applications Load Balancing Systems MultiService Switch Web Caching Appliances Intelligent Backplane Interfaces Edge Router Base Station Controller Redundant Line Cards Base Transceiver Station Serving GRPS Support Node (SGSN) General Packet Radio Services (GGSN) Packet Data Serving Note (PDSN) Digital Subscriber Line Access Multiplexer (DSLAM) Cable Modem Termination System (CMTS) INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS.
Contents Contents 1.0 Introduction..................................................................................................................................19 1.1 1.2 What You Will Find in This Document ................................................................................ 19 Related Documents ............................................................................................................ 19 2.0 General Description ..........................................................
Contents 5.2 5.3 5.4 5.5 5.6 4 5.1.5.1 Speed..................................................................................................... 77 5.1.5.2 Duplex.................................................................................................... 77 5.1.5.3 Copper Auto-Negotiation ....................................................................... 77 5.1.6 Jumbo Packet Support .......................................................................................... 77 5.1.6.
Contents 5.7 5.8 5.9 5.10 5.11 5.12 5.6.2.3 Receiver Operational Overview ........................................................... 104 5.6.2.4 Selective Power-Down ......................................................................... 104 5.6.2.5 Receiver Jitter Tolerance .....................................................................104 5.6.2.6 Transmit Jitter ...................................................................................... 105 5.6.2.7 Receive Jitter ...............
Contents 6.0 Applications ............................................................................................................................... 129 6.1 7.0 Electrical Specifications ........................................................................................................... 131 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 8.0 Document Structure..........................................................................................................
Contents 9.2 9.3 Package Specifics for the IXF1104...................................................................................223 Package Information ......................................................................................................... 224 9.3.1 Example Package Marking .................................................................................. 226 10.0 Product Ordering Information ...........................................................................................
Contents 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 MDIO Write Timing Diagram .................................................................................................... 145 MDIO Read Timing Diagram .................................................................................................... 145 Bus Timing Diagram ................................................................................................................. 146 Write Cycle Diagram....................................
Contents 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 Mode 1 Clock Cycle to Data Bit Relationship ........................................................................... 117 LED_DATA# Decodes .............................................................................................................. 118 LED Behavior (Fiber Mode) ....................................................................
Contents 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 10 Flush TX ($ Port_Index + 0x11)................................................................................................ 166 FC Enable ($ Port_Index + 0x12) ............................................................................................. 167 FC Back Pressure Length ($ Port_Index + 0x13)........
Contents 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 TX FIFO Low Watermark Register Ports 0 - 3 ($0x60A – 0x60D)............................................ 203 TX FIFO MAC Threshold Register Ports 0 - 3 ($0x614 – 0x617) .............................................204 TX FIFO Overflow/Underflow/Out of Sequence Event ($0x61E).............................................. 205 Loop RX Data to TX FIFO (Line-Side Loopback) Ports 0 - 3 ($0x61F) ..........
Contents Revision History Revision Number: 007 Revision Date: March 25, 2004 (Sheet 1 of 5) Page # Description All Globally replaced GBIC with Optical Module Interface. All Globally edited signal names.
Contents Revision Number: 007 Revision Date: March 25, 2004 (Sheet 2 of 5) Page # Description 38 Modified Section 4.3, “Signal Description Tables” [changed heading from “Signal Naming Conventions; added new headings Section 4.1.1, “Signal Name Conventions” and Section 4.1.2, “Register Address Conventions”; and added/enhanced material under headings. 57 Added new Section 4.5, “Multiplexed Ball Connections” with Table 16 “Line Side Interface Multiplexed Balls” and Table 17 “SPI3 MPHY/SPHY Interface”.
Contents Revision Number: 007 Revision Date: March 25, 2004 (Sheet 3 of 5) Page # 14 Description 97 Modified Figure 20 “RX_CTL Behavior” [changed signal names]. 98 Modified Section 5.5, “MDIO Control and Interface” [changed 3.3 us to 3.3 ms in fourth paragraph, third sentence]. 102 Modified/replaced all text under Section 5.6, “SerDes Interface” on page 102 [added Table 29 “SerDes Driver TX Power Levels”]. NA Removed old Section 5.6.2.4 AC/DC Coupling. NA Removed old Section 5.6.2.
Contents Revision Number: 007 Revision Date: March 25, 2004 (Sheet 4 of 5) Page # Description 155 Broke up the old Register Map into Table 59 “MAC Control Registers ($ Port Index + Offset)”, Table 60 “MAC RX Statistics Registers ($ Port Index + Offset)”, Table 61 “MAC TX Statistics Registers ($ Port Index + Offset)”, Table 62 “PHY Autoscan Registers ($ Port Index + Offset)”, Table 63 “Global Status and Configuration Registers ($ 0x500 - 0X50C)”, Table 64 “RX FIFO Registers ($ 0x580 - 0x5BF)”, Table 65 “
Contents Revision Number: 007 Revision Date: March 25, 2004 (Sheet 5 of 5) Page # Description 206 Modified Table 136 “Loop RX Data to TX FIFO (Line-Side Loopback) Ports 0 - 3 ($0x61F)” [renamed heading and bit name]. 207 Modified Table 138 “TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 – 0x624)” [renamed from TX FIFO Number of Frames Removed Ports 3 - 0].
Contents Revision Number: 006 Revision Date: August 21, 2003 (Sheet 2 of 2) Page # Description 140 Modified Table 53 “IPG Receive and Transmit Time Register (Addr: Port_Index + 0x0A – + 0x0C)”. 143 Modified Table 60 “Short Runts Threshold Register (Addr: Port_Index + 0x14)”. 143 Modified Table 61 “Discard Unknown Control Frame Register (Addr: Port_Index + 0x15)”. 143 Modified Table 62 “RX Config Word Register Bit Definition (Addr: Port_Index + 0x16)”.
Contents 18 Datasheet Document Number: 278757 Revision Number: 007 Revision Date: March 25, 2004
IXF1104 4-Port Gigabit Ethernet Media Access Controller 1.0 Introduction This document contains information on the Intel® IXF1104 4-Port 10/100/1000 Mbps Ethernet Media Access Controller (MAC). 1.1 What You Will Find in This Document This document contains the following sections: • Section 2.0, “General Description” on page 20 provides the block diagram system architecture. • Section 3.0, “Ball Assignments and Ball List Tables” on page 22 shows the signal naming methodology and signal descriptions.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 2.0 General Description The IXF1104 provides up to a 4.0 Gbps interface to four individual 10/100/1000 Mbps full-duplex or 10/100 Mbps half-duplex-capable Ethernet Media Access Controllers (MACs). The network processor is supported through a System Packet Interface Phase 3 (SPI3) media interface.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Figure 2 illustrates the IXF1104 internal architecture. Figure 2.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 3.0 Ball Assignments and Ball List Tables 3.1 Ball Assignments See Figure 3, Table 1 “Ball List in Alphanumeric Order by Signal Name” on page 23, and Table 2 “Ball List in Alphanumeric Order by Ball Location” on page 29 for the IXF1104 ball assignments. Figure 3.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 3.2 Ball List Tables 3.2.1 Balls Listed in Alphabetic Order by Signal Name Table 1 shows the ball locations and signal names arranged in alphanumeric order by signal name. The following table notes relate to Table 1 and Table 2: 1. GMII Ball Connection: See Table 16 for connection in RGMII or fiber mode. 2. SPI3 Ball Connection: See Table 17 for proper SPHY and MPHY connection. 3.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Signal Name Ball Location Signal Name Ball Location Signal Name Ball Location GND R2 GND A21 NC P18 GND R6 GND AD21 NC R5 GND 2 I C_CLK R9 2 L23 NC R10 3 L24 NC R12 M24 NC R13 GND R11 I C_DATA_0 GND R14 I2C_DATA_13 GND R16 2 3 N24 NC R15 2 3 P24 NC R20 I C_DATA_2 I C_DATA_3 GND R19 GND R23 LED_CLK K24 NC T6 GND T10 LED_DATA M22 NC T7 GND T15 LED_LATCH L22 NC T8 W24 NC T9 GND U4
IXF1104 4-Port Gigabit Ethernet Media Access Controller Signal Name Ball Location Signal Name Ball Location Signal Name Ball Location No Ball AC1 RDAT_262 G20 RX_ER_01 W5 AC2 2 G21 1 Y12 RX_ER_2 1 AA22 1 U20 No Ball No Ball AC23 2 RDAT_28 2 G22 RX_ER_1 No Ball AC24 RDAT_29 G23 RX_ER_3 No Ball AD1 RDAT_302 G24 RX_LOS_INT3 AD2 2 RDAT_31 AD3 2 No Ball No Ball RENB_0 2 F24 A13 P19 RX_N_0 3 R22 RX_N_1 3 U22 3 R24 No Ball AD22 RENB_1 A18 RX_N_2 No Bal
IXF1104 4-Port Gigabit Ethernet Media Access Controller Signal Name Ball Location Signal Name Ball Location Signal Name Ball Location RXD5_11 AC11 TDAT222 F9 TX_EN_01 AB2 C8 1 Y8 1 AC22 1 RXD5_2 1 RXD5_3 1 RXD6_0 1 RXD6_11 RXD6_2 1 RXD6_3 1 RXD7_0 1 RXD7_11 RXD7_2 1 RXD7_3 1 2 V20 T17 2 TDAT23 2 TDAT24 G4 TX_EN_1 TX_EN_2 AB5 2 TDAT25 G5 TX_EN_3 V12 AA11 TDAT262 G6 TX_ER_01 W1 G7 1 AD6 1 AD17 1 V19 T18 2 TDAT27 2 TDAT28 G8 TX_ER_1 TX_ER_2 AC5
IXF1104 4-Port Gigabit Ethernet Media Access Controller Signal Name Ball Location Signal Name Ball Location Signal Name Ball Location TXD4_11 AA7 UPX_DATA5 N5 VDD H10 TXD4_2 1 AD16 UPX_DATA6 M5 VDD H15 TXD4_3 1 AA14 UPX_DATA7 K5 VDD J11 TXD5_0 1 AC3 UPX_DATA8 P5 VDD J14 TXD5_11 AB8 UPX_DATA9 L6 VDD K4 TXD5_2 1 AB19 UPX_DATA10 L7 VDD K8 TXD5_3 1 Y15 UPX_DATA11 N7 VDD K17 TXD6_0 1 AB4 UPX_DATA12 L8 VDD K21 TXD6_11 AD8 UPX_DATA13 H9 VDD L9 TXD6
IXF1104 4-Port Gigabit Ethernet Media Access Controller Signal Name Ball Location Signal Name Ball Location VDD2 F8 VDD5 N12 VDD2 F12 VDD5 T12 VDD2 H2 VDD5 U2 VDD2 H6 VDD5 U6 VDD2 J12 VDD5 W8 VDD2 M2 VDD5 W12 VDD2 M6 VDD5 AA2 VDD2 M9 VDD5 AC4 VDD2 M12 VDD5 AC8 VDD3 B13 VDD5 AC12 VDD3 B17 VDD3 B21 VDD3 D23 VDD3 F13 VDD3 F17 VDD3 H19 VDD3 H23 VDD3 J13 VDD3 M13 VDD3 M16 VDD3 M19 VDD3 M23 VDD4 N13 VDD4 N16 VDD4 N19 VDD4 N23 VDD4 T13
IXF1104 4-Port Gigabit Ethernet Media Access Controller 3.2.2 Balls Listed in Alphabetic Order by Ball Location Table 2 shows the ball locations and signal names arranged in order by ball location. Table 2.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Location Signal Name Ball Location Signal Name Ball Location Signal Name E6 TDAT172 F20 RPRTY_32 H10 VDD E7 TDAT18 2 F21 VDD H11 UPX_DATA19 TDAT19 2 F22 H12 GND E9 TDAT20 2 F23 GND H13 GND E10 TDAT212 F24 RDAT_312 H14 UPX_DATA24 E11 TERR_22 G1 TDAT92 H15 VDD H16 UPX_DATA29 E8 E12 NC G2 2 RVAL_3 2 2 TDAT10 2 E13 RSX G3 TPRTY_1 H17 GND E14 RDAT_62 G4 TDAT242 H18 NC G5 2 H19 VDD3
IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Location Signal Name Ball Location Signal Name Ball Location Signal Name J24 TDI L14 VDD N4 GND L15 GND N5 UPX_DATA5 K1 TERR_1 K2 GND L16 VDD N6 VDD5 K3 UPX_DATA1 L17 UPX_DATA31 N7 UPX_DATA11 K4 VDD L18 NC N8 GND K5 UPX_DATA7 L19 NC N9 VDD5 K6 GND L20 GND N10 UPX_DATA15 K7 NC L21 NC N11 GND K8 VDD L22 LED_LATCH N12 VDD5 K9 GND L23 I2C_CLK K10 2 UPX_DATA17 L24 I C_DATA_0 N13 VDD
IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Location Signal Name Ball Location Signal Name Ball Location Signal Name P18 NC T8 NC U22 RX_N_13 T9 NC U23 VDD4 T10 GND U24 RX_P_33 3 P19 RX_LOS_INT P20 TXPAUSE_ADD1 P21 TXPAUSE_ADD2 T11 VDD V1 UPX_ADD6 P22 RX_P_03 T12 VDD5 V2 UPX_ADD7 T13 VDD4 V3 UPX_ADD8 P23 3 TX_FAULT_INT 2 3 P24 I C_DATA_3 T14 VDD V4 RXC_01 R1 UPX_ADD3 T15 GND V5 RX_DV_01 R2 GND T16 RXD4_31 V6 UPX_RD_L 1 R3 UPX
IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Location Signal Name Ball Location Signal Name Ball Location Signal Name W12 VDD5 AA2 VDD5 AB16 AVDD1P8_2 AB17 COL_31 AB18 NC AB19 TXD5_21 AB20 TXD0_21 W13 VDD4 AA3 TXD3_0 W14 TXD7_31 AA4 GND 1 W15 GND AA5 CRS_0 W16 TX_P_23 AA6 VDD W17 VDD4 AA7 TXD4_1 AB21 TXD1_21 W18 RXD3_31 AA8 GND AB22 TXD2_21 W19 GND AA9 CRS_11 AB23 TXD3_21 W20 RXD7_21 AA10 VDD AB24 No Ball W21 VDD W22 RXD4_2 W23
IXF1104 4-Port Gigabit Ethernet Media Access Controller Ball Location Signal Name AD6 TX_ER_11 AD7 TXC_11 AD8 TXD6_11 AD9 TXD3_11 AD10 RXD4_11 AD11 RXC_11 AD12 SYS_RST_L AD13 TX_P_13 AD14 TX_N_13 AD15 COL_21 AD16 TXD4_21 AD17 TX_ER_21 AD18 TX_N_33 AD19 CLK125 AD20 AVDD2P5_1 AD21 GND AD22 No Ball AD23 No Ball AD24 No Ball Datasheet Document Number: 278757 Revision Number: 007 Revision Date: March 25, 2004 34
IXF1104 4-Port Gigabit Ethernet Media Access Controller 35 Datasheet Document Number: 278757 Revision Number: 007 Revision Date: March 25, 2004
IXF1104 4-Port Gigabit Ethernet Media Access Controller 4.0 Ball Assignments and Signal Descriptions 4.1 Naming Conventions 4.1.1 Signal Name Conventions Signal names begin with a Signal Mnemonic, and can also contain one or more of the following designations: a differential pair designation, a serial designation, a port designation (RGMII interface), and an active low designation. Signal naming conventions are as follows: Differential Pair + Port Designation.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 4.2 Interface Signal Groups This section describes the IXF1104 signals in groups according to the associated interface or function. Figure 4 shows the various interfaces available on the IXF1104. Figure 4.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 4.3 Signal Description Tables The I/O signals, power supplies, or ground returns associated with each IXF1104 connection ball are described in Table 3 through Table 14. Table 3.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 3. SPI3 Interface Signal Descriptions (Sheet 2 of 8) Signal Name MPHY SPHY Ball Designator Type Standard Description Transmit Parity. TPRTY_0 TPRTY_0 TPRTY_1 TPRTY_2 TPRTY_3 D5 G3 B9 J6 Input 3.3 V LVTTL TPRTY indicates odd parity for the TDAT bus. TPRTY is valid only when a channel asserts either TENB or TSX.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 3. SPI3 Interface Signal Descriptions (Sheet 3 of 8) Signal Name MPHY SPHY Ball Designator Type Standard Description TMOD[1:0] Transmit Word Modulo. 32-bit Multi-PHY mode: TMOD[1:0] indicates the valid data bytes of TDAT[31:0]. During transmission, TMOD[1:0] should always be “00” until the last double word is transferred on TDAT[31:0]. TMOD[1:0] specifies the valid bytes of TDAT when TEOP is asserted: TMOD1 TMOD0 NA D9 A6 Input 3.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 3. SPI3 Interface Signal Descriptions (Sheet 4 of 8) Signal Name MPHY SPHY Ball Designator Type Standard Description DTPA_0:3 Direct Transmit Packet Available. A direct status indication for transmit FIFOs of ports 0:3. DTPA_0 DTPA_1 DTPA_2 DTPA_3 DTPA_0 DTPA_1 DTPA_2 DTPA_3 D3 L1 A9 J7 Output 3.3 V LVTTL When High, DTPA indicates that the amount of data in the TX FIFO is below the TX FIFO High watermark.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 3. SPI3 Interface Signal Descriptions (Sheet 5 of 8) Signal Name MPHY SPHY Ball Designator Type Standard Description Polled-PHY Transmit Packet Available. PTPA allows the polling of the port selected by the TADR address bus. PTPA PTPA B11 Output 3.3 V LVTTL When High, PTPA indicates that the amount of data in the TX FIFO is below the TX FIFO High watermark.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 3. SPI3 Interface Signal Descriptions (Sheet 6 of 8) Signal Name MPHY SPHY RDAT7 RDAT6 RDAT5 RDAT4 RDAT3 RDAT2 RDAT1 RDAT0 RDAT7_0 RDAT6_0 RDAT5_0 RDAT4_0 RDAT3_0 RDAT2_0 RDAT1_0 RDAT0_0 Ball Designator F14 E14 D14 C13 C14 B14 A14 A15 Type Standard Description Receive Data Bus. Output 3.3 V LVTTL RDAT carries payload data and in-band addresses from the IXF1104.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 3. SPI3 Interface Signal Descriptions (Sheet 7 of 8) Signal Name MPHY SPHY Ball Designator Type Standard Description Receive Error. RERR_0 RERR_0 RERR_1 RERR_2 RERR_3 A16 G17 D20 H20 Output 3.3 V LVTTL RERR indicates that the current packet is in error. RERR is only asserted when REOP is asserted. Conditions that can cause RERR to be set include FIFO overflow, CRC error, code error, and runt or giant packets.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 3. SPI3 Interface Signal Descriptions (Sheet 8 of 8) Signal Name MPHY SPHY Ball Designator Type Standard Description Receive End of Packet. REOP_0 REOP_0 REOP_1 REOP_2 REOP_3 C16 D18 C23 J19 REOP indicates the end of a packet when asserted with RVAL. Output 3.3 V LVTTL 32-bit Multi-PHY mode: REOP_0 covers all 32 bits. 4 x 8 Single-PHY mode: The REOP_0:3 bits correspond to the RDAT[7:0]_n channels.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 4. SerDes Interface Signal Descriptions Signal Name Ball Designator Type Standard Description TX_P_0 TX_P_1 TX_P_2 TX_P_3 Y13 AD13 W16 AC18 Output SerDes Transmit Differential Output, Positive. TX_N_0 TX_N_1 TX_N_2 TX_N_3 Y14 AD14 Y16 AD18 Output SerDes Transmit Differential Output, Negative. RX_P_0 RX_P_1 RX_P_2 RX_P_3 P22 V22 T24 U24 Input SerDes Receive Differential Input, Positive.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 5.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 5. GMII Interface Signal Descriptions (Sheet 2 of 2) Signal Name Ball Designator RXD7_0 RXD6_0 RXD5_0 RXD4_0 RXD3_0 RXD2_0 RXD1_0 RXD0_0 AC5 AB5 Y5 Y6 Y7 W7 V7 V8 RXD7_1 RXD6_1 RXD5_1 RXD4_1 RXD3_1 RXD2_1 RXD1_1 RXD0_1 Y10 AA11 AC11 AD10 W9 W11 Y11 Y9 Type Standard Description Receive Data: Each bus carries eight data bits [7:0] of the received data stream. Input 2.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 6. RGMII Interface Signal Descriptions (Sheet 1 of 2) Ball Designator Type Standard TXC_0 TXC_1 TXC_2 TXC_3 AA1 AD7 AC20 AB14 Output 2.5 V CMOS TD3_0 TD2_0 TD1_0 TD0_0 AA3 Y3 Y2 Y1 TD3_1 TD2_1 TD1_1 TD0_1 AD9 AB9 AB7 AC7 Signal Name AB23 AB22 AB21 AB20 TD3_3 TD2_3 TD1_3 TD0_3 V17 V16 V15 V14 Source Synchronous Transmit Clock. This clock is supplied synchronous to the transmit data bus in either RGMII or GMII mode. Transmit Data.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 6. RGMII Interface Signal Descriptions (Sheet 2 of 2) Signal Name Ball Designator RD3_0 RD2_0 RD1_0 RD0_0 Y7 W7 V7 V8 RD3_1 RD2_1 RD1_1 RD0_1 W9 W11 Y11 Y9 Type Y23 Y22 Y21 Y20 RD3_3 RD2_3 RD1_3 RD0_3 W18 Y19 Y18 Y17 Description Receive Data. Input RD3_2 RD2_2 RD1_2 RD0_2 Standard 2.5 V CMOS Bits [3:0] are clocked on the rising edge of RXC. Bits [7:4] are clocked on the falling edge of RXC.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 7.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 8. Transmit Pause Control Interface Signal Descriptions Ball Designator Type Standard TXPAUSEADD2 TXPAUSEADD1 TXPAUSEADD0 P21 P20 N20 Input 2.5 V CMOS TXPAUSEADD[2:0] is the port selection address for pause frame insertion. TXPAUSEFR T20 Input 2.5 V CMOS TX Pause Interface Strobe. Signal Name Table 9.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 9. Optical Module Interface Signal Descriptions (Sheet 2 of 2) Signal Name Ball Designator Type Standard Description Transmitter Fault Interrupt. TX_FAULT_INT is an open drain interrupt output that signals a TX_FAULT condition. TX_FAULT_INT P23 Open Drain Output* 2.5 V CMOS NOTE: An external pull-up resistor is required for proper operation.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 11. LED Interface Signal Descriptions Ball Designator Type Standard LED_CLK K24 Output 2.5 V CMOS LED_CLK is the clock output for the LED block. LED_DATA M22 Output 2.5 V CMOS LED_DATA is the data output for the LED block. LED_LATCH L22 Output 2.5 V CMOS LED_LATCH is the latch enable for the LED block. Signal Name Description Table 12. JTAG Interface Signal Descriptions Ball Designator Type Standard TCLK J22 Input 2.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 14.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 4.4 Ball Usage Summary Table 15.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 4.5 Multiplexed Ball Connections 4.5.1 GMII/RGMII/SerDes/OMI Multiplexed Ball Connections Table 16 lists the balls used for the line-side interfaces (GMII, RGMII, SerDes/OMI) and provides a guide to connect these balls. Some of these balls are multiplexed depending on the mode of operation selected for that port. Note: Do not connect any balls marked as unused (NC). Table 16.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 16. Line Side Interface Multiplexed Balls (Sheet 2 of 2) Copper Mode Fiber Mode Unused Port Ball Designator GMII Signal RGMII Signal Optical Module/ SerDes Signal NC NC TX_FAULT_INT2 NC P23 NC NC RX_LOS_INT2 NC P19 MOD_DEF_INT NC N22 NC NC W24 MDIO NC NC V21 NC I2C_CLK NC L23 NC L24 NC 2 NC MDC MDIO MDC 2 2 NC NC 2 2 I C_DATA_0:3 NC M24 N24 P24 1.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 17. SPI3 MPHY/SPHY Interface (Sheet 2 of 3) SPI3 Signals Ball Number MPHY Comments SPHY TERR_0 TERR_0 A8 GND TERR_1 K1 MPHY: Use TERR_0 as the TERR signal. GND TERR_2 E11 SPHY: Each port has its own dedicated TERR_n signal GND TERR_3 J8 TSOP_0 TSOP_0 C7 GND TSOP_1 E3 MPHY: Use TSOP_0 as the TSOP signal. GND TSOP_2 C10 SPHY: Each port has a dedicated TSOP_n signal.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 17. SPI3 MPHY/SPHY Interface (Sheet 3 of 3) SPI3 Signals Ball Number MPHY 4.6 Comments SPHY RERR_0 RERR_0 A16 NC RERR_1 G17 MPHY: Use RERR_0 as the RERR signal. NC RERR_2 D20 SPHY: Each port has a dedicated RERR_n signal NC RERR_3 H20 RVAL_0 RVAL_0 C15 NC RVAL_1 B18 MPHY: Use RVAL_0 as the RVAL signal. NC RVAL_2 E19 SPHY: Each port has a dedicated RVAL_n signal.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 18. Definition of Output and Bi-directional Balls During Hardware Reset (Sheet 2 of 2) Interface JTAG Ball Name Ball Reset State TDO 0x0 MDIO High Z MDC 0x0 Comment – Bi-directional MDIO UPX_DATA[31:0] High Z – Bi-directional CPU LED GMII/RGMII RGMII UPX_RDY_L 0X1 Open-drain output, requires an external pull-up LED_CLK 0x0 – LED_DATA 0x0 – LED_LATCH 0x0 – Fiber mode is the default. Copper interfaces are disabled.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 4.7 Power Supply Sequencing Follow the power-up and power-down sequences described in this section to ensure correct IXF1104 operation. The sequence described in Section 4.7 covers all IXF1104 digital and analog supplies. Caution: 4.7.1 Failure to follow the sequence described in this section might damage the IXF1104. Power-Up Sequence Ensure that the 1.8 V analog and digital supplies are applied and stable prior to application of the 2.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 19. Power Supply Sequencing Power Supply Power-Up Order VDD, AVDD1P8_1, AVDD1P8_2 First VDD4, VDD5, AVDD2P5_1, AVDD2P5_2 Second Time Delta to Next Supply1 Notes 0 1.8 V supplies 10 µs 2.5 V supplies 1. The value of 10 µs given is a nominal value only. The exact time difference between the application of the 2.5 V analog supply is determined by a number of factors, depending on the power management method used.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Figure 6. Analog Power Supply Filter Network 2.5 or 1.8 V VDD R 0.1 µF Analog Power Ball 0.1 µF Table 21. Analog Power Balls Signal Name 64 Ball Designator A20 Comments AVDD1P8_1 A5 AVDD2P5_1 AD20 AVDD1P8_2 AB16 T23 Need to provide a filter (see Figure 6). AVDD2P5_2 U14 R18 R: AVDD1P8_2 and AVDD2P5_2 = 1.0 Ω resistor. Need to provide a filter (see Figure 6). R: AVDD1P8_1 and AVDD2P5_1 = 5.6 Ω resistor.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller 5.0 Functional Descriptions 5.1 Media Access Controller (MAC) The IXF1104 main functional block consists of four independent 10/100/1000 Mbps Ethernet MACs, which support interfaces for fiber and copper connectivity.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller CRC is removed optionally from receive packets after validation, and is not forwarded to SPI3. Packets with a bad CRC are marked, counted in the statistics block, and may be optionally dropped. A bad packet may be signaled with RERR on the SPI3 interface if it is not dropped. The MAC operates only in full-duplex mode at 1000 Mbps rates on both SerDes and GMII interface connections.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller 5.1.1.3.2 Filter on Multicast Packet Match This feature is enabled when bit 1 of the “RX Packet Filter Control ($ Port_Index + 0x19)" = 1. Any frame received in this mode that does not match the Port Multicast Address (reserved multicast address recognized by MAC) is marked by the MAC to be dropped. The frame is dropped if the appropriate bit in the “RX FIFO Errored Frame Drop Enable ($0x59F)" = 1.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller When the CRC Error Pass Filter bit = 0 (“RX Packet Filter Control ($ Port_Index + 0x19)”), it takes precedence over the other filter bits. Any packet (Pause, Unicast, Multicast or Broadcast packet) with a CRC error will be marked as a bad frame when the CRC Error Pass Filter bit = 0. Table 22.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller The IXF1104 MAC implements the IEEE 802.3x standard RX FIFO threshold-based Flow Control in copper and fiber modes. When appropriately programmed, the MAC can both generate and respond to IEEE standard pause frames in full-duplex operation. The IXF1104 also supports externally triggered flow control through the Transmit Pause Control interface.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Figure 7. Packet Buffering FIFO MDI SPI3 Interface High Watermark TX FIFO Data Flow TX Side MAC Data Flow RX Side MAC MAC Transfer Threshold Low Watermark High Watermark RX FIFO Low Watermark RX FIFO High 802.3 Flow Control TXPAUSEFR (External Strobe) 802.3x Pause Frame Generation B3231-01 5.1.2.1.1 Pause Frame Format PAUSE frames are MAC control frames that are padded to the minimum size (64 bytes).
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Figure 9. PAUSE Frame Format 46 Number of bytes 6 Preamble 1 6 S F D DA* or 01-80C2-0000-01 6 SA 2 2 2 42 4 88-08 Pause Opcode (00-01) Pause Length Pad (with 0s) FCS 64 Bytes Note: In the Intel® IXF1104 architecture, the TX block of the MAC sets this as the pause multicast address. The RX interface of the MAC will process this as the pause multicast or the MAC address. B3218-01 An IEEE 802.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller 5.1.2.1.3 Response to Received PAUSE Command Frames When Flow Control is enabled in the receive direction (bit 0 in the “FC Enable ($ Port_Index + 0x12)"), the IXF1104 responds to PAUSE Command frames received from the link partner as follows: 1. The IXF1104 checks the entire frame to verify that it is a valid PAUSE control frame addressed to the Multicast Address 01-80-C2-00-00-01 (as specified in IEEE 802.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Table 23. Valid Decodes for TXPAUSEADD[2:0] TXPAUSEADD_2:0 Operation of TX Pause Control Interface 0x0 Transmits a PAUSE frame on every port with a pause_time = ZERO (XON) (Cancels all previous pause commands). 0x1 Transmits a PAUSE frame on port 0 with pause_time equal to the value programmed in the port 0 “FC TX Timer Value ($ Port_Index + 0x07)" (XOFF).
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller 5.1.3 Mixed-Mode Operation The Intel® IXF1104 gives the user the option of configuring each port for 10/100 Mbps half-duplex copper, 10/100/1000 Mbps full-duplex copper, or 1000 Mbps full-duplex fiber operation. This gives the Intel® IXF1104 the ability to support both copper and fiber operation line-side interfaces operating at the same time within a single device. (Refer to Figure 16 “Line Side Interface Multiplexed Balls” on page 57.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Table 24.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller When configured for fiber mode, the full set of Optical Module interface control and status signals is presented through re-use of GMII signals on a per-port basis (see Table 4.5 “Multiplexed Ball Connections” on page 57). Fiber mode supports only full-duplex Gigabit operation. 5.1.4.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller user. The RGMII interface supports operation at 10/100/1000 Mbps when a full-duplex link is established, and supports 10/100 Mbps when a half-duplex link is established. The GMII interface only supports a 1000 Mbps full-duplex link. 5.1.5.1 Speed The copper MAC supports 10 Mbps, 100 Mbps, and 1000 Mbps. All required speed adjustments, clocks, etc., are supplied by the MAC.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller The register should be programmed to 0x2667 for the 9.6 KB length jumbo frame, optimized for the IXF1104. The RMON counters are also implemented for jumbo frame support as follows: 5.1.6.1 Rx Statistics • • • • • • • • 5.1.6.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller 5.1.7 Packet Buffer Dimensions 5.1.7.1 TX and RX FIFO Operation 5.1.7.1.1 TX FIFO The IXF1104 TX FIFOs are implemented with 10 KB for each channel. This provides enough space for at least one maximum size (10 KB) packet per-port storage and ensures that no under-run conditions occur, assuming that the sending device can supply data at the required data rate.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Table 25.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Table 25.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller 5.1.8.2 IXF1104 Advantages The following lists additional IXF1104 registers that support features not documented in RMON: • • • • • MAC (flow) control frames VLAN Tagged Sequence Errors Symbol Errors CRC Error These additional counters allow for differentiation beyond standard RMON probes. Note: In fiber mode, a packet transfer with an invalid 10-bit symbol does not always update the statistics registers correctly.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller • SPHY or 4 x 8 mode (four individual 8-bit data buses) 5.2.1 MPHY Operation The MPHY operation mode is selected when bit 21 of the“SPI3 Transmit and Global Configuration ($0x700)” is set to 0 and bit 7 of the “SPI3 Receive Configuration ($0x701)" is set to 1. Data Path The IXF1104 SPI3 interface has a single 32-bit data path in the MPHY configuration mode (see Figure 13).
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller 5.2.2.1 Transmit Timing In MPHY mode a packet transmission starts with the TSX signal indicating port address information is on the data bus. The next clock cycle TENB and TSOP indicate present data on the bus is the first word in the packet and all subsequent clocks will contain valid data as long as TENB is active or until TEOP is asserted. Data transmission can be temporally halted when TENB goes high then resumed when TENB is low.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Figure 12. MPHY Receive Logical Timing TFCLK RENB RSX RSOP REOP RERR RMOD[1:0] RDAT[31:0] 0000 B1-B4 B5-B8 B9-B12 B13-B16 B45-B48 B52-B55 B56-B57 B0001 RPRTY RVAL B3217-01 Figure 13.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller 5.2.2.3 Clock Rates In MPHY mode, the TFCLK and RFCLK can be independent of each other. TFCLK and RFCLK should be common to the IXF1104 and the Network Processor. The IXF1104 requires a single clock source for the transmit path and a single clock source for the receive path. To allow all four IXF1104 ports to operate at 1 Gbps, the IXF1104 is designed to allow this interface to be overclocked.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller 5.2.2.6 SPHY Logical Timing SPI3 interface AC timing for SPHY can be found in Section 7.2, “SPI3 AC Timing Specifications” on page 136. Logical timing in the following diagrams illustrates all signals associated with SPHY mode. SPHY mode is similar to MPHY mode except the following signals are not used: • • • • • 5.2.2.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Figure 15.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Figure 16.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller 5.2.2.8.2 Parity The IXF1104 can be odd or even (the IXF1104 defaults to odd) when calculating parity on the data bus. This can be changed to accommodate even parity if desired, and can be set for transmit and receive ports independently. The RX and TX parity sense bits have a direct relationship to the port parity in SPHY mode.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller The IXF1104 provides the following three types of TPA signals: • Dedicated per port Direct Transmit Packet Available (DTPA) • Selected-PHY Transmit Packet Available (STPA), which is based on the current in-band port address in MPHY mode. • Polled-PHY Transmit packet Available (PTPA), which provides FIFO information on the port selected by the TADR[1:0] signals.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller 5.2.3 Pre-Pending Function The IXF1104 implements a pre-pending feature to allow 1518-byte Ethernet packets to be prepadded with two additional bytes of data so that the packet becomes low-word aligned. The 2-byte pre-pend value is all zeros and is inserted before the destination address of the packet being prepended. This value is fixed and cannot be changed.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller TXC_3:0 TXD[7:0]_0 TXD[7:0]_1 TXD[7:0]_2 TXD[7:0]_3 TX_EN_3:0 TX_ER_3:0 RXC_3:0 RXD[7:0]_0 RXD[7:0]_1 RXD[7:0]_2 RXD[7:0]_3 RX_EN_3:0 RX_ER_3:0 CRS_3:0 COL_3:0 TXC_3:0 TXD[7:0]_0 TXD[7:0]_1 TXD[7:0]_2 TXD[7:0]_3 TX_EN_3:0 TX_ER_3:0 RXC_3:0 RXD[7:0]_0 RXD[7:0]_1 RXD[7:0]_2 RXD[7:0]_3 RX_EN_3:0 RX_ER_3:0 CRS_3:0 COL_3:0 Quad PHY Device Intel® IXF1104 Media Access Controller Figure 17. MAC GMII Interconnect B3203-01 5.3.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Table 26. GMII Interface Signal Definitions IXF1104 Signal GMII Standard Signal Source TXC_0 TXC_1 TXC_2 Transmit Reference Clock: GTX_CLK IXF1104 TXD[7:0]_0 TXD[7:0]_2 125 MHz for Gigabit operation. MII operation for 10/100 Mbps operation is not supported.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller 5.4 Reduced Gigabit Media Independent Interface (RGMII) The IXF1104 supports the RGMII interface standard as defined in the RGMII Version 1.2 specification. The RGMII interface is an alternative to the IEEE 802.3u MII interface. The RGMII interface is intended as an alternative to the IEEE 802.3u MII and the IEEE 802.3z GMII.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller 5.4.2 Timing Specifics The IXF1104 RGMII complies with RGMII Rev1.2a requirements. Table 27 provides the timing specifics. 5.4.3 TX_ER and RX_ER Coding To reduce interface power, the transmit error condition (TX_ER) and the receive error condition (RX_ER) are encoded on the RGMII interface to minimize transitions during normal network operation (refer to Table 28 on page 96 for the encoding method).
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Figure 19. TX_CTL Behavior Valid Frame TXC_0:3 (at Transmitter) TD[3:0]_0:3 TX_CTL_0:3 TD[3:0] TX_EN=True TD[7:4] TX_ER=False TX_EN=False TX_ER=False End-of-Frame Frame with Error TXC_0:3 (at Transmitter) TD[3:0]_0:3 TX_CTL_0:3 TD[3:0] TD[7:4] TX_EN=True TX_ER=False TX_EN=False TX_ER=False End-of-Frame B0616-02 Figure 20.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller 5.4.3.1 In-Band Status Carrier Sense (CRS) is generated by the PHY when a packet is received from the network interface. CRS is indicated when: • RXDV = true. • RXDV = false, RXERR = true, and a value of FF exists on the RXD[7:0] bits simultaneously. • Carrier Extend, Carrier Extend Error, or False Carrier occurs (please reference the HewlettPackard* Version 1.2a RGMII Specification for details.).
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller 5.5.1 MDIO Address The 5-bit PHY address for the MDIO transactions can be set in the “MDIO Single Command ($0x680)". Bits 5:2 of the PHY address are fixed to a value of 0. Bits 1 and 0 are programmable in bits 9 and 8 of “MDIO Single Command ($0x680)". 5.5.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Refer to Figure 42 “MDC Low-Speed Operation Timing” on page 144 for the low frequency MDC timing diagram. 5.5.5 Management Frames The Management Interface serializes the external register access information into the format specified by IEEE 802.3, Section 22.2.4.5 (see Figure 21). Figure 21.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Figure 22.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller 5.5.8 Autoscan Operation The autoscan function allows the 32 registers in each external PHY (up to four) to be stored internally in the IXF1104. Autoscan is enabled by setting bit 1 of the MDI Control register. When enabled, autoscan runs continuously, reading each PHY register. When a PHY register access is instigated through the CPU interface, the current autoscan register Read is completed before the CPU register access starts.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller speed SerDes and are capable of operating in either an AC- or DC-coupled environment. AC coupling is recommended for this interface to ensure that the correct input bias current is supplied at the receiver. The SerDes receive interface receives serialized data at 1.25 GHz. The interface is differential with two signals for the receive operation. The equalizer receives a differential signal that is equalized for the assumed media channel.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Table 29. SerDes Driver TX Power Levels DRVPWRx[3] DRVPWRx[2] DRVPWRx[1] DRVPWRx[0] Normalized Driver Power Setting Driver Power 1 0 1 1 2.0 20 mA 1 1 0 1 1.0 10 mA 1 1 1 0 0.5 5 mA NOTE: All other values are reserved. 5.6.2.3 Receiver Operational Overview The receiver structure performs Clock and Data Recovery (CDR) on the incoming serial data stream.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Figure 23. SerDes Receiver Jitter Tolerance Sinusoidal Jitter Mask 16 ui 375 Hz 16 ui 10+1 Peak-to-Peak Amplitude (UI) 22.5836 kHz 8.5 ui 0 1.9195 MHz 0.1 ui 10-1 100 101 102 103 104 105 106 107 Frequency B0745-02 Note: 5.6.2.6 UI = Unit interval.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller 5.7 Optical Module Interface This section describes the connection of the IXF1104 ports to an Optical Module Interface and details the minimal connections that are supported for correct operation. The registers used for write control and read status information are documented.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Table 30.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller The status of each bit (one for each port) is found in bits [3:0] of the “Optical Module Status Ports 0-3 ($0x799)” on page 221). Any change in the state of these bits causes a logic Low level on the MOD_DEF_INT output if this operation is enabled. 5.7.2.2.2 TX_FAULT_0:3 TX_FAULT_0:3 are inputs to the IXF1104. These signals are pulled to a logic Low level by the optical module during normal operation.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Note: 5.7.3 MOD_DEF_INT, TX_FAULT_INT, and RX_LOS_INT are open-drain type outputs. With the three signals on the device, the system can decide which “Optical Module Status Ports 0-3 ($0x799)" bits to look at to identify the interrupt condition source port. However, this is achieved at the expense of the three device signals. I²C Module Configuration Interface The I²C interface is supported on SFP optical modules.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller b. Initiate the I2C transfer by setting bit [24] of the control register to 0x1. c. Select the port by using bits [17:16]. d. Select the Read mode of operation by setting bit [15] to 0x1. e. Select the Device ID by setting bits [14:11]. f. Select the register address by setting bits [10:0]. 2. Set the Device ID field to 0xA and the register address (bits 10:8) to 0x0 to access the fiber module serial E2PROM.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller d. Set the Device ID Register bits 14:11 to Ah (Atmel compatible). e. Set the 11-bit register address (Register bits 10:0) to 0FFh. f. Enable the I2C controller by setting Register bit 2 to 0x1. g. Initiate the I2C transfer by setting Register bit 24 to 0x1. All other bits in this register should be set to 0x0. This data is written into the “I2C Control Ports 0 - 3 ($0x79B)" in a single cycle via the CPU interface. 2.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Figure 25. Data Validity Timing I2C_Data I2C_Clk DATA STABLE DATA STABLE DATA CHANGE 5.7.3.6.1 Start Condition A High-to-Low transition of I2C_DATA, with I2C_CLK High, is a start condition that must precede any other command (see Figure 26). 5.7.3.6.2 Stop Condition A Low-to-High transition of the I2C_DATA with I2C_CLK High is a stop condition.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Figure 27. Acknowledge Timing I2C_Data DATA IN DATA OUT START 5.7.3.6.4 ACKNOWLEDGE Memory Reset After an interruption in protocol, power loss, or system reset, any 2-wire optical module can be reset by following three steps: 1. Clock up to 9 cycles 2. Wait for I2C_DATA High in each cycle while I2C_CLK is High 3. Initiate a start condition. 5.7.3.6.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Figure 28. Random Read S T A R T W R I T E DEVICE ADDRESS S T A R T WORD ADDRESS I2C_Data Line R E A D DEVICE ADDRESS S T O P M S B L R S / BW START * M S B DUMMYWRITE L A S C B K M S B L S B A C K DATAn N O A C K (* =DON'TCAREbit for 1k) 5.8 LED Interface The IXF1104 uses a Serial interface, consisting of three signals, to provide LED data to some form of external driver.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Table 31. LED Interface Signal Descriptions 5.8.3 Pin Name Pin # Pin Description LED_CLK K24 This signal is an output that provides a continuous clock synchronous to the serial data stream output on the LED_DATA pin. This clock has a maximum speed of 720 Hz. The behavior of this signal remains constant in all modes of operation. LED_DATA M22 This signal provides the data, in various formats, as a serial bit stream.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Table 32. Mode 0 Clock Cycle to Data Bit Relationship LED_CLK Cycle LED_DATA Name LED_DATA Description 1 START BIT This bit synchronizes the M5450 device to expect 35 bits of data to follow. 2:3 PAD BITS These bits are used only as fillers in the data stream to extend the length from the actual 12-bit LED DATA to the required 18-bit frame length. These bits should always be a logic 0.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Note: The LED_DATA signal is now inverted from the state in Mode 0. Figure 30. Mode 1 Timing 1 2 3 4 25 26 27 28 29 30 31 32 33 34 35 1 22 23 24 25 26 27 28 29 30 LED_CLK LED_DATA LED_LATCH Table 33.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Note: The data decode of the LED bits is independent of the Physical mode selection. Table 34.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller 5.8.6.1.2 Copper LED Behavior Table 36. LED Behavior (Copper Mode) Type Link LED Activity LED - Green Status Description Off Port does not have a remote fault and “LED Control ($0x509)” on page 189 bit is not set. Amber On Port has an RGMII RXERR condition detected and “LED Control ($0x509)” on page 189 bit is set Amber Blinking Port has a remote fault and “LED Fault Disable ($0x50B)” on page 190 is not set.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller 5.9.1 Functional Description 5.9.1.1 Read Access Read access involves the following: • • • • Detect assertion of asynchronous Read control signal and latch address Generate internal Read strobe Drive valid data onto processor bus Assert asynchronous Ready signal for required length of time Figure 31 shows the timing of the asynchronous interface for Read access. Figure 31.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Figure 32. Write Timing Diagram - Asynchronous Interface TCAS TCAH uPx_Add[12:0] uPx_CsN uPx_WrN TCWL TCWH TCDWH uPx_Data[31:0] TCDWS TCYD uPx_RdyN TCDWD 5.9.1.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Table 37. Byte Swapper Behavior Little Endian UPX_BADD [1:0] Big Endian 32-bit 16-bit 8-bit1 32-bit 16-bit 8-bit1 UPX_DATA_ [31:0] UPX_DATA_ [15:0] UPX_DATA [7:0] UPX_DATA [31:0] UPX_DATA [15:0] UPX_DATA [7:0] [7:0] [15:8] [7:0] 00 [31:0] [15:0] [7:0] [7:0] [15:8] [23:16 [31:24] 01 – – [15:8] – – [15:8] 10 – [31:16] [23:16] – [23:16] [31:24] [23:16] 11 – – [31:24] – – [31:24] 1.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller 5.10.2 Instruction Register and Supported Instructions The instruction register is a 4-bit register that enacts the boundary scan instructions. After the state machine resets, the default instruction is IDCODE. The decode logic in the TAP controller selects the appropriate data register and configures the boundary scan cells for the current instruction. Table 38 shows the supported boundary-scan instructions. Table 38.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller 5.10.3 ID Register The ID register is a 32-bit register. The IDCODE instruction connects this register between TDI and TDO. See Table 112 “JTAG ID ($0x50C)” on page 191 for detailed information. 5.10.4 Boundary Scan Register The Boundary Scan register is a shift register made up of all the boundary scan cells associated with the device signals.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Figure 33. SPI3 Interface Loopback Path SPI3 Internal Loopback TX FIFO TX SPI3 Interface Block RX MAC Line Side Interface RX FIFO B3229-01 Note: There is a restriction when using this loopback mode. At least one clock cycle is required between a TEOP assertion and a TSOP assertion.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller Figure 34. Line Side Interface Loopback Path Line Side Internal Loopback TX TX FIFO SPI3 Interface Block MAC Line Side Interface RX FIFO RX B3230-01 When the IXF1104 is configured in this loopback mode, all of the MAC functions and features are available, including flow control and pause-packet generation.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller 5.12.1.1 CLK125 The system interface clock, which supplies the clock to the majority of the internal circuitry, is the 125 MHz clock. The source of this clock must meet the following specifications: • 2.5 V CMOS drive • +/- 50 ppm • Maximum duty cycle distortion 40/60 5.12.2 SPI3 Receive and Transmit Clocks The IXF1104 transmit clock requirements include the following: • • • • • 3.
IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller • 43/57 duty cycle for 18 MHz operation 5.12.5 JTAG Clock The IXF1104 supports JTAG. The source of this clock must meet the following specifications: • 3.3 V CMOS drive • Maximum clock frequency 11 MHz • Maximum duty cycle distortion 40/60 5.12.6 I2C Clock The IXF1104 supports a single-output I2C clock to support all ten Optical Module interfaces. The IXF1104 meets the following specifications for this clock: • 2.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 6.0 Applications 6.1 Change Port Mode Initialization Sequence Use the change port mode initialization sequence after power-up and anytime a port is configured into or switching between fiber or copper mode, switching to/from RGMII and GMII modes, or switching speeds and duplex in RGMII mode. The following sequence applies to all four ports and can be done simultaneously for all ports or as a subset of the ports. 1.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Enable packet padding and CRC appending on transmitted packets in bits 6 and 7, as needed. Set bit 5 to 0x0. b. Fiber Mode: Write the reserved bits to the default value. Enable Packet padding and CRC Appending on transmitted packets in bits 6 and 7, as needed. Set bit 5 to 1 to enable auto-negotiation. Set bit 5 to 0 to enable forced mode operation. 13. Assert (set to 1) “Port Enable ($0x500)”. 14. Wait 1 to 2 µs. 15.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 7.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 40. Recommended Operating Conditions Parameter Symbol VDD Recommended supply voltage SerDes Operation Operating Current Transmitting and receiving in 1000 Mbps mode Recommended operating temperature Typ Max Units 1.65 – 1.95 Volts VDD2, VDD3 3.0 – 3.6 Volts VDD4, VDD5 2.3 – 2.7 Volts AVDD1P8_1 AVDD1P8_2 1.65 – 1.95 Volts AVDD2P5_1 AVDD2P5_2 2.3 – 2.7 Volts VDD AVDD1P8_1 AVDD1P8_2 – 0.
IXF1104 4-Port Gigabit Ethernet Media Access Controller See Section 5.1.7, “Packet Buffer Dimensions” on page 79 for additional information regarding I/O buffer types. The related driver characteristics are described in this section. Caution: IXF1104 input signals are not 5 V tolerant. Devices driving the IXF1104 must provide 3.3 V signal levels or use level-shifting buffers to provide 3.3 V compatible levels. Otherwise, damage to the IXF1104 will occur. Table 41.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 42. SerDes Transmit Characteristics (Sheet 2 of 2) Symbol Normalized Power Drive Settings1 Min Typ Max Units Receiver common mode voltage range RxCMV – 900 1275 1650 mV – Receiver termination impedance RxZ – 40 51 62.5 Ω – RxSigDet – 50 125 200 Parameter Signal detect level Comments mVp-pdiff – 1. Refer to Section 5.6.2.2, “Transmitter Programmable Driver-Power Levels” on page 103. Table 43.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 45. RGMII Power Symbol Parameter Conditions Min Max Units VOH Output High Voltage IOH = -1.0 MA; VCC = MIN 2.0 VDD +.3 V VOL Output Low Voltage IOL = 1.0 M A; VCC = MIN GND -.3 0.40 V VIH Input High Voltage VIH > VIH_MIN; VCC = MIN – – V VIL Input Low Voltage VIL < VIL_MAX; VCC = MIN – .70 V IIH Input High Current VCC = MAX; VIN = 2.5V – 15 µA IIL Input Low Current VCC = MAX; VIN = 0.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 7.2 SPI3 AC Timing Specifications 7.2.1 Receive Interface Timing Figure 35 and Table 46 illustrate and provide SPI3 receive interface timing information. Figure 35.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 46. SPI3 Receive Interface Signal Parameters Symbol Parameter Min Max Units – RFCLK frequency – 133 MHz – RFCLK duty cycle 40 60 % Tsrenb RENB setup time to RFCLK 1.8 – ns Threnb RENB hold time to RFCLK 0.5 – ns TPrdat RFCLK High to RDAT valid 1.5 3.7 ns TPrprty RFCLK High to RPRTY valid 1.5 3.7 ns TPrsop RFCLK High to RSOP valid 1.5 3.7 ns TPreop RFCLK High to REOP valid 1.5 3.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 7.2.2 Transmit Interface Timing Figure 36 and Table 47 illustrate and provide SPI3 transmit interface timing information. Figure 36.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 47. SPI3 Transmit Interface Signal Parameters Symbol Parameter Min Max Units – TFCLK frequency – 133 MHz – TFCLK duty cycle 40 60 % TStenb TENB setup time to TFCLK 1.8 – ns THtenb TENB hold time to TFCLK 0.5 – ns TStdat TDAT[31:0] setup time to TFCLK 1.8 – ns THtdat TDAT[31:0} hold time to TFCLK 0.5 – ns TStprty TRPTY setup time to TFCLK 1.8 – ns THtprty TPRTY hold time to TFCLK 0.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 7.3 RGMII AC Timing Specification Figure 37 and Table 48 provide RGMII interface timing parameters. Figure 37. RGMII Interface Timing TXC (at Transmitter) TSkewT TD[3:0] TD[3:0] TD[7:4] TSkewR TX_CTL[n] TXEN TXERR RD[3:0] RD[7:4] RXDV RXERR TXC (at Receiver) RXC (at Transmitter) TSkewT RD[3:0] TSkewR RX_CTL RXC (at Receiver) B3251-01 Table 48.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 7.4 GMII AC Timing Specification 7.4.1 1000 Base-T Operation Figure 38 and Figure 39 and Table 49 and Table 50 provide GMII AC timing specifications. 7.4.1.1 1000 BASE-T Transmit Interface Figure 38. 1000BASE-T Transmit Interface Timing GTX_CLK TXEn t1 t2 TXD[7:0] TXER t3 CPS t4 B0634-01 Table 49. GMII 1000BASE-T Transmit Signal Parameters Symbol Parameter Min Typ1 Max Unit2 t1 TXD[7:0], TXEN, TXER Set-up to TXC High 2.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 7.4.1.2 1000BASE-T Receive Interface Figure 39. 1000BASE-T Receive Interface Timing RX_CLK t1 RxDV t2 RXD[7:0] CRS Table 50. GMII 1000BASE-T Receive Signal Parameters Symbol Parameter Min Typ1 Max Unit2 t1 RXD[7:0], RX_DV, RXER Setup to Rx_CLK High 2.0 – – ns t2 RXD[7:0], RX_DV, RXER Hold after Rx_CLK High 0.0 – – ns o 1.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 7.5 SerDes AC Timing Specification Figure 40. SerDes Timing Diagram Table 51.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 7.6 MDIO AC Timing Specification The MDIO Interface on the IXF1104 can operate in two modes – low-speed and high-speed. In low-speed mode, the MDC clock signal operates at a frequency of 2.5 MHz. In high-speed mode, the MDC clock signal operates at a frequency of 18 MHz. (See Figure 41 through Figure 44 and Table 52.) 7.6.1 MDC High-Speed Operation Timing Figure 41.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 7.6.3 MDIO AC Timing Figure 43. MDIO Write Timing Diagram V MAX MDC V MIN t1 t2 MDIO Figure 44. MDIO Read Timing Diagram VMA X MDC t3 MDIO Table 52. MDIO Timing Parameters Parameter Symbol MDIO Setup before MDC. Min Typ1 Max Units Test Conditions 10 – – ns MDC = 17.8 MHz 10 – – ns MDC = 2.5 MHz 10 – – ns MDC = 17.8 MHz 10 – – ns MDC = 2.5 MHz 0 – 42 ns MDC = 17.8 MHz 0 – 200 ns MDC = 2.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 7.7 Optical Module and I2C AC Timing Specification 7.7.1 I2C Interface Timing Figure 45 and Figure 46 illustrate bus timing and write cycle, and Table 53 shows the I2C Interface AC timing characteristics. Figure 45. Bus Timing Diagram t HIGH t F t R t LOW t LOW I2C_Clk t t SV.SAT HD.STA t HD.DAT t SU.STO t SU.DAT I2C_Data In t BUF t DH t AA I2C_Data Out Figure 46.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 53. I2C AC Timing Characteristics (Sheet 2 of 2) Symbol Parameter Min Max Units tSU.STA Start setup time 4.7 – µs tHD.DAT Data in hold time 0 – µs tSU.DAT Data in setup time 200 – ns tR Inputs rise time – 1.0 µs tF Inputs fall time – 300 ns tSU.STO Stop setup time 4.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 7.8 CPU AC Timing Specification 7.8.1 CPU Interface Read Cycle AC Timing Figure 47, Figure 48, and Table 54 illustrate the CPU interface read and write cycle AC timing. Figure 47. CPU Interface Read Cycle AC Timing TCAS TCAH uPx_ADD[12:0] uPx_CsN TCRR uPx_RdN TCRH uPx_Data[31:0] TCDRS TCDRH uPx_RdyN TCDRD 7.8.2 CPU Interface Write Cycle AC Timing Figure 48.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 54.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 7.9 Transmit Pause Control AC Timing Specification Figure 49 and Table 55 show the pause control AC timing specifications. The Pause Control interface operates as an asynchronous interface relative to the main system clock (CLK125). There is, however, a relationship between the TXPAUSEADD bus and the strobe signal (TXPAUSEFR). Figure 49.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 7.10 JTAG AC Timing Specification Figure 50 and Table 56 provide the JTAG AC timing specifications. Figure 50. JTAG AC Timing Table 56. JTAG AC Timing Parameters Symbol Parameter Min Max Units Tjc TCLK cycle time 90 - ns Tjh TCLK High time 0.4 x Tjc 0.6 x Tjc ns Tjl TCLK low time 0.4 x Tjc 0.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 7.11 System AC Timing Specification Figure 51 and Table 57 illustrate the system reset AC timing specifications. Figure 51. System Reset AC Timing Table 57. System Reset AC Timing Parameters Symbol 152 Parameter Min Max Units Trw Reset pulse width 1.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 7.12 LED AC Timing Specification Figure 52 and Table 58 provide the LED AC timing specifications. Figure 52. LED AC Interface Timing Tcyc Tlow LED_CLK Thi Tdatd LED_DATA Thatl Tlath LED_LATCH Table 58. LED Interface AC Timing Parameters Symbol Parameter Min Max Units Tcyc LED_CLK cycle time 1.36 1.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 8.0 Register Set The registers shown in this section provide access for configuration, alarm monitoring, and control of the chip. Table 59 “MAC Control Registers ($ Port Index + Offset)” on page 155 through Table 69 “Optical Module Registers ($ 0x799 - 0x79F)” on page 161 provide register map details. The registers are listed by ascending address in the table. 8.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 8.3 Per Port Registers Section 8.4 covers all of the registers that are replicated in each port of the IXF1104. These registers perform an identical function in each port. The address vector for the IXF1104 is 11 bits wide. This allows for 7 bits of port-specific access and a 4-bit vector to address each port and all global registers. The address format is shown in Figure 54. Figure 54.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 59.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 60. MAC RX Statistics Registers ($ Port Index + Offset) (Sheet 2 of 2) Register Bit Size Mode1 Ref Page Offset RxUnknownMacControlFrameCounter 32 R 173 0x33 RxVeryLongErrors 32 R 173 0x34 RxRuntErrors 32 R 173 0x35 RxShortErrors 32 R 173 0x36 RxCarrierExtendError 32 R 173 0x37 RxSequenceErrors 32 R 173 0x38 RxSymbolErrors 32 R 173 0x39 Mode1 Ref Page Offset Table 61.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 62.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 64.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 65.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 67.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 8.4.1 MAC Control Registers Table 70 through Table 92 “Port Multicast Address ($ Port_Index +0x1A – +0x1B)” on page 172 provide details on the control and status registers associated with each MAC port. The register address is ‘Port_index + 0x**’, where the port index is set at any value from 0x0 through 0x5. All registers are 32-bit. The unused bits of the registers are read-only and are set permanently to zero. Table 70.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 73. Collision Distance ($ Port_Index + 0x05) Description Address Type1 Default This is a 10-bit value that sets the limit for late collision. Collisions happening at byte times beyond the configured value are considered to be late collisions. (Only valid in half-duplex). Port_Index + 0x05 R/W 0x00000043 Name Collision Distance 1.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 77. IPG Receive Time 1 ($ Port_Index + 0x0A) Name IPG Receive Time 1 Description Address Type1 Default This timer is used during half-duplex operation when there is a packet waiting for transmission from the MAC. This timer starts after CRS is de-asserted. If CRS is asserted during this time, no transmission is initiated and the counter restarts once CRS is deasserted again.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 80. Pause Threshold ($ Port_Index + 0x0E) Name Pause Threshold Description Address Type1 Default When a pause frame has been sent, an internal timer checks when the next pause frame must be scheduled for transmission to keep the link partner in pause mode (this is required only if the flow control has to be extended for one more session).
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 82. MAC IF Mode and RGMII Speed ($ Port_Index + 0x10) Bit Name Description Type1 Default Register Description – MAC IF Mode: Determines the MAC operation frequency and mode per port. Changes to the data setting of this register must be made in conjunction with the “Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794)" to ensure a safe transition to a new operational mode. Changes to this register must follow a proper sequence.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 84. FC Enable ($ Port_Index + 0x12) Bit Name Type1 Description Register Description: Indicates which flow control mode is used for the RX and TX MAC. 31:3 2 Reserved Reserved TX HDFC When TX HDFC is enabled (half-duplex mode only), the MAC generates deliberate collisions on incoming packets when the RX FIFO occupancy crosses the High Watermark (flow control).
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 86. Short Runts Threshold ($ Port_Index + 0x14) Name Address Type1 Default Port_Index + 0x14 R/W 0x00000008 Description The 5-bit configuration holds the value in bytes, which applies to the threshold in determining between runts and short. The bits 4:0 of this register are alone used. A received packet is reported as a short packet when the length (excluding Preamble and SFD) is less than this value.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 88. RX Config Word ($ Port_Index + 0x16) (Sheet 2 of 2) Bit Name Description 19 RX Config 0 = Receiving idle/data stream 1 = Receiving /C/ ordered sets 18 Config Changed 0 = RxConfigWord has changed since last read 1 = RxConfigWord has not changed since last read. Type1 Default RO 0 R 0 RO 0 This bit remains High until the register is read.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 89. TX Config Word ($ Port_Index + 0x17) (Sheet 2 of 2) Bit Name Description Type1 Default R/W 00 Remote fault definitions: 00 = No error, link okay 13:122 Remote Fault [1:0] 01 = Offline 10 = Link failure 11 = Auto-negotiation_Error 11:9 Reserved Write as 0, ignore on Read R/W 000 8 Asym Pause Asym Pause. The ability to send pause frames. R/W 1 7 Sym Pause Sym Pause. The ability to send and receive pause frames.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 90. Diverse Config Write ($ Port_Index + 0x18) (Sheet 2 of 2) Type1 Default Write as 1, ignore on Read. R/W 11 Write as 0, ignore on Read. R/W 0 Write as 1, ignore on Read. R/W 1 Bit Name Description 3:22 Reserved 12 Reserved 2 Reserved 0 1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write 2.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 91. RX Packet Filter Control ($ Port_Index + 0x19) (Sheet 2 of 2) Bit Name Description Type1 Default R/W 0 R/W 0 R/W 0 This bit enables a Global filter on broadcast frames. 2 B/Cast Drop En 0 = All broadcast frames are passed to the SPI3 Interface. 1 = All broadcast frames are dropped.2 This bit enables a filter on multicast frames. 1 M/Cast Match En 0 = All muticast frames are good and passed to the SPI3 Interface.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 8.4.2 MAC RX Statistics Register Overview The MAC RX Statistics registers contain the MAC receiver statistic counters and are cleared when read. The software polls these registers and accumulates values to ensure that the counters do not wrap. The 32-bit counters wrap after approximately 30 seconds. Table 93 covers the RX statistics for the four MAC ports. Port_Index is the port number (0, 1, 2, or 3). Table 93.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 93. MAC RX Statistics ($ Port_Index + 0x20 – + 0x39) (Sheet 2 of 4) Address Type1 Default The total number of packets received (including bad packets) that were 65-127 octets in length. Incremented for tagged packets with a length of 65-127 bytes, including tag field. Port_Index + 0x26 R 0x00000000 RxPkts128t0255 Octets The total number of packets received (including bad packets) that were 128-255 octets in length.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 93. MAC RX Statistics ($ Port_Index + 0x20 – + 0x39) (Sheet 3 of 4) Name Description RxAlignErrors3 Frames with a legal frame size, but containing less than eight additional bits. This occurs when the frame is not byte aligned. The CRC of the frame is wrong when the additional bits are stripped. If the CRC is OK, then the frame is not counted but treated as an OK frame. This counter increments in 10 Mbps or 100 Mbps RGMII mode only.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 93. MAC RX Statistics ($ Port_Index + 0x20 – + 0x39) (Sheet 4 of 4) Address Type1 Default RxRuntErrors3 The total number of packets received that are less than 64 octets in length, but longer than or equal to 96 bit times, which corresponds to a 4byte frame with a well-formed preamble and SFD. This is the shortest fragment and can be transmitted in case of a collision event on a halfduplex segment.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 8.4.3 MAC TX Statistics Register Overview The MAC TX Statistics registers contain all the MAC transmit statistic counters and are cleared when read. The software must poll these registers to accumulate values and to ensure that the counters do not wrap. The 32-bit counters wrap after approximately 30 seconds. Table 94 covers all four MAC ports TX statistics. Port_Index is the port number (0, 1, 2, or 3). Table 94.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 94. MAC TX Statistics ($ Port_Index +0x40 – +0x58) (Sheet 2 of 4) Address Type1 Default The total number of broadcast packets transmitted (excluding bad packets). Port_Index + 0x44 R 0x00000000 TxPkts64Octets The total number of packets transmitted (including bad packets) that were 64 octets in length. Incremented for tagged packets with a length of 64 bytes, including tag field.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 94. MAC TX Statistics ($ Port_Index +0x40 – +0x58) (Sheet 3 of 4) Address Type1 Default Port_Index + 0x4E R 0x00000000 Port_Index + 0x4F R 0x00000000 Port_Index + 0x50 R 0x00000000 Port_Index + 0x51 R 0x00000000 Port_Index + 0x52 R 0x00000000 TxExcessiveLengthDrop Frame transmissions aborted by the MAC because the frame is longer than maximum frame size.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 94. MAC TX Statistics ($ Port_Index +0x40 – +0x58) (Sheet 4 of 4) Address Type1 Default Number of OK frames with VLAN tag. (Type field = 0x8100). Port_Index + 0x55 R 0x00000000 TxCRCError Number of frames transmitted with a legal size but with the wrong CRC field (also called FCS field). Port_Index + 0x56 R 0x00000000 TxPauseFrames Number of pause MAC frames transmitted.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 95.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 96.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 98. PHY Identification 2 ($ Port Index + 0x63) (Sheet 2 of 2) Bit Type1 Default The PHY identifier is composed of register bits 24:19 of the OUI (Organizationally Unique Identifier) RO 011110 Manufacturer’s Model Six bits containing the manufacturer’s part number RO 010000 Manufacturer’s Revision Number Four bits containing the manufacturer’s revision number RO 0000 Name Description PHY ID Number 9:4 3:0 15:10 1.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 99. Auto-Negotiation Advertisement ($ Port Index + 0x64) (Sheet 2 of 2) Bit Type1 Default 0 = DTE is not 10BASE-T, full-duplex mode capable 1 = DTE is 10BASE-T, full-duplex mode capable RO 1 0 = DTE is not 10BASE-T, half-duplex mode capable 1 = DTE is 10BASE-T, half-duplex mode capable RO 1 RO 00001 Name Description 6 10BASE-T Full-Duplex 5 10BASE-T Half-Duplex 00001 =IEEE 802.3 00010 =IEEE 802.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 100.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 102.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 8.4.5 Global Status and Configuration Register Overview Table 103 through Table 112 “JTAG ID ($0x50C)” on page 191 provide an overview for the Global Control and Status Registers. Table 103. Port Enable ($0x500) Bit Name Description Type* Register Description: A control register for each port in the IXF1104. Port ID = bit position in the register. To make a port active, the bit must be set High.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 105. Link LED Enable ($0x502) Bit Name Description Type1 Register Description: Per port bit should be set upon detection of link to enable proper operation of the link LEDs.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 107. MDIO Soft Reset ($0x506) Bit Name Description Type1 Register Description: Software-activated reset of the MDIO module. 31:1 0 Default 0x00000000 Reserved Reserved RO 0x00000000 Software MDIO Reset 0 = Reset inactive 1 = Reset active R/W 0 1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write Table 108.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 110. LED Flash Rate ($0x50A) Bit Name Description Type1 Register Description: Global selection of LED flash rate. 31:3 Reserved Reserved Default 0x00000000 RO 0x00000000 R/W 000 000 =100 ms flash rate 001 =200 ms flash rate 010 =300 ms flash rate 2:0 LED Flash Rate Control 011 = 400 ms flash rate 100 = 500 ms flash rate 101 = Reserved 110 = Reserved 111 = Reserved 1.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 112. JTAG ID ($0x50C) Bit Name Description Type1 Register Description: The value of this register follows the same scheme as the device identification register found in the IEEE 1149.1 specification. The upper four bits correspond to silicon stepping. The next 16 bits store a Part ID Number. The next 11 bits contain a JEDEC manufacturer ID. Bit zero = 1 if the chip is the first in a stack.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 8.4.6 RX FIFO Register Overview Table 113 through Table 131 provide an overview of the RX FIFO registers, which include the RX FIFO High and Low watermarks. Table 113. RX FIFO High Watermark Port 0 ($0x580) Type1 Default Register Description: The default value of 0x0E6 represents 230 eight-byte locations. This equates to 1840 bytes of data. A unit entry in this register equates to 8 bytes of data.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 116. RX FIFO High Watermark Port 3 ($0x583) Type1 Default Register Description: The default value of 0x0E6 represents 230 eight-byte locations. This equates to 1840 bytes of data. A unit entry in this register equates to 8 bytes of data. When the amount of data stored in the RX FIFO exceeds the high watermark, flow control is automatically initiated within the MAC to avoid an overflow condition.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 2 Table 119. RX FIFO Low Watermark Port 2 ($0x58C) Bit Name Type1 Description Register Description: The default value of 0x072 represents 114 eight-byte locations. This equates to 912 bytes of data. A unit entry in this register equates to 8 bytes of data. When the amount of data stored in the RX FIFO falls below the Low Watermark, flow control is automatically de-asserted within the MAC to allow more line-side data to be captured by the RX FIFO.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 122. RX FIFO Port Reset ($0x59E) Bit Name Description Type1 Register Description: The soft reset register for each port in the RX block. Port ID = bit position in the register. To make the reset active, the bit must be set High. For example, reset of port 1 implies register value = 0000_0018. Setting the bit to 0 de-asserts the reset.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 123. RX FIFO Errored Frame Drop Enable ($0x59F) Bit 2 Name Description RX FIFO Errored Frame Drop Enable Port 2 This bit is used in conjunction with MAC filter bits. This allows the user to select whether the errored packets are to be dropped or not. 1 = Frame Drop Enable Type1 Default R/W 0 R/W 0 R/W 0 0 = Frame Drop Disable 1 RX FIFO Errored Frame Drop Enable Port 1 This bit is used in conjunction with MAC filter bits.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 125.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 125.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 127. RX FIFO Padding and CRC Strip Enable ($0x5B3) Bit Name Description Type1 Register Description: This control register enables to pre-pend every packet with two extra bytes and also enables the CRC stripping of a packet.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 128. RX FIFO Transfer Threshold Port 0 ($0x5B8) Bit Name Description Type Register Description: RX FIFO transfer threshold for port 0 in 8-byte location. 31:12 Reserved Reserved Default 0x000000BE RO 0x00000 R/W 0x0BE RX FIFO transfer threshold for port 0. This must be less than the RX FIFO High water mark.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 130. RX FIFO Transfer Threshold Port 2 ($0x5BA) Bit Name Description Type Register Description: RX FIFO transfer threshold for port 2 in 8-byte location. 31:12 Reserved Reserved Default 0x000000BE RO 0x00000 R/W 0x0BE RX FIFO transfer threshold for port 2. This must be less than the RX FIFO High water mark.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 8.4.7 TX FIFO Register Overview Table 132 through Table 139 provide an overview of the TX FIFO registers, which include the TX FIFO High and Low watermark. Table 132. TX FIFO High Watermark Ports 0 - 3 ($0x600 – 0x603) Address Type1 Default High watermark for TX FIFO Port 0. The default value of 0x3E0 represents 992 8-byte locations. This equates to 7936 bytes of data. A unit entry in this register equates to 8 bytes of TX FIFO High data.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 133. TX FIFO Low Watermark Register Ports 0 - 3 ($0x60A – 0x60D) Address Type1 Default Low watermark for TX FIFO Port 0. The default value of 0x0D0 represents 208 8-byte locations. This equates to 1664 bytes of data. A unit entry in this register equates to 8 bytes of TX FIFO Low data.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 134. TX FIFO MAC Threshold Register Ports 0 - 3 ($0x614 – 0x617) Address Type1 Default TX FIFO MAC Threshold Port 0 MAC threshold for TX FIFO Port 0. The default value of 0x1BE represents 446 8-byte locations. This equates to 3568 bytes of data. A unit entry in this register equates to 8 bytes of data.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 135. TX FIFO Overflow/Underflow/Out of Sequence Event ($0x61E) (Sheet 1 of 2) Bit Name Description Type1 Default Register Description: TX FIFO Out of Sequence Event: These register bits provide status information, and indicate if out-of-sequence data has been received. The bit position equals the port number + 8. These bits are cleared on Read.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 135. TX FIFO Overflow/Underflow/Out of Sequence Event ($0x61E) (Sheet 2 of 2) Bit Name 2 FOE2 1 FOE1 0 FOE0 Description Type1 Default R 0 R 0 R 0 Port 2 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred Port 1 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred Port 0 0 = FIFO overflow event did not occur 1 = FIFO overflow event occurred 1.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 137. TX FIFO Port Reset ($0x620) (Sheet 2 of 2) Bit Name Description Type1 Default R/W 0 R/W 0 R/W 0 Port 2 2 Port 2 Reset 1 Port 1 Reset 0 Port 0 Reset 0 = De-assert Reset 1 = Assert Reset Port 1 0 = De-assert Reset 1 = Assert Reset Port 0 0 = De-assert Reset 1 = Assert Reset 1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write Table 138.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 139.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 140. TX FIFO Occupancy Counter for Ports 0 - 3 ($0x62D – 0x630) Name Description Address Type Default Occupancy for Tx FIFO Port 0 This register gives the Occupancy for TX FIFO Port 0. This is a Read only register 0x62D R 0x00000000 Occupancy for Tx FIFO Port 1 This register gives the Occupancy for TX FIFO Port 1.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 8.4.8 MDIO Register Overview Table 142 through Table 145 provide an overview of the MDIO registers. Table 142. MDIO Single Command ($0x680) Bit Name Description Type1 Register Description: Gives the CPU the ability to perform single MDIO read and write accesses to the external PHY for ports that are configured in copper mode. 31:21 20 19:18 Reserved MDIO Command Reserved Reserved Performs the MDIO operation. Cleared when done.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 144. Autoscan PHY Address Enable ($0x682) Bit Name Description Type1 Default Register Description: Defines valid PHY addresses. Each bit enables the corresponding PHY address. 0x00000000 0 = Disable the PHY address 1 = Enable the PHY address NOTE: Autoscan is only applicable for the ports in copper mode.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 8.4.9 SPI3 Register Overview Table 146 through Table 148 “Address Parity Error Packet Drop Counter ($0x70A)” on page 218 provide an overview of the SPI3 registers. Table 146. SPI3 Transmit and Global Configuration ($0x700) (Sheet 1 of 3) Bit Name Description Type1 Register Description: This register gives the configuration related to the SPI3 Transmitter and Global configuration (4 x 8 mode).
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 146. SPI3 Transmit and Global Configuration ($0x700) (Sheet 2 of 3) Type1 Default Dat_prtyer_drp Port 0 SPHY/MPHY Mode: Indicates whether to drop packets with data parity error for port 0. 0 = Do not drop packets with data parity error (default) 1 = Drop packets with data parity error R/W 0 Reserved Write as 0, ignore on Read. R/W 00000000 7 SPHY Mode: Indicates the parity sense to check the parity on TDAT bus for port 3.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 146.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 147. SPI3 Receive Configuration ($0x701) (Continued) Bit 25 24 23:22 21:20 19:18 Type1 Default B2B_PAUSE Port 1 SPHY Mode: Indicates the number of pause cycles to be introduced between back-to-back transfers for port 1. 0 = Zero pause cycles 1 = Two pause cycles MPHY Mode: NA R/W 0 B2B_PAUSE Port 0 SPHY Mode: Indicates the number of pause cycles to be introduced between back-to-back transfers for port 0.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 147. SPI3 Receive Configuration ($0x701) (Continued) Bit 17:16 15 14 13 12 Type1 Default RX_BURST Port 0 SPHY Mode: Selects the maximum burst size on the RX path for port 0. 0x = 64 bytes maximum burst size 10 = 128 bytes maximum burst size 11 = 256 bytes maximum burst size MPHY Mode: Selects the maximum burst size on the RX path for all ports.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 147. SPI3 Receive Configuration ($0x701) (Continued) Bit 11 10 9 8 7 6:1 0 Type1 Default Rx_port_enable Port 3 SPHY Mode: 0 = Disables the selected SPI3 RX port. 1 = Enables the selected SPI3 RX port. MPHY Mode: 0 = Disables the selected SPI3 RX port. 1 = Enables the selected SPI3 RX port. R/W 0xF Rx_port_enable Port 2 SPHY Mode: 0 = Disables the selected SPI3 RX port. 1 = Enables the selected SPI3 RX port.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 148. Address Parity Error Packet Drop Counter ($0x70A) Bit Name Description Type1 Register Description: This register counts the number of packets dropped due to parity error detection during the address selection cycle. 31:8 7:0 Reserved Reserved Address Parity Error Packet Drop Counter This is an 8-bit counter that counts the number of packets dropped due to parity error detection during the address selection cycle.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 8.4.10 SerDes Register Overview Table 149 through Table 152 “Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794)” on page 220 define the contents of the SerDes registers at base location 0x780, which contain the control and status for the four SerDes interfaces on the IXF1104. Table 149.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 152. Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794) Bit Name Description Type1 Register Description: This register is used when a change to the operational mode or speed of the IXF1104 is required. This register ensures that when a change is made that the internal clocking of the IXF1104 is managed correctly and no unexpected effects of the operational or speed change are observable on the line interfaces.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 8.4.11 Optical Module Register Overview Table 153 through Table 156 “I2C Data Ports 0 - 3 ($0x79F)” on page 222 provide an overview of the Optical Module Registers. Note: All registers in this section are only applicable to ports that are configured in fiber mode. Table 153.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Table 155. I2C Control Ports 0 - 3 ($0x79B) Bit Name Description Type1 Register Description: This register controls and monitors the interface to the optical modules when used in fiber mode. 31:28 Default 0x00000000 Reserved Reserved RO 0x0 wp_err An attempt to write to the protected E2PROM has occurred. R 0 26 no_ack_err This bit is set to 1 when a write and subsequent read from an Optical Module Interface has failed.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 9.0 Mechanical Specifications The IXF1104 is packaged in a 576-ball BGA package with 6 balls removed diagonally from each corner, for a total of 552 balls used measuring 25 mm x 25 mm. The pitch of the balls on the package is 1 mm. 9.1 Overview CBGA packages are suited for applications requiring high I/O counts and high electrical performance. They are recommended for high-power applications with high noise immunity requirements. 9.1.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 9.3 Package Information Figure 55. CBGA Package Diagram Chip 47P6802 (25 ± 0.2) 7.804 3.902 Substrate 3.938 7.877 (25 ± 0.2) Note: All dimensions are in mm. (0.825 MAX) (0.325 MIN) (0.825 MAX) (0.325 MIN) (575X) (ø 0.8 ± 0.05) ø 0.20 L D A S B S (I/O Pads) (Reference) = Ball = No ball (23x) TYP (23) (25 ± 0.2) (Reference) B0034-01 (23x) TYP Chip Carrier A01 Corner (23) (25 ± 0.2) Note: All dimensions are in mm.
IXF1104 4-Port Gigabit Ethernet Media Access Controller Figure 56. CBGA Package Side View Diagram 45L4867 (552) Solder ball C4 Encapsulant Fillet Chip 0.81 ± 0.1 (2.47 Max) (2.03 Min) (6X) (0.77 Max) (0.69 Min) (6X) (3.24 Max) (2.72 Min) (6X) (4.16 Max) (3.43 Min) (0.857 Max) (0.779 Min) (3.327 Max) (2.809 Min) (4.237 Max) (3.619 Min) 0.15 C Seating Plane Note: All dimensions are in mm.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 9.3.1 Example Package Marking Figure 57.
IXF1104 4-Port Gigabit Ethernet Media Access Controller 10.0 Product Ordering Information Table 157 and Figure 58 provide IXF1104 product ordering information. Table 157. Product Information Number Revision Qualification MM Number Ship Media B0 S 853714 Tray HFIXF1104CE.B0 S 853714 Figure 58.