Intel® Core™ Duo Processor and Intel® Core™ Solo Processor on 65 nm Process Specification Update February 2009 Revision 019 Doc #309222
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Contents Revision History..................................................................................................................... 4 Preface ................................................................................................................................. 6 Summary Tables of Changes ................................................................................................... 8 Identification Information ........................................................................
Revision History Revision History Document Number Revision Description Date 309222 -001 Initial release January 2006 309222 -002 Updated Processor Identification (Table 1) April 2006 309222 -003 Added Errata AE35-AE40 May 2006 Updated Errata A14 and AE29 Updated Processor Identification (Table 1) 309222 -004 Added Errata AE41-AE46 June 2006 Updated Processor Identification (Table 1) Updated Description for Code „A‟ in Summary Table of Changes 309222 -005 Added Errata A
Revision History Updated Erratum AE34 Added Erratum AE83 309222 -015 Added Specification Clarification AE2 January 2008 Updated Stepping Codes Used in Summary Table 309222 -016 Updated Erratum AE32 February 2008 Updated Erratum AE60 309222 -017 Updated Stepping Codes Used in Summary Table July 2008 309222 -018 Added Erratum AE84 October 2008 Updated Stepping Codes Used in Summary Table 309222 -019 Updated Erratum AE64 February 2009 Updated Stepping Codes Used in Su
Preface Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
Preface Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics (e.g. core speed, L2 cache size, package type) as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number Errata are design defects or errors.
Summary Tables of Changes Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed Processor steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
Summary Tables of Changes Note: Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel‟s microprocessor Specification Updates: A= Dual-Core Intel® Xeon® processor 7000 sequence C= Intel® Celeron® processor D= Dual-Core Intel® Xeon® processor 2.
Summary Tables of Changes AK = Intel® Core™2 Extreme quad-core processor QX6000Δ sequence and Intel® Core™2 Quad processor Q6000Δ sequence AL = Dual-Core Intel® Xeon® processor 7100 series AM = Intel® Celeron® processor 400 sequence AN = Intel® Pentium® dual-core processor AO = Quad-Core Intel® Xeon® processor 3200 series AP = Dual-Core Intel® Xeon® processor 3000 series AQ = Intel® Pentium® dual-core desktop processor E2000 sequence AR = Intel® Celeron processor 500 series AS = Intel® Xeo
Summary Tables of Changes Number Stepping Plans ERRATA C0 D0 Dual Core Only AE1 X X No Fix FST Instruction with Numeric and Null Segment Exceptions May Take Numeric Exception with Incorrect FPU Operand Pointer AE2 X X No Fix Code Segment Limit Violation May Occur on 4-Gbyte Limit Check AE3 Errata – Removed AE4 X X No Fix REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types May Use an Incorrect Data Size or Lead to Memory-Orderi
Summary Tables of Changes Number 12 Stepping Plans C0 D0 Dual Core Only AE21 X X X AE22 X AE23 ERRATA No Fix Disable Execution-Disable Bit (IA32_MISC_ENABLES [34]) Is Shared between Cores X No Fix Last Branch Records (LBR) Updates May Be Incorrect after a Task Switch X X No Fix Address Reported by Machine-Check Architecture (MCA) on Single-Bit L2 ECC Errors May Be Incorrect AE24 X X No Fix Disabling of Single-Step On Branch Operation May Be Delayed following a POPFD Instruction
Summary Tables of Changes Number Stepping C0 D0 AE40 X X AE41 X X AE42 X X AE43 X AE44 X X AE45 X AE46 Plans ERRATA Dual Core Only No Fix A Write to an APIC Register Sometimes May Appear to Have Not Occurred X No Fix IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly X No Fix Simultaneous Access to the Same Page Table Entries by Both Cores May Lead to Unexpected Processor Behavior X Fixed IO_SMI Indication in SMRAM State Save Area May Be Lost X No Fix Logic
Summary Tables of Changes Number Stepping Plans ERRATA C0 D0 Dual Core Only AE60 X X No Fix An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception AE61 X X No Fix Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update AE62 X X No Fix Values for LBR/BTS/BTM Will Be Incorrect after an Exit from SMM AE63 14 Erratum Removed AE64 X
Summary Tables of Changes Number Stepping Plans ERRATA C0 D0 AE81 X X No Fix Store Ordering May be Incorrect between WC and WP Memory Types AE82 X X No Fix Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions AE83 X X No Fix A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to Memory-Ordering Violations AE84 X X No Fix Corruption of CS Segment Register During RSM While Transitioning From Real Mode to Protected Mode Number Dual Core Only SPECIFICA
Identification Information Identification Information Component Identification via Programming Interface The Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65 nm process can be identified by the following register contents: 1. 2.
Identification Information QDF/SSPEC# Processor # Package Stepping CPUID FSB(MHz) Speed HFM/LFM (GHz) Notes Table 1. Intel® Core™ Duo Processor and Intel® Core™ Solo Processor on 65 nm Process Identification Information SL9JP T2700 Micro-FCPGA D-0 06ECh 667 2.33/1.00 3 SL9K4 T2700 Micro-FCBGA D-0 06ECh 667 2.33/1.00 3 SL9JN T2600 Micro-FCPGA D-0 06ECh 667 2.16/1.00 3 SL9K3 T2600 Micro-FCBGA D-0 06ECh 667 2.16/1.00 3 SL9EH T2500 Micro-FCPGA D-0 06ECh 667 2.
QDF/SSPEC# Processor # Package Stepping CPUID FSB(MHz) Speed HFM/LFM (GHz) Notes Identification Information SL92X T1400 Micro-FCBGA C-0 06E8h 667 1.83/1.00 1,2 SL8VY T1300 Micro-FCPGA C-0 06E8h 667 1.66/1.00 1,2 SL8W3 T1300 Micro-FCBGA C-0 06E8h 667 1.66/1.00 1,2 SL8VW L2400 Micro-FCBGA C-0 06E8h 667 1.66/1.00 6 SL8VX L2300 Micro-FCBGA C-0 06E8h 667 1.50/1.00 6 SL99V U2500 Micro-FCBGA C-0 06E8h 533 1.20/.
Errata Errata AE1. FST Instruction with Numeric and Null Segment Exceptions May Take Numeric Exception with Incorrect FPU Operand Pointer Problem: If execution of an FST (Store Floating Point Value) instruction would generate both numeric and Null segment exceptions, the numeric exceptions may be taken first and with the Null x87 FPU Instruction Operand (Data) Pointer.
Errata AE4. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types May Use an Incorrect Data Size or Lead to Memory-Ordering Violations Problem: Under certain conditions as described in the IA-32 Intel® Architecture Software Developers Manual, section titled Out-of-Order Stores for String Operations in Pentium® 4, Intel® Xeon®, and P6 Family Processors, the processor performs REP MOVS or REP STOS as fast strings.
Errata AE6. Problem: VM Bit Is Cleared on Second Fault Handled by Task Switch from Virtual-8086 (VM86) Following a task switch to any fault handler that was initiated while the processor was in VM86 mode, if there is an additional fault while servicing the original task switch then the VM bit will be incorrectly cleared in EFLAGS, data segments will not be pushed and the processor will not return to the correct mode upon completion of the second fault handler via IRET.
Errata AE9. LTR Instruction May Result in Unexpected Behavior Problem: Under certain circumstances an LTR (Load Task Register) instruction may result in an unexpected behavior if all the following conditions are met: Invalid data selector of the TR (Task Register) resulting with either #GP (General Protection Fault) or #NP (Segment Not Present Fault). GDT (Global Descriptor Table) is not 8-bytes aligned.
Errata AE12. FP Inexact-Result Exception Flag May Not Be Set Problem: When the result of a floating-point operation is not exactly representable in the destination format (1/3 in binary form, for example), an inexact-result (precision) exception occurs. When this occurs, the PE bit (bit 5 of the FPU status word) is normally set by the processor. Under certain rare conditions, this bit may not be set when this rounding occurs.
Errata AE14. Problem: MOV to/from Debug Register Causes Debug Exception When in V86 mode, if a MOV instruction is executed to/from a debug registers, a general-protection exception (#GP) should be generated. However, in the case when the general detect enable flag (GD) bit is set, the observed behavior is that a debug exception (#DB) is generated instead. Implication: With debug-register protection enabled (i.e.
Errata AE17. Problem: Machine Check Exception May Occur When Interleaving Code between Different Memory Types A small window of opportunity exists where code fetches interleaved between different memory types may cause a machine check exception. A complex set of microarchitectural boundary conditions is required to expose this window. Implication: Interleaved instruction fetches between different memory types may result in a machine check exception.
Errata AE20. LOCK# Asserted during a Special Cycle Shutdown Transaction May Unexpectedly Deassert Problem: During a processor shutdown transaction, when LOCK# is asserted and if a DEFER# is received during a snoop phase and the Locked transaction is pipelined on the front side bus (FSB), LOCK# may unexpectedly deassert. Implication: When this erratum occurs, the system may hang during shutdown. Intel has not observed this erratum with any commercially-available systems or software.
Errata AE24. Problem: Disabling of Single-Step On-branch Operation May Be Delayed following a POPFD Instruction Disabling of Single-step On-branch Operation may be delayed, if the following conditions are met: 1. “Single Step On Branch Mode” is enabled (DebugCtlMSR.BTF and EFLAGS.TF are set). 2. POPFD used to clear EFLAGS.TF. 3. A jump instruction (JMP, Jcc, etc.) is executed immediately after POPFD.
Errata AE27. General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit Violation above 4-G Limit Problem: Memory accesses to flat data segments (base = 00000000h) that occur above the 4-G limit (0ffffffffh) may not signal a #GP fault. Implication: When such memory accesses occur, the system may not issue a #GP fault. Workaround: Software should ensure that memory accesses do not occur above the 4-G limit (0ffffffffh).
Errata AE31. Data Breakpoint/Single Step on MOV SS/POP SS May Be Lost after Entry into SMM Problem: Data Breakpoint/Single Step exceptions are normally blocked for one instruction following MOV SS/POP SS instructions. Immediately after executing these instructions, if the processor enters SMM (System Management Mode), upon RSM (resume from SMM) operation, normal processing of Data Breakpoint/Single Step exceptions is restored.
Errata AE34. Problem: Pending x87 FPU Exceptions (#MF) following STI May Be Serviced before Higher Priority Interrupts Interrupts that are pending prior to the execution of the STI (Set Interrupt Flag) instruction are normally serviced immediately after the instruction following the STI. An exception to this is if the following instruction triggers a #MF. In this situation, the interrupt should be serviced before the #MF.
Errata AE37. The Processor May Report a #TS Instead of a #GP Fault Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception) instead of a #GP fault (general protection exception). Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP fault. Intel has not observed this erratum with any commercially-available software. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AE38.
Errata AE40. A Write to an APIC Register Sometimes May Appear to Have Not Occurred Problem: With respect to the retirement of instructions, stores to the uncacheable memorybased APIC register space are handled in a non-synchronized way. For example if an instruction that masks the interrupt flag, e.g.
Errata AE42. Problem: Simultaneous Access to the Same Page Translation Entries by Both Cores May Lead to Unexpected Processor Behavior When the following conditions occur simultaneously, this may create a rare internal condition which may lead to unexpected processor behavior. One core is updating a page table entry, including the processor setting the Accessed and/or Dirty bits in the PTE as the result of an access The other core is using the same translation entry.
Errata AE45. Last Exception Record (LER) MSRs May Be Incorrectly Updated Problem: The LASTINTTOIP and LASTINTFROMIP MSRs (1DDH-1DEH) may contain incorrect values after the following events: masked SSE2 floating-point exception, StopClk, NMI and INT.
Errata AE47. Problem: Writing the Local Vector Table (LVT) When an Interrupt Is Pending May Cause an Unexpected Interrupt If a local interrupt is pending when the LVT entry is written, an interrupt may be taken on the new interrupt vector even if the mask bit is set. Implication: An interrupt may immediately be generated with the new vector when a LVT entry is written, even if the new LVT entry has the mask bit set.
Errata Implication: Software cannot enable/disable only one of the two PerfMon counters through the corresponding Counter Enable bit [22] of IA32_CR_PerfEvtSel0/1. Workaround: Software should enable/disable both PerfMon counters together through Counter Enable bit [22] of IA32_CR_PerfEvtSel0 only. Alternatively, Software can effectively disable any one of the counters by clearing both Krnl and App bits [17:16] in the corresponding IA32_CR_PerfEvtSel0/1.
Errata Implication: There may be a smaller than expected value in the INST_RETIRED performance monitoring counter. The extent to which this value is smaller than expected is determined by the frequency of the above cases. Workaround: None identified. Status: AE52. Problem: For the steppings affected, see the Summary Tables of Changes.
Errata AE55. Problem: Shutdown Condition May Disable Non-Bootstrap Processors When a logical processor encounters an error resulting in shutdown, non-bootstrap processors in the package may be unexpectedly disabled. Implication: Non-bootstrap logical processors in the package that have not observed the error condition may be disabled and may not respond to INIT#, SMI#, NMI#, SIPI or other events Workaround: When this erratum occurs, RESET# must be asserted to restore multi-core functionality.
Errata (IA32_MPERF), the current and subsequent RDMSR instructions for these MSRs may contain incorrect data. Implication: After an MCE event, accesses to the IA32_APERF and IA32_MPERF MSRs may return incorrect data. A subsequent reset will clear this condition. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AE59.
Errata Problem: A partial memory state save of the 512-byte FXSAVE image or a partial memory state restore of the FXRSTOR image may occur if a memory address exceeds the 64-KB limit while the processor is operating in 16-bit mode or if a memory address exceeds the 4-GB limit while the processor is operating in 32-bit mode. Implication: FXSAVE/FXRSTOR will incur a #GP fault due to the memory limit violation as expected but the memory state may be only partially saved or restored.
Errata AE65. Returning to Real Mode from SMM with EFLAGS.VM Set May Result in Unpredictable System Behavior Problem: Returning back from SMM mode into real mode while EFLAGS.VM is set in SMRAM may result in unpredictable system behavior. Implication: If SMM software changes the values of the EFLAGS.VM in SMRAM, it may result in unpredictable system behavior. Intel has not observed this behavior in commerciallyavailable software. Workaround: SMM software should not change the value of EFLAGS.
Errata DR7 GD (General Detect, bit 13) being bit set INT1 instruction Code breakpoint Implication: The BS flag may be incorrectly set for non-single-step #DB exception. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AE69.
Errata AE72. Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame Problem: The ENTER instruction is used to create a procedure stack frame. Due to this erratum, if execution of the ENTER instruction results in a fault, the dynamic storage area of the resultant stack frame may contain unexpected values (i.e., residual stack data as a result of processing the fault). Implication: Data in the created stack frame may be altered following a fault on the ENTER instruction.
Errata AE75. Problem: Microcode Updates Performed During VMX Non-root Operation Could Result in Unexpected Behavior When Intel® Virtualization Technology is enabled, microcode updates are allowed only during VMX root operations. Attempts to apply microcode updates while in VMX nonroot operation should be silently ignored. Due to this erratum, the processor may allow microcode updates during VMX non-root operations if not explicitly prevented by the host software.
Errata Status: For the steppings affected, see the Summary Tables of Changes. AE78. Performance Monitoring Event for Hardware Prefetch Requests (4EH) and Hardware Prefetch Request Cache Misses (4FH) May Not Be Accurate Problem: Performance monitoring event that count hardware prefetch requests and prefetch misses may not be accurate. Implication: This erratum may cause inaccurate counting for Hardware Prefetch Requests and Hardware Prefetch Request Cache Misses. Workaround: None Identified.
Errata Workaround: None identified Status: For the steppings affected, see the Summary Tables of Changes. AE82. Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions Problem: Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask 01H) counts transitions from x87 Floating Point (FP) to MMX™ technology instructions.
Errata Implication: The corruption of the bottom two bits of the CS segment register will have no impact unless software explicitly examines the CS segment register between enabling protected mode and the first far JMP. Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A: System Programming Guide, Part 1, in the section titled "Switching to Protected Mode" recommends the far JMP immediately follows the write to CR0 to enable protected mode.
Specification Changes Specification Changes There are no specification changes in this specification update revision.
Specification Clarifications Specification Clarifications AE2 Enhanced Cache Error Reporting for D0 Stepping Beginning with the D0 stepping, enhanced cache error reporting - as described in Section 14.4 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual (SDM), Volume 3A: System Programming Guide – is supported by the processor. Older steppings use the original cache error reporting scheme. Please see the SDM, Volume 3A, for more details.
Documentation Changes Documentation Changes There are no documentation changes in this specification update revision. Note: Documentation changes for IA-32 Intel® Architecture Software Developer’s Manuals volumes 1, 2A, 2B, 3A and 3B will be posted in a separate document IA-32 Intel® Architecture and Intel® Extended Memory 64 Technology Software Developer’s Manual Documentation Changes. Follow the link below to become familiar with this file.
