Intel® Core™ Duo Processor and Intel® Core™ Solo Processor on 65 nm Process Datasheet January 2007 Document Number: 309221-006
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Contents 1 Introduction .............................................................................................................. 7 1.1 Terminology ....................................................................................................... 9 1.2 References ......................................................................................................... 9 2 Low Power Features ................................................................................................ 11 2.
5.1.6 PROCHOT# Signal Pin .............................................................................90 Figures 1 2 3 4 5 6 7 8 9 10 Package-Level Low Power States ................................................................................12 Core Low Power States..............................................................................................12 Active VCC and ICC Loadline for Intel Core Duo Processor (SV, LV & ULV) and Intel Core Solo Processor SV .....................................
Revision History Revision -001 Description Initial Release • • April 2006 • Added Intel® Core™ Duo Processor T2300E and Intel® Core™ Solo Processor T1400 specifications. May 2006 • Added references to Intel Core Duo Processor, Ultra Low Voltage (ULV) throughout the document CxE low power states now also referred to as Extended Low Power States Section 3.
Datasheet
Introduction 1 Introduction The Intel® CoreTM Duo processor and the Intel® CoreTM Solo processor are built on Intel’s next generation 65 nanometer process technology with copper interconnect. The Intel Core Solo processor refers to a single core processor and the Intel Core Duo processor refers to a dual core processor. This document provides specifications for all Intel Core Duo processor and Intel Core Solo processor in standard voltage (SV), low voltage (LV) and ultra low voltage (ULV) products.
Introduction In addition to supporting the existing Streaming SIMD Extensions 2 (SSE2), there are 13 new instructions which extend the capabilities of Intel processor technology further. These new instructions are called Streaming SIMD Extensions 3 (SSE3). 3D graphics and other entertainment applications, such as gaming, will have the opportunity to take advantage of these new instructions as platforms with the processor and SSE3 become available in the market place.
Introduction 1.1 Terminology Term 1.2 Definition # A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted.
Introduction 10 Datasheet
Low Power Features 2 Low Power Features 2.1 Clock Control and Low Power States The Intel Core Duo processor and Intel Core Solo processor support low power states both at the individual core level and the package level for optimal power management. A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, and C4 low power states. Refer to Figure 2 for a visual representation of the core low power states for the Intel Core Duo processor and Intel Core Solo processor.
Low Power Features Figure 1. Package-Level Low Power States SLP# asserted STPCLK# asserted DPSLP# asserted Stop Grant Normal Sleep STPCLK# de-asserted SLP# de-asserted Snoop serviced DPRSTP# asserted Deeper † Sleep Deep Sleep DPSLP# de-asserted DPRSTP# de-asserted Snoop occurs Stop Grant Snoop † — Deeper Sleep includes the Deeper Sleep and the Intel Enhanced Deeper Sleep state. Figure 2.
Low Power Features 2.1.1 Core Low-Power States 2.1.1.1 C0 State This is the normal operating state for the Intel Core Duo processor and Intel Core Solo processor. 2.1.1.2 C1/AutoHALT Powerdown State C1/AutoHALT is a low power state entered when the processor core executes the HALT instruction. The processor core will transition to the C0 state upon the occurrence of SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the processor to immediately initialize itself.
Low Power Features 2.1.1.5 Core C3 State Core C3 state is a very low power state the processor core can enter while maintaining context. Individual cores of the Intel Core Duo processor and Intel Core Solo processor can enter the C3 state by initiating a P_LVL3 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering the C3 state, the processor core flushes the contents of its L1 caches into the processor’s L2 cache.
Low Power Features RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. When RESET# is asserted by the system the STPCLK#, SLP#, DPSLP#, and DPRSTP# pins must be deasserted more than 450 µs prior to RESET# deassertion. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be deasserted ten or more bus clocks after the deassertion of SLP#.
Low Power Features 2.1.2.5 Deep Sleep State Deep Sleep state is a very low power state the processor can enter while maintaining context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform level power savings.
Low Power Features 2.1.2.6.2 Dynamic Cache Sizing Dynamic Cache Sizing allows the processor to flush and disable a programmable number of L2 cache ways upon each Deeper Sleep entry under the following conditions: • The second core is already in C4 and the Intel Enhanced Deeper Sleep state is enabled (as specified in Section 2.1.2.6.1). • The C0 timer, which tracks continuous residency in the Normal package state, has not expired.
Low Power Features — The bus protocol (BNR# mechanism) is used to block snooping • Improved Intel® Thermal Monitor mode. — When the on-die thermal sensor indicates that the die temperature is too high, the processor can automatically perform a transition to a lower frequency/ voltage specified in a software programmable MSR. — The processor waits for a fixed time period. If the die temperature is down to acceptable levels, an up transition to the previous frequency/voltage point occurs.
Low Power Features entry resulting in the processor either executing for a longer time at the lowest operating point or running idle at a high operating point. Observations and analyses show this behavior should not significantly impact total power savings or performance score while providing power benefits in most other cases. 2.
Low Power Features 20 Datasheet
Electrical Specifications 3 Electrical Specifications 3.1 Power and Ground Pins For clean, on-chip power distribution, the processor will have a large number of VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop. Please contact your Intel representative for more details.
Electrical Specifications Table 2. 22 Voltage Identification Definition (Sheet 2 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 0 0 1 0 0 0 0 1.3000 0 0 1 0 0 0 1 1.2875 0 0 1 0 0 1 0 1.2750 0 0 1 0 0 1 1 1.2625 0 0 1 0 1 0 0 1.2500 0 0 1 0 1 0 1 1.2375 0 0 1 0 1 1 0 1.2250 0 0 1 0 1 1 1 1.2125 0 0 1 1 0 0 0 1.2000 0 0 1 1 0 0 1 1.1875 0 0 1 1 0 1 0 1.1750 0 0 1 1 0 1 1 1.1625 0 0 1 1 1 0 0 1.
Electrical Specifications Table 2. Datasheet Voltage Identification Definition (Sheet 3 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 0 1 1 0 1 1 0 0.8250 0 1 1 0 1 1 1 0.8125 0 1 1 1 0 0 0 0.8000 0 1 1 1 0 0 1 0.7875 0 1 1 1 0 1 0 0.7750 0 1 1 1 0 1 1 0.7625 0 1 1 1 1 0 0 0.7500 0 1 1 1 1 0 1 0.7375 0 1 1 1 1 1 0 0.7250 0 1 1 1 1 1 1 0.7125 1 0 0 0 0 0 0 0.7000 1 0 0 0 0 0 1 0.
Electrical Specifications Table 2. 3.4 Voltage Identification Definition (Sheet 4 of 4) VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC (V) 1 0 1 1 1 0 0 0.3500 1 0 1 1 1 0 1 0.3375 1 0 1 1 1 1 0 0.3250 1 0 1 1 1 1 1 0.3125 1 1 0 0 0 0 0 0.3000 1 1 0 0 0 0 1 0.2875 1 1 0 0 0 1 0 0.2750 1 1 0 0 0 1 1 0.2625 1 1 0 0 1 0 0 0.2500 1 1 0 0 1 0 1 0.2375 1 1 0 0 1 1 0 0.2250 1 1 0 0 1 1 1 0.
Electrical Specifications 3.5 Signal Terminations and Unused Pins All RSVD (RESERVED) pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Section 4.2 for a pin listing of the processor and the location of all RSVD pins. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level.
Electrical Specifications Table 4. FSB Pin Groups Signal Group Signals1 Type AGTL+ Common Clock Input Synchronous to BCLK[1:0] BPRI#, DEFER#, DPWR#, PREQ#, RESET#, RS[2:0]#, TRDY# AGTL+ Common Clock I/O Synchronous to BCLK[1:0] ADS#, BNR#, BPM[3:0]#3, BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY#3 Signals AGTL+ Source Synchronous I/O Synchronous to Assoc.
Electrical Specifications 3.8 CMOS Signals CMOS input signals are shown in Table 4. Legacy output FERR#, IERR# and other nonAGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals are required to be asserted for at least three BCLKs in order for the processor to recognize them. See Section 3.10 for the DC specifications for the CMOS signal groups. 3.
Electrical Specifications 3.10 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Table 4 for the pin signal definitions and signal pin assignments. Most of the signals on the FSB are in the AGTL+ signal group. The DC specifications for these signals are listed in Table 12. DC specifications for the CMOS group are listed in Table 13.
Electrical Specifications Table 6. Voltage and Current Specifications for Intel Core Duo Processor SV (Standard Voltage) (Sheet 2 of 2) Symbol Parameter Min Typ Max Unit Notes LFM 11.8 A 3, 4 HFM 20.9 ICC Deep Sleep IDSLP IDPRSLP ICC Deeper Sleep 7.6 A 3, 4 IDC4 ICC Intel Enhanced Deeper Sleep 6.7 A 4 dICC/DT VCC Power Supply Current Slew Rate at CPU Package Pin 600 A/µs ICCA ICC for VCCA Supply 120 mA ICC for VCCP Supply before VCC Stable 6.
Electrical Specifications Table 7. Voltage and Current Specifications for Intel Core Solo Processor SV (Standard Voltage) Symbol Parameter Min Typ Max Unit Notes VCCHFM VCC at Highest Frequency Mode (HFM) 1.1625 1.3 V 1, 2 VCCLFM VCC at Lowest Frequency Mode (LFM) 0.7625 1.0 V 1, 2 VCC,BOOT Default VCC Voltage for Initial Power Up V 2, 8 VCCP AGTL+ Termination Voltage 0.997 1.05 1.102 V 2 VCCA PLL Supply Voltage 1.425 1.5 1.
Electrical Specifications 6. 7. 8. 9. 10. 11. 12. Based on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal VCC. Not 100% tested. Measured at the bulk capacitors on the motherboard. VCC, boot tolerance is shown in Figure 3. This is a steady-state Iccp current specification, which is applicable when both VCCP and Vcc core are high. This is a power-up peak current specification, which is applicable when VCCP is high and Vcc core is low.
Electrical Specifications NOTES: 1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or C1E). 2.
Electrical Specifications Table 9. Symbol Voltage and Current Specifications Intel Core Duo Processor Ultra Low Voltage (ULV) (Sheet 2 of 2) Parameter Min Typ Max Unit Notes IDC4 ICCC Intel Enhanced Deeper Sleep 3.3 A dICC/DT VCC Power Supply Current Slew Rate at CPU Package Pin 600 A/µs ICCA ICC for VCCA Supply 120 mA ICC for VCCP Supply before VCC Stable 6.0 A 11 ICC for VCCP supply after VCC Stable 2.5 A 10 ICCP 4 6, 8 NOTES: 1.
Electrical Specifications Table 10. Voltage and Current Specifications for Intel Core Solo Processor ULV (Ultra Low Voltage) (Sheet 2 of 2) Symbol Parameter Min Typ Max Unit Notes ICC for Intel Core Solo Processor ULV ICC IAH, ISGNT Processor Number Core Frequency/Voltage U1500 1.33 GHz and HFM VCC 8 U1400 1.20 GHz and HFM VCC 8 U1300 1.06 GHz and HFM VCC 8 N/A 800 MHz and LFM VCC 6.4 A 3,11 A 3,4 A 3,4 A 3,4 ICC Auto-Halt & Stop-Grant LFM 3.9 HFM 4.
Electrical Specifications Figure 3. Active VCC and ICC Loadline for Intel Core Duo Processor (SV, LV & ULV) and Intel Core Solo Processor SV VCC [V] Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. VCC max {HFM|LFM} VCC, DC max {HFM|LFM} 10mV= RIPPLE VCC nom {HFM|LFM} VCC, DC min {HFM|LFM} VCC min {HFM|LFM} +/-VCC nom * 1.5% = VR St. Pt. Error 1/ ICC [A] 0 ICC max {HFM|LFM} Note 1/ VCC Set Point Error Tolerance is per below: Tolerance --------------+/-1.
Electrical Specifications Figure 4. Deeper Sleep VCC and ICC Loadline for Intel Core Duo Processor (SV, LV & ULV) and Intel Core Solo Processor SV VCC-CORE [V] Slope = -2.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. VCC-CORE max {Deeper Sleep} 13mV= RIPPLE for PSI# Asserted VCC-CORE, DC max {Deeper Sleep} VCC-CORE nom {Deeper Sleep} VCC-CORE, DC min {Deeper Sleep} VCC-CORE min {Deeper Sleep} +/-VCC-CORE Tolerance = VR St. Pt.
Electrical Specifications Figure 5. Active VCC and ICC Loadline for Intel Core Solo Processor ULV VCC-CORE [V] Slope = -5.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. VCC-CORE max {HFM|LFM} VCC-CORE, DC max {HFM|LFM} 10mV= RIPPLE VCC-CORE nom {HFM|LFM} VCC-CORE, DC min {HFM|LFM} VCC-CORE min {HFM|LFM} +/-VCC-CORE Tolerance = VR St. Pt.
Electrical Specifications Figure 6. Deeper Sleep VCC and ICC Loadline for Intel Core Solo Processor ULV VCC-CORE[V] Slope = -5.1 mV/A at package VccSense, VssSense pins. Differential Remote Sense required. VCC-CORE max {Deeper Sleep} VCC-CORE, DC max {Deeper Sleep} 10 mV= RIPPLE VCC-CORE nom {Deeper Sleep} VCC-CORE, DC min {Deeper Sleep} VCC-CORE min {Deeper Sleep} +/-VCC-CORE Tolerance = VR St. Pt.
Electrical Specifications Table 11. Symbol FSB Differential BCLK Specifications Parameter VIL Input Low Voltage VIH Input High Voltage VCROSS Crossing Voltage ΔVCROSS Min Typ 0 Threshold Region ILI Input Leakage Current Cpad Pad Capacitance Unit Notes1 V 0.660 0.710 0.85 V 0.25 0.35 0.55 V 2 0.14 V 6 VCROSS+0.100 V 3 ± 100 µA 4 1.45 pF 5 Range of Crossing Points VTH Max VCROSS -0.100 0.95 1.2 NOTES: 1.
Electrical Specifications . Table 13. Symbol CMOS Signal Group DC Specifications Parameter Min Typ Max Unit Notes1 VCCP I/O Voltage 1.0 1.05 1.10 V VIL Input Low Voltage CMOS -0.1 0.0 0.33 V 2, 3 VIH Input High Voltage 0.7 1.05 1.20 V 2 VOL Output Low Voltage -0.1 0 0.11 V 2 VOH Output High Voltage 0.9 VCCP 1.20 V 2 IOL Output Low Current 1.3 4.1 mA 4 IOH Output High Current 1.3 4.
Package Mechanical Specifications and Pin Information 4 Package Mechanical Specifications and Pin Information 4.1 Package Mechanical Specifications The Intel Core Duo processor and Intel Core Solo processor are available in 478-pin Micro-FCPGA and 479-ball Micro-FCBGA packages. The package mechanical dimensions are shown in Figure 7 through Figure 10. Table 15 (two sheets) shows a top-view of package pin-out with their functionalities.
Package Mechanical Specifications and Pin Information Figure 7.
Package Mechanical Specifications and Pin Information Figure 8.
Package Mechanical Specifications and Pin Information Figure 9.
Package Mechanical Specifications and Pin Information Figure 10.
Package Mechanical Specifications and Pin Information 4.1.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted in the keepout areas. The location and quantity of the capacitors may change, but will remain within the component keep-in. See Figure 7 and Figure 9 for keep-out zones. 4.1.
Package Mechanical Specifications and Pin Information 4.2 Processor Pinout and Pin List Table 15 shows the top view pinout of the processor. The pin list arranged in two different formats is shown in the following pages. Table 15.
Package Mechanical Specifications and Pin Information Table 16.
Package Mechanical Specifications and Pin Information 4.3 Alphabetical Signals Reference Table 17. Signal Description (Sheet 1 of 9) Name A[31:3]# A20M# Type Description Input/ Output A[31:3]# (Address) define a 232-byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information.
Package Mechanical Specifications and Pin Information Table 17. Signal Description (Sheet 2 of 9) Name BPM[2:1]# BPM[3,0]# Type Description Output BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[3:0]# should connect the appropriate pins of all processor FSB agents.This includes debug or performance monitoring tools.
Package Mechanical Specifications and Pin Information Table 17. Signal Description (Sheet 3 of 9) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64bit data path between the FSB agents, and must connect the appropriate pins on both agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period.
Package Mechanical Specifications and Pin Information Table 17. Signal Description (Sheet 4 of 9) Name Type Description DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle.
Package Mechanical Specifications and Pin Information Table 17. Signal Description (Sheet 5 of 9) Name FERR#/PBE# Type Output Description FERR# (Floating-point Error)PBE#(Pending Break Event) is a multiplexed signal and its meaning is qualified with STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating point when the processor detects an unmasked floating-point error.
Package Mechanical Specifications and Pin Information Table 17. Signal Description (Sheet 6 of 9) Name INIT# Type Input Description INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal.
Package Mechanical Specifications and Pin Information Table 17. Signal Description (Sheet 7 of 9) Name PROCHOT# Type Input/ Output Description As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled.
Package Mechanical Specifications and Pin Information Table 17. Signal Description (Sheet 8 of 9) Name SLP# SMI# Type Description Input SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts.
Package Mechanical Specifications and Pin Information Table 17. Signal Description (Sheet 9 of 9) Name THERMTRIP# Type Output Description The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 125°C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin.
Package Mechanical Specifications and Pin Information 58 Datasheet
Package Mechanical Specifications and Pin Information Table 18. Table 18.
Package Mechanical Specifications and Pin Information Table 18. Pin Listing by Pin Name Table 18.
Package Mechanical Specifications and Pin Information Table 18. Pin Listing by Pin Name Table 18.
Package Mechanical Specifications and Pin Information Table 18. Pin Listing by Pin Name Table 18.
Package Mechanical Specifications and Pin Information Table 18. Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type RSVD C23 RSVD Table 18.
Package Mechanical Specifications and Pin Information Table 18. Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type VCC AC12 VCC Table 18.
Package Mechanical Specifications and Pin Information Table 18. Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type VCC C9 VCC Table 18.
Package Mechanical Specifications and Pin Information Table 18. Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type VSS AD13 VSS Table 18.
Package Mechanical Specifications and Pin Information Table 18. Pin Listing by Pin Name Pin Name Pin Number Signal Buffer Type VSS M2 VSS Table 18.
Package Mechanical Specifications and Pin Information Table 18.
Package Mechanical Specifications and Pin Information Table 19. Table 19.
Package Mechanical Specifications and Pin Information Table 19. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type AB9 VCC AB10 Table 19.
Package Mechanical Specifications and Pin Information Table 19. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type AD10 VCC AD11 Table 19.
Package Mechanical Specifications and Pin Information Table 19. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type AF14 VCC AF15 Table 19.
Package Mechanical Specifications and Pin Information Table 19. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type Direction C20 DBR# CMOS Output C21 BSEL[2] CMOS Output C22 VSS Power/Other C23 RSVD Reserved C24 RSVD Reserved C25 VSS Power/Other C26 TEST1 Test D1 VSS Power/Other D2 RSVD Reserved D3 RSVD Reserved D4 VSS Power/Other D5 STPCLK# CMOS Input D6 PWRGOOD CMOS D7 SLP# CMOS D8 VSS D9 Table 19.
Package Mechanical Specifications and Pin Information Table 19.
Package Mechanical Specifications and Pin Information Table 19. Pin Listing by Pin Number Pin Number Pin Name Signal Buffer Type H24 VSS Power/Other H25 D[15]# Source Synch Input/ Output Direction Table 19.
Package Mechanical Specifications and Pin Information Table 19. Pin Listing by Pin Number Table 19.
Package Mechanical Specifications and Pin Information Table 19.
Package Mechanical Specifications and Pin Information Table 19.
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations The processor requires a thermal solution to maintain temperatures within operating limits as set forth in Section 5.1. Any attempt to operate that processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems.
Thermal Specifications and Design Considerations Table 20. Power Specifications for the Intel Core Duo Processor SV (Standard Voltage) Symbol Processor Number Core Frequency & Voltage Unit Notes W Notes 1, 4, 5 Max Unit Notes at HFM VCC 15.8 W at LFM VCC 4.8 T2700 2.33 GHz & HFM VCC 31 2.16 GHz & HFM VCC 2.00 GHz & HFM VCC 31 T2500 31 T2400 1.83 GHz & HFM VCC 31 T2300 1.66 GHz & HFM VCC 31 T2300E 1.66 GHz & HFM VCC 31 N/A 1.00 GHz & LFM VCC 13.
Thermal Specifications and Design Considerations Table 21. Power Specifications for the Intel Core Solo Processor SV (Standard Voltage) Symbol TDP Processor Number Core Frequency & Voltage Thermal Design Power T1400 1.83 GHz & HFM VCC 27 T1300 1.66 GHz & HFM VCC 27 N/A 1.00 GHz & LFM VCC 13.1 Symbol PAH, PSGNT Parameter Min Typ Unit W Max Unit at HFM VCC 15.8 W at LFM VCC 4.8 Auto Halt, Stop Grant Power Sleep Power PSLP at HFM VCC 15.5 at LFM VCC 4.
Thermal Specifications and Design Considerations Table 22. Power Specifications for the Intel Core Duo Processor LV (Low Voltage) Symbol TDP Processor Number Core Frequency & Voltage Thermal Design Power L2500 1.83 GHz & HFM VCC 15 L2400 1.66 GHz & HFM VCC 15 L2300 1.50 GHz & HFM VCC 15 N/A 1.00 GHz & LFM VCC 13.1 Symbol PAH, PSGNT Parameter Min Typ Unit W Max Unit at HFM VCC 6.0 W at LFM VCC 4.8 Auto Halt, Stop Grant Power Sleep Power PSLP at HFM VCC 5.8 at LFM VCC 4.
Thermal Specifications and Design Considerations Table 23. Power Specifications for the Intel Core Duo Processor, Ultra Low Voltage (ULV) Processor Number Symbol TDP PSGNT Thermal Design Power U2500 1.20 GHz & HFM VCC 9 U2400 1.06 GHz & HFM VCC 9 N/A 800 MHz & LFM VCC 7.5 Symbol PAH, Core Frequency & Voltage Parameter Min Typ Unit W Max Unit at HFM VCC 3.7 W at LFM VCC 2.6 Auto Halt, Stop Grant Power Sleep Power PSLP at HFM VCC 3.6 at LFM VCC 2.
Thermal Specifications and Design Considerations Table 24. Power Specifications for the Intel Core Solo Processor ULV (Ultra Low Voltage) Symbol Processor Number U1500 TDP Core Frequency & Voltage Thermal Design Power 1.33 GHz and HFM VCC 5.5 1.20 GHz and HFM VCC1.06 GHz and LFM VCC U1400 U1300 5.5 PAH, PSGNT Parameter W 5.5 Min Typ Max Unit at HFM VCC 3.0 W at LFM VCC 2.2 Auto Halt, Stop Grant Power Sleep Power PSLP at HFM VCC 2.9 at LFM VCC 2.
Thermal Specifications and Design Considerations 5.1 Thermal Specifications The processor incorporates three methods of monitoring die temperature, the digital thermal sensor (DTS), Intel Thermal Monitor and the thermal diode. The Intel Thermal Monitor (detailed in Section 5.1.3) must be used to determine when the maximum specified processor junction temperature has been reached. 5.1.
Thermal Specifications and Design Considerations Table 26. Thermal Diode Parameters using Diode Mode Symbol Min Typ Max Unit Notes Forward Bias Current 5 - 200 µA 1 n Diode Ideality Factor 1.000 1.009 1.050 - 2, 3, 4 RT Series Resistance 2.79 4.52 6.24 Ω 2, 3, 5 IFW Parameter NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias.
Thermal Specifications and Design Considerations When calculating a temperature based on thermal diode measurements, a number of parameters must be either measured or assumed. Most devices measure the diode ideality and assume a series resistance and ideality trim value, although some are capable of also measuring the series resistance. Calculating the temperature is then accomplished using the equations listed under Table 25.
Thermal Specifications and Design Considerations The Intel Thermal Monitor controls the processor temperature by modulating (starting and stopping) the processor core clocks or by initiating an Enhanced Intel SpeedStep Technology transition when the processor silicon reaches its maximum operating temperature. The Intel Thermal Monitor uses two modes to activate the TCC: Automatic mode and on-demand mode. If both modes are activated, Automatic mode takes precedence.
Thermal Specifications and Design Considerations if the system tries to enable the TCC via on-demand mode at the same time automatic mode is enabled and a high temperature condition exists, automatic mode will take precedence. An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active.
Thermal Specifications and Design Considerations and thermal attach and software application. The system designer is required to use the DTS to guarantee proper operation of the processor within its temperature operating specifications Changes to the temperature can be detected via two programmable thresholds located in the processor MSRs. These thresholds have the capability of generating interrupts via the core's local APIC. 5.1.
Thermal Specifications and Design Considerations short periods of time when running the most power intensive applications. An underdesigned thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss.
