Intel® Core™2 Duo Processor E8000Δ and E7000Δ Series Specification Update — on 45 nm Process in the 775-land LGA Package December 2010 Notice: The Intel® CoreTM2 Duo processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
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Contents Contents .............................................................................................................................3 Revision History ...................................................................................................................4 Preface ...............................................................................................................................6 Summary Tables of Changes ......................................................................
Revision History Revision Number Description Date Initial release of Intel® Core™2 Duo Desktop Processor E8000 Series Specification Update 001 Jan 7th 2008 Feb 1st 2008 002 • Added Erratum AW51 003 • Added Errata AW52 to AW54 Feb 13th 2008 004 • Changed document title to include E7000 series • Included E7200 and E8300 processor information April 20th 2008 005 • Included M0 stepping information • Added new errata AW55-AW57 May 14th 2008 • Added Spec Clarification AW1 4 006 • Updated Errat
Revision Number Description 017 • Added Errata AW77 and AW78 018 • Added Errata AW79 019 • Added Errata AW80 • Removed Item Numbering Section 020 • Added Erratum AW81 Intel® Core™2 Duo Processor Specification Update – December 2010 Date July 15th 2009 March 16th, 2010 July 19th, 2010 December 8th 2010 5
Preface Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
Preface Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics (e.g., core speed, L2 cache size, package type, etc.) as described in the processor identification information table. Care should be taken to read all notes associated with each S-Spec number QDF Number is a several digit code that is used to distinguish between engineering samples. These processors are used for qualification and early design validation.
Summary Tables of Changes Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
Summary Tables of Changes The Specification Updates for the Pentium® processor, Pentium® Pro processor, and other Intel products do not use this convention.
Summary Tables of Changes 10 NO C0 M0 E0 R0 Plan ERRATA AW20 X X X X No Fix EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after Shutdown AW21 X X X X No Fix Premature Execution of a Load Operation Prior to Exception Handler Invocation AW22 X X X X No Fix Performance Monitoring Events for Retired Instructions (C0H) May Not Be Accurate AW23 X X X X No Fix Returning to Real Mode from SMM with EFLAGS.
Summary Tables of Changes NO C0 M0 E0 R0 Plan AW40 X X X X No Fix A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to Memory-Ordering Violations AW41 X Fixed VM Exit with Exit Reason “TPR Below Threshold” Can Cause the Blocking by MOV/POP SS and Blocking by STI Bits to be Cleared in the Guest Interruptibility-State Field AW42 X No Fix Using Memory Type Aliasing with cacheable and WC Memory Types May Lead to Memory Ordering Violations AW43 X No Fix VM Exit Caused by a SIPI Res
Summary Tables of Changes NO C0 M0 R0 Plan AW61 X X No Fix Processor May Hold-off / Delay a PECI Transaction Longer than Specified by the PECI Protocol AW62 X No Fix VM Entry May Use Wrong Address to Access Virtual-APIC Page AW63 X X No Fix XRSTOR Instruction May Cause Extra Memory Reads AW64 X X Plan Fix CPUID Instruction May Return Incorrect Brand String AW65 X AW66 X AW67 AW68 No Fix Global Instruction TLB Entries May Not be Invalidated on a VM Exit or VM Entry X No Fix
Summary Tables of Changes Number - SPECIFICATION CHANGES There are no Specification Changes in this Specification Update revision. Number AW1 SPECIFICATION CLARIFICATIONS Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Number - DOCUMENTATION CHANGES There are no Documentation Changes in this Specification Update revision.
Identification Information Identification Information Figure 1.
Component Identification Information Component Identification Information The Intel® Core™2 duo processor can be identified by the following values: Reserved Extended Family1 31:28 Extended Reserved Model2 27:20 19:16 00000000b 0001b 15:14 Processor Type3 Family Code4 Model Number5 Stepping ID6 13:12 11:8 7:4 3:0 00b 0110b 0111b XXXXb When EAX is initialized to a value of 1, the CPUID instruction returns the Extended Family, Extended Model, Type, Family, Model and Stepping value in the E
Component Identification Information Table 1. Intel® Core™2 Duo Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Processor Number Speed Core/Bus Package Notes SLAPC M0 3 MB 10676h E7200 2.53 GHz / 1066 MHz 775-land LGA 1, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 14 SLAVN M0 3 MB 10676h E7200 2.53 GHz / 1066 MHz 775-land LGA 1, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13 SLAVP M0 3 MB 10676h E7300 2.
Component Identification Information 7. These 8. These 9. These 10. These 11. These 12. These 13. These 14. These parts parts parts parts parts parts parts parts have THERMTRIP# enabled support Thermal Monitor 2 (TM2) feature have PECI enabled have Enhanced Intel SpeedStep® Technology (EIST) enabled have Extended HALT State (C1E) enabled have Extended Stop Grant State (C2E) enabled.
Errata Errata AW1. EFLAGS Discrepancy on Page Faults after a Translation Change Problem: This erratum is regarding the case where paging structures are modified to change a linear address from writable to non-writable without software performing an appropriate TLB invalidation.
Errata AW3. Store to WT Memory Data May be Seen in Wrong Order by Two Subsequent Loads Problem: When data of Store to WT memory is used by two subsequent loads of one thread and another thread performs cacheable write to the same address the first load may get the data from external memory or L2 written by another core, while the second load will get the data straight from the WT Store. Implication: Software that uses WB to WT memory aliasing may violate proper store ordering.
Errata Violation #GP (General Protection Fault).
Errata Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AW9. A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware Problem: The MONITOR instruction is used to arm the address monitoring hardware for the subsequent MWAIT instruction. The hardware is triggered on subsequent memory store operations to the monitored address range.
Errata AW12. Code Segment Limit Violation May Occur on 4 Gigabyte Limit Check Problem: Code Segment limit violation may occur on 4 Gigabyte limit check when the code streamwraps around in a way that one instruction ends at the last byte of the segment and the next instruction begins at 0x0. Implication: This is a rare condition that may result in a system hang. Intel has not observed this erratum with any commercially available software, or system.
Errata AW15. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering Violations. Problem: Under certain conditions as described in the Software Developers Manual section “Out-of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors” the processor performs REP MOVS or REP STOS as fast strings.
Errata Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AW18. Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher Priority Interrupts/Exceptions Problem: Normally, when the processor encounters a Segment Limit or Canonical Fault due to code execution, a #GP (General Protection Exception) fault is generated after all higher priority Interrupts and exceptions are serviced.
Errata AW21. Premature Execution of a Load Operation Prior to Exception Handler Invocation Problem: If any of the below circumstances occur, it is possible that the load portion of the instruction will have executed before the exception handler is entered. 1) If an instruction that performs a memory load causes a code segment limit violation. 2) If a waiting X87 floating-point (FP) instruction or MMX™ technology (MMX) instruction that performs a memory load has a floating-point exception pending.
Errata b) RSM from an SMI during a HLT instruction. Implication: There may be a smaller than expected value in the INST_RETIRED performance monitoring counter. The extent to which this value is smaller than expected is determined by the frequency of the above cases. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AW23. Returning to Real Mode from SMM with EFLAGS.
Errata will be left set in the in-service register and mask all interrupts at the same or lower priority. Workaround: Any vector programmed into an LVT entry must have an ISR associated with it, even if that vector was programmed as masked. This ISR routine must do an EOI to clear any unexpected interrupts that may occur. The ISR associated with the spurious vector does not generate an EOI, therefore the spurious vector should not be used when writing the LVT.
Errata • The processor is in protected mode with paging enabled and the page global enable flag is set (PGE bit of CR4 register) • G bit for the page table entry is set • TLB entry is present in TLB when INIT occurs Implication: Software may encounter unexpected page fault or incorrect address translation due to a TLB entry erroneously left in TLB after INIT.
Errata Problem: Software which is written so that multiple agents can modify the same shared unaligned memory location at the same time may experience a memory ordering issue if multiple loads access this shared data shortly thereafter. Exposure to this problem requires the use of a data write which spans a cache line boundary. Implication: This erratum may cause loads to be observed out of order. Intel has not observed this erratum with any commercially available software or system.
Errata Problem: CPUID leaf 0Ah reports the architectural performance monitoring version that is available in EAX[7:0]. Due to this erratum CPUID reports the supported version as 2 instead of 1. Implication: Software will observe an incorrect version number in CPUID.0Ah.EAX [7:0] in comparison to which features are actually supported.
Errata Workaround: BIOS must leave the xTPR update transactions disabled (default). Status: For the steppings affected, see the Summary Tables of Changes. AW37. Performance Monitoring Event IA32_FIXED_CTR2 May Not Function Properly when Max Ratio is a Non-Integer Core-to-Bus Ratio Problem: Performance Counter IA32_FIXED_CTR2 (MSR 30BH) event counts CPU reference clocks when the core is not in a halt state. This event is not affected by core frequency changes (e.g.
Errata Implication: This erratum has not been observed with commercially available software. Workaround: Although it is possible to have a single physical page mapped by two different linear addresses with different memory types, Intel has strongly discouraged this practice as it may lead to undefined results. Software that needs to implement memory aliasing should manage the memory type consistency. Status: For the steppings affected, see the Summary Tables of Changes. AW40.
Errata VM-execution control field above that of the TPR shadow while either of those bits is 1, incorrect behavior may result. This may lead to VMM software prematurely injecting an interrupt into a guest. Intel has not observed this erratum with any commercially available software. Workaround: VMM software raising the value of the TPR-threshold VM-execution control field should compare it to the TPR shadow.
Errata should (1) save from the VMCS (using VMREAD) the value of RIP before any VM entry to the wait-for SIPI state; and (2) restore to the VMCS (using VMWRITE) that value before the next VM entry that resumes the guest in any state other than wait-for-SIPI. Status: For the steppings affected, see the Summary Tables of Changes. AW44.
Errata Problem: If instructions from at least three different ways in the same instruction cache set exist in the pipeline combined with some rare internal state, selfmodifying code (SMC) or cross-modifying code may not be detected and/or handled. Implication: An instruction that should be overwritten by another instruction while in the processor pipeline may not be detected/modified, and could retire without detection. Alternatively the instruction may cause a Machine Check Exception.
Errata AW49. RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results Problem: RSM instruction execution, under certain conditions triggered by a complex sequence of internal processor micro-architectural events, may lead to processor hang, or unexpected instruction execution results.
Errata AW52. An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception Problem: A MOV SS/POP SS instruction should inhibit all interrupts including debug breakpoints until after execution of the following instruction. This is intended to allow the sequential execution of MOV SS/POP SS and MOV [r/e]SP, [r/e]BP instructions without having an invalid stack during interrupt handling.
Errata AW54. IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check Error Reporting Enable Correctly Problem: IA32_MC1_STATUS MSR (405H) bit[60] (EN- Error Enabled) is supposed to indicate whether the enable bit in the IA32_MC1_CTL MSR (404H) was set at the time of the last update to the IA32_MC1_STATUS MSR. Due to this erratum, IA32_MC1_STATUS MSR bit[60] instead reports the current value of the IA32_MC1_CTL MSR enable bit.
Errata Implication: A VM Exit will occur when a VMX Abort was expected. Workaround: An SMM VMM should always set the “IA-32e guest” VM-entry control in the SMM VMCS to be the value that was in the LMA bit (IA32_EFER.LMA.LMA[bit 10]) in the IA32_EFER MSR (C0000080H) at the time of the last SMM VM exit. If this guideline is followed, that value will be 1 only if the “host address-space size” VM-exit control is 1 in the executive VMCS. Status: For the steppings affected, see the Summary Tables of Changes.
Errata AW59. Thermal Interrupts are Dropped During and While Exiting Intel® Deep Power-Down State Problem: Thermal interrupts are ignored while the processor is in Intel Deep PowerDown State as well as during a small window of time while exiting from Intel Deep Power-Down State. During this window, if the PROCHOT signal is driven or the internal value of the sensor reaches the programmed thermal trip point, then the associated thermal interrupt may be lost.
Errata beginning of a PECI message coincides with a C-state transition, and the processor is executing a long instruction flow. Note that the processor can still complete the PECI transaction if the host chooses to process the remainder of the message. Implication: Due to this erratum, the processor may violate the PECI hold-off protocol. Workaround: PECI hosts can choose to either complete or not complete PECI transactions when the processor goes beyond the hold-off limit.
Errata Implication: When this erratum occurs, the processor may report an incorrect brand string. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AW65. Global Instruction TLB Entries May Not be Invalidated on a VM Exit or VM Entry Problem: If a VMM is using global page entries (CR4.
Errata Workaround: It is possible for the BIOS to contain a workaround for this erratum. Do not initialize PECI before processor update is loaded. Also, load processor update as soon as possible after RESET as documented in the RS – Wolfdale Processor Family Bios Writers Guide, Section 14.8.3 Bootstrap Processor Initialization Requirements. Status: For the steppings affected, see the Summary Tables of Changes. AW68.
Errata exception/interrupt occurs right after the execution of an instruction at the lower canonical boundary (0x00007FFFFFFFFFFF) in 64-bit mode, the LBR return registers will save a wrong return address with bits 63 to 48 incorrectly sign extended to all 1’s. Subsequent BTS and BTM operations which report the LBR will also be incorrect. Implication: LBR, BTS and BTM may report incorrect information in the event of an exception/interrupt. Workaround: None identified.
Errata Status: For the steppings affected, see the Summary Tables of Changes. AW73. Store Ordering Violation When Using XSAVE Problem: The store operations done as part of the XSAVE instruction may cause a store ordering violation with older store operations. The store operations done to save the processor context in the XSAVE instruction flow , when XSAVE is used to store only the SSE context, may appear to execute before the completion of older store operations.
Errata behaviors. In the event that unpredictable execution causes a GPF the application executing the unsynchronized XMC operation would be terminated by the operating system. Workaround: In order to avoid this erratum, programmers should use the XMC synchronization algorithm as detailed in the Intel Architecture Software Developer's Manual Volume 3: System Programming Guide, Section: Handling Self- and Cross-Modifying Code. Status: For the steppings affected, see the Summary Tables of Changes. AW76.
Errata with no virtual-NMI blocking but with blocking of events by either MOV SS or STI, such a VM exit should occur after execution of one instruction in VMX non-root operation. Due to this erratum, the VM exit may be delayed by one additional instruction. Implication: VMM software using “NMI-window exiting” for NMI virtualization should generally be unaffected, as the erratum causes at most a one-instruction delay in the injection of a virtual NMI, which is virtually asynchronous.
Errata Workaround: Software seeking to load the IA32_DEBUGCTL MSR as part of VM entry should place the desired value in the guest IA32_DEBUGCTL field in the VMCS and set the “load debug controls” VM-entry control to 1. Status: For the steppings affected, see the Summary Tables of Changes. AW81. A 64-bit Register IP-relative Instruction May Return Unexpected Results Problem: Under an unlikely and complex sequence of conditions in 64-bit mode, a register IP-relative instruction result may be incorrect.
Specification Changes Specification Changes The Specification Changes listed in this section apply to the following documents: • • Intel® Core™2 Duo Processor E8000 and E7000 Series Datasheet Intel® 64 and IA-32 Architectures Software Developer’s Manual volumes 1,2A, 2B, 3A, and 3B All Specification Changes will be incorporated into a future version of the appropriate processor documentation.
Specification Clarifications Specification Clarifications The Specification Clarifications listed in this section apply to the following documents: • • Intel® Core™2 Duo Processor E8000 and E7000 Series Datasheet Intel® 64 and IA-32 Architectures Software Developer’s Manual volumes 1,2A, 2B, 3A, and 3B All Specification Clarifications will be incorporated into a future version of the appropriate processor documentation. AW1. Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation Section 10.
Documentation Changes Documentation Changes The Documentation Changes listed in this section apply to the following documents: • Intel® Core™2 Duo Processor E8000 and E7000 Series Datasheet All Documentation Changes will be incorporated into a future version of the appropriate processor documentation.
