Intel® Core™2 Extreme Processor X6800Δ and Intel® Core™2 Duo Desktop Processor E6000Δ and E4000Δ Series Datasheet —on 65 nm Process in the 775-land LGA Package and supporting Intel® 64 Architecture and supporting Intel® Virtualization Technology± March 2008 Document Number: 313278-008
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Contents 1 Introduction ............................................................................................................ 11 1.1 Terminology ..................................................................................................... 12 1.1.1 Processor Terminology ............................................................................ 12 1.2 References .......................................................................................................
5.3 5.4 5.2.4 PROCHOT# Signal ..................................................................................87 5.2.5 THERMTRIP# Signal ................................................................................87 Thermal Diode...................................................................................................88 Platform Environment Control Interface (PECI) ......................................................90 5.4.1 Introduction ....................................................
Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Datasheet VCC Static and Transient Tolerance ............................................................................. 23 VCC Overshoot Example Waveform ............................................................................. 24 Differential Clock Waveform ......................................................................................
Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 6 Reference Documents ...............................................................................................14 Voltage Identification Definition ..................................................................................17 Market Segment Selection Truth Table for MSID[1:0] ...................................................18 Absolute Maximum and Minimum Ratings ...........
Revision History Revision Number -001 -002 -003 -004 Description • Initial release July 2006 • Corrected L1 Cache information September 2006 • • • • • • • Added Intel® Core™2 Duo Desktop Processor E4300 information Updated Table 5, DC Voltage and Current Specification Added Section 2.3, PECI DC Specifications Updated Section 5.3, Platform Environment Control Interface (PECI) Updated Section 7.1.
Datasheet
Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Series Features • Available at 2.93 GHz (Intel Core™2 Extreme processor X6800 only) • Available at 3.00 GHz, 2.66 GHz, 2.40 GHz, 2.33 GHz, 2.13 GHz, and 1.86 GHz (Intel Core™2 Duo desktop processor E6850, E6750, E6700, E6600, E6540, E6540, E6420, E6400, E6320, and E6300 only) • Available at 2.40 GHz, 2.20 GHz, 2.00 GHz, and 1.
Datasheet
Introduction 1 Introduction The Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000 and E4000 series combine the performance of the previous generation of desktop products with the power efficiencies of a low-power microarchitecture to enable smaller, quieter systems. These processors are 64-bit processors that maintain compatibility with IA-32 software.
Introduction 1.1 Terminology A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted.
Introduction • Functional operation — Refers to normal operating conditions in which all processor specifications, including DC, AC, system bus, signal quality, mechanical and thermal are satisfied. • Execute Disable Bit — Allows memory to be marked as executable or nonexecutable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system.
Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Table 1. Reference Documents Document Location Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Series Specification Update www.intel.com/design/ processor/specupdt/ 313279.htm Intel® Core™2 Duo Processor and Intel® Pentium® Dual Core Processor Thermal and Mechanical Design Guidelines http://www.intel.
Electrical Specifications 2 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided. 2.1 Power and Ground Lands The processor has VCC (power), VTT and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to VCC, while all VSS lands must be connected to a system ground plane.
Electrical Specifications 2.2.3 FSB Decoupling The processor integrates signal termination on the die. In addition, some of the high frequency capacitance required for the FSB is included on the processor package. However, additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation. 2.
Electrical Specifications Table 2. Voltage Identification Definition VID6 VID5 VID4 VID3 VID2 VID1 VID (V) VID6 VID5 VID4 VID3 VID2 VID1 VID (V) 1 1 1 1 0 1 0.8500 0 1 1 1 1 0 1.2375 1 1 1 1 0 0 0.8625 0 1 1 1 0 1 1.2500 1 1 1 0 1 1 0.8750 0 1 1 1 0 0 1.2625 1 1 1 0 1 0 0.8875 0 1 1 0 1 1 1.2750 1 1 1 0 0 1 0.9000 0 1 1 0 1 0 1.2875 1 1 1 0 0 0 0.9125 0 1 1 0 0 1 1.3000 1 1 0 1 1 1 0.9250 0 1 1 0 0 0 1.
Electrical Specifications 2.4 Market Segment Identification (MSID) The MSID[1:0] signals may be used as outputs to determine the Market Segment of the processor. Table 3 provides details regarding the state of MSID[1:0]. A circuit can be used to prevent 130 W TDP processors from booting on boards optimized for 65 W TDP. Table 3.
Electrical Specifications The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below.
Electrical Specifications Table 4. Absolute Maximum and Minimum Ratings Symbol Parameter Min Max Unit Notes1, VCC Core voltage with respect to VSS –0.3 1.55 V - VTT FSB termination voltage with respect to VSS –0.3 1.55 V - TC Processor case temperature See Chapter 5 See Chapter 5 °C - TSTORAGE Processor storage temperature –40 85 °C 3, 4, 5 2 NOTES: 1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied.
Electrical Specifications Table 5. Voltage and Current Specifications Symbol VCCPLL Parameter PLL VCC Processor Number ICC VTT VTT_OUT_LEFT and VTT_OUT_RIGHT ICC ITT Min Typ Max - 5% 1.50 + 5% Unit Notes1, 2 ICC for 775_VR_CONFIG_06 E6850 E6750 E6700 E6600 E6550 E6540 E6400/E6420 E6300/E6320 E4700 E4600 E4500 E4400 E4300 3.00 2.66 2.66 2.40 2.33 2.33 2.13 1.86 2.60 2.40 2.20 2.00 1.
Electrical Specifications Table 6. VCC Static and Transient Tolerance Voltage Deviation from VID Setting (V)1, 2, 3, 4 ICC (A) Maximum Voltage 1.30 mΩ Typical Voltage 1.425 mΩ Minimum Voltage 1.55 mΩ 0 0.000 -0.019 -0.038 5 -0.007 -0.026 -0.046 10 -0.013 -0.033 -0.054 15 -0.020 -0.040 -0.061 20 -0.026 -0.048 -0.069 25 -0.033 -0.055 -0.077 30 -0.039 -0.062 -0.085 35 -0.046 -0.069 -0.092 40 -0.052 -0.076 -0.100 45 -0.059 -0.083 -0.108 50 -0.065 -0.090 -0.
Electrical Specifications Figure 1. VCC Static and Transient Tolerance Icc [A] 0 10 20 30 40 50 60 70 VID - 0.000 VID - 0.013 VID - 0.025 Vcc Maximum VID - 0.038 VID - 0.050 Vcc [V] VID - 0.063 VID - 0.075 Vcc Typical VID - 0.088 VID - 0.100 Vcc Minimum VID - 0.113 VID - 0.125 VID - 0.138 VID - 0.150 VID - 0.163 NOTES: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.6.3. 2.
Electrical Specifications 2.6.3 VCC Overshoot The processor can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high to low current load condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot voltage). The time duration of the overshoot event must not exceed TOS_MAX (TOS_MAX is the maximum allowable time duration above VID).
Electrical Specifications 2.7 Signaling Specifications Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. Platforms implement a termination voltage level for GTL+ signals defined as VTT. Because platforms implement separate power planes for each processor (and chipset), separate VCC and VTT supplies are necessary.
Electrical Specifications Table 8.
Electrical Specifications 2.7.2 CMOS and Open Drain Signals Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input buffers. All of the CMOS and Open Drain signals are required to be asserted/deasserted for at least four BCLKs in order for the processor to recognize the proper signal state. See Section 2.7.3 for the DC. See Section 6.2 for additional timing requirements for entering and leaving the low power states. 2.7.
Electrical Specifications . Table 13. CMOS Signal Group DC Specifications Symbol Parameter Min Max Unit Notes1 VIL Input Low Voltage -0.10 VTT * 0.30 V 2, 3 VIH Input High Voltage VTT * 0.70 VTT + 0.10 V 3, 4, 5 VOL Output Low Voltage -0.10 VTT * 0.10 V 3 VOH Output High Voltage 0.90 * VTT VTT + 0.10 V 3, 6, 5 IOL Output Low Current 1.70 4.70 mA 3, 7 IOH Output High Current 1.70 4.
Electrical Specifications 2.7.4 Clock Specifications 2.7.5 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor’s core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its default ratio during manufacturing. Refer to Table 15 for the processor supported ratios.
Electrical Specifications Table 16. 2.7.7 BSEL[2:0] Frequency Table for BCLK[1:0] BSEL2 BSEL1 BSEL0 FSB Frequency L L L 266 MHz L L H RESERVED L H H RESERVED L H L 200 MHz H H L RESERVED H H H RESERVED H L H RESERVED H L L 333 MHz Phase Lock Loop (PLL) and Filter An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is used for the PLL. Refer to Table 5 for DC specifications. 2.7.
Electrical Specifications Figure 3. Differential Clock Waveform CLK 0 VCROSS Median + 75 mV VCROSS median VCROSS VCROSS Max 550 mV VCROSS VCROSS Min 300 mV Median - 75 mV CLK 1 High Time median Low Time Period Figure 4. Differential Clock Crosspoint Specification 650 Crossing Point (mV) 600 550 550 mV 500 450 550 + 0.5 (VHavg - 700) 400 300 + 0.5 (VHavg - 700) 350 300 250 300 mV 200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg (mV) Figure 5.
Electrical Specifications 2.7.9 BCLK[1:0] Specifications (CK410 based Platforms) Table 18. Front Side Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes1 VL Input Low Voltage -0.150 0.000 N/A V 3 - VH Input High Voltage 0.660 0.700 0.850 V 3 - VCROSS(abs) Absolute Crossing Point 0.250 N/A 0.550 V 3, 4 2, 3 VCROSS(rel) Relative Crossing Point 0.250 + 0.5(VHavg – 0.700) N/A 0.550 + 0.5(VHavg – 0.
Electrical Specifications 2.8 PECI DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors (may also include chipset components in the future) and external thermal monitoring devices. The processor contains Digital Thermal Sensors (DTS) distributed throughout die.
Electrical Specifications 34 Datasheet
Package Mechanical Specifications 3 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications Figure 8.
Package Mechanical Specifications Figure 9.
Package Mechanical Specifications Figure 10.
Package Mechanical Specifications 3.1.1 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 8 and Figure 9 for keep-out zones.
Package Mechanical Specifications 3.1.4 Package Insertion Specifications The processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket Mechanical Design Guide. 3.1.5 Processor Mass Specification The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package. 3.1.
Package Mechanical Specifications Figure 12. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E6000 Series with 4 MB L2 Cache with 1066 MHz FSB INTEL M ©'05 INTEL® CORE™2 DUO 6700 SLxxx [COO] 2.66GHZ/4M/1066/06 [FPO] e4 ATPO S/N Figure 13. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E6000 Series with 2 MB L2 Cache INTEL M ©'05 INTEL® CORE™2 DUO 6400 SLxxx [COO] 2.
Package Mechanical Specifications Figure 14. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E4000 Series with 2 MB L2 Cache INTEL M ©'05 E4500 INTEL® CORE™2 DUO SLxxx [COO] 2.20GHZ/2M/800/06 [FPO] e4 ATPO S/N E E Figure 15. Processor Top-Side Markings for the Intel® Core™2 Extreme Processor X6800 INTEL M ©'05 INTEL® CORE™2 EXTREME 6800 SLxxx [COO] 2.
Package Mechanical Specifications 3.1.8 Processor Land Coordinates Figure 16 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. . Figure 16.
Package Mechanical Specifications 44 Datasheet
Land Listing and Signal Descriptions 4 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown in Figure 17 and Figure 18. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array (top view).
Land Listing and Signal Descriptions Figure 17.
Land Listing and Signal Descriptions Figure 18.
Land Listing and Signal Descriptions Table 23. Land Name 48 Alphabetical Land Assignments Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Datasheet Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name 50 Alphabetical Land Assignments Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Datasheet Alphabetical Land Assignments Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23. Land Name 52 Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Datasheet Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name 54 Alphabetical Land Assignments Land Signal Buffer # Type Table 23.
Land Listing and Signal Descriptions Table 23. Land Name Datasheet Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name 56 Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23.
Land Listing and Signal Descriptions Table 23. Land Name VSS Datasheet Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23.
Land Listing and Signal Descriptions Table 24. Land # 58 Numerical Land Assignment Land Name Signal Buffer Type A2 VSS Power/Other A3 RS2# Common Clock A4 D02# A5 D04# Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Land # Land Name C20 DBI3# C21 D58# C22 VSS C23 C24 Signal Buffer Type Table 24.
Land Listing and Signal Descriptions Table 24. 60 Numerical Land Assignment Land # Land Name F11 D23# F12 D24# Signal Buffer Type Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Table 24.
Land Listing and Signal Descriptions Table 24. Land # 62 Numerical Land Assignment Land Name Signal Buffer Type Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Land # Land Name Signal Buffer Type U28 VCC U29 U30 Table 24.
Land Listing and Signal Descriptions Table 24. 64 Numerical Land Assignment Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Land # Land Name Signal Buffer Type AF12 VCC Table 24.
Land Listing and Signal Descriptions Table 24. Land # 66 Numerical Land Assignment Land Name Signal Buffer Type Table 24.
Land Listing and Signal Descriptions Table 24. Datasheet Numerical Land Assignment Land # Land Name Signal Buffer Type AL18 VCC AL19 AL20 Table 24.
Land Listing and Signal Descriptions 4.2 Alphabetical Signals Reference Table 25. Signal Description (Sheet 1 of 9) Name A[35:3]# Type Input/ Output Description A[35:3]# (Address) define a 236-byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# should connect the appropriate pins/lands of all processor FSB agents. BPM[5:0]# Input/ Output BPM4# provides PRDY# (Probe Ready) functionality for the TAP port.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will, thus, be driven four times in a common clock period.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name DEFER# DRDY# Type Input Input/ Output Description DEFER# is asserted by an agent to indicate that a transaction cannot be ensured in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or input/ output agent. This signal must connect the appropriate pins/lands of all processor FSB agents.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name HIT# HITM# IERR# Type Input/ Output Input/ Output Output Description HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any FSB agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together. IERR# (Internal Error) is asserted by a processor as the result of an internal error.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins/lands of all processor FSB agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. LOCK# Input/ Output MSID[1:0] Output These signals indicate the Market Segment for the processor.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description RESERVED All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description Output In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 °C above the maximum TC. Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur.
Land Listing and Signal Descriptions Table 25. Signal Description (Sheet 1 of 9) Name Type Description VRDSEL Input This input should be left as a no connect in order for the processor to boot. The processor will not boot on legacy platforms where this land is connected to VSS. VSS Input VSS are the ground pins for the processor and should be connected to the system ground plane. VSSA Input VSSA is the isolated ground for internal PLLs.
Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations 5.1 Processor Thermal Specifications The processor requires a thermal solution to maintain temperatures within the operating limits as described in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system.
Thermal Specifications and Design Considerations complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 26 instead of the maximum processor power consumption. The Thermal Monitor feature is designed to protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained periods of time. For more details on the usage of this feature, refer to Section 5.2.
Thermal Specifications and Design Considerations Table 27. Thermal Profile 1 Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 44.7 24 54.8 48 64.9 2 45.5 26 55.6 50 65.7 4 46.4 28 56.5 52 66.5 6 47.2 30 57.3 54 67.4 8 48.1 32 58.1 56 68.2 10 48.9 34 59.0 58 69.1 12 49.7 36 59.8 60 69.9 14 50.6 38 60.7 62 70.7 16 51.4 40 61.5 64 71.6 18 52.3 42 62.3 65 72.0 20 53.1 44 63.2 22 53.9 46 64.
Thermal Specifications and Design Considerations Table 28. Thermal Profile 2 Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 43.2 24 49.4 48 55.7 2 43.7 26 50.0 50 56.2 4 44.2 28 50.5 52 56.7 6 44.8 30 51.0 54 57.2 8 45.3 32 51.5 56 57.8 10 45.8 34 52.0 58 58.3 12 46.3 36 52.6 60 58.8 14 46.8 38 53.1 62 59.3 16 47.4 40 53.6 64 59.8 18 47.9 42 54.1 65 60.1 20 48.4 44 54.6 22 48.9 46 55.
Thermal Specifications and Design Considerations Table 29. Thermal Profile 3 Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 45.3 24 55.6 48 65.9 2 46.2 26 56.5 50 66.8 4 47.0 28 57.3 52 67.7 6 47.9 30 58.2 54 68.5 8 48.7 32 59.1 56 69.4 10 49.6 34 59.9 58 70.2 12 50.5 36 60.8 60 71.1 14 51.3 38 61.6 62 72.0 16 52.2 40 62.5 64 72.8 18 53.0 42 63.4 65 73.3 20 53.9 44 64.2 22 54.8 46 65.
Thermal Specifications and Design Considerations Table 30. Thermal Profile 4 Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 43.2 24 49.9 48 56.6 2 43.8 26 50.5 50 57.2 4 44.3 28 51.0 52 57.8 6 44.9 30 51.6 54 58.3 8 45.4 32 52.2 56 58.9 10 46.0 34 52.7 58 59.4 12 46.6 36 53.3 60 60.0 14 47.1 38 53.8 62 60.6 16 47.7 40 54.4 64 61.1 18 48.2 42 55.0 65 61.4 20 48.8 44 55.5 22 49.4 46 56.
Thermal Specifications and Design Considerations Table 31. Thermal Profile 5 Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) Power (W) Maximum Tc (°C) 0 43.2 26 49.2 52 55.2 2 43.7 28 49.6 54 55.6 4 44.1 30 50.1 56 56.1 6 44.6 32 50.6 58 56.5 8 45.0 34 51.0 60 57.0 10 45.5 36 51.5 62 57.5 12 46.0 38 51.9 64 57.9 14 46.4 40 52.4 66 58.2 16 46.9 42 52.9 68 58.8 18 47.3 44 53.3 70 59.3 20 47.8 46 53.8 72 59.8 22 48.3 48 54.
Thermal Specifications and Design Considerations 5.1.2 Thermal Metrology The maximum and minimum case temperatures (TC) for the processor is specified in Table 26. This temperature specification is meant to help ensure proper operation of the processor. Figure 24 illustrates where Intel recommends TC thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2). Figure 24.
Thermal Specifications and Design Considerations and in some cases may result in a TC that exceeds the specified maximum temperature and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. Refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2) for information on designing a thermal solution.
Thermal Specifications and Design Considerations Figure 25. Thermal Monitor 2 Frequency and Voltage Ordering TTM2 Temperature fMAX fTM2 Frequency VID VIDTM2 VID PROCHOT# The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled. It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on demand mode. The Thermal Monitor TCC, however, can be activated through the use of the on demand mode.
Thermal Specifications and Design Considerations 5.2.4 PROCHOT# Signal An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.
Thermal Specifications and Design Considerations 5.3 Thermal Diode The processor incorporates an on-die PNP transistor where the base emitter junction is used as a thermal "diode", with its collector shorted to ground. A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management and fan speed control. Table 32,Table 33, and Table 34 provide the "diode" parameter and interface specifications.
Thermal Specifications and Design Considerations Table 33. Thermal “Diode” Parameters using Transistor Model Symbol Parameter Min Typ Max Unit Notes 1, 2 IFW Forward Bias Current 5 — 200 µA IE Emitter Current 5 — 200 µA nQ Transistor Ideality 0.997 1.001 1.005 - 3, 4, 5 0.391 — 0.760 2.79 4.52 6.24 Ω 3, 6 Beta RT Series Resistance 3, 4 NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Same as IFW in Table 32. 3.
Thermal Specifications and Design Considerations 5.4 Platform Environment Control Interface (PECI) 5.4.1 Introduction PECI offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire, thus alleviating routing congestion issues. Figure 26 shows an example of the PECI topology in a system. PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices.
Thermal Specifications and Design Considerations . Figure 27. Conceptual Fan Control on PECI-Based Platforms TCONTROL Setting TCC Activation Temperature PECI = 0 Max Fan Speed (RPM) PECI = -10 Min PECI = -20 Temperature Note: Not intended to depict actual implementation . Figure 28.
Thermal Specifications and Design Considerations 5.4.2 PECI Specifications 5.4.2.1 PECI Device Address The PECI device address for the socket is 30h. For more information on PECI domains, refer to the Platform Environment Control Interface Specification. 5.4.2.2 PECI Command Support PECI command support is covered in detail in the Platform Environment Control Interface Specification. Refer to this document for details on supported PECI command function and codes. 5.4.2.
Features 6 Features 6.1 Power-On Configuration Options Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 36. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features Figure 29.
Features The system can generate a STPCLK# while the processor is in the HALT powerdown state. When the system de-asserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in HALT Power powerdown, the processor processes bus snoops. 6.2.2.2 Extended HALT Powerdown State Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS.
Features 6.2.3.2 Extended Stop Grant State Extended Stop Grant is a low power state entered when the STPCLK# signal is asserted and Extended Stop Grant has been enabled via the BIOS. The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended Stop Grant state. When entering the low power state, the processor will first switch to the lower bus ratio and then transition to the lower VID.
Features points. It alters the performance of the processor by changing the bus to core frequency ratio and voltage. This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system. The processor has hardware logic that coordinates the requested voltage (VID) between the processor cores. The highest voltage that is requested for either of the processor cores is selected for that processor package.
Features 98 Datasheet
Boxed Processor Specifications 7 Boxed Processor Specifications The processor is also offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor.
Boxed Processor Specifications 7.1 Mechanical Specifications 7.1.1 Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 30 shows a mechanical representation of the boxed processor. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling.
Boxed Processor Specifications Figure 33. Space Requirements for the Boxed Processor (Overall View) Boxed Proc OverallView 7.1.2 Boxed Processor Fan Heatsink Weight The boxed processor fan heatsink will not weigh more than 550 grams. See Chapter 5 and the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2) for details on the processor weight and heatsink requirements. 7.1.
Boxed Processor Specifications The boxed processor's fanheat sink requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control. The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power header identification and location should be documented in the platform documentation, or on the system board itself. Figure 35 shows the location of the fan power connector relative to the processor socket.
Boxed Processor Specifications Figure 35. Baseboard Power Header Placement Relative to Processor Socket R110 [4.33] B C Boxed Proc PwrHeaderPlacement 7.3 Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. 7.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a fan heatsink.
Boxed Processor Specifications Figure 36. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view) Figure 37.
Boxed Processor Specifications 7.3.2 Fan Speed Control Operation (Intel® Core2 Extreme Processor X6800 Only) The boxed processor fan heatsink is designed to operate continuously at full speed to allow maximum user control over fan speed. The fan speed can be controlled by hardware and software from the motherboard. This is accomplished by varying the duty cycle of the Control signal on the 4th pin (see Table 38).
Boxed Processor Specifications Table 38. Fan Heatsink Power and Signal Specifications Boxed Processor Fan Heatsink Set Point (°C) Boxed Processor Fan Speed Notes X ≤ 30 When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. Recommended maximum internal chassis temperature for nominal operating environment. 1 Y = 35 When the internal chassis temperature is at this point, the fan operates between its lowest and highest speeds.
Balanced Technology Extended (BTX) Boxed Processor Specifications 8 Balanced Technology Extended (BTX) Boxed Processor Specifications The processor is offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from largely standard components. The boxed processor will be supplied with a cooling solution known as the Thermal Module Assembly (TMA). Each processor will be supplied with one of the two available types of TMAs – Type I or Type II.
Balanced Technology Extended (BTX) Boxed Processor Specifications Figure 40. Mechanical Representation of the Boxed Processor with a Type II TMA NOTE: The duct, clip, heatsink and fan can differ from this drawing representation but the basic shape and size will remain the same. 8.1 Mechanical Specifications 8.1.1 Balanced Technology Extended (BTX) Type I and Type II Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor TMA.
Balanced Technology Extended (BTX) Boxed Processor Specifications Figure 41. Requirements for the Balanced Technology Extended (BTX) Type I Keep-out Volumes NOTE: Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation.
Balanced Technology Extended (BTX) Boxed Processor Specifications Figure 42. Requirements for the Balanced Technology Extended (BTX) Type II Keep-out Volume NOTE: Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. 8.1.2 Boxed Processor Thermal Module Assembly Weight The boxed processor thermal module assembly for Type I BTX will not weigh more than 1200 grams.
Balanced Technology Extended (BTX) Boxed Processor Specifications 8.1.3 Boxed Processor Support and Retention Module (SRM) The boxed processor TMA requires an SRM assembly provided by the chassis manufacturer. The SRM provides the attach points for the TMA and provides structural support for the board by distributing the shock and vibration loads to the chassis base pan. The boxed processor TMA will ship with the heatsink attach clip assembly, duct and screws for attachment.
Balanced Technology Extended (BTX) Boxed Processor Specifications 8.2 Electrical Requirements 8.2.1 Thermal Module Assembly Power Supply The boxed processor's Thermal Module Assembly (TMA) requires a +12 V power supply. The TMA will include power cable to power the integrated fan and will plug into the 4wire fan header on the baseboard. The power cable connector and pinout are shown in Figure 44. Baseboards must provide a compatible power header to support the boxed processor.
Balanced Technology Extended (BTX) Boxed Processor Specifications Table 39. TMA Power and Signal Specifications Description Min Typ Max Unit 10.2 12 13.8 V - Peak Fan current draw — 1.0 1.5 A - Fan start-up current draw — — 2.0 A - Fan start-up current draw maximum duration — — 1.0 Second SENSE: SENSE frequency — 2 — pulses per fan revolution 1 CONTROL 21 25 28 kHz 2, 3 +12V: 12 volt fan power supply Notes IC: NOTES: 1.
Balanced Technology Extended (BTX) Boxed Processor Specifications 8.3 Thermal Specifications This section describes the cooling requirements of the thermal module assembly solution used by the boxed processor. 8.3.1 Boxed Processor Cooling Requirements The boxed processor may be directly cooled with a TMA. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator.
Balanced Technology Extended (BTX) Boxed Processor Specifications Figure 46. Boxed Processor TMA Set Points Higher Set Point Highest Noise Level Increasing Fan Speed & Noise Lower Set Point Lowest Noise Level X Y Z Internal Chassis Temperature (Degrees C) Table 40.
Balanced Technology Extended (BTX) Boxed Processor Specifications the motherboard that sends out a PWM control signal to the 4th pin of the connector labeled as CONTROL. The fan speed is based on a combination of actual processor temperature and thermistor temperature. If the 4-wire PWM controlled fan in the TMA solution is connected to a 3-pin baseboard processor fan header it will default back to a thermistor controlled mode, allowing compatibility with existing 3-pin baseboard designs.
Debug Tools Specifications 9 Debug Tools Specifications 9.1 Logic Analyzer Interface (LAI) Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor.
Debug Tools Specifications 118 Datasheet
