Intel® Xeon® Processor MP Specification Update October 2005 Notice: The Intel® Xeon® Processor MP and Intel® Xeon® Processor MP with up to 4MB cache on 0.13-micron process may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.
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Contents Revision History ................................................................................................................. 5 Preface ............................................................................................................................... 7 Identification Information .................................................................................................... 8 Mixed Steppings In MP Systems.........................................................................
Intel® Xeon® Processor MP Specification Update
Revision History Revision History Version Description Date -001 • Initial release. March 2002 -002 • Addition of “Mixed Steppings in MP Systems” section. April 2002 • Added five new Documentation Changes. • Added erratum O39. -003 • Added PWRGOOD Specification Change. May 2002 • Added errata O40. • Updated errata O12, O29. • Added Specification Changes O1 and O2. • Added Documentation Changes O1-O3. -004 • Added errata O41 and O42.
Revision History Version -016 Description • Added B0 Stepping. Date July 2003 • Added new processor S-Specs. • Added new Processor Signature (0F25h). • Added new identification information. • Added erratum O57. • Updated Summary of Errata Table. • Updated Table 2. • Removed Specification Clarifications and Specification Changes. -017 • Added erratum O58. July 2003 -018 • Updated incorrect stepping information (Updated B0 to B1 stepping). July 2003 -019 • Added errata O59 - O60.
Preface Preface Affected/Related Documents This document is an update to the specifications contained in the following documents: Document Title Document Number ® 290740 ® Intel Xeon™ Processor MP with up to 4MB L3 Cache (on 0.
Identification Information Identification Information Intel® Xeon® Processor MP and Intel® Xeon® Processor MP with up to 4MB L3 Cache (on 0.13 Micron Process) Markings (603-pin INT-mPGA) Figure 1. Top Side Processor Marking – Production Part 2D Matrix OR Intel® Xeon™ i(m) ©’02 Dynamic Laser Mark Area Figure 2. Bottom Side Processor Marking Dynamic Laser Mark Area Product Code S-Spec Country of Assy 1500MP/512/400/1.
Identification Information The Intel Xeon processor MP can be identified by the following values: Family1 Model2 Brand ID3 1111 0001 00001110 1111 0010 000010114 1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan. 2.
Identification Information Table 1. Intel® Xeon® Processor MP Identification Information(Sheet 2 of 2) S-Spec Core Stepping SL6Z2 B1 Processor Signature 0F25h Speed Core/Data Bus (GHz/MHz) L2 Cache Size L3 Cache Size HyperThreading Technology Processor Interposer Revision 2.50/400 512-KB 1-MB Yes 01 SL6Z7 SL6YL B1 0F25h 2.80/400 512-KB 2-MB Yes 01 SL6Z8 Package And Revision2 603-pin micro-PGA interposer with 42.5 mm FC-BGA package 603-pin micro-PGA interposer with 42.
Mixed Steppings In MP Systems Mixed Steppings In MP Systems Intel Corporation fully supports mixed steppings of Intel Xeon Processors MP. The following list and processor matrix describes the requirements to support mixed steppings: • Mixed steppings are only supported with processors that have identical family numbers as indicated by the CPUID instruction. The Intel Xeon Processor MP is available with two different Model numbers as indicated by the CPUID.
Mixed Steppings In MP Systems Table 2. MP Platform Population Matrix for the Intel® Xeon® Processor MP Processor Signature/Core Stepping 0F11h/C0 0F22h/A0 0F25h/B1 0F26h/C02 0F26h/C03 0F11h/C0 NI X X X X 0F22h/A0 X NI NI NI X 0F25h/B1 X NI NI NI X 0F26h/C02 X NI NI NI X 3 X X X X NI 0F26h/C0 NOTES: 1. Some of these processors are affected by errata that may affect the features an MP system is able to support.
Summary Tables of Changes Summary Tables of Changes The following table indicates the Errata, Documentation Changes, Specification Clarifications, or Specification Changes that apply to the Intel Xeon Processor MP. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or specification changes as noted.
Summary Tables of Changes T = U = V = W = X = Y = Z = AC = Note: 14 Mobile Intel® Pentium® 4 processor-M 64-bit Intel® Xeon® processor MP with up to 8 MB L3 cache Mobile Intel® Celeron® processor on .
Summary Tables of Changes Errata (Sheet 1 of 4) No.
Summary Tables of Changes Errata (Sheet 2 of 4) No.
Summary Tables of Changes Errata (Sheet 3 of 4) No.
Summary Tables of Changes Errata (Sheet 4 of 4) No.
Errata Errata O1 UC code in same line as write back (WB) data may lead to data corruption Problem: This erratum occurs when both code (being accessed as uncacheable [UC] or write combining [WC]) and data (being accessed as write back [WB]) are placed in the same cache line. The UC fetch will cause the processor to self-snoop and generate an implicit WB. The data supplied by this implicit WB may be corrupted due to the way the processor is currently handling self-modifying code.
Errata O5 Shutdown and IERR# may result due to a machine check exception on a Hyper-Threading Technology enabled processor Problem: When a Machine Check Exception (MCE) occurs due to an internal error, both logical processors on a Hyper-Threading (HT) Technology enabled processor normally vector to the MCE handler. However, if one of the logical processors is in the “Wait for SIPI” state, that logical processor will not have a MCE handler and will shut down and assert IERR#.
Errata O8 Writing a performance counter may result in an incorrect counter value Implication: Accessing a performance counter also enables the counter input so that writing one half of the counter can cause the other half to increment. When a performance counter is written and the event counter for the event being monitored is non-zero, the performance counter will be incremented by the value on that event counter.
Errata proceed. Instead, the transaction is not properly removed from the bus queue, the bus queue is blocked, and the processor will hang. • When a hardware prefetch results in an uncorrectable tag error in the L2 cache, MC0_STATUS.UNCOR and MC0_STATUS.PCC are set but no machine check exception (MCE) is signaled. No data loss or corruption occurs because the data being prefetched has not been used. If the data location with the uncorrectable tag error is subsequently accessed, an MCE will occur.
Errata • If RESET# is asserted, then de-asserted, and reasserted, before the processor has cleared the MCA registers, then the information in the MCA registers may not be reliable, regardless of the state or state transitions of PWRGOOD. • If MCERR# is asserted by one processor and observed by another processor, the observing processor does not log the assertion of MCERR#. The MCE handler called upon assertion of MCERR# will not have any way to determine the cause of the MCE.
Errata • When a data breakpoint is set on the ninth and/or tenth byte(s) of a floating point store using the Extended Real data type, and an unmasked floating point exception occurs on the store, the break point will not be captured. • When any instruction has multiple debug register matches, and any one of those debug Implication: registers is enabled in DR7, all of the matches should be reported in DR6 when the processor goes to the debug handler. This is not true during a REP instruction.
Errata O15 EMON event counting of x87 loads may not work as expected Problem: If a performance counter is set to count x87 loads and floating-point exceptions are unmasked, the FPU Operand (Data) Pointer (FDP) may become corrupted. Implication: When this erratum occurs, the FDP may become corrupted. Workaround: This erratum will not occur with floating-point exceptions masked. If floating-point exceptions are unmasked, then performance counting of x87 loads should be disabled.
Errata Status: For the steppings effected, see the Summary Table of Changes. O19 PAT index MSB may be calculated incorrectly Problem: When Mode C or Mode B paging support is enabled and all of the following events occur: • A page walk returns the page directory entry (PDE) for a large page from memory. • A subsequent page walk returns the page table entry (PTE) for a 4k page from memory and the page attribute table (PAT) upper index bit (bit 7) in this PTE is set to 1b.
Errata Implication: The L1 cache may contain corrupted data. No known commercially available chipsets trigger the failure conditions. Workaround: The chipset could issue a BIL (snoop) to the deferred processor to eliminate the failure conditions. Status: For the steppings effected, see the Summary Table of Changes.
Errata O26 Processor issues inconsistent transaction size attributes for locked operations Problem: When the processor is in the page address extension (PAE) mode and detects the need to set the Access and/or Dirty bits in the page directory or page table entries, the processor sends an 8 byte load lock onto the system bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte store unlock occurs.
Errata O30 When the processor is in the system management mode (SMM), debug registers may be fully writeable Problem: When in system management mode (SMM), the processor executes code and stores data in the SMRAM space. When the processor is in this mode and writes are made to DR6 and DR7, the processor should block writes to the reserved bit locations. Due to this erratum, the processor may not block these writes. This may result in invalid data in the reserved bit locations.
Errata Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings effected, see the Summary Table of Changes.
Errata cache at the same time that a prefetch RFO is issued to this address. A boundary condition exists in the bus logic where the prefetch may be issued on the system bus before the modified data in the L3 is written back to main memory. Consequently the RFO gets stale data for the adjacent sector from main memory and fills the cache with this stale data. Implication: The processor may use stale data from the cache.
Errata Implication: The processor unexpectedly does not flag #GP on a non-zero write to the upper 32 bits of IA32_CR_SYSENTER_EIP or IA32_CR_SYSENTER_ESP. No known commercially available operating system has been identified to be affected by this erratum. Workaround: None at this time. Status: For the steppings effected, see the Summary Table of Changes.
Errata processor with HT Technology enabled, the processor should return 50h (64 entries). Due to this erratum, the CPUID instruction always returns 50h (64 entries). Implication: Software may incorrectly report the number of ITLB entries. Operation of the processor is not affected. Workaround: None at this time. Status: For the steppings effected, see the Summary Table of Changes.
Errata Workaround: None at this time. Status: For the steppings effected, see the Summary Table of Changes. O50 Processor may hang under certain frequencies and 12.5% STPCLK# duty cycle Problem: If a system de-asserts STPCLK# at a 12.5% duty cycle, the processor is running below 2 GHz, and the processor thermal control circuit (TCC) on-demand clock modulation is active, the processor may hang. This erratum does not occur under the automatic mode of the TCC.
Errata Implication: This only impacts JTAG/TAP accesses to the processor. Other bus accesses are not affected. Workaround: To minimize the effects of this issue, reduce noise on the TCK-net at the processor relative to ground, and position TCK relative to BCLK to minimize the TAP error rate. Decreasing rise times to under 800ps reduced the failure rate but does not stop all failures. Status: For the steppings effected, see the Summary Table of Changes.
Errata Implication: The processor will break at the instruction breakpoint address instead of single stepping. Workaround: Execution after the break will continue if DR7 bit 1 (Global Breakpoint Enable) is manually cleared. Status: For the steppings affected, see the Summary Table of Changes.
Errata O62 Incorrect PIROM L3 cache present value Problem: The L3 Cache Present bit, located at 78:0h in the processor information read only memory (PIROM), should be programmed to 3Fh - indicating that an L3 cache is present. The L3 cache present bit value returned is 3Eh, which indicates that the L3 cache is not present. L3 cache size is not affected by the L3 cache present bit. L3 cache size can be determined by reading the L3 cache size register located at 29 -2Ah in the PIROM.
Errata O66 xAPIC may not report some illegal vector errors Problem: The local xAPIC has an error status register, which records all errors. The bit 6 (the Receive illegal Vector bit) of this register, is set when the local xAPIC detects an illegal vector in a received message. When an illegal vector error is received on the same internal clock that the error status register is being written (due to a previous error), bit 6 does not get set and illegal vector errors are not flagged.
Errata O70 Missing Stop Grant Acknowledge special bus cycle may cause a system hang Problem: If a Stop Grant Acknowledge special bus cycle is deferred by the processor for a period of time long enough for the chipset to de-assert and then re-assert STPCLK# signal, a processor supporting Hyper-Threading Technology may fail to detect the de-assertion and re-assertion of STPCLK# signal.
Errata O74 With Trap Flag (TF) asserted, FP instruction that triggers an unmasked FP exception may take single step trap before retirement of instruction Problem: If an FP instruction generates an unmasked exception with the EFLAGS.TF=1, it is possible for external events to occur, including a transition to a lower power state. When resuming from the lower power state, it may be possible to take the single step trap before the execution of the original FP instruction completes.
Errata requires complete invalidation. This data retention may also occur when a BWIL transaction’s self-snooping yields HITM snoop results. Implication: A system may suffer memory ordering failures if its central agent incorporates coherence sequencing which depends on full self-invalidation of the cache line associated with (1) BWIL and BLW transactions, or (2) all HITM snoop results without regard to the transaction type and snoop results’ source. Workaround: 1.
Specification Changes Specification Changes There are no new Specification Changes for this month.
Specification Clarifications Specification Clarifications There are no new Specification Clarifications for this revision.
Specification Clarifications Members of the processor families increment the time-stamp counter differently: • For Pentium M processors (family [06H], models [09H, 0DH]); for Pentium 4 processors, Intel Xeon processors (family [0FH], models [00H, 01H, or 02H]); and for P6 family processors: the time-stamp counter increments with every internal processor clock cycle. The internal processor clock cycle is determined by the current core-clock to bus-clock ratio.
Specification Clarifications • Non-halted clockticks — Measures clock cycles in which the specified logical processor is not halted and is not in any power-saving state. When Hyper-Threading Technology is enabled, this these ticks can be measured on a per-logical-processor basis. • Non-sleep clockticks — Measures clock cycles in which the specified physical processor is not in a sleep mode or in a power-saving state. These ticks cannot be measured on a logical-processor basis.
Documentation Changes Documentation Changes There are no new Documentation Changes for this revision. Note: Documentation changes for IA-32 Intel® Architecture Software Developer’s Manual, Volumes 1, 2A, 2B, 3 will be posted in a separate document IA-32 Intel® Architecture and Intel® Extended Memory 64 Technology Software Developer’s Manual Documentation Changes. Follow the link below to become familiar with this file: • http://developer.intel.com/design/pentium4/specupdt/252046.
