Dual-Core Intel® Xeon® Processor 2.80 GHz Specification Update October 2006 Notice: The Dual-Core Intel® Xeon® processor 2.80 GHz may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this specification update.
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Contents Revision History ................................................................................................................. 5 Preface ............................................................................................................................... 6 Identification Information .................................................................................................... 7 Summary Tables of Changes.............................................................................
Dual-Core Intel® Xeon® Processor 2.
Revision History Version Description Date -001 Initial release of the Dual-Core Intel® Xeon® Processor 2.80 GHz Specification Update October 2005 -002 Added erratum D53. November 2005 -003 Added erratum D54. December 2005 -004 In Documentation changes, updated reference to IA-32 Intel® Architecture Software Developer’s Manual to reflect volumes 3A and 3B. Updated errata D55 - D58. April 2006 -005 Added AE and AF to Coddes Used in Summary Table. Added erratum D59.
Preface Preface This document is an update to the specifications contained in the following documents: 1. Dual-Core Intel® Xeon® Processor 2.80 GHz Datasheet (Document Number 309158) Link: http://developer.intel.com/design/xeon/datashts/309158.htm This document is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Nomenclature S-Spec Number is a five-digit code used to identify products.
Identification Information Identification Information Dual-Core Intel® Xeon® Processor 2.80 GHz Package Markings (604-pin FC-mPGA4 package) Figure 1. Top-Side Processor Marking Example P ro c e s s o r N am e i(m ) © ’0 4 2 D M a trix In c lu d e s A T P O a n d S e ria l N u m b e r (fro n t e n d m a rk ) ATPO S e ria l N u m b e r P in 1 In d ic a to r NOTES: 1. All characters will be in upper case. 2. Drawing is not to scale. Figure 2.
Identification Information The Dual-Core Intel® Xeon® processor 2.80 GHz can be identified by the following register contents: Family1 Model2 1111b 0100b NOTES: 1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan. 2.
Summary Tables of Changes Summary Tables of Changes The following table indicates the Errata, Specification Changes, Specification Clarifications, or Documentation Changes which apply to the Dual-Core Intel® Xeon® processor 2.80 GHz. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted.
Summary Tables of Changes U = V = W = X = Y = Z = AA = AB = AC = AD = AE = AF = 64-bit Intel® Xeon® processor MP with up to 8 MB L3 cache Mobile Intel® Celeron® processor on .
Summary Tables of Changes Errata (Sheet 2 of 3) No.
Summary Tables of Changes Errata (Sheet 3 of 3) No. A0 Plans Description D52 x No Fix Writing the local vector table (LVT) when an interrupt is pending may cause an unexpected interrupt D53 x No Fix The processor may issue multiple code fetches to the same cache line for systems with slow memory D54 x No Fix IRET under certain conditions may cause an unexpected Alignment Check Exception D55 x No Fix Using 2M/4M pages when A20M# is asserted may result in incorrect address translations.
Errata Errata D1. Transaction is not retired after BINIT# Problem: If the first transaction of a locked sequence receives a HITM# and DEFER# during the snoop phase it should be retried and the locked sequence restarted. However, if BINIT# is also asserted during this transaction, the transaction will not be retried. Implication: When this erratum occurs, locked transactions will not be retried. Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. D2.
Errata memory types) does not however introduce any functional failures such as system hangs or memory corruption. Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. D5. Machine check architecture error reporting and recovery may not work as expected Problem: When the processor detects errors it should attempt to report and/or recover from the error.
Errata if any further errors occur, the MCA overflow bit will not be updated, thereby incorrectly indicating only one error has been received. • If an I/O instruction (IN, INS, REP INS, OUT, OUTS, or REP OUTS) is being executed, and if the data for this instruction become corrupted, the processor will signal a Machine Check Exception (MCE). If the instruction is directed at a device that is powered down, the processor may also receive an assertion of SMI#.
Errata Once the chipset receives its last Stop Grant special cycle it is allowed to ignore any bus activity from the processors. As a result, processor accesses to the machine check handler may not be acknowledged, resulting in a processor hang. Implication: The processor is unable to correctly report and/or recover from certain errors Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. D6.
Errata D8. EMON event counting of x87 loads may not work as expected Problem: If a performance counter is set to count x87 loads and floating-point exceptions are unmasked, the FPU operand (Data) pointer (FDP) may become corrupted. Implication: When this erratum occurs, FPU operand (Data) pointer (FDP) may become corrupted. Workaround: This erratum will not occur with floating point exceptions masked.
Errata D12. Processor issues inconsistent transaction size attributes for locked operation Problem: When the processor is in the page address extension (PAE) mode and detects the need to set the Access and/or Dirty bits in the page directory or page table entries, the processor sends an 8 byte load lock onto the System Bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte store unlock occurs.
Errata behavior for a single processor to have a BWL and a BRL/BRIL concurrently outstanding to the same address, this may represent an unexpected scenario to system logic within the chipset. Implication: The processor may not be able to fully execute the machine check handler in response to the fatal cache error if system logic does not ensure forward progress on the System Bus under this scenario. Workaround: System logic should ensure completion of the outstanding transactions.
Errata instruction causing the FP event, the load in the microcode routine will trigger the data breakpoint resulting in a Debug Exception. Implication: An incorrect Debug Exception (#DB) may occur if data breakpoint is placed on an FP instruction. Intel has not observed this erratum with any commercially available software or system. Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. D21.
Errata Implication: When this erratum occurs, an incorrect instruction stream may be executed resulting in unpredictable software behavior. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Table of Changes. D25. Using STPCLK# and executing code from very slow memory could lead to a system hang Problem: The system may hang when the following conditions are met: 1.
Errata Status: For the steppings affected, see the Summary Table of Changes. D29. MOV CR3 performs incorrect reserved bit checking when in PAE paging Problem: The MOV CR3 instruction should perform reserved bit checking on the upper unimplemented address bits. This checking range should match the address width reported by CPUID instruction 0x8000008. This erratum applies whenever PAE is enabled.
Errata D33. FXRSTOR may not restore non-canonical effective addresses on processors with Intel® Extended Memory 64 Technology (Intel® EM64T) Enabled Problem: If an x87 data instruction has been executed with a non-canonical effective address, FXSAVE may store that non-canonical FP data pointer (FDP) value into the save image. An FXRSTOR instruction executed with 64-bit operand size may signal a General Protection Fault (#GP) if the FDP or FP instruction pointer (FIP) is in non-canonical form.
Errata D37. IA32_MCi_STATUS MSR may improperly indicate that additional MCA information may have been captured Problem: When a data parity error is detected and the bus queue is busy, the ADDRV and MISCV bits of the IA32_MCi_STATUS register may be asserted even though the contents of the IA32_MCi_ADDR and IA32_MCi_MISC MSRs were not properly captured.
Errata Implication: A system may suffer memory ordering failures if its central agent incorporates coherence sequencing which depends on full self-invalidation of the cache line associated (1) with BWIL and BLW transactions, or (2) all HITM snoop results without regard to the transaction type and snoop results source. Workaround: 1.
Errata Status: For the steppings affected, see the Summary Table of Changes. D44. An REP LODSB or an REP LODSD or an REP LODSQ instruction with RCX >= 2^32 may cause a system hang on processors supporting Intel® Extended Memory 64 Technology (Intel® EM64T) Problem: In IA-32e mode using Intel EM64T-enabled processors, an REP LODSB or an REP LODSD or an REP LODSQ instruction executed with the register RCX >= 2^32 may fail to complete execution causing a system hang.
Errata Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. D48. PDE/PTE Loads and continuous locked updates to the same cache line may cause a system livelock Problem: In a multiprocessor configuration, if one processor is continuously doing locked updates to a cache line that is being accessed by another processor doing a page table walk, the page table walk may not complete.
Errata that vector the system will GP fault. If the ISR does not do an end of interrupt (EOI) the bit for the vector will be left set in the in-service register and mask all interrupts at the same or lower priority. Workaround: Any vector programmed into an LVT entry must have an ISR associated with it, even if that vector was programmed as masked. This ISR routine must do an EOI to clear any unexpected interrupts that may occur.
Errata Status: No Fix J56. Writing shared unaligned data that crosses a cache line without proper semaphores or barriers may expose a memory ordering issue. Problem: Software which is written so that multiple agents can modify the same shared unaligned memory location at the same time may experience a memory ordering issue if multiple loads access this shared data shortly thereafter. Exposure to this problem requires the use of a data write which spans a cache line boundary.
Errata Workaround: None identified. Status: No Fix D60.
Specification Changes Specification Changes There are no new Specification Changes for this revision. The Specification Changes listed in this section apply to the following documents: 1. Dual-Core Intel® Xeon® Processor 2.80 GHz Datasheet (Document Number 309158) All Specification Changes will be incorporated into a future version of the appropriate Dual-Core Intel® Xeon® processor 2.80 GHz documentation. Dual-Core Intel® Xeon® Processor 2.
Specification Clarifications Specification Clarifications There are no new Specification Clarifications for this revision. The Specification Clarifications listed in this section apply to the following documents: 1. Dual-Core Intel® Xeon® Processor 2.80 GHz Datasheet (Document Number 309158) All Specification Changes will be incorporated into a future version of the appropriate Dual-Core Intel® Xeon® processor 2.80 GHz documentation. 32 Dual-Core Intel® Xeon® Processor 2.
Documentation Changes Documentation Changes Note: Documentation changes for IA-32 Intel® Architecture Software Developer’s Manual volumes 1, 2A, 2B, 3A and 3B will be posted in the separate document IA-32 Intel® Architecture Software Developer’s Manual Documentation Changes. Follow the link below to become familiar with this file. http://developer.intel.com/design/pentium4/specupdt/252046.htm There are no new Documentation Changes for this revision.
Documentation Changes 34 Dual-Core Intel® Xeon® Processor 2.
