64-bit Intel® Xeon® Processor MP with 1 MB L2 Cache Specification Update June 2006 Notice: The 64-bit Intel® Xeon® Processor MP with up to 1 MB L2 Cache Specification Update may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are documented in this specification update.
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Contents Revision History ................................................................................................................. 5 Preface ............................................................................................................................... 6 Package Markings.............................................................................................................. 7 Identification Information ............................................................................
64-bit Intel® Xeon® Processor MP with up to 1 MB L2 Cache Specification Update
Revision History Version Description Date -001 Initial revision of 64-bit Intel® Xeon® processor MP with 1 MB L2 Cache Specification Update March 2005 -002 Added erratum J66. July 2005 -003 Added errata J67. August 2005 -004 Added errata J68-J69; added stepping B0 to S-spec table and summary table. September 2005 -005 Added erratum J70. October 2005 -006 Added erratum J71. November 2005 -007 Added erratum J72. December 2005 -008 Updated erratum J17.
Preface Preface This document is an update to the specifications contained in the Affected/Related Documents table below. This document is a compilation of device and documentation errata, specification clarifications, and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. This document may also contain information that was not previously published.
Package Markings Package Markings 64-bit Intel® Xeon® Processor MP (604-pin FC-mPGA4 package) Figure 1. Top-Side Processor Marking Example 2D Matrix Includes ATPO and Serial Number (front end mark) ATPO Serial Number’ Pin 1 Indicator Figure 2.
Identification Information Identification Information The 64-bit Intel® Xeon® processor MP with 1 MB L2 Cache processor can be identified by the following values: Family1 Model2 1111b 0100b NOTES: 1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan. 2.
Identification Information Mixed Steppings in MP Systems Intel Corporation fully supports mixed steppings of the 64-bit Intel Xeon processor with up to 1 MB L2 cache system bus. The following list and processor matrix describes the requirements to support mixed steppings: • Mixed steppings are only supported with processors that have identical family numbers as indicated by the CPUID instruction.
Summary Table of Changes Summary Table of Changes The following table indicates the Errata, Documentation Changes, Specification Clarifications, or Specification Changes that apply to Intel processors. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or specification changes as noted.
Summary Table of Changes V = W = X = Y = Z = AA = AB = AC = AD = AE = AF = Mobile Intel® Celeron® processor on .
Summary Table of Changes Errata (Sheet 2 of 4) No.
Summary Table of Changes Errata (Sheet 3 of 4) No. A-0/ 0F41h B-0/ 0F49H J49 X X No Fix Writes to IA32_MISC_ENABLE may not update flags for both logical processors J50 X X No Fix Execute disable bit set with CR4.
Summary Table of Changes Errata (Sheet 4 of 4) No. A-0/ 0F41h B-0/ 0F49H J74 X X No Fix Writing shared unaligned data that crosses a cache line without proper semaphores or barriers may expose a memory ordering issue. J75 X X No Fix Processor may hang during entry into No-Fill Mode or No-Eviction Mode. J76 X X No Fix FPU Operand pointer may not be cleared following FINIT/FNINIT.
Summary Table of Changes Specification Changes No. Specification Changes 3A Updated reference to IA-32 Intel® Architecture Software Developer's Manual to reflect volumes 3A. 3B Updated reference to IA-32 Intel® Architecture Software Developer's Manual to reflect volumes 3B Specification Clarifications No. J1 Specification Clarifications Specification Clarification with respect to Time Stamp Counter Documentation Changes No. Documentation Changes None for this revision of the Specification Update.
Errata Errata J1. Transaction is not retired after BINIT# Problem: If the first transaction of a locked sequence receives a HITM# and DEFER# during the snoop phase it should be retried and the locked sequence restarted. However, if BINIT# is also asserted during this transaction, the transaction will not be retried. Implication: When this erratum occurs, locked transactions will not be retried. Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. J2.
Errata modify it before those data are snooped out by another processor. In the case of this erratum, the use-once protocol incorrectly activates for split load lock instructions. A load lock operation accesses data that split across a page boundary with both pages of WB memory type. The use-once protocol activates and the memory type for the split halves get forced to UC. Since use-once does not apply to stores, the store unlock instructions go out as WB memory type.
Errata • If a memory access receives a machine check error on both 64 byte halves of a 128-byte L2 cache sector, the IA32_MC0_STATUS register records this event as multiple errors, i.e., the valid error bit and the overflow error bit are both set indicating that a machine check error occurred while the results of a previous error were in the error-reporting bank. The IA32_MC1_STATUS register should also record this event as multiple errors but instead records this event as only one correctable error.
Errata The processor may hang when the following events occur and the machine check exception is enabled, CR4.MCE=1. A processor that has it’s STPCLK# pin asserted will internally enter the Stop Grant State and finally issue a Stop Grant Acknowledge special cycle to the bus. If an uncorrectable error is generated during the Stop Grant process it is possible for the Stop Grant special cycle to be issued to the bus before the processor vectors to the machine check handler.
Errata Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. J8. EMON event counting of x87 loads may not work as expected Problem: If a performance counter is set to count x87 loads and floating-point exceptions are unmasked, the FPU Operand (Data) Pointer (FDP) may become corrupted. Implication: When this erratum occurs, FPU Operand (Data) Pointer (FDP) may become corrupted.
Errata J12. Processor issues inconsistent transaction size attributes for locked operation Problem: When the processor is in the Page Address Extension (PAE) mode and detects the need to set the Access and/or Dirty bits in the page directory or page table entries, the processor sends an 8 byte load lock onto the System Bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte store unlock occurs.
Errata J16. System may hang if a fatal cache error causes Bus Write Line (BWL) transaction to occur to the same cache line address as an outstanding Bus Read Line (BRL) or Bus Read-Invalidate Line (BRIL) Problem: A processor internal cache fatal data ECC error may cause the processor to issue a BWL transaction to the same cache line address as an outstanding BRL or BRIL.
Errata J20. Locks and SMC detection may cause the processor to temporarily hang Problem: The processor may temporarily hang in an HT Technology enabled system, if one logical processor executes a synchronization loop that includes one or more bus locks and is waiting for release by the other logical processor.
Errata J24. Task Priority Register (TPR) Updates during voltage transitions of power management events may cause a system hang Problem: Systems with Echo TPR Disable (R/W) bit (bit [23] of IA32_MISC_ENABLE register) set to '0' (default), where xTPR messages are being transmitted on the system bus to the processor, may experience a system hang during voltage transitions caused by the power management events.
Errata J28. Using STPCLK# and executing code from very slow memory could lead to a system hang Problem: The system may hang when the following conditions are met: 1. Periodic STPCLK# mechanism is enabled via the chipset 2. Hyper-Threading Technology is enabled 3. One logical processor is waiting for an event (i.e. hardware interrupt) 4. The other logical processor executes code from very slow memory such that every code fetch is deferred long enough for the STPCLK# to be re-asserted.
Errata When one-half of a 64-byte instruction fetch from the L2 cache has an uncorrectable error and the other 32-byte half of the same fetch from the L2 cache has a correctable error, the processor will attempt to correct the correctable error but cannot proceed due to the uncorrectable error. When this occurs the processor will hang.
Errata The MCA Error Code field of the IA32_MC0_STATUS register gets written by a different mechanism than the rest of the register. For uncorrectable errors, the other fields in the IA32_MC0_STATUS register are only updated by the first error. Any further errors that are detected will update the MCA Error Code field without updating the rest of the register, thereby leaving the IA32_MC0_STATUS register with stale information.
Errata Status: For the steppings affected, see the Summary Table of Changes. J33. Machine check exceptions may not update Last-exception Record MSRs (LERs) Problem: The Last-Exception Record MSRs (LERs) may not get updated when Machine Check Exceptions occur. Implication: When this erratum occurs, the LER may not contain information relating to the machine check exception. They will contain information relating to the exception prior to the machine check exception. Workaround: None identified.
Errata Implication: Operating systems or drivers that reference a selector in non-canonical space may experience an unexpected #GP fault. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. J38.
Errata J42. FXRSTOR may not restore non-canonical effective addresses on processors with Intel*sup Problem: Intel EM64T enabled. Problem: If an x87 data instruction has been executed with a non-canonical effective address, FXSAVE may store that non-canonical FP Data Pointer (FDP) value into the save image. An FXRSTOR instruction executed with 64-bit operand size may signal a General Protection Fault (#GP) if the FDP or FP Instruction Pointer (FIP) is in non-canonical form.
Errata Implication: When this erratum occurs, a page fault exception may occur. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Table of Changes. J47. Execute disable bit set with AD assist may cause livelock Problem: If Execute Disable Bit is set and the resulting page requires the processor to set the A and/or D bit (Access and/or Dirty bit) in the PTE, then the processor may livelock.
Errata BIOS provides only valid physical address ranges to the operating system, this erratum will not occur. Workaround: BIOS must provide valid physical address ranges to the operating system. Status: For the steppings affected, see the Summary Table of Changes. J52.
Errata A BTS/PEBS record can be written that will wrap at the 4G boundary (IA32) or 2^64 boundary (Intel EM64T mode), and write memory outside of the BTS/PEBS buffer. Implication: Software that uses BTS/PEBS near the 4G boundary (IA32) or 2^64 boundary (EM64T mode), and defines the buffer such that it does not hold an integer multiple of records can update memory outside the BTS/PEBS buffer.
Errata J59. An REP MOVS or an REP STOS instruction with RCX >= 2^32 may fail to execute to completion or may write to incorrect memory locations on processors supporting Intel® Extended Memory 64 Technology (Intel® EM64T) Problem: In IA-32e mode using Intel EM64T-enabled processors, an REP MOVS or an REP STOS instruction executed with the register RCX >= 2^32, may fail to execute to completion or may write data to incorrect memory locations.
Errata L1 data cache adaptive mode (IA32_MISC_ENABLES MSR 0x1a0, bit 24). This behavior will only be visible when SMRAM is mapped into WB/WT cacheable memory on SMM entry and exit. Implication: This erratum can have multiple failure symptoms, including incorrect data in memory. Intel has not observed this erratum with any commercially available software.
Errata When these conditions are met, the processor may incorrectly - and indefinitely - assert a snoop stall for the Defer Reply transaction. Such an event will block further progress on the FSB. Implication: If this erratum occurs, the system may hang. Intel has not observed this erratum with any commercially available system. Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. J68.
Errata Implication: This erratum may slow down system boot time. Intel has not observed a failure, as a result of this erratum, in a commercially available system. Workaround: None identified. Status: For the steppings affected, see the Summary Table of Changes. J72.
Errata • The shared data is aligned. • Proper semaphores or barriers are used in order to prevent concurrent data accesses. Status: No Fix J75. Processor may hang during entry into No-Fill Mode or No-Eviction Mode. Problem: Only one logical processor per core can be active when processor is put in No-Fill Mode or No-Eviction Mode.
Errata J78. The IA32_MC0_STATUS/ IA32_MC1_STATUS Overflow Bit is not set when Multiple Un-correctable Machine Check Errors occur at the same time Problem: When two MC0/MC1 enabled un-correctable machine check errors are detected in the same internal clock cycle, the highest priority error will be logged in IA32_MC0_STATUS / IA32_MC1_STATUS register, but the overflow bit may not be set.
Specification Changes Specification Changes There are no new Specification Changes for this month. The Specification Changes listed in this section apply to the following documents: 1. 64-bit Intel® Xeon® Processor MP with 1 MB L2 Cache Datasheet (Document Number 306751) 2. IA-32 Intel® Architecture Software Developer’s Manual, Volume 1: Basic Architecture (Document Number 253665) 3. IA-32 Intel® Architecture Software Developer’s Manual, Volume 2A: Instruction Set Reference, A-M (Document Number 253666) 4.
Specification Clarifications Specification Clarifications There are no new Specification Clarifications for this month. The Specification Changes listed in this section apply to the following documents: 1. 64-bit Intel® Xeon® Processor MP with 1 MB L2 Cache Datasheet (Document Number 306751) 2. IA-32 Intel® Architecture Software Developer’s Manual, Volume 1: Basic Architecture (Document Number 253665) 3.
Specification Clarifications instruction or the external STPCLK# pin. Note that the assertion of the external DPSLP# pin may cause the time-stamp counter to stop. Members of the processor families increment the time-stamp counter differently: • For Pentium M processors (family [06H], models [09H, 0DH]); for Pentium 4 processors, Intel Xeon processors (family [0FH], models [00H, 01H, or 02H]); and for P6 family processors: the time-stamp counter increments with every internal processor clock cycle.
Specification Clarifications • The processor is asleep as a result of being halted or because of a power-management scheme. There are different levels of sleep. In the some deep sleep levels, the time-stamp counter stops counting. There are three ways to count processor clock cycles to monitor performance. These are: • Non-halted clockticks — Measures clock cycles in which the specified logical processor is not halted and is not in any power-saving state.
Documentation Changes Documentation Changes Note: Documentation changes for IA-32 Intel® Architecture Software Developer’s Manual volumes 1, 2A, 2B, 3A and 3B will be posted in the separate document IA-32 Intel® Architecture Software Developer’s Manual Documentation Changes. Follow the link below to become familiar with this file. http://developer.intel.com/design/pentium4/specupdt/252046.htm There are no new Documentation Changes for this month.
