Dual-Core Intel® Xeon® Processor LV and ULV Specification Update February 2009 Revision 015 Document Number: 311392-015
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Contents Preface ................................................................................................................................. 7 Summary Tables of Changes ................................................................................................... 9 Identification Information ...................................................................................................... 16 Errata................................................................................................
Revision History Revision Description -001 Initial Release -002 AF3 – change status to ‗Plan Fix‘ Date March 2006 May 2006 AF4 – Problem, implication, workaround changed.
-005 Added list of additional processors. August 2006 Added status column for D0-step processors Added new D0 stepping S-Spec numbers AF4 – All sections updated. AF14 – Updated. AF32 – changed status to ‗No Fix‘ AF51 – Updated. Added new Errata AF62, AF63, AF64 -006 Updated with ULV product information Added ULV product SSpec #.
AF33 – updated AF58 – Updated -014 Updated Summary Table of Changes (Product prefix table) July 2008 Added AF81 -015 Updated Summary Table of Changes (Product prefix table) February 2009 AF63 - Updated § 6 Specification Update
Preface Preface This document is an update to the specifications contained in the following processors: • Dual-Core Intel® Xeon® Processor LV • Dual-Core Intel® Xeon® Processor ULV • Intel® Celeron® Processor 1.66 GHz This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table.
Preface Intel® 64 and IA-32 Intel® Architecture Optimization Reference Manual 248966 Nomenclature Errata are design defects or errors. Errata may cause the Dual-Core Intel® Xeon® processor LV‘s behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. Specification Changes are modifications to the current published specifications.
Summary Tables of Changes Summary Tables of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
Summary Tables of Changes Note: Each Specification Update item is prefixed with a capital letter to distinguish the product. The key below details the letters that are used in Intel‘s microprocessor Specification Updates: A= C= D= E= F= I= J= K= L= M= N= O= P= Q= R= S= T= U= V= W= X= Y= Z= AA = AB = AC = AD = AE = AF = AG = AH = AI = AJ = AK = AL = AM = AN = 10 Dual-Core Intel® Xeon® processor 7000 sequence Intel® Celeron® processor Dual-Core Intel® Xeon® processor 2.
Summary Tables of Changes AO = AP = AQ = AR = AS = Quad-Core Intel® Xeon® processor 3200 series Dual-Core Intel® Xeon® processor 3000 series Intel® Pentium® dual-core desktop processor E2000 sequence Intel® Celeron® processor 500 series Intel® Xeon® processor 7200, 7300 series AV = Intel Core™2 Extreme processor QX9650 and Intel Core™2 Quad processor Q9000 series AW = Intel Core™ 2 Duo processor E8000 series AX = Quad-Core Intel Xeon processor 5400 series AY = Dual-Core Intel Xeon processor 5200 s
Summary Tables of Changes Number Stepping Plans C0 D0 AF1 X X No Fix FST Instruction with Numeric and Null Segment Exceptions May take Numeric Exception with Incorrect FPU Operand Pointer AF2 X X No Fix Code Segment Limit Violation May Occur on 4 Gbyte Limit Check AF3 12 ERRATA Errata – Removed.
Summary Tables of Changes Number Stepping Plans ERRATA C0 D0 AF23 X X No Fix Disabling of Single-step On Branch Operation May be Delayed following a POPFD Instruction AF24 X X No Fix Performance Monitoring Counters that Count External Bus Events May Report Incorrect Values after Processor Power State Transitions AF25 X X No Fix VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (LER) MSR AF26 X X No Fix General Protection (#GP) Fault May Not Be Signaled
Summary Tables of Changes Number Stepping Plans C0 D0 AF45 X X No Fix Simultaneous Access to the Same Page Table Entries by both Cores May Lead to Unexpected Processor Behavior AF46 X X No Fix Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt AF47 X X No Fix Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address Translations AF48 X X No Fix Counter Enable bit [22] of IA32_CR_PerfEvtSel0 and IA32_CR_PerfEvtSel1 Do Not
Summary Tables of Changes Number Stepping Plans ERRATA C0 D0 AF67 X X No Fix An Asynchronous MCE During a Far Transfer May Corrupt ESP AF68 X X No Fix BTM/BTS Branch-From Instruction Address May be Incorrect for Software Interrupts AF69 X X No Fix Store to WT Memory Data May be Seen in Wrong Order by Two Subsequent Loads AF70 X X No Fix Single Step Interrupts with Floating Point Exception Pending May Be Mishandled AF71 X X No Fix Non-Temporal Data Store May be Observed in Wrong P
Identification Information Identification Information Component Identification via Programming Interface The processor stepping can be identified by the following register contents: NOTES: 1. 2. Family1 Model2 0110 1110 The family corresponds to bit [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan.
Identification Information Table 1. Processor Identification Information SSPEC# FSB Speed Package Steppin g CPUID Speed HFM/LFM (GHz) VID HFM/.LFM (Volts) SL9HS 667 MHz Micro-FCPGA D-0 06ECh 1.66/1.00 1.0-1.2125/ 0.825 – 1.11 (ULV) SL9HP 667 MHz Micro-FCPGA D-0 06ECh 1.66/1.00 1.1125-1.275/ 0.825 – 1.11 (LV) SL9HN 667 MHz Micro-FCPGA D-0 06ECh 2.00/1.00 1.1125-1.275/ 0.825 – 1.11 (LV) SL9S3 667 MHz Micro-FCPGA D-0 06ECh 1.66/1.00 1.1125-1.275/ 0.825 – 1.
Errata Errata AF1. FST Instruction with Numeric and Null Segment Exceptions May take Numeric Exception with Incorrect FPU Operand Pointer Problem: If execution of an FST (Store Floating Point Value) instruction would generate both numeric and null segment exceptions, the numeric exception may be taken first and with the Null x87 FPU Instruction Operand (Data) Pointer.
Errata AF4. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering Violation Problem: Under certain conditions as described in the Software Developers Manual section ―Outof-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors‖ the processor performs REP MOVS or REP STOS as fast strings.
Errata AF7. Page with PAT (Page Attribute Table) Set to USWC (Uncacheable Speculative Write Combine) While Associated MTRR (Memory Type Range Register) Is UC (Uncacheable) May Consolidate to UC Problem: A page whose PAT memory type is USWC while the relevant MTRR memory type is UC, the consolidated memory type may be treated as UC (rather than WC as specified in IA-32 Intel® Architecture Software Developer's Manual). Implication: When this erratum occurs, the memory page may be as UC (rather than WC).
Errata AF10. Invalid Entries in Page-Directory-Pointer-Table Register (PDPTR) May Cause General Protection (#GP) Exception If the Reserved Bits Are Set to One Problem: Invalid entries in the Page-Directory-Pointer-Table Register (PDPTR) that have the reserved bits set to one may cause a General Protection (#GP) exception. Implication: Intel has not observed this erratum with any commercially available software. Workaround: Do not set the reserved bits to one when PDPTR entries are invalid.
Errata The PE bit of the FPU status word may not always be set upon receiving an inexactresult exception. Thus, if these exceptions are unmasked, a floating-point error exception handler may not recognize that a precision exception occurred. Note that this is a ―sticky‖ bit, i.e., once set by an inexact-result condition, it remains set until cleared by software. Workaround: This condition can be avoided by inserting two non-floating-point instructions between the two floating-point instructions.
Errata Workaround: Write to CR3, CR4 (setting bits PSE, PGE or PAE) or CR0 (setting bits PG or PE) registers before writing to memory early in BIOS code to clear all the global entries from TLB. Status: For the steppings affected, see the Summary Tables of Changes. AF16.
Errata Workaround: Software should enable Data Prefetch performance monitoring events on one core at a time. Status: For the steppings affected, see the Summary Tables of Changes. AF19. LOCK# Asserted During a Special Cycle Shutdown Transaction May Unexpectedly De-assert Problem: During a processor shutdown transaction, when LOCK# is asserted and if a DEFER# is received during a snoop phase and the Locked transaction is pipelined on the front side bus (FSB), LOCK# may unexpectedly de-assert.
Errata Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AF23. Disabling of Single-step On Branch Operation May be Delayed following a POPFD Instruction Problem: Problem: Disabling of Single-step On Branch Operation may be delayed, if the following conditions are met: 1. ―Single Step On Branch Mode‖ is enabled (DebugCtlMSR.BTF and EFLAGS.TF are set) 2. POPFD used to clear EFLAGS.TF 3. A jump instruction (JMP, Jcc, etc.
Errata Workaround: Software exception handlers that rely on the LER MSR value should read the LER MSR before executing VERW/VERR/LSL/LAR instructions. Status: For the steppings affected, see the Summary Tables of Changes. AF26. General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit Violation above 4-G Limit Problem: Memory accesses to flat data segments (base = 00000000h) that occur above the 4G limit (0ffffffffh) may not signal a #GP fault.
Errata Problem: The Resume from System Management Mode (RSM) instruction does not flush global pages from the Data Translation Look-Aside Buffer (DTLB) prior to reloading the saved architectural state. Implication: If SMM turns on paging with global paging enabled and then maps any of linear addresses of SMRAM using global pages, RSM may load data from the wrong location. Workaround: Workaround: Do not use global pages in System Management Mode.
Errata AF32. Hardware Prefetch Performance Monitoring Events May Be Counted Inaccurately Problem: Hardware prefetch activity is not accurately reflected in the hardware prefetch performance monitoring. Implication: This erratum may cause inaccurate counting for all hardware prefetch performance monitoring events. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of Changes. AF33.
Errata Status: For the steppings affected, see the Summary Tables of Changes. AF36. BTS Message May Be Lost When the STPCLK# Signal is Active Problem: STPCLK# is asserted to enable the processor to enter a low-power state. Under some circumstances, when STPCLK# becomes active, a pending BTS (Branch Trace Store) message may be either lost and not written or written with corrupted branch address to the Debug Store area. Implication: BTS messages may be lost in the presence of STPCLK# assertions.
Errata set by: • • • • • IO A non-I/O instruction SMI is pending while a lower priority event interrupts A REP I/O read An I/O read that redirects to MWAIT In systems supporting Intel® Virtualization Technology a fault in the middle of an operation that causes a VM Exit Implication: SMM handlers may get false IO_SMI indication. Workaround: The SMM handler has to evaluate the saved context to determine if the SMI was triggered by an instruction that read from an I/O port.
Errata AF42. Last Exception Record (LER) MSRs May be Incorrectly Updated Problem: The LASTINTTOIP and LASTINTFROMIP MSRs (1DDH-1DEH) may contain incorrect values after the following events: masked SSE2 floating-point exception, StopClk, NMI and INT.
Errata Status: For the steppings affected, see the Summary Tables of Changes. AF45. Simultaneous Access to the Same Page Translation Entries by Both Cores May Lead to Unexpected Processor Behavior Problem: When the following conditions occur simultaneously, this may create a rare internal condition which may lead to unexpected processor behavior.
Errata Workaround: Operating systems should not allow A20M# to be enabled if the masking of address bit 20 could be applied to an address that references a large page. A20M# is normally only used with the first megabyte of memory. Status: For the steppings affected, see the Summary Tables of Changes. AF48.
Errata Status: For the steppings affected, see the Summary Tables of Changes. AF50. Performance Monitoring Events for Retired Instructions (C0H) May Not Be Accurate Problem: The INST_RETIRED performance monitor may miscount retired instructions as follows: • Repeat string and repeat I/O operations are not counted when a hardware interrupt is received during or after the last iteration of the repeat flow. • VMLAUNCH and VMRESUME instructions are not counted.
Errata AF53. SSE/SSE2 Streaming Store Resulting in a Self-Modifying Code (SMC) Event May Cause Unexpected Behavior Problem: An SSE or SSE2 streaming store that results in a Self-Modifying Code (SMC) event may cause unexpected behavior. The SMC event occurs on a full address match of code contained in L1 cache. Implication: Due to this erratum, any of the following events may occur: 1.
Errata Problem: Software which is written so that multiple agents can modify the same shared unaligned memory location at the same time may experience a memory ordering issue if multiple loads access this shared data shortly thereafter. Exposure to this problem requires the use of a data write which spans a cache line boundary. Implication: This erratum may cause loads to be observed out of order. Intel has not observed this erratum with any commercially available software or system.
Errata since the MOV [r/e]SP, [r/e]BP will not generate a floating point exception. Developers of debug tools should be aware of the potential incorrect debug event signaling created by this erratum. Status: For the steppings affected, see the Summary Tables of Changes. AF59.
Errata AF62. AF62. Errata -- removed AF63. EFLAGS Discrepancy on Page Faults after a Translation Change Problem: This erratum is regarding the case where paging structures are modified to change a linear address from writable to non-writable without software performing an appropriate TLB invalidation.
Errata Workaround: Status: For the steppings affected, see the Summary Tables of Changes. AF66.
Errata the data from external memory or L2 written by another core, while the second load will get the data straight from the WT Store. Implication: Software that uses WB to WT memory aliasing may violate proper store ordering. Workaround: Do not use WB to WT aliasing. Status: For the steppings affected, see the Summary Tables of Changes. AF70.
Errata transferring to ring 0. Intel has not observed this erratum on any commercially available software. Workaround: Software that conforms to the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, section ―Buffering of Write Combining Memory Locations‖ will operate correctly. Status: For the steppings affected, see the Summary Tables of Changes. AF73.
Errata Status: For the steppings affected, see the Summary Tables of Changes. AF77. Performance Monitoring Events for Hardware Prefetch Requests (4EH) and Hardware Prefetch Request Cache Misses (4FH) May Not be Accurate Problem: Performance monitoring events that count hardware prefetch requests and prefetch misses may not be accurate. Implication: This erratum may cause inaccurate counting for Hardware Prefetch Requests and Hardware Prefetch Request Cache Misses. Workaround: None identified.
Errata Implication: A write-back store may be observed before a previous string or FXSAVE related store. Intel has not observed this erratum with any commercially available software. Workaround: Software desiring strict ordering of string/FXSAVE operations relative to subsequent write-back stores should add an MFENCE or SFENCE instruction between the string/FXSAVE operation and following store-order sensitive code such as that used for synchronization.
Specification Changes Specification Changes There are no Specification Changes in this Specification Update revision. Note: All specification changes will be incorporated into a future version of the appropriate processor documentation.
Specification Clarifications Specification Clarifications 1. Enhanced Cache Error Reporting for D0 Stepping Specification Clarification Beginning with the D0 stepping, enhanced cache error reporting - as described in Section 14.4 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual (SDM), Volume 3A: System Programming Guide – is supported by the processor. Older steppings use the original cache error reporting scheme. Please see the SDM, Volume 3A, for more details.
Documentation Changes Documentation Changes There are no documentation changes in this Specification Update revision. Note: All document changes will be incorporated into a future version of the processor documentation. Note: Documentation changes for Intel® 64 and IA-32 Architectures Software Developer Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate document named Intel® 64 and IA-32 Architectures Software Developer's Manual Documentation Changes.
