R Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.
VRM and EVRD 10.0 Design Guidelines R INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
VRM and EVRD 10.0 Design Guidelines R Contents 1 Applications ............................................................................................................... 8 1.1 2 Output Voltage Requirements................................................................................. 10 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 3 Vcc Power-Good (Vcc_PWRGD) PROPOSED ......................................... 26 Voltage Regulator Hot (VR_hot#) PROPOSED.........................................
VRM and EVRD 10.0 Design Guidelines R 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 9 Operating Temperature PROPOSED ........................................................ 32 VRM Board Temperature REQUIRED....................................................... 32 Non-Operating Temperature PROPOSED ................................................ 32 Humidity PROPOSED ................................................................................ 32 Altitude PROPOSED ..........................................
VRM and EVRD 10.
VRM and EVRD 10.0 Design Guidelines R Revision History 6 Date Revision Description June 2004 001 Initial release.
VRM and EVRD 10.
VRM and EVRD 10.0 Design Guidelines R 1 Applications This document defines DC-to-DC converters designed to help meet the power requirements of the Intel® Xeon™ processor with 800 MHz system bus and Low Voltage Intel® Xeon™ processor with 800 MHz system bus. The intent of this document is to define the electrical, thermal, and mechanical specifications for VRM 10.0.
VRM and EVRD 10.
VRM and EVRD 10.0 Design Guidelines R 2 Output Voltage Requirements 2.1 Voltage and Current REQUIRED A 6-bit VID code provided by the processor to the VRM/EVRD determines a reference output voltage, as described in Section 3.2. Sections 2.2 and 2.3 specify deviations from the VID reference voltage. The load lines in Section 2.2 show the relationship between Vcc and Icc for the processor.
VRM and EVRD 10.0 Design Guidelines R For the Low Voltage Intel® Xeon™ processor with 800MHz system bus, the VRM/EVRD will be required to support the following: • A continuous load current (Icc(TDC)) of 56A • A maximum load current (Icc(Max)) of 60A • A maximum load current step (Icc(Step)), within a 1 µs period, of 38.5A • A maximum current slew rate at the pins of the processor of 308A/µs Figure 2 displays the load current requirements over time. Figure 2 VRM/EVRD 10.0 Load Current vs.
VRM and EVRD 10.0 Design Guidelines R Table 1. Icc Guidelines Icc(TDC) (A) Icc(Max) (A) Icc(Step) (A) Slew Rate (A/µs) Intel® Xeon™ Processor with 800 MHz System Bus 85 100 70 560 Low Voltage Intel® Xeon™ processor with 800 MHz system bus 56 60 38.5 308 NOTES: 1. See the Intel® Xeon™ Processor with 800 MHz System Bus Datasheet and Low Voltage Intel® Xeon™ processor with 800 MHz System Bus Datasheet for the latest specifications. 2.
VRM and EVRD 10.0 Design Guidelines R 2.3 Voltage Tolerance REQUIRED The voltage ranges shown in Section 2.2 include the following tolerances: • Initial DC output voltage set-point error • Output ripple and noise • No-load offset centering error • Current sensing and droop errors • Component aging effects • Full ambient temperature range and warm up • • 2.
VRM and EVRD 10.0 Design Guidelines R 2.5 Stability REQUIRED The VRM/EVRD needs to be unconditionally stable under all specified output voltage ranges and current transients of any duty cycle and up to repetition rates of 1 MHz. The VRM/EVRD should be stable under a no load condition. 2.6 Processor Power Sequencing REQUIRED The VRM/EVRD must support platforms with defined power-up sequences.
VRM and EVRD 10.0 Design Guidelines R 2.7 Dynamic Voltage Identification (VID) REQUIRED VRM/EVRD 10.0 supports dynamic VID across the entire VID table, which requires the ability to reduce the load line voltage shown in Figure 3 by 450 mV. The VRM/EVRD must be capable of accepting voltage level changes of 12.5 mV steps every 5 µs, up to 36 steps (450 mV) in 180 µs. The low voltage state will be maintained for at least 50 µs.
VRM and EVRD 10.0 Design Guidelines R Figure 8. Example Processor VID Transition States 36 VID steps @ 5 µs each step = 180 µs VID 5 400 ns worst case VID settling time VID 0 VID 1 VID 2 VID 3 VID 4 Upper equals Final VID-1.25mΩ*Icc 450 mV low VID to high VID Vcc transition high VID to low VID Vcc transition Maximum Vcc settling 50 µs maximum settling from registering final VID 50 µs maximum settling from registering final VID Lower equals Start VID-1.25mΩ*Icc - 40mV Upper equals Start VID-1.
VRM and EVRD 10.0 Design Guidelines R to the processor socket as the keepout zones allow. If backside passive components are allowed in the design, it would be beneficial to place the 32 capacitors under the processor socket on the backside of the baseboard. Five of the 560 µF capacitors should be placed on one side of the processor socket and five on the other side as close to the processor socket as the keepout zones allow.
VRM and EVRD 10.0 Design Guidelines R 3 Control Signals 3.1 Output Enable (OUTEN) REQUIRED The VRM/EVRD should accept an input signal to enable its output voltage. When disabled, the VRM/EVRD output voltage should go to a high impedance state and should not sink or source current. When OUTEN is pulled low during the shutdown process, the VRM/EVRD should not exceed the previous voltage level regardless of the VID setting during the shutdown process.
VRM and EVRD 10.0 Design Guidelines R Table 5. Voltage Identification (VID) Processor Pins (0 = low, 1 = high) Vout (V) Processor Pins (0 = low, 1 = high) Vout (V) VID4 VID3 VID2 VID1 VID0 VID5 0.8375 1 1 0 1 0 0 1.2125 1 0.8500 1 1 0 0 1 1 1.2250 0 0.8625 1 1 0 0 1 0 1.2375 0 1 0.8750 1 1 0 0 0 1 1.2500 0 0 0 0.8875 1 1 0 0 0 0 1.2625 1 1 1 0.9000 1 0 1 1 1 1 1.2750 1 1 1 0 0.9125 1 0 1 1 1 0 1.2875 0 1 1 0 1 0.
VRM and EVRD 10.0 Design Guidelines R 3.3 Differential Remote Sense (VO_SEN+/–) REQUIRED The PWM controller will include differential sense inputs to compensate for an output voltage offset of <300 mV in the power distribution path. This common mode voltage is expected to occur due to transient currents and parasitic inductances and is not expected to be caused by parasitic resistances. The remote sense lines should draw no more than 10 mA, to minimize offset errors. 3.
VRM and EVRD 10.
VRM and EVRD 10.0 Design Guidelines R 4 Input Voltage and Current 4.1 Input Voltages EXPECTED The power source for the VRM/EVRD is 12 V +5/–8%. This voltage is supplied by a separate power supply. For input voltages outside the normal operating range, the VRM/EVRD should either operate properly or shut down. 4.
VRM and EVRD 10.
VRM and EVRD 10.0 Design Guidelines R 5 Processor Voltage Output Protection These are features built into the VRM/EVRD to help prevent damage to itself, the processor, or other system components. 5.1 Over-Voltage Protection (OVP) PROPOSED The OVP circuit monitors the processor core voltage (Vcc) for an over-voltage condition. If the output is more than 200 mV above the VID level, the VRM/EVRD shuts off the output. 5.
VRM and EVRD 10.
VRM and EVRD 10.0 Design Guidelines R 6 Output Indicators 6.1 Vcc Power-Good (Vcc_PWRGD) PROPOSED The VRM/EVRD may provide a power-good output signal, which remains in the low state until a maximum of 10 ms after the output voltage reaches the range specified in Section NOTES:22.2. The signal should then remain asserted as long as the VRM/EVRD output is operating within specification. It will be an open-collector/drain or equivalent signal.
VRM and EVRD 10.0 Design Guidelines R It is recommended that hysteresis be designed into the thermal sense circuit to prevent a scenario in which the VR_hot# signal is rapidly being asserted and deasserted. 6.3 Load Indicator Output (Load_current) PROPOSED The VRM/EVRD may have an output with a voltage level that varies linearly with the VRM/EVRD output current. The PWM controller supplier may specify a voltage-current relationship consistent with the controller’s current sensing method.
VRM and EVRD 10.0 Design Guidelines R 7 VRM – Mechanical Guidelines 7.1 VRM Connector EXPECTED The VRM interface with the baseboard is a 31-pin pair edge connector. The connector uses latches to hold the VRM in place. Table 9 shows the connector vendors and part numbers. Table 9. VRM 10.0 Connector Vendor and Part Numbers Vendor Part Number Notes Tyco/Amp 1489930-2 1 Foxconn 2EV04607-NW 1 NOTES: 1.
VRM and EVRD 10.0 Design Guidelines R Table 10. VRM 10.0 Connector Pin Descriptions Name Type Description Load_current Output Analog signal representing the output load current. OUTEN Input Output Enable. Vcc_PWRGD Output Output signal indicating that the output voltage of the VRM is in the specified range. VID[5:0] Input Voltage ID pins used to specify the VRM output voltage. VIN+ Power VRM Input Voltage. VIN− Ground VRM Input Ground. VO+ Power VRM Output Voltage.
VRM and EVRD 10.0 Design Guidelines R Table 11.
VRM and EVRD 10.0 Design Guidelines R 7.4 Mechanical Dimensions PROPOSED The mechanical dimensions for the VRM 10.0 module and connector are shown in Figure 10. 7.4.1 Gold Finger Specification The VRM board must contain gold lands (fingers) for interfacing with the VRM connector that are 1.27 mm ±0.05 mm [0.050 inches ±0.002 inches] wide by 5.08 mm [0.200 inches] minimum long and spaced 2.54 mm ±0.05 mm [0.100 inches ±0.002 inches] apart.
VRM and EVRD 10.0 Design Guidelines R 8 VRM – Environmental Conditions The VRM design, including materials, should be consistent with the manufacture of units that meet the environmental requirements specified below. 8.1 Operating Temperature PROPOSED The VRM shall meet all electrical requirements when operated at the Thermal Design Current (Icc(TDC)) over an ambient temperature of 0 ºC to +60 ºC with a minimum airflow of 400 LFM or 0 ºC to +45 ºC with a minimum airflow of 200 LFM.
VRM and EVRD 10.0 Design Guidelines R 8.6 Electrostatic Discharge PROPOSED Testing shall be in accordance with IEC 61000-4-2. Operating: 15 kV initialization level. The direct ESD event shall cause no out-of-regulation conditions – including overshoot, undershoot and nuisance trips of over-voltage protection, overcurrent protection, or remote shutdown circuitry. Non-operating: 25 kV initialization level. The direct ESD event shall not cause damage to the VRM circuitry. 8.
VRM and EVRD 10.0 Design Guidelines R 9 Manufacturing Considerations 9.1 Lead Free (Pb Free) Intel recommends that designers be aware of legislation regarding the use of lead in computer products such as the European Union (EU) Restriction on Hazardous Materials directive, also known as RoHS (commonly pronounced ‘rowhass’). The commission directive may be found at the following URL: http://europa.eu.int/eur-lex/pri/en/oj/dat/2003/l_037/l_03720030213en00190023.
VRM and EVRD 10.
