Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.
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Contents 1 Applications ........................................................................................................................ 7 1.1 2 Output Voltage Requirements ............................................................................................ 9 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 3 Power Good (Vcc_PWRGD) - PROPOSED ......................................................................27 Voltage Regulator Hot (VR_hot#) - PROPOSED.......................................
8.5 8.6 8.7 8.8 8.9 8.10 9 Altitude - PROPOSED....................................................................................................... 35 Electrostatic Discharge - PROPOSED .............................................................................. 36 Shock and Vibration - PROPOSED .................................................................................. 36 Electromagnetic Compatibility - PROPOSED ...................................................................
Revision History Document Number Revision Number Description Date 302732 001 • Initial release June 2004 302732 002 • Updated release to include 64-bit Intel® Xeon™ processor with 2 MB L2 cache launch February 2005 302732 003 • Incorporated 64-bit Intel® Xeon™ processor MP March 2005 NOTE: Not all revisions may be published. Guideline Categories REQUIRED: An essential part of the design – necessary to meet processor voltage and current specifications and follow processor layout guidelines.
Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.
1 Applications 1.1 Introduction and Terminology This document defines DC-to-DC converters to help meet the power requirements of computer systems using Intel® Xeon™ processor with 800 MHz system bus and 64-bit Intel® Xeon™ processor MP. Some SKUs of the Intel® Xeon™ processor with 800 MHz system bus only require the power requirements of VRM/EVRD 10.0, although all SKUs are capable of operating under VRM/EVRD 10.1 envelope.
Applications 8 Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.
2 Output Voltage Requirements 2.1 Voltage and Current - REQUIRED There will be independent selectable voltage identification (VID) codes for the core voltage regulator. The regulator’s 6-bit code (VID) will be provided by the processor to the VRM/EVRDs, which will determine a reference output voltage, as described in Section 3.2. Sections Load Line Definitions - REQUIRED and Voltage Tolerance - REQUIRED specify deviations from the VID reference voltage. The load line tolerance in Section 2.
Output Voltage Requirements The continuous load current can also be referred to as the Thermal Design Current (TDC). TDC is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and defines the current to use for the voltage regulator temperature assessment. At TDC, switching FETs reach maximum allowed temperature and may heat the baseboard layers and neighboring components.
Output Voltage Requirements Table 2-1. LL0, LL1 Codes LL0 LL1 0 0 VRM 10.0 SKUs of the Intel® Xeon™ processor with 800 MHz system bus mPGA604 Die Load Line 0 1 VRM 10.1 SKUs of the 64-bit Intel® Xeon™ processor MP with up to 8MB L3 cache and 64-bit Intel® Xeon™ with 1MB L2 cache 1 0 VRM 10.1 SKUs of the Intel® Xeon™ processor with 800 MHz system bus mPGA604 Die Load Line 1 1 Reserved LL0 LL1 0 0 0 1 1 2.3 1 0 1 Processor Vcc Tolerance / Load Line VccMAX = VID (V) – 1.
Output Voltage Requirements 2.4 Processor Vcc Overshoot - REQUIRED The Intel® Xeon™ processor with 800 MHz system bus can tolerate short transient overshoot events where Vcc exceeds the VID voltage when transitioning from a high-to-low current load condition. This processor Vcc overshoot does not apply to the 64-bit Intel® Xeon™ processor MP. This overshoot cannot exceed VID + VOS_MAX. The overshoot duration, which is the time that the overshoot can remain above VID, cannot exceed TOS_MAX.
Output Voltage Requirements Figure 2-4. Power-On Sequence Block Diagram Vcc VRM/EVRD VID[5:0] VID[5:0] VIDPWRGD To System Vcc VID_PWRGOOD VTT Delay * VTT CPU Vtt VR PWRGD VCC Vcc_PWRGD OUTEN * This Delay could be built into the V TT VR Figure 2-5. Power-On Sequence Timing Diagram Stage 1 90% of Vtt 1 Vtt 1ms
Output Voltage Requirements 2.7 Dynamic Voltage Identification (VID) - REQUIRED VRM/EVRD 10.1 supports dynamic VID across the entire VID table. The VRM/EVRD must be capable of accepting voltage level changes of 12.5 mV steps every 5 µs, up to 36 steps (450 mV) in 180 µs. The low voltage state will be maintained for at least 50 µs. The worst case settling time, including line-to-line skew, for the six VID lines is 400 ns.
Output Voltage Requirements Figure 2-7. Dynamic VID Transition States Illustration 36 VID steps @ 5 µs each step = 180 µs VID 5 400 ns worst case VID settling time VID 0 VID 1 VID 2 VID 3 VID 4 Upper equals Final VID-1.25mΩ*Icc 450 mV low VID to high VID Vcc transition high VID to low VID Vcc transition Maximum Vcc settling 50 µs maximum settling from registering final VID 50 µs maximum settling from registering final VID Lower equals Start VID-1.25mΩ*Icc - 40mV Upper equals Start VID-1.
Output Voltage Requirements Table 2-2. Recommended Decoupling and Other Specifications Processor 560 µF AlumPolymer 10 µF MLCC Slew Rate (di/dt) A/µs Thermal Design Current (A) Max Icc (A) 14 45 930 105 120 Intel® Xeon™ processor with 800 MHz system bus and 64-bit Intel® Xeon™ processor MP Figure 2-8 is a recommended example of a baseboard decoupling solution and a processor load. The number of capacitors needed may change based on updated processor power requirements.
Output Voltage Requirements Table 2-3. VRM 10.1 Decoupling Capacitor Recommendations Value Temperature Coefficient Tolerance ESR (mΩ) ESL (nH) 560 µF Al-Polymer ±20% N/A 7 4 10 µF Ceramic ±20% X5R or X6S 10 1.2 Note 1 NOTE: 1. Only the decoupling caps inside the socket cavity need to have the temperature coefficient of “X6S”. In Figure 2-8, the capacitance labeled “mPGA604 Socket and Package Pins” is supplied by Intel Corporation and is beyond the control of the system designer.
Output Voltage Requirements 18 Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.
3 Control Signals 3.1 Output Enable (OUTEN) - REQUIRED The VRM/EVRD should accept an input signal to enable its output voltage. When disabled, the regulator’s output should go to a high impedance state and should not sink or source current. When OUTEN is pulled low during the shutdown process, the VRM/EVRD should not exceed the previous voltage level regardless of the VID setting during the shutdown process. Once operating after power-up, it should respond to a deasserted OUTEN within 500 ms.
Control Signals Table 3-3. Voltage Identification (VID) Processor Pins (0 = low, 1 = high) VID4 VID3 VID2 VID1 VID0 VID5 0 1 0 1 0 0 0 1 0 0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 Vout (V) Processor Pins (0 = low, 1 = high) Vout (V) VID4 VID3 VID2 VID1 VID0 VID5 0.8375 1 1 0 1 0 0 1.2125 1 0.8500 1 1 0 0 1 1 1.2250 1 0 0.8625 1 1 0 0 1 0 1.2375 0 0 1 0.8750 1 1 0 0 0 1 1.2500 0 0 0 0.8875 1 1 0 0 0 0 1.2625 1 1 1 1 0.
Control Signals 3.3 Differential Remote Sense (VO_SEN±) - REQUIRED The PWM controller should include differential sense inputs to compensate for an output voltage offset of <300 mV in the power distribution path. This common mode voltage is expected to occur due to transient currents and parasitic inductances and is not expected to be caused by parasitic resistances. The remote sense lines should draw no more than 10m A, to minimize offset errors. 3.
Control Signals 22 Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.
4 Input Voltage and Current 4.1 Input Voltages - EXPECTED The power source for the VRM/EVRD is 12V +5% / –8%. This voltage is supplied by a separate power supply. For input voltages outside the normal operating range, the VRM/EVRD should either operate properly or shut down. 4.2 Load Transient Effects on Input Current EXPECTED The design of the VRM/EVRD, including the input power delivery filter, must ensure that the maximum slew rate of the input current does not exceed 0.
Input Voltage and Current 24 Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.
5 Processor Voltage Output Protection These are features built into the VRM/EVRD to help prevent damage to itself, the processor, or other system components. 5.1 Over-Voltage Protection (OVP) - PROPOSED The OVP circuit monitors the processor core voltage (Vcc) for an over-voltage condition. If the output is more than 200 mV above the VID level, the VRM/EVRD shuts off the output. 5.
Processor Voltage Output Protection 26 Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.
6 Output Indicators 6.1 Power Good (Vcc_PWRGD) - PROPOSED The VRM/EVRD may provide a power-good output signal, which remains in the low state until a maximum of 10 ms after the output voltage reaches the range specified in Section 2.2. The signal should then remain asserted as long as the VRM/EVRD output is operating within specification. It will be an open-collector/drain or equivalent signal. The pull-up resistor and voltage source will be located on the baseboard.
Output Indicators It is recommended that hysteresis be designed into the thermal sense circuit to prevent a scenario in which the VR_hot# signal is rapidly being asserted and de-asserted. 6.3 Load Indicator Output (Load Current) - PROPOSED The VRM/EVRD may have an output with a voltage (Load Current) level that varies linearly with the VRM/EVRD output current. The PWM controller supplier may specify a voltage-current relationship consistent with the controller’s current sensing method.
7 VRM – Mechanical Guidelines 7.1 VRM Connector - EXPECTED The part number and vendor name for the connector can be found in Table 7-1. The VRM interface with the system board is a 31-pin pair edge connector. The connector uses latches to hold the VRM in place. The connector will be rated to handle a continuous load current of 115 A. Table 7-1. VRM10.1 Connector Part Number and Vendor Name Connector Vendor Part Number Note Tyco/Amp 1489930-1 1 Foxconn 2EV04507-NW 1 NOTE: 1.
VRM – Mechanical Guidelines 7.3 Pin Descriptions and Assignments Table 7-2 shows the VRM10.1 connector pin description. The pins 4 and 59 labeled VIN+ and VIN- are used on the VRM10.1 module as an additional input voltage pair. Those pins are labeled “Reserved” in VRM10.0 and should not be used if there are plans to use VRM10.0 modules in this connector. See the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.0 Design Guidelines for more information.
VRM – Mechanical Guidelines Table 7-3. VRM 10.
VRM – Mechanical Guidelines 7.4 Mechanical Dimensions - PROPOSED The mechanical dimensions for the VRM 10.1 module and connector are shown in Figure 7-1. 7.4.1 Gold Finger Specification The VRM board must contain gold lands (fingers) for interfacing with the VRM connector that is 1.27 mm ±0.05 mm [0.050” ±0.002”] wide by 5.08 mm [0.200”] minimum long and spaced 2.54 mm ±0.05 mm [0.100” ±0.002”] apart. Traces from the lands to the power plane should be a minimum of 0.89 mm [0.
Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.1 Design Guidelines 9.60mm (0.378") MAX PIN 62 PIN 1 PIN 62 PIN 62 PIN 58 15.67mm (0.617") PIN 1 23.78mm (0.936") View A Com ponent Keepout 2.54mm (0.10") hole diameter 1.02+/-0.08mm (.040+/- .003") PIN 32 PCB Footprint PIN 32 CLOSED Latches 97.10mm (3.823") MAX OPEN Latches 113.0mm (4.449") MAX FAR SIDE Components NEAR SIDE Components 80.92mm +/- .05 (3.186" +/-.002) PIN 53 4.0mm +/-.10 (0.158"+/-.004) 3.
VRM – Mechanical Guidelines 34 Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.
8 VRM – Environmental Conditions The VRM design, including materials, should be consistent with the manufacture of units that meet the environmental requirements specified below. 8.1 Operating Temperature - PROPOSED The VRM shall meet all electrical requirements when operated at Thermal Design Current (Icc (TDC)) over an ambient temperature range of 0ºC to +45ºC with a minimum airflow of 400 LFM.
VRM – Environmental Conditions 8.6 Electrostatic Discharge - PROPOSED Testing shall be in accordance with IEC 61000-4-2. Operating – 15 kV initialization level. The direct ESD event shall cause no out-of-regulation conditions – including overshoot, undershoot and nuisance trips of over-voltage protection, overcurrent protection or remote shutdown circuitry. Non-operating –25 kV initialization level. The direct ESD event shall not cause damage to the VRM circuitry. 8.
9 Manufacturing Considerations 9.1 Lead Free (Pb Free) Intel recommends that designers be aware of legislation regarding the use of lead in computer products such as the European Union (EU) Restriction on Hazardous Materials directive, also known as RoHS (commonly pronounced ‘rowhass’). The commission directive may be found at the following URL: http://europa.eu.int/eur-lex/pri/en/oj/dat/2003/l_037/l_03720030213en00190023.
Manufacturing Considerations 38 Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.
