Intel® Xeon® Processor Specification Update December 2006 Notice: The Intel® Xeon® processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this specification update.
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Contents Revision History ................................................................................................................. 5 Preface ............................................................................................................................... 9 Identification Information .................................................................................................. 10 Mixed Steppings in DP Systems .........................................................................
Intel® Xeon® Processor Specification Update
Revision History Revision History Version Description Date -001 • Initial release. May 2001 -002 • Added errata P27-P28. June 2001 -003 • Updated erratum P25. June 2001 -004 • Added RCPPS, RCPSS, RSQRTPS and RSQRTSS instruction specification clarification. July 2001 -005 • Added errata P29-P32. August 2001 • Added Unused outputs specification clarifications. -006 • Added errata P33-34. September 2001 • Production mark update to include 2D matrix.
Revision History Version -015 Description Date • Added erratum P49. June 2002 • Updated errata P24, P40 status. • Added Document Changes P1-P2. -016 • Added new erratum P50. July 2002 • Added new Documentation Changes P3-P12. • Edited Summary of Errata Table erratum P40 to Plan Fix. • Minor edits to processor markings. -017 • Edited DP Matrix table. August 2002 • Updated the Summary of Errata table w C1 Step info. -018 • Added errata P51, P52. Edited erratum P14.
Revision History Version -028 Description Intel® Xeon® • Added new Processor Processor with 1-MB L3 Cache with Processor Signature=0F25H (M0 Stepping). Date July 2003 • Added New S-specs to the processor ID table for 0F25H (M0 Stepping) and 0F29h (D1 Stepping). • Added new processor with Processor Signature=0F29H (D1 Stepping). • Updated DP Platform Population Matrix for the Intel® Xeon® Processor to include 0F25H and 0F29H. • Removed Specification Clarification P3.
Revision History Version Description Date -051 • Updated erratum P53 and added erratum P83. January 2006 -052 • Updated links to Software Developers Manuals. Added s-spec SL8TJ. March 2006 -053 • Added S-specs SL8TK, SL8TL, SL8SE and SL8TH. April 2006 -054 • Updated Summary Table of Changes. October 2006 • Updated the Software Developer Manual Name. 8 -055 • Made changes to the DP Platform Population Matrix. November 2006 -056 • Updated Summary Table of Changes.
Preface Preface This document is an update to the specifications contained in the documents listed in the following Affected Documents/Related Documents table. It is a compilation of device and document errata and specification clarifications and changes, and is intended for hardware system manufacturers and for software developers of applications, operating system, and tools.
Identification Information Identification Information Intel® Xeon® Processor Markings, 256-KB Cache (603-pin Interposer INT-mPGA Package) Figure 1. Top Side Processor Marking 2D Matrix OR Intel® Xeon™ i(m) ©’01 Dynamic Laser Mark Area ATPO Mark (8 Characters) D0096109 0032 Serial Number Mark (4 digits) Figure 2. Bottom Side Processor Marking Dynamic Laser Mark Area Speed / Cache / Bus / Voltage S-Spec Country of Assy 1700DP/256/400/1.
Identification Information Intel® Xeon® Processor, 512-KB Cache, 400 and 533 MHz FSB Markings, (603-pin Interposer INT-mPGA Package and 604-pin Fc-mPGA2 Package) Figure 3. Top Side Processor Marking Intel® Xeon™ i m c ‘02 2D Matrix Includes ATPO and Serial Number (front end mark) Figure 4. Bottom Side Processor Marking Dynamic Laser Mark Area Speed / Cache / Bus / Voltage S-Spec Country of Assy 1800DP/512/400/1.
Identification Information Figure 5. Example of Production Mark – Top View Top View Brand Intel® Xeon™ i m c ‘01 Copyright information 2D Matrix Includes ATPO and Serial Number (front end mark) Pin A1 Triangle Figure 6. Example of Production Mark – Bottom View Bottom View Product Code with feature information: Speed/cache/bus/ voltage S-Spec and Assembly Site FPO and Serial Number (End of Line Mark) 1700DP/256L2/400/1.
Identification Information Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the Processor Signature instruction is executed with a 2 in the EAX register. Please refer to the Intel Processor Identification and the Processor Signature Instruction Application Note (AP-485) for further information on the Processor Signature instruction. Table 1.
Identification Information Table 1. Intel® Xeon® Processor Identification and Package Information (Sheet 2 of 5) S-Spec Number Core Stepping Processor Signature Speed Core/Front Side Bus (GHz/MHz) L2 Size (Kbytes) SL5ZA B0 0F24h 2.20/400 512-KB 01 603-pin micro-PGA interposer with 35 mm FC-BGA package 1 SL624 B0 0F24h 2.20/400 512-KB 01 603-pin micro-PGA interposer with 35 mm FC-BGA package 1, 2 SL687 B0 0F24h 2.
Identification Information Table 1. Intel® Xeon® Processor Identification and Package Information (Sheet 3 of 5) S-Spec Number Core Stepping Processor Signature Speed Core/Front Side Bus (GHz/MHz) L2 Size (Kbytes) SL6NR C1 0F27H 2.66/533 512-KB 01 604-pin micro-PGA interposer with 42.5 mm FC-PGA2 package 2, 5 SL6NS C1 0F27H 2.8/533 512-KB 01 604-pin micro-PGA interposer with 42.5 mm FC-PGA2 package 2, 5 SL6RQ C1 0F27H 2/533 512-KB 01 604-pin micro-PGA interposer with 42.
Identification Information Table 1. Intel® Xeon® Processor Identification and Package Information (Sheet 4 of 5) S-Spec Number Core Stepping Processor Signature Speed Core/Front Side Bus (GHz/MHz) L2 Size (Kbytes) SL74T D1 0F29H 2.40/533 512-KB 01 604-pin micro-PGA interposer with 42.5 mm FC-PGA2 package 7 SL6VK D1 0F29H 2/533 512-KB 01 604-pin micro-PGA Interposer with 42.5 mm FC-PGA2 package 5 604-pin micro-PGA interposer with 42.
Identification Information Table 1. Intel® Xeon® Processor Identification and Package Information (Sheet 5 of 5) S-Spec Number Core Stepping Processor Signature Speed Core/Front Side Bus (GHz/MHz) L2 Size (Kbytes) SL8TL L0 0F29H 2.40/533 512-KB L3 Size (Kbytes) Processor Interposer Revision 01 Package and Revision Notes 604-pin micro-PGA interposer with 42.5 mm FC-PGA2 package 5 2 SL8SE L0 0F29H 2/400 512-KB 01 604-pin micro-PGA interposer with 42.
Mixed Steppings in DP Systems Mixed Steppings in DP Systems Intel Corporation fully supports mixed steppings of Intel Xeon processors. The following list and processor matrix describes the requirements to support mixed steppings: • Mixed steppings are only supported with processors that have identical family numbers as indicated by the Processor Signature instruction. The Intel Xeon processor is available with two different Model numbers as indicated by the Processor Signature.
Mixed Steppings in DP Systems Table 2. DP Platform Matrix for the Intel® Xeon® Processor2 Processor Signature/Core Stepping 0F0Ah/C1 0F12h/D0 0F24h/B0 0F27h/C1 0F29h/D1 0F25h/M03 0F25h/M04 0F0Ah/C1 NI Note 1 X X X X X 0F12h/D0 Note 1 NI X X X X X 0F24h/B0 X X NI NI NI NI X 0F27h/C1 X X NI NI NI NI X 0F29h/D1 X X NI NI NI NI X 0F25h/M0 X X NI NI NI NI NI 0F29h/L0 X X NI NI NI NI X NOTES: 1.
Summary Table of Changes Summary Table of Changes The following table indicates the Specification Changes, Errata, Specification Clarifications or Documentation Changes, which apply to the listed MCH steppings. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted.
Summary Table of Changes Mobile Intel® Pentium® 4 processor-M 64-bit Intel® Xeon® processor MP with up to 8MB L3 Cache Mobile Intel® Celeron® processor on .
Summary Table of Changes Errata (Sheet 1 of 4) No.
Summary Table of Changes Errata (Sheet 2 of 4) No.
Summary Table of Changes Errata (Sheet 3 of 4) No.
Summary Table of Changes Errata (Sheet 4 of 4) No.
Summary Table of Changes Specification Changes No. P1 SPECIFICATION CHANGES Context ID feature added to processor signature instruction feature Flags/IA32_MISC_Enable registers Specification Clarifications No. SPECIFICATION CLARIFICATIONS P1 Maximum ITCC specification correction P2 Specification Clarification with respect to Time-Stamp Counter Documentation Changes No. DOCUMENTATION CHANGES None for this revision of the Specification Update.
Errata Errata P1 UC Code in same line as write back (WB) data may lead to data corruption Problem: This erratum occurs when both code (being accessed as uncacheable [UC] or write combining [WC]) and data (being accessed as write back [WB]) are placed in the same cache line. The UC fetch will cause the processor to self-snoop and generate an implicit WB. The data supplied by this implicit WB may be corrupted due to the way the processor is currently handling self-modifying code.
Errata P5 Processor may hang due to speculative page walks to nonexistent system memory Problem: A load operation issued speculatively by the processor that misses the data translation lookaside buffer (DTLB) results in a page walk. A branch instruction older than the load retires so that this load operation is now in the mispredicted branch path. Due to an internal boundary condition, in some instances the load is not canceled before the page walk is issued.
Errata Implication: When this erratum occurs, data corruption may occur. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Table of Changes.
Errata the L1 cache, the cache controller logic may write the physical address from a subsequent load or store operation into the IA32_MC1_ADDR register.
Errata occurs and the address is not available because the linear to physical address translation is not complete or an internal resource conflict has occurred, the Address Valid bit is incorrectly set. • The processor may hang when an instruction code fetch receives a hard failure response from the system bus. This occurs because the bus control logic does not return data to the core, leaving the processor empty. IA32_MC0_STATUS MSR does indicate that a hard fail response occurred.
Errata P12 Processor may live-lock if PDEs or PTEs are in UC space Problem: The processor may livelock under the following boundary conditions: • The page-directory entries (PDEs) or page-table entries (PTEs) are in uncacheable (UC) space. • An instruction fetch misses the ITLB resulting in a page walk. • This instruction fetch is immediately followed by a store that splits a page boundary. Implication: When this erratum occurs, the processor will livelock.
Errata Implication: When this erratum occurs, FPU Operand (Data) Pointer (FDP) may become corrupted. Workaround: This erratum will not occur with floating point exceptions masked. If FP exceptions are unmasked, then performance counting of x87 loads should be disabled. Status: For the steppings affected, see the Summary Table of Changes.
Errata corrected page tables are left in a non-accessed or non-modified state) the processor may livelock. Intel has not been able to reproduce this erratum with commercial software. Implication: This erratum occurs in systems where page tables are being modified by other processors. If this erratum is encountered, the processor will livelock resulting in a system hang or operating system failure. Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Errata P24 Bus invalidate line requests that returns unexpected data may result in L1 cache corruption Problem: When a bus invalidate line (BIL) request receives unexpected data from a deferred reply, and a store operation write combines to the same address, there is a small window where the L1 cache is corrupt, and loads can retire with this corrupted data. This erratum occurs in the following scenario: • A RFO transaction is issued by the processor and hits a line in shared state in the L2 cache.
Errata P27 Incorrect data may be returned when page tables are located in write combining (WC) memory Problem: If page directories and/or page tables are located in WC memory, speculative loads to cacheable memory may complete with incorrect data. Implication: Cacheable loads to memory mapped using page tables located in WC memory may return incorrect data. Intel has not been able to reproduce this erratum with commercially available software.
Errata P31 Multiple accesses to the same S-state L2 cache line and ECC error combination may result in loss of cache coherency Problem: When a RFO cycle has a 64 bit address match with an outstanding read hit on a line in the L2 cache which is in the S-state AND that line contains an ECC error, the processor should recycle the RFO until the ECC error is handled. Due to this erratum, the processor does not recycle the RFO and attempt to service both the RFO and the read hit at the same time.
Errata Status: For the steppings affected, see the Summary Table of Changes. P35 Livelock may occur when bus parking is disabled Problem: A livelock may occur when processor bus parking is disabled, and when (1) the processor is the symmetric owner of the bus with one internal request pending, and (2) the processor observes the assertion of BPRI#, BNR# or a full IOQ.
Errata • Simultaneously, an event that requires micro-architectural synchronization among the two logical processors occurs on the second logical processor. This event may cause an invalid instruction pointer to be stored on the ring 0 stack during the transition to GP fault handler on the first logical processor. Implication: The instruction pointer stored on the stack may be invalid, potentially causing errors during execution of or return from the GP fault handler.
Errata P42 Machine check exception (MCE) observed on DP platforms Problem: A system bus address parity error may be signaled if two processors run at odd core frequency to system Bus-ratios (17:1, 19:1, etc.) on DP processor platforms. This address parity error signaling issue does not occur if the processors run at even bus-ratios. Implication: A MCE may be observed on DP platforms.
Errata 1. A read to B misses in the L2 cache and allocates cache line B and its associated second-sector pre-fetch into an almost full bus queue. 2. A BRL to cache line B completes with HIT# and fills data in Shared (S) state. 3. The bus queue full condition causes the prefetch to cache line A to be canceled, cache line A will remain M in the WC buffers and I in the L2 while cache line B will be in the S state. Then, if the further conditions occur: a.
Errata P50 Simultaneous assertion of A20M# and INIT# may result in incorrect data fetch Problem: If A20M# and INIT# are simultaneously asserted by software, followed by a data access to the 0xFFFFFXXX memory region, with A20M# still asserted, incorrect data will be accessed. With A20M# asserted, an access to 0xFFFFFXXX should result in a load from physical address 0xFFEFFXXX.
Errata P54 STPCLK# signal assertion under certain conditions may cause a system hang Problem: The assertion of STPCLK# signal before a logical processor awakens from the “Wait-for-SIPI” state for the first time, may cause a system hang. A processor supporting HT Technology may fail to initialize appropriately, and may not issue a Stop Grant Acknowledge special bus cycle in response to the second STPCLK# assertion.
Errata Status: For the steppings affected, see the Summary Table of Changes. P59 Disabling a local APIC disables both logical processor on a Hyper-Threading Technology enabled processor Problem: Disabling a local APIC on one logical processor of a HT Technology enabled processor by clearing bit 11 of the IA32_APIC_BASE MSR will effectively disable the local APIC on the other logical processor.
Errata behavior in the presence of hardware task switches, therefore, may be unpredictable as a result of this erratum. This erratum has not been observed in commercially available software. Workaround: None at this time. Status: For the steppings affected, see the Summary Table of Changes.
Errata P66 Locks and SMC detection may cause the processor to temporarily hang Problem: The processor may temporarily hang in an HT Technology enabled system if one logical processor executes a synchronization loop that includes one or more bus locks and is waiting for release by the other logical processor.
Errata P70 Incorrect duty cycle is chosen when On-Demand Clock Modulation is enabled in a processor supporting Hyper-Threading Technology Problem: When a processor supporting HT Technology enables On-Demand Clock modulation on both logical processors, the processor is expected to select the lowest duty cycle of the two potentially different values. When one logical processor enters the AUTOHALT state, the duty cycle implemented should be unaffected by the halted logical processor.
Errata P74 Machine check exceptions may not update Last-Exception Record MSRs (LERs) Problem: The Last-Exception Record MSRs (LERs) may not get updated when machine check exceptions (MCE) occur. Implication: When this erratum occurs, the LER may not contain information relating to the MCE. They will contain information relating to the exception prior to the MCE. Workaround: None at this time. Status: For the steppings affected, see the Summary Table of Changes.
Errata Implication: Due to this erratum, the system may livelock until some external event interrupts the locked update. Intel has not observed this erratum with any commercially available software. Workaround: None at this time. Status: For the steppings affected, see the Summary Table of Changes.
Errata b. Update the associated cache line state information to shared state on the originating bus (rather than invalid state) in reaction to a BWIL or BLW. Status: For the steppings affected, see the Summary Table of Changes.
Specification Changes Specification Changes There are no new Specification Changes for this month. The Specification Changes listed in this section apply to the following documents: • Intel® Xeon® Processor at 1.40 GHz, 1.50 GHz, 1.70 and 2 GHz Datasheet (Order Number 249665) • Intel® Xeon® Processor with 512 KB L2 Cache at 1.80 GHz to 3.0 GHz Datasheet (Order Number 298642) • Intel® Xeon® Processor with 533 MHz Front Side Bus at 2 GHz to 3.
Specification Changes ECX [Bits] 10 52 Descriptions of Feature Flag Value Context ID. A value of ‘1’ indicates the L1 data cache mode can be set to either adaptive mode or shared mode. A value of ‘0’ this feature is not supported. See definition of the IA32_MISC_ENABLE MSR Bit 24 (L1 Data Cache Context Mode) for more details.
Specification Clarifications Specification Clarifications The Specification Clarifications listed in this section apply to the following documents: • Intel® Xeon® Processor at 1.40 GHz, 1.50 GHz, 1.70 and 2 GHz Datasheet (Order Number 249665) • Intel® Xeon® Processor with 512 KB L2 Cache at 1.80 GHz to 3.0 GHz Datasheet (Order Number 298642) • Intel® Xeon® Processor with 533 MHz Front Side Bus at 2 GHz to 3.20 GHz Datasheet (Order Number 252135) • Low Voltage Intel® Xeon® Processor at 1.60 GHz to 2.
Specification Clarifications 15.8 Time-Stamp Counter The IA-32 architecture (beginning with the Pentium® processor) defines a time-stamp counter mechanism that can be used to monitor and identify the relative time occurrence of processor events. The counter’s architecture includes the following components: • TSC flag — A feature bit that indicates the availability of the time-stamp counter. The counter is available in an IA-32 processor implementation if the function CPUID.1:EDX.TSC[bit 4] = 1.
Specification Clarifications The RDMSR and WRMSR instructions read and write the time-stamp counter, treating the time-stamp counter as an ordinary MSR (address 10H). In the Pentium 4, Intel Xeon, and P6 family processors, all 64-bits of the time-stamp counter are read using RDMSR (just as with RDTSC).
Documentation Changes Documentation Changes There are no new Documentation Changes for this month. Note: Documentation changes for Intel® 64 and IA-32 Intel® Architectures Software Developer’s Manual, volumes 1, 2A, 2B, 3A, and 3B will be posted in the separate document IA-32 Intel® Architecture and Intel® Extended Memory 64 Technology Software Developer’s Manual Documentation Changes. Follow the link below to become familiar with this file. http://developer.intel.com/design/pentium4/specupdt/252046.
