Voltage Regulator Module (VRM) 10.
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Contents 1 Applications ........................................................................................................................ 7 1.1 2 Output Voltage Requirements ............................................................................................ 9 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 Power Good (Vcc_PWRGD) - PROPOSED ......................................................................25 Voltage Regulator Hot (VR_hot#) - PROPOSED............................................
8.6 8.7 8.8 8.9 8.10 9 Electrostatic Discharge - PROPOSED .............................................................................. 34 Shock and Vibration - PROPOSED .................................................................................. 34 Electromagnetic Compatibility - PROPOSED ................................................................... 34 Reliability - PROPOSED ...................................................................................................
Revision History Document Number Revision Number 306761 001 Description • Initial release of this document Date March 2005 NOTE: Not all revisions may be published. Guideline Categories REQUIRED: An essential part of the design – necessary to meet processor voltage and current specifications and follow processor layout guidelines. EXPECTED: Part of Intel’s processor power definitions; necessary for consistency among the designs of many systems and power devices.
Voltage Regulator Module (VRM) 10.
1 Applications 1.1 Introduction and Terminology This document defines DC-to-DC converters to meet the power requirements of computer systems using 64-bit Intel® Xeon™ processor MP with up to 8MB L3 cache and 64-bit Intel® Xeon™ processor MP with 1MB L2 cache processor. Requirements will vary according to the needs of different computer systems and processors that a specific voltage regulator is expected to support.
Applications 8 Voltage Regulator Module (VRM) Design Guidelines
2 Output Voltage Requirements 2.1 Voltage and Current - REQUIRED There will be independent selectable voltage identification (VID) codes for the core voltage regulator. The regulator’s 6-bit code (VID) will be provided by the processor to the VRM, which will determine a reference output voltage, as described in Section 3.2. Section 2.2 and Section 2.3 specify deviations from the VID reference voltage. The load line tolerance in Section 2.2 shows the relationship between Vcc and Icc for the processor.
Output Voltage Requirements The continuous load current can also be referred to as the Thermal Design Current (TDC). TDC is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and defines the current to use for the voltage regulator temperature assessment. At TDC, switching FETs reach maximum allowed temperature and may heat the baseboard layers and neighboring components.
Output Voltage Requirements The encoding in Table 2-1 for the load lines is valid for the range of load current from 0 A to 120 A. The Load Line 0 (LL0) and Load Line 1 (LL1) control signals from Section 3.4, form a 2-bit load line selection and will be used to configure the Vcc VRM to supply the proper load lines for the processor. For implementation of LL0 and LL1 on the baseboard refer to the appropriate platform design guidelines. Table 2-1.
Output Voltage Requirements 2.4 Stability - REQUIRED The VRM needs to be unconditionally stable under all specified output voltage ranges, current transients of any duty cycle, and up to repetition rates of 1 MHz. The VRM should be stable under a no load condition. 2.5 Processor Power Sequencing - REQUIRED The VRM must support platforms with defined power-up sequences.
Output Voltage Requirements Figure 2-4. Power-On Sequence Timing Diagram Stage 1 90% of Vtt 1 Vtt 1ms
Output Voltage Requirements Figure 2-5. Processor Transition States VID High Load Line 2 A 3 Icc-max 5 VID Low Load Line 1 4 B Figure 2-6 is an example of dynamic VID. The diagram in Figure 2-6 assumes steady state, constant current during the dynamic VID transition for ease of illustration; actual processor behavior allows for any dIcc/dt during the transitions, depending on the code it is executing at that time.
Output Voltage Requirements 2.7 Overshoot at Turn-On or Turn-Off - REQUIRED The core VRM output voltage should remain within the load-line regulation band for the VID setting, while the VRM is turning on or turning off, with no over or undershoot out of regulation. No negative voltage below –100 mV may be present at the VRM output during turn-on or turn-off. 2.8 Output Filter Capacitance - REQUIRED The output filter capacitance for VRM based designs will be located on the baseboard.
Output Voltage Requirements Figure 2-8. 64-bit Intel® Xeon™ Processor MP with up to 1MB L2 Cache Load Model This design incorporates 560 µF Aluminum-polymer bulk capacitors and 10 µF ceramic highfrequency capacitors. Eight of the 10 µF capacitors should be placed in the cavity of the processor socket. The remaining 10 µF capacitors should be split evenly such that half are on one side of the processor socket and half are on the other side as close to the processor socket as the keepout zones allow.
3 Control Signals 3.1 Output Enable (OUTEN) - REQUIRED The VRM should accept an input signal to enable its output voltage. When disabled, the regulator’s output should go to a high impedance state and should not sink or source current. When OUTEN is pulled low during the shutdown process, the VRM should not exceed the previous voltage level regardless of the VID setting during the shutdown process. Once operating after power-up, it should respond to a deasserted OUTEN within 500 ms.
Control Signals Table 3-3. Voltage Identification (VID) Processor Pins (0 = low, 1 = high) VID4 VID3 VID2 VID1 VID0 VID5 0 1 0 1 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 Vout (V) Processor Pins (0 = low, 1 = high) Vout (V) VID4 VID3 VID2 VID1 VID0 VID5 0.8375 1 1 0 1 0 0 1.2125 1 0.8500 1 1 0 0 1 1 1.2250 0 0.8625 1 1 0 0 1 0 1.2375 0 1 0.8750 1 1 0 0 0 1 1.2500 0 0 0 0.8875 1 1 0 0 0 0 1.2625 1 1 1 1 0.
Control Signals 3.3 Differential Remote Sense (VO_SEN±) - REQUIRED The PWM controller should include differential sense inputs to compensate for an output voltage offset of <300 mV in the power distribution path. This common mode voltage is expected to occur due to transient currents and parasitic inductances and is not expected to be caused by parasitic resistances. The remote sense lines should draw no more than 10 mA, to minimize offset errors. 3.
Control Signals 20 Voltage Regulator Module (VRM) 10.
4 Input Voltage and Current 4.1 Input Voltages - EXPECTED The power source for the VRM is 12V +5% / –8%. This voltage is supplied by a separate power supply. For input voltages outside the normal operating range, the VRM should either operate properly or shut down. 4.2 Load Transient Effects on Input Current EXPECTED The design of the VRM, including the input power delivery filter, must ensure that the maximum slew rate of the input current does not exceed 0.
Input Voltage and Current 22 Voltage Regulator Module (VRM) 10.
5 Processor Voltage Output Protection These are features built into the VRM to prevent damage to itself, the processor, or other system components. 5.1 Over-Voltage Protection (OVP) - PROPOSED The OVP circuit monitors the processor core voltage (Vcc) for an over-voltage condition. If the output is more than 200 mV above the VID level, the VRM shuts off the output. 5.
Processor Voltage Output Protection 24 Voltage Regulator Module (VRM) 10.
6 Output Indicators 6.1 Power Good (Vcc_PWRGD) - PROPOSED The VRM may provide a power-good output signal, which remains in the low state until a maximum of 10 ms after the output voltage reaches the range specified in Section 2.2. The signal should then remain asserted as long as the VRM output is operating within specification. It will be an open-collector/drain or equivalent signal. The pull-up resistor and voltage source will be located on the baseboard.
Output Indicators It is recommended that hysteresis be designed into the thermal sense circuit to prevent a scenario in which the VR_hot# signal is rapidly being asserted and de-asserted. 6.3 Load Indicator Output (Load Current) - PROPOSED The VRM may have an output with a voltage (Load Current) level that varies linearly with the VRM output current. The PWM controller supplier may specify a voltage-current relationship consistent with the controller’s current sensing method.
7 VRM – Mechanical Guidelines 7.1 VRM Connector - EXPECTED The part number and vendor name for the connector can be found in Table 3-4. The VRM interface with the system board is a 27-pin pair edge connector. The connector uses latches to hold the VRM in place. The connector is rated to handle a continuous load current of 130 A. Table 7-1. VRM10.
VRM – Mechanical Guidelines Table 7-2. VRM 10.
VRM – Mechanical Guidelines Table 7-3. VRM 10.
VRM – Mechanical Guidelines 7.4 Mechanical Dimensions - PROPOSED The mechanical dimensions for the VRM 10.2 module and connector are shown in Figure 7-1. 7.4.1 Gold Finger Specification The VRM board must contain gold lands (fingers) for interfacing with the VRM connector that is 1.50 mm ±0.2 mm [0.059” ±0.008”] wide by 6.00 mm [0.236”] minimum long and spaced 2.50 mm [0.098”] apart. Traces from the lands to the power plane should be a minimum of 0.89 mm [0.035”] wide and of a minimal length.
Voltage Regulator Module (VRM) 10.2L Design Guidelines 9 .0 3 m m (0 . 3 5 6 " ) MAX 1 3 .1 8 m m (0 . 5 1 9 " ) 3 .0 0 m m (0 .1 1 8 " ) 1 3 .5 0 m m (0 . 5 3 1 " ) P IN 1 3 .3 3 m m (0 . 1 3 1 " ) P IN 5 4 P IN 1 P IN 5 4 1 5 .5 0 m m ( 0 .6 1 0 ") 5 1 .8 4 m m ( 2 .0 4 ”) V ie w A 2 8 .9 m m ( 1 .1 3 8 ") 7 .8 7 m m ( 0 .3 1 0 " ) 8 x 2 .5 0 m m (0 .0 9 8 " ) P C B F o o tp r i n t 5 .0 8 m m (0 . 2 0 0 " ) P IN 2 8 2 0 .0 m m ( 0 . 7 9 ") 6 5 .3 4 m m (2 .5 7 " ) MAX R 0 .
VRM – Mechanical Guidelines 32 Voltage Regulator Module (VRM) 10.
8 VRM – Environmental Conditions The VRM design, including materials, should be consistent with the manufacture of units that meet the environmental requirements specified below. 8.1 Operating Temperature - PROPOSED The VRM shall meet all electrical requirements when operated at Thermal Design Current (Icc (TDC)) over an ambient temperature range of 0ºC to +45ºC with a minimum airflow of 400 LFM.
VRM – Environmental Conditions 8.6 Electrostatic Discharge - PROPOSED Testing shall be in accordance with IEC 61000-4-2. Operating – 15 kV initialization level. The direct ESD event shall cause no out-of-regulation conditions – including overshoot, undershoot and nuisance trips of over-voltage protection, overcurrent protection or remote shutdown circuitry. Non-operating –25 kV initialization level. The direct ESD event shall not cause damage to the VRM circuitry. 8.
9 Manufacturing Considerations 9.1 Lead Free (Pb Free) The use of lead in electronic products is an increasingly visible environmental and political concern. The drivers for the reduction or elimination of lead in electronic products include: • • • • Customer desire for environmentally friendly (‘green’) products. Manufacturer desire to be environmentally friendly, and be perceived as such. Government initiatives regarding recycling of electronic products. Planned and potential legislation.
Manufacturing Considerations 36 Voltage Regulator Module (VRM) 10.
