64-bit Intel® Xeon® Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update June 2006 Notice: The 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2 cache versions) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this specification update.
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Contents Revision History ................................................................................................................. 5 Preface ............................................................................................................................... 6 Identification Information .................................................................................................... 7 Summary Table of Changes..............................................................................
64-bit Intel® Xeon® Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update
Revision History Revision History Version -001 Description • Initial release of the document. Date July 2004 -002 • Removed erratum P18 and renumbered existing errata. July 2004 -003 • Added errata S32-S35. Renamed errata numbering from P to S. August 2004 • Removed erratum S29 and renumbered existing errata. September 2004 -004 • Added errata S35-S65. • Added E0 step processor information to Table 1, “Identification Information”.
Preface Preface This document is an update to the specifications contained in the following documents: 1. 64-bit Intel® Xeon® Processor with 2 MB L2 Cache Datasheet (Document Number 306249) Link: http://developer/design/xeon/datashts/306249.htm 2. Intel® Xeon® Processor with 800 MHz System Bus Datasheet (Document Number 302355) Link: http://developer/design/xeon/datashts/302355.
Identification Information Identification Information 64-bit Intel® Xeon® Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Package Markings (604-pin FC-mPGA4 Package) Figure 1. Top-Side Processor Marking Example Intel Confidential 2D Matrix Includes ATPO and Serial Number (front end mark) Pin 1 Indicator Figure 2.
Identification Information Table 1. Identification Information Family1 Model2 Brand ID3 1111b 0011b 0000b 1111b 0100b 0000b NOTES: 1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID registers accessible through Boundary Scan 2.
Identification Information Table 2. 64-bit Intel® Xeon® Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Identification Information (Sheet 2 of 2) S-Spec Core Stepping CPUID Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision SL8KP G-1 0F49h 3 800 1 MB SL8KQ G-1 0F49h 3.20 800 SL8KR G-1 0F49h 3.40 SL8KS G-1 0F49h SL8RW G-1 SL7ZC Package and Revision Notes 01 604-pin micro-PGA with 42.5 x 42.
Identification Information Mixed Steppings in DP Systems Intel Corporation fully supports mixed steppings of the 64-bit Intel Xeon processor with 800 MHz system bus as well as mixed steppings of the 64-bit Intel Xeon processor with 2 MB L2 cache. The following list and processor matrix describes the requirements to support mixed steppings: • Mixed steppings are only supported with processors that have identical family numbers as indicated by the CPUID instruction.
Identification Information Table 3. DP Platform Population Matrix for the 64-bit Intel® Xeon® Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) FC-PGA4 Package Processor Signature / Core Stepping 0F34h / D-0 0F41h / E-0 0F49h / G-1 0F43h / N-0 0F4Ah / R-0 0F34h / D-0 NI NI NI X X 0F41h / E-0 NI NI NI X X 0F49h / G-1 NI NI NI X X 0F43h / N-0 X X X NI NI 0F4Ah / R-0 X X X NI NI NOTES: 1. X = Mixing processors of different steppings is not supported.
Summary Table of Changes Summary Table of Changes The following table indicates the Errata, Documentation Changes, Specification Clarifications, or Specification Changes that apply to Intel processors. Intel intends to fix some of the errata in a future stepping of the component, and to account for the other outstanding issues through documentation or specification changes as noted.
Summary Table of Changes W = X = Y = Z = AC = Intel® Celeron® M processor Intel® Pentium® M processor on 90 nm process with 2 MB L2 cache Intel® Pentium® M processor Mobile Intel® Pentium® 4 processor with 533 MHz system bus Intel® Celeron® processor in 478-pin package The Specification Updates for the Pentium® processor, Pentium® Pro processor, and other Intel products do not use this convention.
Summary Table of Changes Errata (Sheet 2 of 5) No.
Summary Table of Changes Errata (Sheet 3 of 5) D-0/ 0F34h E-0/ 0F41h S43 X X S44 X S45 X S46 No.
Summary Table of Changes Errata (Sheet 4 of 5) No. D-0/ 0F34h E-0/ 0F41h G-1/ 0F49h N-0/ 0F43h R-0/ 0F4Ah Plans Errata S63 X Fixed Writes to IA32_MISC_ENABLE may not update flags for both logical processors S64 X Fixed Execute Disable Bit set with CR4.
Summary Table of Changes Errata (Sheet 5 of 5) D-0/ 0F34h E-0/ 0F41h G-1/ 0F49h N-0/ 0F43h R-0/ 0F4Ah Plans S81 X X X X X Plan Fix Running in System Management Mode (SMM) and L1 data cache adaptive mode may cause unexpected system behavior when SMRAM is mapped to cacheable memory S82 X X X X X No Fix A 64-bit value of Linear Instruction Pointer (LIP) may be reported incorrectly in the Branch Trace Store (BTS) memory record or in the Precise Event Based Sampling (PEBS) memory record S8
Summary Table of Changes Specification Changes No. SPECIFICATION CHANGES None for this revision of the Specification Update. Specification Clarifications No. SPECIFICATION CLARIFICATIONS None for this revision of the Specification Update. Documentation Changes No. DOCUMENTATION CHANGES None for this revision of the Specification Update.
Errata Errata S1 Transaction is not retired after BINIT# Problem: If the first transaction of a locked sequence receives a HITM# and DEFER# during the snoop phase it should be retried and the locked sequence restarted. However, if BINIT# is also asserted during this transaction, the transaction will not be retried. Implication: When this erratum occurs, locked transactions will not be retried. Workaround: None at this time. Status: For the steppings affected, see the Summary Table of Changes.
Errata accesses data that splits across a page boundary with both pages of WB memory type. The use-once protocol activates and the memory type for the split halves get forced to UC. Since use-once does not apply to stores, the store unlock instructions go out as WB memory type. The full sequence on the Bus is: locked partial read (UC), partial read (UC), partial write (WB), locked partial write (WB). The Use-once protocol should not be applied to Load locks.
Errata occurred while the results of a previous error were in the error-reporting bank. The IA32_MC1_STATUS register should also record this event as multiple errors but instead records this event as only one correctable error. • The overflow bit should be set to indicate when more than one error has occurred. The overflow bit being set indicates that more than one error has occurred.
Errata special cycle to be issued to the bus before the processor vectors to the machine check handler. Once the chipset receives its last Stop Grant special cycle it is allowed to ignore any bus activity from the processors. As a result, processor accesses to the machine check handler may not be acknowledged, resulting in a processor hang. Implication: The processor is unable to correctly report and/or recover from certain errors Workaround: None at this time.
Errata S8 EMON event counting of x87 loads may not work as expected Problem: If a performance counter is set to count x87 loads and floating-point exceptions are unmasked, the FPU Operand (Data) Pointer (FDP) may become corrupted. Implication: When this erratum occurs, FPU Operand (Data) Pointer (FDP) may become corrupted. Workaround: This erratum will not occur with floating point exceptions masked.
Errata S12 Processor issues inconsistent transaction size attributes for locked operation Problem: When the processor is in the Page Address Extension (PAE) mode and detects the need to set the Access and/or Dirty bits in the page directory or page table entries, the processor sends an 8-byte load lock onto the system bus. A subsequent 8 byte store unlock is expected, but instead a 4 byte store unlock occurs.
Errata S16 System may hang if a fatal cache error causes bus write line (BWL) transaction to occur to the same cache line address as an outstanding bus read line (BRL) or bus read-invalidate line (BRIL) Problem: A processor internal cache fatal data ECC error may cause the processor to issue a bus write line (BWL) transaction to the same cache line address as an outstanding bus read line (BRL) or bus read-invalidate line (BRIL).
Errata S20 A 16-bit address wrap resulting from a near branch (jump or call) may cause an incorrect address to be reported to the #GP exception handler Problem: If a 16-bit application executes a branch instruction that causes an address wrap to a target address outside of the code segment, the address of the branch instruction should be provided to the general protection exception handler.
Errata error status register is being written due to a previous error, bit 6 does not get set and illegal vector errors are not flagged. Implication: The xAPIC may not report some Illegal Vector errors when they occur at approximately the same time as other xAPIC errors. The other xAPIC errors will continue to be reported. Workaround: None at this time. Status: For the steppings affected, see the Summary Table of Changes.
Errata Workaround: BIOS should initialize the second thread of the processor supporting HT Technology prior to STPCLK# assertion. Status: For the steppings affected, see the Summary Table of Changes.
Errata store unlock occurs. Correct data is provided since only the lower bytes change, however external logic monitoring the data transfer may be expecting an 8 byte load lock. Implication: No known commercially available chipsets are affected by this erratum. Workaround: None at this time. Status: For the steppings affected, see the Summary Table of Changes.
Errata S38 Stores to page tables may not be visible to pagewalks for subsequent loads without serializing or invalidating the page table entry Problem: Under rare timing circumstances, a page table load on behalf of a programmatically younger memory access may not get data from a programmatically older store to the page table entry if there is not a fencing operation or page translation invalidate operation between the store and the younger memory access.
Errata S43 Recursive page walks may cause a system hang Problem: A page walk, accessing the same page table entry multiple times but at different levels of the page table, which causes the page table entry to have its Access bit set may result in a system hang. Implication: When this erratum occurs, the system may experience a hang. Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary Table of Changes.
Errata S48 The base of a null segment may be non-zero on a processor supporting Intel® Extended Memory 64 Technology (Intel® EM64T) Problem: In IA-32e mode of the Intel EM64T processor, the base of a null segment may be non-zero. Implication: Due to this erratum, Intel EM64T enabled systems may encounter unexpected behavior when accessing memory using the null selector. Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Errata Implication: When this erratum occurs, systems may encounter unexpected behavior. Intel has not observed this erratum with any commercially available software. Workaround: Software should prevent LDT selector accesses from crossing the 0xffff limit. Status: For the steppings affected, see the Summary Table of Changes.
Errata S57 A push of ESP that faults may zero the upper 32-bits of RSP Problem: In the event that a push ESP instruction, that faults, is executed in compatibility mode, the processor will incorrectly zero upper 32-bits of RSP. Implication: A Push of ESP in compatibility mode will zero the upper 32-bits of RSP. Due to this erratum, this instruction fault may change the contents of RSP. This erratum has not been observed in commercially available software. Workaround: None at this time.
Errata S62 The Execute Disable Bit fault may be reported before other types of page fault when both occur Problem: If the Execute Disable Bit is enabled and both the Execute Disable Bit fault and page faults occur, the Execute Disable Bit fault will be reported prior to other types of page fault being reported. Implication: No impact to properly written code since both types of faults will be generated but in the opposite order.
Errata Status: For the steppings affected, see the Summary Table of Changes. S67 IA32_MCi_STATUS MSR may improperly indicate that additional MCA information may have been captured Problem: When a data parity error is detected and the bus queue is busy, the ADDRV and MISCV bits of the IA32_MCi_STATUS register may be asserted even though the contents of the IA32_MCi_ADDR and IA32_MCi_MISC MSRs were not properly captured.
Errata 2. The BTS/PEBS absolute maximum is less than a record size from the end of the virtual address space, and 3. The record that would cross the BTS/PEBS absolute maximum will also continue past the end of the virtual address space, a. BTS/PEBS record can be written that will wrap at the 4-Gbyte boundary (IA-32) or 2^64 boundary (Intel EM64T mode), and write memory outside of the BTS/PEBS buffer.
Errata Workaround: It is possible for the BIOS to contain a workaround for this erratum. Status: For the steppings affected, see the Summary of Changes.
Errata S78 REP MOVS or REP STOS instruction with RCX >= 2^32 may fail to execute to completion or may write to incorrect memory locations on processors supporting Intel® Extended Memory 64 Technology (Intel® EM64T) Problem: In IA-32e mode using Intel EM64T-enabled processors, an REP MOVS or an REP STOS instruction executed with the register RCX >= 2^32, may fail to execute to completion or may write data to incorrect memory locations.
Errata S82 A 64-bit value of Linear Instruction Pointer (LIP) may be reported incorrectly in the Branch Trace Store (BTS) memory record or in the Precise Event Based Sampling (PEBS) memory record Problem: On a processor supporting Intel EM64T, • If an instruction fetch wraps around the 4G boundary in Compatibility mode, the 64-bit value of LIP in the BTS memory record will be incorrect (upper 32 bits will be set to FFFFFFFFh when they should be 0).
Errata S86 Front Side Bus machine checks may be reported as a result of on-going transactions during warm reset Problem: Processor Front Side Bus (FSB) protocol/signal integrity machine checks may be reported if the transactions are initiated or in-progress during a warm reset. A warm reset is where the chipset asserts RESET# when the system is running. Implication: The processor may log FSB protocol/signal integrity machine checks if transactions are allowed to occur during RESET# assertions.
Errata S90 IRET under certain conditions may cause an unexpected Alignment Check Exception Problem: In IA-32e mode, it is possible to get an Alignment Check Exception (#AC) on the IRET instruction even though alignment checks were disabled at the start of the IRET. This can only occur if the IRET instruction is returning from CPL3 code to CPL3 code. IRETs from CPL0/1/2 are not affected.
Errata S93 Debug Status Register (DR6) Breakpoint Condition Detected Flags May be Set Incorrectly Problem: The Debug Status Register (DR6) may report detection of a spurious breakpoint condition under certain boundary conditions when either: • A "MOV SS" or "POP SS" instruction is immediately followed by a hardware debugger breakpoint instruction, or • Any debug register access ("MOV DRx, r32" or "MOV r32, DRx") results in a general-detect exception condition.
Specification Changes Specification Changes There are no new Specification Changes for this revision of the 64-bit Intel® Xeon® Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update. The Specification Changes listed in this section apply to the following documents: 1. 64-bit Intel® Xeon® Processor with 2 MB L2 Cache Datasheet (Document Number 306249) Link: http://developer/design/xeon/datashts/306249.htm 2.
Specification Clarifications Specification Clarifications There are no new Specification Clarifications for this revision of the 64-bit Intel® Xeon® Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache Versions) Specification Update. The Specification Clarifications listed in this section apply to the following documents: 1. 64-bit Intel® Xeon® Processor with 2 MB L2 Cache Datasheet (Document Number 306249) Link: http://developer/design/xeon/datashts/306249.htm 2.
Documentation Changes Documentation Changes Note: Documentation changes for IA-32 Intel® Architecture Software Developer’s Manual, Volumes 1, 2A, 2B, and 3 will be posted in the separate document IA-32 Intel® Architecture Software Developer’s Manual Documentation Changes. Follow the link below to become familiar with this file. http://developer.intel.com/design/pentium4/specupdt/252046.
